1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMR35J18B 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR35J18B_PIO_ 31 #define _SAMR35J18B_PIO_ 32 33 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 34 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 35 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 36 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 37 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 38 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 39 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 40 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 41 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 42 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 43 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 44 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 45 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 46 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 47 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 48 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 49 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 50 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 51 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 52 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 53 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 54 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 55 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 56 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 57 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 58 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 59 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 60 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 61 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 62 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 63 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 64 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 65 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 66 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 67 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 68 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 69 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 70 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 71 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 72 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 73 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 74 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 75 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 76 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 77 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 78 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 79 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 80 #define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */ 81 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 82 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 83 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 84 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 85 #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ 86 #define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ 87 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 88 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 89 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 90 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 91 #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ 92 #define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ 93 #define PIN_PB16 48 /**< \brief Pin Number for PB16 */ 94 #define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ 95 #define PIN_PB17 49 /**< \brief Pin Number for PB17 */ 96 #define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ 97 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 98 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 99 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 100 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 101 #define PIN_PB30 62 /**< \brief Pin Number for PB30 */ 102 #define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ 103 #define PIN_PB31 63 /**< \brief Pin Number for PB31 */ 104 #define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ 105 #define PIN_PC18 82 /**< \brief Pin Number for PC18 */ 106 #define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ 107 #define PIN_PC19 83 /**< \brief Pin Number for PC19 */ 108 #define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ 109 /* ========== PORT definition for RSTC peripheral ========== */ 110 #define PIN_PA00A_RSTC_EXTWAKE0 _L_(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ 111 #define MUX_PA00A_RSTC_EXTWAKE0 _L_(0) 112 #define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) 113 #define PORT_PA00A_RSTC_EXTWAKE0 (_UL_(1) << 0) 114 #define PIN_PA01A_RSTC_EXTWAKE1 _L_(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ 115 #define MUX_PA01A_RSTC_EXTWAKE1 _L_(0) 116 #define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) 117 #define PORT_PA01A_RSTC_EXTWAKE1 (_UL_(1) << 1) 118 #define PIN_PA04A_RSTC_EXTWAKE4 _L_(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ 119 #define MUX_PA04A_RSTC_EXTWAKE4 _L_(0) 120 #define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) 121 #define PORT_PA04A_RSTC_EXTWAKE4 (_UL_(1) << 4) 122 #define PIN_PA05A_RSTC_EXTWAKE5 _L_(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ 123 #define MUX_PA05A_RSTC_EXTWAKE5 _L_(0) 124 #define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) 125 #define PORT_PA05A_RSTC_EXTWAKE5 (_UL_(1) << 5) 126 #define PIN_PA06A_RSTC_EXTWAKE6 _L_(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ 127 #define MUX_PA06A_RSTC_EXTWAKE6 _L_(0) 128 #define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) 129 #define PORT_PA06A_RSTC_EXTWAKE6 (_UL_(1) << 6) 130 #define PIN_PA07A_RSTC_EXTWAKE7 _L_(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ 131 #define MUX_PA07A_RSTC_EXTWAKE7 _L_(0) 132 #define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) 133 #define PORT_PA07A_RSTC_EXTWAKE7 (_UL_(1) << 7) 134 /* ========== PORT definition for SUPC peripheral ========== */ 135 #define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ 136 #define MUX_PB02H_SUPC_OUT1 _L_(7) 137 #define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) 138 #define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) 139 #define PIN_PB00H_SUPC_PSOK _L_(32) /**< \brief SUPC signal: PSOK on PB00 mux H */ 140 #define MUX_PB00H_SUPC_PSOK _L_(7) 141 #define PINMUX_PB00H_SUPC_PSOK ((PIN_PB00H_SUPC_PSOK << 16) | MUX_PB00H_SUPC_PSOK) 142 #define PORT_PB00H_SUPC_PSOK (_UL_(1) << 0) 143 #define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ 144 #define MUX_PB03H_SUPC_VBAT _L_(7) 145 #define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) 146 #define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) 147 /* ========== PORT definition for GCLK peripheral ========== */ 148 #define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ 149 #define MUX_PB22H_GCLK_IO0 _L_(7) 150 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) 151 #define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) 152 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 153 #define MUX_PA14H_GCLK_IO0 _L_(7) 154 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 155 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 156 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 157 #define MUX_PA27H_GCLK_IO0 _L_(7) 158 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 159 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 160 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 161 #define MUX_PA30H_GCLK_IO0 _L_(7) 162 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 163 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 164 #define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */ 165 #define MUX_PA28H_GCLK_IO0 _L_(7) 166 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) 167 #define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28) 168 #define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ 169 #define MUX_PB15H_GCLK_IO1 _L_(7) 170 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) 171 #define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) 172 #define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ 173 #define MUX_PB23H_GCLK_IO1 _L_(7) 174 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) 175 #define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) 176 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 177 #define MUX_PA15H_GCLK_IO1 _L_(7) 178 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 179 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 180 #define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ 181 #define MUX_PB16H_GCLK_IO2 _L_(7) 182 #define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) 183 #define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) 184 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 185 #define MUX_PA16H_GCLK_IO2 _L_(7) 186 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 187 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 188 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 189 #define MUX_PA17H_GCLK_IO3 _L_(7) 190 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 191 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 192 #define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ 193 #define MUX_PB17H_GCLK_IO3 _L_(7) 194 #define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) 195 #define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) 196 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 197 #define MUX_PA10H_GCLK_IO4 _L_(7) 198 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 199 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 200 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 201 #define MUX_PA11H_GCLK_IO5 _L_(7) 202 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 203 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 204 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 205 #define MUX_PA22H_GCLK_IO6 _L_(7) 206 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 207 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 208 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 209 #define MUX_PA23H_GCLK_IO7 _L_(7) 210 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 211 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 212 /* ========== PORT definition for EIC peripheral ========== */ 213 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 214 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 215 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 216 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 217 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 218 #define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ 219 #define MUX_PB00A_EIC_EXTINT0 _L_(0) 220 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) 221 #define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) 222 #define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ 223 #define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ 224 #define MUX_PB16A_EIC_EXTINT0 _L_(0) 225 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) 226 #define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) 227 #define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ 228 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 229 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 230 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 231 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 232 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 233 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 234 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 235 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 236 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 237 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 238 #define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ 239 #define MUX_PB17A_EIC_EXTINT1 _L_(0) 240 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) 241 #define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) 242 #define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ 243 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 244 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 245 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 246 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 247 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 248 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 249 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 250 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 251 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 252 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 253 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 254 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 255 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 256 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 257 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 258 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 259 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 260 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 261 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 262 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 263 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 264 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 265 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 266 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 267 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 268 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 269 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 270 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 271 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 272 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 273 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 274 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 275 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 276 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 277 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 278 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 279 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 280 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 281 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 282 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 283 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 284 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 285 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 286 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 287 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 288 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 289 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 290 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 291 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 292 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 293 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 294 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 295 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 296 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 297 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 298 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 299 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 300 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 301 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 302 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 303 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 304 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 305 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 306 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 307 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 308 #define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */ 309 #define MUX_PA28A_EIC_EXTINT8 _L_(0) 310 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) 311 #define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28) 312 #define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */ 313 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 314 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 315 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 316 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 317 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 318 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 319 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 320 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 321 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 322 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 323 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 324 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 325 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 326 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 327 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 328 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 329 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 330 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 331 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 332 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 333 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 334 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 335 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 336 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 337 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 338 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 339 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 340 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 341 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 342 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 343 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 344 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 345 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 346 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 347 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 348 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 349 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 350 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 351 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 352 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 353 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 354 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 355 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 356 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 357 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 358 #define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ 359 #define MUX_PB30A_EIC_EXTINT14 _L_(0) 360 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) 361 #define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) 362 #define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ 363 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 364 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 365 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 366 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 367 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 368 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 369 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 370 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 371 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 372 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 373 #define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ 374 #define MUX_PB15A_EIC_EXTINT15 _L_(0) 375 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) 376 #define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) 377 #define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ 378 #define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ 379 #define MUX_PB31A_EIC_EXTINT15 _L_(0) 380 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) 381 #define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) 382 #define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ 383 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 384 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 385 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 386 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 387 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 388 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 389 #define MUX_PA08A_EIC_NMI _L_(0) 390 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 391 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 392 /* ========== PORT definition for SERCOM0 peripheral ========== */ 393 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 394 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 395 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 396 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 397 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 398 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 399 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 400 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 401 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 402 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 403 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 404 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 405 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 406 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 407 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 408 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 409 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 410 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 411 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 412 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 413 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 414 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 415 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 416 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 417 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 418 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 419 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 420 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 421 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 422 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 423 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 424 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 425 /* ========== PORT definition for SERCOM1 peripheral ========== */ 426 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 427 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 428 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 429 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 430 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 431 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 432 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 433 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 434 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 435 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 436 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 437 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 438 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 439 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 440 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 441 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 442 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 443 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 444 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 445 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 446 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 447 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 448 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 449 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 450 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 451 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 452 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 453 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 454 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 455 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 456 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 457 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 458 /* ========== PORT definition for SERCOM2 peripheral ========== */ 459 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 460 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 461 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 462 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 463 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 464 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 465 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 466 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 467 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 468 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 469 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 470 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 471 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 472 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 473 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 474 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 475 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 476 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 477 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 478 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 479 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 480 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 481 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 482 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 483 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 484 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 485 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 486 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 487 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 488 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 489 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 490 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 491 /* ========== PORT definition for SERCOM3 peripheral ========== */ 492 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 493 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 494 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 495 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 496 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 497 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 498 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 499 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 500 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 501 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 502 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 503 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 504 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 505 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 506 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 507 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 508 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 509 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 510 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 511 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 512 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 513 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 514 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 515 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 516 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 517 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 518 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 519 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 520 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 521 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 522 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 523 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 524 /* ========== PORT definition for SERCOM4 peripheral ========== */ 525 #define PIN_PA12D_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ 526 #define MUX_PA12D_SERCOM4_PAD0 _L_(3) 527 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) 528 #define PORT_PA12D_SERCOM4_PAD0 (_UL_(1) << 12) 529 #define PIN_PA13D_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ 530 #define MUX_PA13D_SERCOM4_PAD1 _L_(3) 531 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) 532 #define PORT_PA13D_SERCOM4_PAD1 (_UL_(1) << 13) 533 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 534 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 535 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 536 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 537 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 538 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 539 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 540 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 541 #define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ 542 #define MUX_PB15C_SERCOM4_PAD3 _L_(2) 543 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) 544 #define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) 545 /* ========== PORT definition for TCC0 peripheral ========== */ 546 #define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ 547 #define MUX_PA04E_TCC0_WO0 _L_(4) 548 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) 549 #define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) 550 #define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 551 #define MUX_PA08E_TCC0_WO0 _L_(4) 552 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 553 #define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) 554 #define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ 555 #define MUX_PB30E_TCC0_WO0 _L_(4) 556 #define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) 557 #define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) 558 #define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ 559 #define MUX_PA05E_TCC0_WO1 _L_(4) 560 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) 561 #define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) 562 #define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 563 #define MUX_PA09E_TCC0_WO1 _L_(4) 564 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 565 #define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) 566 #define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ 567 #define MUX_PB31E_TCC0_WO1 _L_(4) 568 #define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) 569 #define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) 570 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 571 #define MUX_PA10F_TCC0_WO2 _L_(5) 572 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 573 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 574 #define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 575 #define MUX_PA18F_TCC0_WO2 _L_(5) 576 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 577 #define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) 578 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 579 #define MUX_PA11F_TCC0_WO3 _L_(5) 580 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 581 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 582 #define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 583 #define MUX_PA19F_TCC0_WO3 _L_(5) 584 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 585 #define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) 586 #define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ 587 #define MUX_PA22F_TCC0_WO4 _L_(5) 588 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) 589 #define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) 590 #define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ 591 #define MUX_PB16F_TCC0_WO4 _L_(5) 592 #define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) 593 #define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) 594 #define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ 595 #define MUX_PA14F_TCC0_WO4 _L_(5) 596 #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) 597 #define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) 598 #define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ 599 #define MUX_PA15F_TCC0_WO5 _L_(5) 600 #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) 601 #define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) 602 #define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ 603 #define MUX_PA23F_TCC0_WO5 _L_(5) 604 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) 605 #define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) 606 #define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ 607 #define MUX_PB17F_TCC0_WO5 _L_(5) 608 #define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) 609 #define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) 610 #define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ 611 #define MUX_PA12F_TCC0_WO6 _L_(5) 612 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) 613 #define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) 614 #define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ 615 #define MUX_PA16F_TCC0_WO6 _L_(5) 616 #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) 617 #define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) 618 #define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ 619 #define MUX_PA13F_TCC0_WO7 _L_(5) 620 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) 621 #define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) 622 #define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ 623 #define MUX_PA17F_TCC0_WO7 _L_(5) 624 #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) 625 #define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) 626 /* ========== PORT definition for TCC1 peripheral ========== */ 627 #define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 628 #define MUX_PA06E_TCC1_WO0 _L_(4) 629 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 630 #define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6) 631 #define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 632 #define MUX_PA10E_TCC1_WO0 _L_(4) 633 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 634 #define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10) 635 #define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 636 #define MUX_PA30E_TCC1_WO0 _L_(4) 637 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 638 #define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30) 639 #define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 640 #define MUX_PA07E_TCC1_WO1 _L_(4) 641 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 642 #define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7) 643 #define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 644 #define MUX_PA11E_TCC1_WO1 _L_(4) 645 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 646 #define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11) 647 #define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 648 #define MUX_PA31E_TCC1_WO1 _L_(4) 649 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 650 #define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31) 651 #define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */ 652 #define MUX_PA08F_TCC1_WO2 _L_(5) 653 #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) 654 #define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8) 655 #define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 656 #define MUX_PA24F_TCC1_WO2 _L_(5) 657 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 658 #define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24) 659 #define PIN_PB30F_TCC1_WO2 _L_(62) /**< \brief TCC1 signal: WO2 on PB30 mux F */ 660 #define MUX_PB30F_TCC1_WO2 _L_(5) 661 #define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) 662 #define PORT_PB30F_TCC1_WO2 (_UL_(1) << 30) 663 #define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */ 664 #define MUX_PA09F_TCC1_WO3 _L_(5) 665 #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) 666 #define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9) 667 #define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 668 #define MUX_PA25F_TCC1_WO3 _L_(5) 669 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 670 #define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25) 671 #define PIN_PB31F_TCC1_WO3 _L_(63) /**< \brief TCC1 signal: WO3 on PB31 mux F */ 672 #define MUX_PB31F_TCC1_WO3 _L_(5) 673 #define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) 674 #define PORT_PB31F_TCC1_WO3 (_UL_(1) << 31) 675 /* ========== PORT definition for TCC2 peripheral ========== */ 676 #define PIN_PA12E_TCC2_WO0 _L_(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */ 677 #define MUX_PA12E_TCC2_WO0 _L_(4) 678 #define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) 679 #define PORT_PA12E_TCC2_WO0 (_UL_(1) << 12) 680 #define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 681 #define MUX_PA16E_TCC2_WO0 _L_(4) 682 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 683 #define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16) 684 #define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */ 685 #define MUX_PA00E_TCC2_WO0 _L_(4) 686 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) 687 #define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0) 688 #define PIN_PA13E_TCC2_WO1 _L_(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */ 689 #define MUX_PA13E_TCC2_WO1 _L_(4) 690 #define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) 691 #define PORT_PA13E_TCC2_WO1 (_UL_(1) << 13) 692 #define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 693 #define MUX_PA17E_TCC2_WO1 _L_(4) 694 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 695 #define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17) 696 #define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */ 697 #define MUX_PA01E_TCC2_WO1 _L_(4) 698 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) 699 #define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1) 700 /* ========== PORT definition for TC0 peripheral ========== */ 701 #define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ 702 #define MUX_PA22E_TC0_WO0 _L_(4) 703 #define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) 704 #define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) 705 #define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ 706 #define MUX_PA23E_TC0_WO1 _L_(4) 707 #define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) 708 #define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) 709 /* ========== PORT definition for TC1 peripheral ========== */ 710 #define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ 711 #define MUX_PA24E_TC1_WO0 _L_(4) 712 #define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) 713 #define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) 714 #define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ 715 #define MUX_PA25E_TC1_WO1 _L_(4) 716 #define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) 717 #define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) 718 #define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ 719 #define MUX_PB15E_TC1_WO1 _L_(4) 720 #define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) 721 #define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) 722 /* ========== PORT definition for TC2 peripheral ========== */ 723 #define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ 724 #define MUX_PB02E_TC2_WO0 _L_(4) 725 #define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) 726 #define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) 727 #define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ 728 #define MUX_PB16E_TC2_WO0 _L_(4) 729 #define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) 730 #define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) 731 #define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ 732 #define MUX_PB03E_TC2_WO1 _L_(4) 733 #define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) 734 #define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) 735 #define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ 736 #define MUX_PB17E_TC2_WO1 _L_(4) 737 #define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) 738 #define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) 739 /* ========== PORT definition for TC3 peripheral ========== */ 740 #define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ 741 #define MUX_PB00E_TC3_WO0 _L_(4) 742 #define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) 743 #define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) 744 #define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ 745 #define MUX_PB22E_TC3_WO0 _L_(4) 746 #define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) 747 #define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) 748 #define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ 749 #define MUX_PB23E_TC3_WO1 _L_(4) 750 #define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) 751 #define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) 752 /* ========== PORT definition for DAC peripheral ========== */ 753 #define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ 754 #define MUX_PA05B_DAC_VOUT1 _L_(1) 755 #define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) 756 #define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) 757 /* ========== PORT definition for SERCOM5 peripheral ========== */ 758 #define PIN_PA22D_SERCOM5_PAD0 _L_(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ 759 #define MUX_PA22D_SERCOM5_PAD0 _L_(3) 760 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) 761 #define PORT_PA22D_SERCOM5_PAD0 (_UL_(1) << 22) 762 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 763 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 764 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 765 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 766 #define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ 767 #define MUX_PB30D_SERCOM5_PAD0 _L_(3) 768 #define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) 769 #define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) 770 #define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ 771 #define MUX_PB16C_SERCOM5_PAD0 _L_(2) 772 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) 773 #define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) 774 #define PIN_PA23D_SERCOM5_PAD1 _L_(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ 775 #define MUX_PA23D_SERCOM5_PAD1 _L_(3) 776 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) 777 #define PORT_PA23D_SERCOM5_PAD1 (_UL_(1) << 23) 778 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 779 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 780 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 781 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 782 #define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ 783 #define MUX_PB31D_SERCOM5_PAD1 _L_(3) 784 #define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) 785 #define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) 786 #define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ 787 #define MUX_PB17C_SERCOM5_PAD1 _L_(2) 788 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) 789 #define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) 790 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 791 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 792 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 793 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 794 #define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ 795 #define MUX_PB00D_SERCOM5_PAD2 _L_(3) 796 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) 797 #define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) 798 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 799 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 800 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 801 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 802 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 803 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 804 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 805 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 806 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 807 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 808 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 809 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 810 /* ========== PORT definition for TC4 peripheral ========== */ 811 #define PIN_PA18E_TC4_WO0 _L_(18) /**< \brief TC4 signal: WO0 on PA18 mux E */ 812 #define MUX_PA18E_TC4_WO0 _L_(4) 813 #define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) 814 #define PORT_PA18E_TC4_WO0 (_UL_(1) << 18) 815 #define PIN_PA14E_TC4_WO0 _L_(14) /**< \brief TC4 signal: WO0 on PA14 mux E */ 816 #define MUX_PA14E_TC4_WO0 _L_(4) 817 #define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) 818 #define PORT_PA14E_TC4_WO0 (_UL_(1) << 14) 819 #define PIN_PA19E_TC4_WO1 _L_(19) /**< \brief TC4 signal: WO1 on PA19 mux E */ 820 #define MUX_PA19E_TC4_WO1 _L_(4) 821 #define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) 822 #define PORT_PA19E_TC4_WO1 (_UL_(1) << 19) 823 #define PIN_PA15E_TC4_WO1 _L_(15) /**< \brief TC4 signal: WO1 on PA15 mux E */ 824 #define MUX_PA15E_TC4_WO1 _L_(4) 825 #define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) 826 #define PORT_PA15E_TC4_WO1 (_UL_(1) << 15) 827 /* ========== PORT definition for ADC peripheral ========== */ 828 #define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ 829 #define MUX_PA04B_ADC_AIN4 _L_(1) 830 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) 831 #define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) 832 #define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ 833 #define MUX_PA05B_ADC_AIN5 _L_(1) 834 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) 835 #define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) 836 #define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ 837 #define MUX_PA06B_ADC_AIN6 _L_(1) 838 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) 839 #define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) 840 #define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ 841 #define MUX_PA07B_ADC_AIN7 _L_(1) 842 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) 843 #define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) 844 #define PIN_PB00B_ADC_AIN8 _L_(32) /**< \brief ADC signal: AIN8 on PB00 mux B */ 845 #define MUX_PB00B_ADC_AIN8 _L_(1) 846 #define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) 847 #define PORT_PB00B_ADC_AIN8 (_UL_(1) << 0) 848 #define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ 849 #define MUX_PB02B_ADC_AIN10 _L_(1) 850 #define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) 851 #define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) 852 #define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ 853 #define MUX_PB03B_ADC_AIN11 _L_(1) 854 #define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) 855 #define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) 856 #define PIN_PA08B_ADC_AIN16 _L_(8) /**< \brief ADC signal: AIN16 on PA08 mux B */ 857 #define MUX_PA08B_ADC_AIN16 _L_(1) 858 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) 859 #define PORT_PA08B_ADC_AIN16 (_UL_(1) << 8) 860 #define PIN_PA09B_ADC_AIN17 _L_(9) /**< \brief ADC signal: AIN17 on PA09 mux B */ 861 #define MUX_PA09B_ADC_AIN17 _L_(1) 862 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) 863 #define PORT_PA09B_ADC_AIN17 (_UL_(1) << 9) 864 #define PIN_PA10B_ADC_AIN18 _L_(10) /**< \brief ADC signal: AIN18 on PA10 mux B */ 865 #define MUX_PA10B_ADC_AIN18 _L_(1) 866 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) 867 #define PORT_PA10B_ADC_AIN18 (_UL_(1) << 10) 868 #define PIN_PA11B_ADC_AIN19 _L_(11) /**< \brief ADC signal: AIN19 on PA11 mux B */ 869 #define MUX_PA11B_ADC_AIN19 _L_(1) 870 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) 871 #define PORT_PA11B_ADC_AIN19 (_UL_(1) << 11) 872 #define PIN_PA04B_ADC_VREFP _L_(4) /**< \brief ADC signal: VREFP on PA04 mux B */ 873 #define MUX_PA04B_ADC_VREFP _L_(1) 874 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) 875 #define PORT_PA04B_ADC_VREFP (_UL_(1) << 4) 876 /* ========== PORT definition for AC peripheral ========== */ 877 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 878 #define MUX_PA04B_AC_AIN0 _L_(1) 879 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 880 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 881 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 882 #define MUX_PA05B_AC_AIN1 _L_(1) 883 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 884 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 885 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 886 #define MUX_PA06B_AC_AIN2 _L_(1) 887 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 888 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 889 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 890 #define MUX_PA07B_AC_AIN3 _L_(1) 891 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 892 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 893 #define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ 894 #define MUX_PA12H_AC_CMP0 _L_(7) 895 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) 896 #define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) 897 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 898 #define MUX_PA18H_AC_CMP0 _L_(7) 899 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 900 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 901 #define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ 902 #define MUX_PA13H_AC_CMP1 _L_(7) 903 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) 904 #define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) 905 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 906 #define MUX_PA19H_AC_CMP1 _L_(7) 907 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 908 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 909 /* ========== PORT definition for CCL peripheral ========== */ 910 #define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ 911 #define MUX_PA04I_CCL_IN0 _L_(8) 912 #define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) 913 #define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) 914 #define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ 915 #define MUX_PA16I_CCL_IN0 _L_(8) 916 #define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) 917 #define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) 918 #define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ 919 #define MUX_PB22I_CCL_IN0 _L_(8) 920 #define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) 921 #define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) 922 #define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ 923 #define MUX_PA05I_CCL_IN1 _L_(8) 924 #define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) 925 #define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) 926 #define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ 927 #define MUX_PA17I_CCL_IN1 _L_(8) 928 #define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) 929 #define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) 930 #define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ 931 #define MUX_PB00I_CCL_IN1 _L_(8) 932 #define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) 933 #define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) 934 #define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ 935 #define MUX_PA06I_CCL_IN2 _L_(8) 936 #define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) 937 #define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) 938 #define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ 939 #define MUX_PA18I_CCL_IN2 _L_(8) 940 #define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) 941 #define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) 942 #define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ 943 #define MUX_PA08I_CCL_IN3 _L_(8) 944 #define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) 945 #define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) 946 #define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ 947 #define MUX_PA30I_CCL_IN3 _L_(8) 948 #define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) 949 #define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) 950 #define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ 951 #define MUX_PA09I_CCL_IN4 _L_(8) 952 #define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) 953 #define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) 954 #define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ 955 #define MUX_PA10I_CCL_IN5 _L_(8) 956 #define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) 957 #define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) 958 #define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ 959 #define MUX_PA22I_CCL_IN6 _L_(8) 960 #define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) 961 #define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) 962 #define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ 963 #define MUX_PA23I_CCL_IN7 _L_(8) 964 #define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) 965 #define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) 966 #define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ 967 #define MUX_PA24I_CCL_IN8 _L_(8) 968 #define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) 969 #define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) 970 #define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ 971 #define MUX_PB15I_CCL_IN10 _L_(8) 972 #define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) 973 #define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) 974 #define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ 975 #define MUX_PB16I_CCL_IN11 _L_(8) 976 #define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) 977 #define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) 978 #define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ 979 #define MUX_PA07I_CCL_OUT0 _L_(8) 980 #define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) 981 #define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) 982 #define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ 983 #define MUX_PA19I_CCL_OUT0 _L_(8) 984 #define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) 985 #define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) 986 #define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ 987 #define MUX_PB02I_CCL_OUT0 _L_(8) 988 #define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) 989 #define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) 990 #define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ 991 #define MUX_PB23I_CCL_OUT0 _L_(8) 992 #define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) 993 #define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) 994 #define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ 995 #define MUX_PA11I_CCL_OUT1 _L_(8) 996 #define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) 997 #define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) 998 #define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ 999 #define MUX_PA31I_CCL_OUT1 _L_(8) 1000 #define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) 1001 #define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) 1002 #define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ 1003 #define MUX_PA25I_CCL_OUT2 _L_(8) 1004 #define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) 1005 #define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) 1006 #define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ 1007 #define MUX_PB17I_CCL_OUT3 _L_(8) 1008 #define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) 1009 #define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) 1010 1011 #endif /* _SAMR35J18B_PIO_ */ 1012
