1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMD51G18A 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD51G18A_PIO_ 31 #define _SAMD51G18A_PIO_ 32 33 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 34 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 35 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 36 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 37 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 38 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 39 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 40 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 41 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 42 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 43 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 44 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 45 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 46 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 47 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 48 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 49 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 50 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 51 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 52 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 53 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 54 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 55 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 56 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 57 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 58 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 59 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 60 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 61 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 62 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 63 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 64 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 65 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 66 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 67 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 68 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 69 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 70 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 71 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 72 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 73 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 74 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 75 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ 76 #define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ 77 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 78 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 79 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 80 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 81 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 82 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 83 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 84 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 85 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 86 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 87 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 88 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 89 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 90 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 91 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 92 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 93 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 94 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 95 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 96 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 97 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 98 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 99 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ 100 #define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ 101 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ 102 #define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ 103 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 104 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 105 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 106 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 107 /* ========== PORT definition for CM4 peripheral ========== */ 108 #define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ 109 #define MUX_PA30H_CM4_SWCLK _L_(7) 110 #define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) 111 #define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) 112 /* ========== PORT definition for ANAREF peripheral ========== */ 113 #define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ 114 #define MUX_PA03B_ANAREF_VREF0 _L_(1) 115 #define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) 116 #define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) 117 #define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ 118 #define MUX_PA04B_ANAREF_VREF1 _L_(1) 119 #define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) 120 #define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) 121 #define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ 122 #define MUX_PA06B_ANAREF_VREF2 _L_(1) 123 #define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) 124 #define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) 125 /* ========== PORT definition for GCLK peripheral ========== */ 126 #define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ 127 #define MUX_PA30M_GCLK_IO0 _L_(12) 128 #define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) 129 #define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) 130 #define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ 131 #define MUX_PA14M_GCLK_IO0 _L_(12) 132 #define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) 133 #define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) 134 #define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ 135 #define MUX_PB22M_GCLK_IO0 _L_(12) 136 #define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) 137 #define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) 138 #define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ 139 #define MUX_PA15M_GCLK_IO1 _L_(12) 140 #define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) 141 #define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) 142 #define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ 143 #define MUX_PB23M_GCLK_IO1 _L_(12) 144 #define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) 145 #define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) 146 #define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ 147 #define MUX_PA27M_GCLK_IO1 _L_(12) 148 #define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) 149 #define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) 150 #define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ 151 #define MUX_PA16M_GCLK_IO2 _L_(12) 152 #define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) 153 #define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) 154 #define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ 155 #define MUX_PA17M_GCLK_IO3 _L_(12) 156 #define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) 157 #define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) 158 #define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ 159 #define MUX_PA10M_GCLK_IO4 _L_(12) 160 #define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) 161 #define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) 162 #define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ 163 #define MUX_PB10M_GCLK_IO4 _L_(12) 164 #define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) 165 #define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) 166 #define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ 167 #define MUX_PA11M_GCLK_IO5 _L_(12) 168 #define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) 169 #define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) 170 #define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ 171 #define MUX_PB11M_GCLK_IO5 _L_(12) 172 #define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) 173 #define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) 174 /* ========== PORT definition for EIC peripheral ========== */ 175 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 176 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 177 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 178 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 179 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 180 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 181 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 182 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 183 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 184 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 185 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 186 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 187 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 188 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 189 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 190 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 191 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 192 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 193 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 194 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 195 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 196 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 197 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 198 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 199 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 200 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 201 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 202 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 203 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 204 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 205 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 206 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 207 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 208 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 209 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 210 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 211 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 212 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 213 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 214 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 215 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 216 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 217 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 218 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 219 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 220 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 221 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 222 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 223 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 224 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 225 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 226 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 227 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 228 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 229 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 230 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 231 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 232 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 233 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 234 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 235 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 236 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 237 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 238 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 239 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 240 #define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ 241 #define MUX_PA21A_EIC_EXTINT5 _L_(0) 242 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 243 #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) 244 #define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ 245 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 246 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 247 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 248 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 249 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 250 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 251 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 252 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 253 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 254 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 255 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 256 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 257 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 258 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 259 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 260 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 261 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 262 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 263 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 264 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 265 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 266 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 267 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 268 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 269 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 270 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 271 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 272 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 273 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 274 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 275 #define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ 276 #define MUX_PA24A_EIC_EXTINT8 _L_(0) 277 #define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) 278 #define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) 279 #define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 280 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 281 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 282 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 283 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 284 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 285 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 286 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 287 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 288 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 289 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 290 #define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ 291 #define MUX_PA25A_EIC_EXTINT9 _L_(0) 292 #define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) 293 #define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) 294 #define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 295 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 296 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 297 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 298 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 299 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 300 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 301 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 302 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 303 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 304 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 305 #define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ 306 #define MUX_PB10A_EIC_EXTINT10 _L_(0) 307 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 308 #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) 309 #define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ 310 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 311 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 312 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 313 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 314 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 315 #define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ 316 #define MUX_PA27A_EIC_EXTINT11 _L_(0) 317 #define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) 318 #define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) 319 #define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 320 #define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ 321 #define MUX_PB11A_EIC_EXTINT11 _L_(0) 322 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 323 #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) 324 #define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ 325 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 326 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 327 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 328 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 329 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 330 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 331 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 332 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 333 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 334 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 335 #define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ 336 #define MUX_PA30A_EIC_EXTINT14 _L_(0) 337 #define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) 338 #define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) 339 #define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 340 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 341 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 342 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 343 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 344 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 345 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 346 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 347 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 348 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 349 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 350 #define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ 351 #define MUX_PA31A_EIC_EXTINT15 _L_(0) 352 #define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) 353 #define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) 354 #define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 355 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 356 #define MUX_PA08A_EIC_NMI _L_(0) 357 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 358 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 359 /* ========== PORT definition for SERCOM0 peripheral ========== */ 360 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 361 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 362 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 363 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 364 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 365 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 366 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 367 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 368 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 369 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 370 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 371 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 372 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 373 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 374 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 375 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 376 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 377 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 378 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 379 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 380 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 381 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 382 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 383 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 384 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 385 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 386 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 387 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 388 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 389 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 390 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 391 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 392 /* ========== PORT definition for SERCOM1 peripheral ========== */ 393 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 394 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 395 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 396 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 397 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 398 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 399 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 400 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 401 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 402 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 403 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 404 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 405 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 406 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 407 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 408 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 409 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 410 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 411 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 412 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 413 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 414 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 415 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 416 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 417 #define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ 418 #define MUX_PB22C_SERCOM1_PAD2 _L_(2) 419 #define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) 420 #define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) 421 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 422 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 423 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 424 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 425 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 426 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 427 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 428 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 429 #define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ 430 #define MUX_PB23C_SERCOM1_PAD3 _L_(2) 431 #define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) 432 #define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) 433 /* ========== PORT definition for TC0 peripheral ========== */ 434 #define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ 435 #define MUX_PA04E_TC0_WO0 _L_(4) 436 #define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) 437 #define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) 438 #define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ 439 #define MUX_PA08E_TC0_WO0 _L_(4) 440 #define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) 441 #define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) 442 #define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ 443 #define MUX_PA05E_TC0_WO1 _L_(4) 444 #define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) 445 #define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) 446 #define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ 447 #define MUX_PA09E_TC0_WO1 _L_(4) 448 #define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) 449 #define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) 450 /* ========== PORT definition for TC1 peripheral ========== */ 451 #define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ 452 #define MUX_PA06E_TC1_WO0 _L_(4) 453 #define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) 454 #define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) 455 #define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ 456 #define MUX_PA10E_TC1_WO0 _L_(4) 457 #define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) 458 #define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) 459 #define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ 460 #define MUX_PA07E_TC1_WO1 _L_(4) 461 #define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) 462 #define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) 463 #define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ 464 #define MUX_PA11E_TC1_WO1 _L_(4) 465 #define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) 466 #define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) 467 /* ========== PORT definition for USB peripheral ========== */ 468 #define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ 469 #define MUX_PA24H_USB_DM _L_(7) 470 #define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) 471 #define PORT_PA24H_USB_DM (_UL_(1) << 24) 472 #define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ 473 #define MUX_PA25H_USB_DP _L_(7) 474 #define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) 475 #define PORT_PA25H_USB_DP (_UL_(1) << 25) 476 #define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ 477 #define MUX_PA23H_USB_SOF_1KHZ _L_(7) 478 #define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) 479 #define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) 480 #define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ 481 #define MUX_PB22H_USB_SOF_1KHZ _L_(7) 482 #define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) 483 #define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) 484 /* ========== PORT definition for SERCOM2 peripheral ========== */ 485 #define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ 486 #define MUX_PA09D_SERCOM2_PAD0 _L_(3) 487 #define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) 488 #define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) 489 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 490 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 491 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 492 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 493 #define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ 494 #define MUX_PA08D_SERCOM2_PAD1 _L_(3) 495 #define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) 496 #define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) 497 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 498 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 499 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 500 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 501 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 502 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 503 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 504 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 505 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 506 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 507 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 508 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 509 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 510 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 511 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 512 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 513 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 514 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 515 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 516 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 517 /* ========== PORT definition for SERCOM3 peripheral ========== */ 518 #define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ 519 #define MUX_PA17D_SERCOM3_PAD0 _L_(3) 520 #define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) 521 #define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) 522 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 523 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 524 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 525 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 526 #define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ 527 #define MUX_PA16D_SERCOM3_PAD1 _L_(3) 528 #define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) 529 #define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) 530 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 531 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 532 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 533 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 534 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 535 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 536 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 537 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 538 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 539 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 540 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 541 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 542 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 543 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 544 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 545 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 546 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 547 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 548 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 549 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 550 #define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ 551 #define MUX_PA21D_SERCOM3_PAD3 _L_(3) 552 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 553 #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) 554 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 555 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 556 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 557 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 558 /* ========== PORT definition for TCC0 peripheral ========== */ 559 #define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ 560 #define MUX_PA20G_TCC0_WO0 _L_(6) 561 #define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) 562 #define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) 563 #define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ 564 #define MUX_PA08F_TCC0_WO0 _L_(5) 565 #define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) 566 #define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) 567 #define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ 568 #define MUX_PA21G_TCC0_WO1 _L_(6) 569 #define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) 570 #define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) 571 #define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ 572 #define MUX_PA09F_TCC0_WO1 _L_(5) 573 #define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) 574 #define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) 575 #define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ 576 #define MUX_PA22G_TCC0_WO2 _L_(6) 577 #define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) 578 #define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) 579 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 580 #define MUX_PA10F_TCC0_WO2 _L_(5) 581 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 582 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 583 #define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ 584 #define MUX_PA23G_TCC0_WO3 _L_(6) 585 #define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) 586 #define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) 587 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 588 #define MUX_PA11F_TCC0_WO3 _L_(5) 589 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 590 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 591 #define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ 592 #define MUX_PA16G_TCC0_WO4 _L_(6) 593 #define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) 594 #define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) 595 #define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ 596 #define MUX_PB10F_TCC0_WO4 _L_(5) 597 #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) 598 #define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) 599 #define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ 600 #define MUX_PA17G_TCC0_WO5 _L_(6) 601 #define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) 602 #define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) 603 #define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ 604 #define MUX_PB11F_TCC0_WO5 _L_(5) 605 #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) 606 #define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) 607 #define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ 608 #define MUX_PA18G_TCC0_WO6 _L_(6) 609 #define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) 610 #define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) 611 #define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ 612 #define MUX_PA12F_TCC0_WO6 _L_(5) 613 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) 614 #define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) 615 #define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ 616 #define MUX_PA19G_TCC0_WO7 _L_(6) 617 #define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) 618 #define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) 619 #define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ 620 #define MUX_PA13F_TCC0_WO7 _L_(5) 621 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) 622 #define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) 623 /* ========== PORT definition for TCC1 peripheral ========== */ 624 #define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ 625 #define MUX_PB10G_TCC1_WO0 _L_(6) 626 #define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) 627 #define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) 628 #define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ 629 #define MUX_PA16F_TCC1_WO0 _L_(5) 630 #define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) 631 #define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) 632 #define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ 633 #define MUX_PB11G_TCC1_WO1 _L_(6) 634 #define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) 635 #define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) 636 #define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ 637 #define MUX_PA17F_TCC1_WO1 _L_(5) 638 #define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) 639 #define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) 640 #define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ 641 #define MUX_PA12G_TCC1_WO2 _L_(6) 642 #define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) 643 #define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) 644 #define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ 645 #define MUX_PA14G_TCC1_WO2 _L_(6) 646 #define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) 647 #define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) 648 #define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ 649 #define MUX_PA18F_TCC1_WO2 _L_(5) 650 #define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) 651 #define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) 652 #define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ 653 #define MUX_PA13G_TCC1_WO3 _L_(6) 654 #define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) 655 #define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) 656 #define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ 657 #define MUX_PA15G_TCC1_WO3 _L_(6) 658 #define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) 659 #define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) 660 #define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ 661 #define MUX_PA19F_TCC1_WO3 _L_(5) 662 #define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) 663 #define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) 664 #define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ 665 #define MUX_PA08G_TCC1_WO4 _L_(6) 666 #define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) 667 #define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) 668 #define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ 669 #define MUX_PA20F_TCC1_WO4 _L_(5) 670 #define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) 671 #define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) 672 #define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ 673 #define MUX_PA09G_TCC1_WO5 _L_(6) 674 #define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) 675 #define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) 676 #define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ 677 #define MUX_PA21F_TCC1_WO5 _L_(5) 678 #define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) 679 #define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) 680 #define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ 681 #define MUX_PA10G_TCC1_WO6 _L_(6) 682 #define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) 683 #define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) 684 #define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ 685 #define MUX_PA22F_TCC1_WO6 _L_(5) 686 #define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) 687 #define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) 688 #define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ 689 #define MUX_PA11G_TCC1_WO7 _L_(6) 690 #define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) 691 #define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) 692 #define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ 693 #define MUX_PA23F_TCC1_WO7 _L_(5) 694 #define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) 695 #define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) 696 /* ========== PORT definition for TC2 peripheral ========== */ 697 #define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ 698 #define MUX_PA12E_TC2_WO0 _L_(4) 699 #define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) 700 #define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) 701 #define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ 702 #define MUX_PA16E_TC2_WO0 _L_(4) 703 #define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) 704 #define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) 705 #define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ 706 #define MUX_PA00E_TC2_WO0 _L_(4) 707 #define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) 708 #define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) 709 #define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ 710 #define MUX_PA01E_TC2_WO1 _L_(4) 711 #define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) 712 #define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) 713 #define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ 714 #define MUX_PA13E_TC2_WO1 _L_(4) 715 #define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) 716 #define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) 717 #define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ 718 #define MUX_PA17E_TC2_WO1 _L_(4) 719 #define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) 720 #define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) 721 /* ========== PORT definition for TC3 peripheral ========== */ 722 #define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ 723 #define MUX_PA18E_TC3_WO0 _L_(4) 724 #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) 725 #define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) 726 #define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ 727 #define MUX_PA14E_TC3_WO0 _L_(4) 728 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) 729 #define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) 730 #define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ 731 #define MUX_PA15E_TC3_WO1 _L_(4) 732 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) 733 #define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) 734 #define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ 735 #define MUX_PA19E_TC3_WO1 _L_(4) 736 #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) 737 #define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) 738 /* ========== PORT definition for TCC2 peripheral ========== */ 739 #define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ 740 #define MUX_PA14F_TCC2_WO0 _L_(5) 741 #define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) 742 #define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) 743 #define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ 744 #define MUX_PA30F_TCC2_WO0 _L_(5) 745 #define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) 746 #define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) 747 #define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ 748 #define MUX_PA15F_TCC2_WO1 _L_(5) 749 #define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) 750 #define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) 751 #define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ 752 #define MUX_PA31F_TCC2_WO1 _L_(5) 753 #define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) 754 #define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) 755 #define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ 756 #define MUX_PA24F_TCC2_WO2 _L_(5) 757 #define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) 758 #define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) 759 #define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ 760 #define MUX_PB02F_TCC2_WO2 _L_(5) 761 #define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) 762 #define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) 763 /* ========== PORT definition for PDEC peripheral ========== */ 764 #define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ 765 #define MUX_PB23G_PDEC_QDI0 _L_(6) 766 #define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) 767 #define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) 768 #define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ 769 #define MUX_PA24G_PDEC_QDI0 _L_(6) 770 #define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) 771 #define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) 772 #define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ 773 #define MUX_PA25G_PDEC_QDI1 _L_(6) 774 #define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) 775 #define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) 776 #define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ 777 #define MUX_PB22G_PDEC_QDI2 _L_(6) 778 #define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) 779 #define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) 780 /* ========== PORT definition for AC peripheral ========== */ 781 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 782 #define MUX_PA04B_AC_AIN0 _L_(1) 783 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 784 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 785 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 786 #define MUX_PA05B_AC_AIN1 _L_(1) 787 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 788 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 789 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 790 #define MUX_PA06B_AC_AIN2 _L_(1) 791 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 792 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 793 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 794 #define MUX_PA07B_AC_AIN3 _L_(1) 795 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 796 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 797 #define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ 798 #define MUX_PA12M_AC_CMP0 _L_(12) 799 #define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) 800 #define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) 801 #define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ 802 #define MUX_PA18M_AC_CMP0 _L_(12) 803 #define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) 804 #define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) 805 #define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ 806 #define MUX_PA13M_AC_CMP1 _L_(12) 807 #define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) 808 #define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) 809 #define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ 810 #define MUX_PA19M_AC_CMP1 _L_(12) 811 #define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) 812 #define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) 813 /* ========== PORT definition for QSPI peripheral ========== */ 814 #define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ 815 #define MUX_PB11H_QSPI_CS _L_(7) 816 #define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) 817 #define PORT_PB11H_QSPI_CS (_UL_(1) << 11) 818 #define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ 819 #define MUX_PA08H_QSPI_DATA0 _L_(7) 820 #define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) 821 #define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) 822 #define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ 823 #define MUX_PA09H_QSPI_DATA1 _L_(7) 824 #define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) 825 #define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) 826 #define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ 827 #define MUX_PA10H_QSPI_DATA2 _L_(7) 828 #define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) 829 #define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) 830 #define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ 831 #define MUX_PA11H_QSPI_DATA3 _L_(7) 832 #define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) 833 #define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) 834 #define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ 835 #define MUX_PB10H_QSPI_SCK _L_(7) 836 #define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) 837 #define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) 838 /* ========== PORT definition for CCL peripheral ========== */ 839 #define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ 840 #define MUX_PA04N_CCL_IN0 _L_(13) 841 #define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) 842 #define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) 843 #define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ 844 #define MUX_PA16N_CCL_IN0 _L_(13) 845 #define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) 846 #define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) 847 #define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ 848 #define MUX_PB22N_CCL_IN0 _L_(13) 849 #define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) 850 #define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) 851 #define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ 852 #define MUX_PA05N_CCL_IN1 _L_(13) 853 #define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) 854 #define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) 855 #define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ 856 #define MUX_PA17N_CCL_IN1 _L_(13) 857 #define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) 858 #define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) 859 #define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ 860 #define MUX_PA06N_CCL_IN2 _L_(13) 861 #define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) 862 #define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) 863 #define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ 864 #define MUX_PA18N_CCL_IN2 _L_(13) 865 #define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) 866 #define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) 867 #define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ 868 #define MUX_PA08N_CCL_IN3 _L_(13) 869 #define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) 870 #define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) 871 #define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ 872 #define MUX_PA30N_CCL_IN3 _L_(13) 873 #define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) 874 #define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) 875 #define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ 876 #define MUX_PA09N_CCL_IN4 _L_(13) 877 #define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) 878 #define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) 879 #define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ 880 #define MUX_PA10N_CCL_IN5 _L_(13) 881 #define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) 882 #define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) 883 #define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ 884 #define MUX_PA22N_CCL_IN6 _L_(13) 885 #define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) 886 #define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) 887 #define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ 888 #define MUX_PA23N_CCL_IN7 _L_(13) 889 #define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) 890 #define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) 891 #define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ 892 #define MUX_PA24N_CCL_IN8 _L_(13) 893 #define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) 894 #define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) 895 #define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ 896 #define MUX_PB08N_CCL_IN8 _L_(13) 897 #define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) 898 #define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) 899 #define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ 900 #define MUX_PB10N_CCL_IN11 _L_(13) 901 #define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) 902 #define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) 903 #define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ 904 #define MUX_PA07N_CCL_OUT0 _L_(13) 905 #define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) 906 #define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) 907 #define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ 908 #define MUX_PA19N_CCL_OUT0 _L_(13) 909 #define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) 910 #define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) 911 #define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ 912 #define MUX_PB02N_CCL_OUT0 _L_(13) 913 #define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) 914 #define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) 915 #define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ 916 #define MUX_PB23N_CCL_OUT0 _L_(13) 917 #define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) 918 #define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) 919 #define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ 920 #define MUX_PA11N_CCL_OUT1 _L_(13) 921 #define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) 922 #define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) 923 #define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ 924 #define MUX_PA31N_CCL_OUT1 _L_(13) 925 #define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) 926 #define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) 927 #define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ 928 #define MUX_PB11N_CCL_OUT1 _L_(13) 929 #define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) 930 #define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) 931 #define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ 932 #define MUX_PA25N_CCL_OUT2 _L_(13) 933 #define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) 934 #define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) 935 #define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ 936 #define MUX_PB09N_CCL_OUT2 _L_(13) 937 #define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) 938 #define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) 939 /* ========== PORT definition for SERCOM4 peripheral ========== */ 940 #define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ 941 #define MUX_PA13D_SERCOM4_PAD0 _L_(3) 942 #define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) 943 #define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) 944 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 945 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 946 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 947 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 948 #define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ 949 #define MUX_PA12D_SERCOM4_PAD1 _L_(3) 950 #define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) 951 #define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) 952 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 953 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 954 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 955 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 956 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 957 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 958 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 959 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 960 #define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ 961 #define MUX_PB10D_SERCOM4_PAD2 _L_(3) 962 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 963 #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) 964 #define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ 965 #define MUX_PB11D_SERCOM4_PAD3 _L_(3) 966 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 967 #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) 968 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 969 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 970 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 971 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 972 /* ========== PORT definition for SERCOM5 peripheral ========== */ 973 #define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ 974 #define MUX_PA23D_SERCOM5_PAD0 _L_(3) 975 #define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) 976 #define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) 977 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 978 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 979 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 980 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 981 #define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ 982 #define MUX_PA22D_SERCOM5_PAD1 _L_(3) 983 #define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) 984 #define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) 985 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 986 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 987 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 988 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 989 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 990 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 991 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 992 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 993 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 994 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 995 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 996 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 997 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 998 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 999 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 1000 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 1001 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 1002 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 1003 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 1004 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 1005 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 1006 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 1007 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 1008 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 1009 #define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ 1010 #define MUX_PA21C_SERCOM5_PAD3 _L_(2) 1011 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 1012 #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) 1013 /* ========== PORT definition for ADC0 peripheral ========== */ 1014 #define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ 1015 #define MUX_PA02B_ADC0_AIN0 _L_(1) 1016 #define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) 1017 #define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) 1018 #define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ 1019 #define MUX_PA03B_ADC0_AIN1 _L_(1) 1020 #define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) 1021 #define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) 1022 #define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ 1023 #define MUX_PB08B_ADC0_AIN2 _L_(1) 1024 #define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) 1025 #define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) 1026 #define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ 1027 #define MUX_PB09B_ADC0_AIN3 _L_(1) 1028 #define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) 1029 #define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) 1030 #define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ 1031 #define MUX_PA04B_ADC0_AIN4 _L_(1) 1032 #define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) 1033 #define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) 1034 #define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ 1035 #define MUX_PA05B_ADC0_AIN5 _L_(1) 1036 #define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) 1037 #define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) 1038 #define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ 1039 #define MUX_PA06B_ADC0_AIN6 _L_(1) 1040 #define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) 1041 #define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) 1042 #define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ 1043 #define MUX_PA07B_ADC0_AIN7 _L_(1) 1044 #define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) 1045 #define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) 1046 #define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ 1047 #define MUX_PA08B_ADC0_AIN8 _L_(1) 1048 #define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) 1049 #define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) 1050 #define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ 1051 #define MUX_PA09B_ADC0_AIN9 _L_(1) 1052 #define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) 1053 #define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) 1054 #define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ 1055 #define MUX_PA10B_ADC0_AIN10 _L_(1) 1056 #define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) 1057 #define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) 1058 #define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ 1059 #define MUX_PA11B_ADC0_AIN11 _L_(1) 1060 #define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) 1061 #define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) 1062 #define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ 1063 #define MUX_PB02B_ADC0_AIN14 _L_(1) 1064 #define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) 1065 #define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) 1066 #define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ 1067 #define MUX_PB03B_ADC0_AIN15 _L_(1) 1068 #define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) 1069 #define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) 1070 #define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ 1071 #define MUX_PA03O_ADC0_DRV0 _L_(14) 1072 #define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) 1073 #define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) 1074 #define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ 1075 #define MUX_PB08O_ADC0_DRV1 _L_(14) 1076 #define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) 1077 #define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) 1078 #define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ 1079 #define MUX_PB09O_ADC0_DRV2 _L_(14) 1080 #define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) 1081 #define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) 1082 #define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ 1083 #define MUX_PA04O_ADC0_DRV3 _L_(14) 1084 #define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) 1085 #define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) 1086 #define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ 1087 #define MUX_PA06O_ADC0_DRV4 _L_(14) 1088 #define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) 1089 #define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) 1090 #define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ 1091 #define MUX_PA07O_ADC0_DRV5 _L_(14) 1092 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) 1093 #define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) 1094 #define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ 1095 #define MUX_PA08O_ADC0_DRV6 _L_(14) 1096 #define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) 1097 #define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) 1098 #define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ 1099 #define MUX_PA09O_ADC0_DRV7 _L_(14) 1100 #define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) 1101 #define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) 1102 #define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ 1103 #define MUX_PA10O_ADC0_DRV8 _L_(14) 1104 #define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) 1105 #define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) 1106 #define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ 1107 #define MUX_PA11O_ADC0_DRV9 _L_(14) 1108 #define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) 1109 #define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) 1110 #define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ 1111 #define MUX_PA16O_ADC0_DRV10 _L_(14) 1112 #define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) 1113 #define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) 1114 #define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ 1115 #define MUX_PA17O_ADC0_DRV11 _L_(14) 1116 #define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) 1117 #define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) 1118 #define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ 1119 #define MUX_PA18O_ADC0_DRV12 _L_(14) 1120 #define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) 1121 #define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) 1122 #define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ 1123 #define MUX_PA19O_ADC0_DRV13 _L_(14) 1124 #define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) 1125 #define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) 1126 #define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ 1127 #define MUX_PA20O_ADC0_DRV14 _L_(14) 1128 #define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) 1129 #define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) 1130 #define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ 1131 #define MUX_PA21O_ADC0_DRV15 _L_(14) 1132 #define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) 1133 #define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) 1134 #define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ 1135 #define MUX_PA22O_ADC0_DRV16 _L_(14) 1136 #define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) 1137 #define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) 1138 #define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ 1139 #define MUX_PA23O_ADC0_DRV17 _L_(14) 1140 #define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) 1141 #define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) 1142 #define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ 1143 #define MUX_PA27O_ADC0_DRV18 _L_(14) 1144 #define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) 1145 #define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) 1146 #define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ 1147 #define MUX_PA30O_ADC0_DRV19 _L_(14) 1148 #define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) 1149 #define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) 1150 #define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ 1151 #define MUX_PB02O_ADC0_DRV20 _L_(14) 1152 #define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) 1153 #define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) 1154 #define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ 1155 #define MUX_PB03O_ADC0_DRV21 _L_(14) 1156 #define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) 1157 #define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) 1158 #define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ 1159 #define MUX_PA03B_ADC0_PTCXY0 _L_(1) 1160 #define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) 1161 #define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) 1162 #define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ 1163 #define MUX_PB08B_ADC0_PTCXY1 _L_(1) 1164 #define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) 1165 #define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) 1166 #define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ 1167 #define MUX_PB09B_ADC0_PTCXY2 _L_(1) 1168 #define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) 1169 #define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) 1170 #define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ 1171 #define MUX_PA04B_ADC0_PTCXY3 _L_(1) 1172 #define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) 1173 #define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) 1174 #define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ 1175 #define MUX_PA06B_ADC0_PTCXY4 _L_(1) 1176 #define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) 1177 #define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) 1178 #define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ 1179 #define MUX_PA07B_ADC0_PTCXY5 _L_(1) 1180 #define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) 1181 #define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) 1182 #define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ 1183 #define MUX_PA08B_ADC0_PTCXY6 _L_(1) 1184 #define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) 1185 #define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) 1186 #define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ 1187 #define MUX_PA09B_ADC0_PTCXY7 _L_(1) 1188 #define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) 1189 #define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) 1190 #define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ 1191 #define MUX_PA10B_ADC0_PTCXY8 _L_(1) 1192 #define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) 1193 #define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) 1194 #define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ 1195 #define MUX_PA11B_ADC0_PTCXY9 _L_(1) 1196 #define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) 1197 #define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) 1198 #define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ 1199 #define MUX_PA16B_ADC0_PTCXY10 _L_(1) 1200 #define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) 1201 #define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) 1202 #define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ 1203 #define MUX_PA17B_ADC0_PTCXY11 _L_(1) 1204 #define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) 1205 #define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) 1206 #define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ 1207 #define MUX_PA18B_ADC0_PTCXY12 _L_(1) 1208 #define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) 1209 #define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) 1210 #define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ 1211 #define MUX_PA19B_ADC0_PTCXY13 _L_(1) 1212 #define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) 1213 #define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) 1214 #define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ 1215 #define MUX_PA20B_ADC0_PTCXY14 _L_(1) 1216 #define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) 1217 #define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) 1218 #define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ 1219 #define MUX_PA21B_ADC0_PTCXY15 _L_(1) 1220 #define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) 1221 #define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) 1222 #define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ 1223 #define MUX_PA22B_ADC0_PTCXY16 _L_(1) 1224 #define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) 1225 #define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) 1226 #define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ 1227 #define MUX_PA23B_ADC0_PTCXY17 _L_(1) 1228 #define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) 1229 #define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) 1230 #define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ 1231 #define MUX_PA27B_ADC0_PTCXY18 _L_(1) 1232 #define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) 1233 #define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) 1234 #define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ 1235 #define MUX_PA30B_ADC0_PTCXY19 _L_(1) 1236 #define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) 1237 #define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) 1238 #define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ 1239 #define MUX_PB02B_ADC0_PTCXY20 _L_(1) 1240 #define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) 1241 #define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) 1242 #define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ 1243 #define MUX_PB03B_ADC0_PTCXY21 _L_(1) 1244 #define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) 1245 #define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) 1246 /* ========== PORT definition for ADC1 peripheral ========== */ 1247 #define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ 1248 #define MUX_PB08B_ADC1_AIN0 _L_(1) 1249 #define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) 1250 #define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) 1251 #define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ 1252 #define MUX_PB09B_ADC1_AIN1 _L_(1) 1253 #define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) 1254 #define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) 1255 #define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ 1256 #define MUX_PA08B_ADC1_AIN2 _L_(1) 1257 #define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) 1258 #define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) 1259 #define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ 1260 #define MUX_PA09B_ADC1_AIN3 _L_(1) 1261 #define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) 1262 #define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) 1263 /* ========== PORT definition for DAC peripheral ========== */ 1264 #define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ 1265 #define MUX_PA02B_DAC_VOUT0 _L_(1) 1266 #define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) 1267 #define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) 1268 #define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ 1269 #define MUX_PA05B_DAC_VOUT1 _L_(1) 1270 #define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) 1271 #define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) 1272 /* ========== PORT definition for PCC peripheral ========== */ 1273 #define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ 1274 #define MUX_PA14K_PCC_CLK _L_(10) 1275 #define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) 1276 #define PORT_PA14K_PCC_CLK (_UL_(1) << 14) 1277 #define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ 1278 #define MUX_PA16K_PCC_DATA0 _L_(10) 1279 #define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) 1280 #define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) 1281 #define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ 1282 #define MUX_PA17K_PCC_DATA1 _L_(10) 1283 #define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) 1284 #define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) 1285 #define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ 1286 #define MUX_PA18K_PCC_DATA2 _L_(10) 1287 #define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) 1288 #define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) 1289 #define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ 1290 #define MUX_PA19K_PCC_DATA3 _L_(10) 1291 #define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) 1292 #define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) 1293 #define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ 1294 #define MUX_PA20K_PCC_DATA4 _L_(10) 1295 #define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) 1296 #define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) 1297 #define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ 1298 #define MUX_PA21K_PCC_DATA5 _L_(10) 1299 #define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) 1300 #define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) 1301 #define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ 1302 #define MUX_PA22K_PCC_DATA6 _L_(10) 1303 #define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) 1304 #define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) 1305 #define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ 1306 #define MUX_PA23K_PCC_DATA7 _L_(10) 1307 #define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) 1308 #define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) 1309 #define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ 1310 #define MUX_PA12K_PCC_DEN1 _L_(10) 1311 #define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) 1312 #define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) 1313 #define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ 1314 #define MUX_PA13K_PCC_DEN2 _L_(10) 1315 #define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) 1316 #define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) 1317 /* ========== PORT definition for SDHC0 peripheral ========== */ 1318 #define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ 1319 #define MUX_PA06I_SDHC0_SDCD _L_(8) 1320 #define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) 1321 #define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) 1322 #define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ 1323 #define MUX_PA12I_SDHC0_SDCD _L_(8) 1324 #define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) 1325 #define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) 1326 #define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ 1327 #define MUX_PB11I_SDHC0_SDCK _L_(8) 1328 #define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) 1329 #define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) 1330 #define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ 1331 #define MUX_PA08I_SDHC0_SDCMD _L_(8) 1332 #define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) 1333 #define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) 1334 #define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ 1335 #define MUX_PA09I_SDHC0_SDDAT0 _L_(8) 1336 #define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) 1337 #define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) 1338 #define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ 1339 #define MUX_PA10I_SDHC0_SDDAT1 _L_(8) 1340 #define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) 1341 #define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) 1342 #define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ 1343 #define MUX_PA11I_SDHC0_SDDAT2 _L_(8) 1344 #define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) 1345 #define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) 1346 #define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ 1347 #define MUX_PB10I_SDHC0_SDDAT3 _L_(8) 1348 #define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) 1349 #define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) 1350 #define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ 1351 #define MUX_PA07I_SDHC0_SDWP _L_(8) 1352 #define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) 1353 #define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) 1354 #define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ 1355 #define MUX_PA13I_SDHC0_SDWP _L_(8) 1356 #define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) 1357 #define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) 1358 1359 #endif /* _SAMD51G18A_PIO_ */ 1360
