1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMD21G15A 5 * 6 * Copyright (c) 2017 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21G15A_PIO_ 30 #define _SAMD21G15A_PIO_ 31 32 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 33 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 34 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 35 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 36 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 37 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 38 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 39 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 40 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 41 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 42 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 43 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 44 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 45 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 46 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 47 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 48 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 49 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 50 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 51 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 52 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 53 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 54 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 55 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 56 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 57 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 58 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 59 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 60 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 61 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 62 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 63 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 64 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 65 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 66 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 67 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 68 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 69 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 70 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 71 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 72 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 73 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 74 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ 75 #define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ 76 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 77 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 78 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 79 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 80 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 81 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 82 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 83 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 84 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 85 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 86 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 87 #define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */ 88 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 89 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 90 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 91 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 92 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 93 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 94 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 95 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 96 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 97 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 98 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 99 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 100 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ 101 #define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ 102 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ 103 #define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ 104 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 105 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 106 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 107 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 108 /* ========== PORT definition for GCLK peripheral ========== */ 109 #define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ 110 #define MUX_PB22H_GCLK_IO0 _L_(7) 111 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) 112 #define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) 113 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 114 #define MUX_PA14H_GCLK_IO0 _L_(7) 115 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 116 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 117 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 118 #define MUX_PA27H_GCLK_IO0 _L_(7) 119 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 120 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 121 #define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */ 122 #define MUX_PA28H_GCLK_IO0 _L_(7) 123 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) 124 #define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28) 125 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 126 #define MUX_PA30H_GCLK_IO0 _L_(7) 127 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 128 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 129 #define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ 130 #define MUX_PB23H_GCLK_IO1 _L_(7) 131 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) 132 #define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) 133 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 134 #define MUX_PA15H_GCLK_IO1 _L_(7) 135 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 136 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 137 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 138 #define MUX_PA16H_GCLK_IO2 _L_(7) 139 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 140 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 141 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 142 #define MUX_PA17H_GCLK_IO3 _L_(7) 143 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 144 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 145 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 146 #define MUX_PA10H_GCLK_IO4 _L_(7) 147 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 148 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 149 #define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ 150 #define MUX_PA20H_GCLK_IO4 _L_(7) 151 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) 152 #define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) 153 #define PIN_PB10H_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux H */ 154 #define MUX_PB10H_GCLK_IO4 _L_(7) 155 #define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) 156 #define PORT_PB10H_GCLK_IO4 (_UL_(1) << 10) 157 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 158 #define MUX_PA11H_GCLK_IO5 _L_(7) 159 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 160 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 161 #define PIN_PA21H_GCLK_IO5 _L_(21) /**< \brief GCLK signal: IO5 on PA21 mux H */ 162 #define MUX_PA21H_GCLK_IO5 _L_(7) 163 #define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) 164 #define PORT_PA21H_GCLK_IO5 (_UL_(1) << 21) 165 #define PIN_PB11H_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux H */ 166 #define MUX_PB11H_GCLK_IO5 _L_(7) 167 #define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) 168 #define PORT_PB11H_GCLK_IO5 (_UL_(1) << 11) 169 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 170 #define MUX_PA22H_GCLK_IO6 _L_(7) 171 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 172 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 173 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 174 #define MUX_PA23H_GCLK_IO7 _L_(7) 175 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 176 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 177 /* ========== PORT definition for EIC peripheral ========== */ 178 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 179 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 180 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 181 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 182 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 183 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 184 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 185 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 186 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 187 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 188 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 189 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 190 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 191 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 192 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 193 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 194 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 195 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 196 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 197 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 198 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 199 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 200 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 201 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 202 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 203 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 204 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 205 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 206 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 207 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 208 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 209 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 210 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 211 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 212 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 213 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 214 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 215 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 216 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 217 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 218 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 219 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 220 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 221 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 222 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 223 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 224 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 225 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 226 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 227 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 228 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 229 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 230 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 231 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 232 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 233 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 234 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 235 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 236 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 237 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 238 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 239 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 240 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 241 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 242 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 243 #define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ 244 #define MUX_PA21A_EIC_EXTINT5 _L_(0) 245 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 246 #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) 247 #define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ 248 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 249 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 250 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 251 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 252 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 253 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 254 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 255 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 256 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 257 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 258 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 259 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 260 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 261 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 262 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 263 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 264 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 265 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 266 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 267 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 268 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 269 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 270 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 271 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 272 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 273 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 274 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 275 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 276 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 277 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 278 #define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */ 279 #define MUX_PA28A_EIC_EXTINT8 _L_(0) 280 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) 281 #define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28) 282 #define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */ 283 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 284 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 285 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 286 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 287 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 288 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 289 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 290 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 291 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 292 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 293 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 294 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 295 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 296 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 297 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 298 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 299 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 300 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 301 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 302 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 303 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 304 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 305 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 306 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 307 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 308 #define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ 309 #define MUX_PB10A_EIC_EXTINT10 _L_(0) 310 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 311 #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) 312 #define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ 313 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 314 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 315 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 316 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 317 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 318 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 319 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 320 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 321 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 322 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 323 #define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ 324 #define MUX_PB11A_EIC_EXTINT11 _L_(0) 325 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 326 #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) 327 #define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ 328 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 329 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 330 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 331 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 332 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 333 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 334 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 335 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 336 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 337 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 338 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 339 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 340 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 341 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 342 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 343 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 344 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 345 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 346 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 347 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 348 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 349 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 350 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 351 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 352 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 353 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 354 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 355 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 356 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 357 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 358 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 359 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 360 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 361 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 362 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 363 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 364 #define MUX_PA08A_EIC_NMI _L_(0) 365 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 366 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 367 /* ========== PORT definition for USB peripheral ========== */ 368 #define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ 369 #define MUX_PA24G_USB_DM _L_(6) 370 #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) 371 #define PORT_PA24G_USB_DM (_UL_(1) << 24) 372 #define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ 373 #define MUX_PA25G_USB_DP _L_(6) 374 #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) 375 #define PORT_PA25G_USB_DP (_UL_(1) << 25) 376 #define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ 377 #define MUX_PA23G_USB_SOF_1KHZ _L_(6) 378 #define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) 379 #define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) 380 /* ========== PORT definition for SERCOM0 peripheral ========== */ 381 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 382 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 383 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 384 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 385 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 386 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 387 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 388 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 389 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 390 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 391 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 392 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 393 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 394 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 395 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 396 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 397 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 398 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 399 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 400 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 401 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 402 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 403 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 404 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 405 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 406 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 407 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 408 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 409 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 410 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 411 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 412 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 413 /* ========== PORT definition for SERCOM1 peripheral ========== */ 414 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 415 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 416 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 417 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 418 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 419 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 420 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 421 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 422 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 423 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 424 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 425 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 426 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 427 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 428 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 429 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 430 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 431 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 432 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 433 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 434 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 435 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 436 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 437 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 438 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 439 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 440 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 441 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 442 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 443 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 444 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 445 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 446 /* ========== PORT definition for SERCOM2 peripheral ========== */ 447 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 448 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 449 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 450 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 451 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 452 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 453 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 454 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 455 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 456 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 457 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 458 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 459 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 460 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 461 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 462 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 463 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 464 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 465 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 466 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 467 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 468 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 469 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 470 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 471 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 472 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 473 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 474 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 475 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 476 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 477 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 478 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 479 /* ========== PORT definition for SERCOM3 peripheral ========== */ 480 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 481 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 482 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 483 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 484 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 485 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 486 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 487 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 488 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 489 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 490 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 491 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 492 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 493 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 494 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 495 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 496 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 497 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 498 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 499 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 500 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 501 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 502 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 503 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 504 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 505 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 506 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 507 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 508 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 509 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 510 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 511 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 512 #define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ 513 #define MUX_PA21D_SERCOM3_PAD3 _L_(3) 514 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 515 #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) 516 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 517 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 518 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 519 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 520 /* ========== PORT definition for SERCOM4 peripheral ========== */ 521 #define PIN_PA12D_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ 522 #define MUX_PA12D_SERCOM4_PAD0 _L_(3) 523 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) 524 #define PORT_PA12D_SERCOM4_PAD0 (_UL_(1) << 12) 525 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 526 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 527 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 528 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 529 #define PIN_PA13D_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ 530 #define MUX_PA13D_SERCOM4_PAD1 _L_(3) 531 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) 532 #define PORT_PA13D_SERCOM4_PAD1 (_UL_(1) << 13) 533 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 534 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 535 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 536 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 537 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 538 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 539 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 540 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 541 #define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ 542 #define MUX_PB10D_SERCOM4_PAD2 _L_(3) 543 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 544 #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) 545 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 546 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 547 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 548 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 549 #define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ 550 #define MUX_PB11D_SERCOM4_PAD3 _L_(3) 551 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 552 #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) 553 /* ========== PORT definition for SERCOM5 peripheral ========== */ 554 #define PIN_PA22D_SERCOM5_PAD0 _L_(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ 555 #define MUX_PA22D_SERCOM5_PAD0 _L_(3) 556 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) 557 #define PORT_PA22D_SERCOM5_PAD0 (_UL_(1) << 22) 558 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 559 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 560 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 561 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 562 #define PIN_PA23D_SERCOM5_PAD1 _L_(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ 563 #define MUX_PA23D_SERCOM5_PAD1 _L_(3) 564 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) 565 #define PORT_PA23D_SERCOM5_PAD1 (_UL_(1) << 23) 566 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 567 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 568 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 569 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 570 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 571 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 572 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 573 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 574 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 575 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 576 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 577 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 578 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 579 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 580 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 581 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 582 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 583 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 584 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 585 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 586 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 587 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 588 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 589 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 590 #define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ 591 #define MUX_PA21C_SERCOM5_PAD3 _L_(2) 592 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 593 #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) 594 /* ========== PORT definition for TCC0 peripheral ========== */ 595 #define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ 596 #define MUX_PA04E_TCC0_WO0 _L_(4) 597 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) 598 #define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) 599 #define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 600 #define MUX_PA08E_TCC0_WO0 _L_(4) 601 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 602 #define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) 603 #define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ 604 #define MUX_PA05E_TCC0_WO1 _L_(4) 605 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) 606 #define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) 607 #define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 608 #define MUX_PA09E_TCC0_WO1 _L_(4) 609 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 610 #define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) 611 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 612 #define MUX_PA10F_TCC0_WO2 _L_(5) 613 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 614 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 615 #define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 616 #define MUX_PA18F_TCC0_WO2 _L_(5) 617 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 618 #define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) 619 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 620 #define MUX_PA11F_TCC0_WO3 _L_(5) 621 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 622 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 623 #define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 624 #define MUX_PA19F_TCC0_WO3 _L_(5) 625 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 626 #define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) 627 #define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ 628 #define MUX_PA14F_TCC0_WO4 _L_(5) 629 #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) 630 #define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) 631 #define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ 632 #define MUX_PA22F_TCC0_WO4 _L_(5) 633 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) 634 #define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) 635 #define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ 636 #define MUX_PB10F_TCC0_WO4 _L_(5) 637 #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) 638 #define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) 639 #define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ 640 #define MUX_PA15F_TCC0_WO5 _L_(5) 641 #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) 642 #define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) 643 #define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ 644 #define MUX_PA23F_TCC0_WO5 _L_(5) 645 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) 646 #define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) 647 #define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ 648 #define MUX_PB11F_TCC0_WO5 _L_(5) 649 #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) 650 #define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) 651 #define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ 652 #define MUX_PA12F_TCC0_WO6 _L_(5) 653 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) 654 #define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) 655 #define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ 656 #define MUX_PA20F_TCC0_WO6 _L_(5) 657 #define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) 658 #define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) 659 #define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ 660 #define MUX_PA16F_TCC0_WO6 _L_(5) 661 #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) 662 #define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) 663 #define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ 664 #define MUX_PA13F_TCC0_WO7 _L_(5) 665 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) 666 #define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) 667 #define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ 668 #define MUX_PA21F_TCC0_WO7 _L_(5) 669 #define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) 670 #define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) 671 #define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ 672 #define MUX_PA17F_TCC0_WO7 _L_(5) 673 #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) 674 #define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) 675 /* ========== PORT definition for TCC1 peripheral ========== */ 676 #define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 677 #define MUX_PA06E_TCC1_WO0 _L_(4) 678 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 679 #define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6) 680 #define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 681 #define MUX_PA10E_TCC1_WO0 _L_(4) 682 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 683 #define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10) 684 #define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 685 #define MUX_PA30E_TCC1_WO0 _L_(4) 686 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 687 #define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30) 688 #define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 689 #define MUX_PA07E_TCC1_WO1 _L_(4) 690 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 691 #define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7) 692 #define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 693 #define MUX_PA11E_TCC1_WO1 _L_(4) 694 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 695 #define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11) 696 #define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 697 #define MUX_PA31E_TCC1_WO1 _L_(4) 698 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 699 #define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31) 700 #define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */ 701 #define MUX_PA08F_TCC1_WO2 _L_(5) 702 #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) 703 #define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8) 704 #define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 705 #define MUX_PA24F_TCC1_WO2 _L_(5) 706 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 707 #define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24) 708 #define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */ 709 #define MUX_PA09F_TCC1_WO3 _L_(5) 710 #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) 711 #define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9) 712 #define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 713 #define MUX_PA25F_TCC1_WO3 _L_(5) 714 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 715 #define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25) 716 /* ========== PORT definition for TCC2 peripheral ========== */ 717 #define PIN_PA12E_TCC2_WO0 _L_(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */ 718 #define MUX_PA12E_TCC2_WO0 _L_(4) 719 #define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) 720 #define PORT_PA12E_TCC2_WO0 (_UL_(1) << 12) 721 #define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 722 #define MUX_PA16E_TCC2_WO0 _L_(4) 723 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 724 #define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16) 725 #define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */ 726 #define MUX_PA00E_TCC2_WO0 _L_(4) 727 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) 728 #define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0) 729 #define PIN_PA13E_TCC2_WO1 _L_(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */ 730 #define MUX_PA13E_TCC2_WO1 _L_(4) 731 #define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) 732 #define PORT_PA13E_TCC2_WO1 (_UL_(1) << 13) 733 #define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 734 #define MUX_PA17E_TCC2_WO1 _L_(4) 735 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 736 #define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17) 737 #define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */ 738 #define MUX_PA01E_TCC2_WO1 _L_(4) 739 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) 740 #define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1) 741 /* ========== PORT definition for TC3 peripheral ========== */ 742 #define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ 743 #define MUX_PA18E_TC3_WO0 _L_(4) 744 #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) 745 #define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) 746 #define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ 747 #define MUX_PA14E_TC3_WO0 _L_(4) 748 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) 749 #define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) 750 #define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ 751 #define MUX_PA19E_TC3_WO1 _L_(4) 752 #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) 753 #define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) 754 #define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ 755 #define MUX_PA15E_TC3_WO1 _L_(4) 756 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) 757 #define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) 758 /* ========== PORT definition for TC4 peripheral ========== */ 759 #define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ 760 #define MUX_PA22E_TC4_WO0 _L_(4) 761 #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) 762 #define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) 763 #define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ 764 #define MUX_PB08E_TC4_WO0 _L_(4) 765 #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) 766 #define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) 767 #define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ 768 #define MUX_PA23E_TC4_WO1 _L_(4) 769 #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) 770 #define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) 771 #define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ 772 #define MUX_PB09E_TC4_WO1 _L_(4) 773 #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) 774 #define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) 775 /* ========== PORT definition for TC5 peripheral ========== */ 776 #define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ 777 #define MUX_PA24E_TC5_WO0 _L_(4) 778 #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) 779 #define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) 780 #define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ 781 #define MUX_PB10E_TC5_WO0 _L_(4) 782 #define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) 783 #define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) 784 #define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ 785 #define MUX_PA25E_TC5_WO1 _L_(4) 786 #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) 787 #define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) 788 #define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ 789 #define MUX_PB11E_TC5_WO1 _L_(4) 790 #define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) 791 #define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) 792 /* ========== PORT definition for ADC peripheral ========== */ 793 #define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ 794 #define MUX_PA02B_ADC_AIN0 _L_(1) 795 #define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) 796 #define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) 797 #define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ 798 #define MUX_PA03B_ADC_AIN1 _L_(1) 799 #define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) 800 #define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) 801 #define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ 802 #define MUX_PB08B_ADC_AIN2 _L_(1) 803 #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) 804 #define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) 805 #define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ 806 #define MUX_PB09B_ADC_AIN3 _L_(1) 807 #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) 808 #define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) 809 #define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ 810 #define MUX_PA04B_ADC_AIN4 _L_(1) 811 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) 812 #define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) 813 #define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ 814 #define MUX_PA05B_ADC_AIN5 _L_(1) 815 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) 816 #define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) 817 #define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ 818 #define MUX_PA06B_ADC_AIN6 _L_(1) 819 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) 820 #define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) 821 #define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ 822 #define MUX_PA07B_ADC_AIN7 _L_(1) 823 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) 824 #define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) 825 #define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ 826 #define MUX_PB02B_ADC_AIN10 _L_(1) 827 #define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) 828 #define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) 829 #define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ 830 #define MUX_PB03B_ADC_AIN11 _L_(1) 831 #define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) 832 #define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) 833 #define PIN_PA08B_ADC_AIN16 _L_(8) /**< \brief ADC signal: AIN16 on PA08 mux B */ 834 #define MUX_PA08B_ADC_AIN16 _L_(1) 835 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) 836 #define PORT_PA08B_ADC_AIN16 (_UL_(1) << 8) 837 #define PIN_PA09B_ADC_AIN17 _L_(9) /**< \brief ADC signal: AIN17 on PA09 mux B */ 838 #define MUX_PA09B_ADC_AIN17 _L_(1) 839 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) 840 #define PORT_PA09B_ADC_AIN17 (_UL_(1) << 9) 841 #define PIN_PA10B_ADC_AIN18 _L_(10) /**< \brief ADC signal: AIN18 on PA10 mux B */ 842 #define MUX_PA10B_ADC_AIN18 _L_(1) 843 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) 844 #define PORT_PA10B_ADC_AIN18 (_UL_(1) << 10) 845 #define PIN_PA11B_ADC_AIN19 _L_(11) /**< \brief ADC signal: AIN19 on PA11 mux B */ 846 #define MUX_PA11B_ADC_AIN19 _L_(1) 847 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) 848 #define PORT_PA11B_ADC_AIN19 (_UL_(1) << 11) 849 #define PIN_PA04B_ADC_VREFP _L_(4) /**< \brief ADC signal: VREFP on PA04 mux B */ 850 #define MUX_PA04B_ADC_VREFP _L_(1) 851 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) 852 #define PORT_PA04B_ADC_VREFP (_UL_(1) << 4) 853 /* ========== PORT definition for AC peripheral ========== */ 854 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 855 #define MUX_PA04B_AC_AIN0 _L_(1) 856 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 857 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 858 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 859 #define MUX_PA05B_AC_AIN1 _L_(1) 860 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 861 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 862 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 863 #define MUX_PA06B_AC_AIN2 _L_(1) 864 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 865 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 866 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 867 #define MUX_PA07B_AC_AIN3 _L_(1) 868 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 869 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 870 #define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ 871 #define MUX_PA12H_AC_CMP0 _L_(7) 872 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) 873 #define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) 874 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 875 #define MUX_PA18H_AC_CMP0 _L_(7) 876 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 877 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 878 #define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ 879 #define MUX_PA13H_AC_CMP1 _L_(7) 880 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) 881 #define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) 882 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 883 #define MUX_PA19H_AC_CMP1 _L_(7) 884 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 885 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 886 /* ========== PORT definition for DAC peripheral ========== */ 887 #define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */ 888 #define MUX_PA02B_DAC_VOUT _L_(1) 889 #define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) 890 #define PORT_PA02B_DAC_VOUT (_UL_(1) << 2) 891 #define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */ 892 #define MUX_PA03B_DAC_VREFP _L_(1) 893 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) 894 #define PORT_PA03B_DAC_VREFP (_UL_(1) << 3) 895 /* ========== PORT definition for I2S peripheral ========== */ 896 #define PIN_PA11G_I2S_FS0 _L_(11) /**< \brief I2S signal: FS0 on PA11 mux G */ 897 #define MUX_PA11G_I2S_FS0 _L_(6) 898 #define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) 899 #define PORT_PA11G_I2S_FS0 (_UL_(1) << 11) 900 #define PIN_PA21G_I2S_FS0 _L_(21) /**< \brief I2S signal: FS0 on PA21 mux G */ 901 #define MUX_PA21G_I2S_FS0 _L_(6) 902 #define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) 903 #define PORT_PA21G_I2S_FS0 (_UL_(1) << 21) 904 #define PIN_PA09G_I2S_MCK0 _L_(9) /**< \brief I2S signal: MCK0 on PA09 mux G */ 905 #define MUX_PA09G_I2S_MCK0 _L_(6) 906 #define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) 907 #define PORT_PA09G_I2S_MCK0 (_UL_(1) << 9) 908 #define PIN_PB10G_I2S_MCK1 _L_(42) /**< \brief I2S signal: MCK1 on PB10 mux G */ 909 #define MUX_PB10G_I2S_MCK1 _L_(6) 910 #define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) 911 #define PORT_PB10G_I2S_MCK1 (_UL_(1) << 10) 912 #define PIN_PA10G_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux G */ 913 #define MUX_PA10G_I2S_SCK0 _L_(6) 914 #define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) 915 #define PORT_PA10G_I2S_SCK0 (_UL_(1) << 10) 916 #define PIN_PA20G_I2S_SCK0 _L_(20) /**< \brief I2S signal: SCK0 on PA20 mux G */ 917 #define MUX_PA20G_I2S_SCK0 _L_(6) 918 #define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) 919 #define PORT_PA20G_I2S_SCK0 (_UL_(1) << 20) 920 #define PIN_PB11G_I2S_SCK1 _L_(43) /**< \brief I2S signal: SCK1 on PB11 mux G */ 921 #define MUX_PB11G_I2S_SCK1 _L_(6) 922 #define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) 923 #define PORT_PB11G_I2S_SCK1 (_UL_(1) << 11) 924 #define PIN_PA07G_I2S_SD0 _L_(7) /**< \brief I2S signal: SD0 on PA07 mux G */ 925 #define MUX_PA07G_I2S_SD0 _L_(6) 926 #define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) 927 #define PORT_PA07G_I2S_SD0 (_UL_(1) << 7) 928 #define PIN_PA19G_I2S_SD0 _L_(19) /**< \brief I2S signal: SD0 on PA19 mux G */ 929 #define MUX_PA19G_I2S_SD0 _L_(6) 930 #define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) 931 #define PORT_PA19G_I2S_SD0 (_UL_(1) << 19) 932 #define PIN_PA08G_I2S_SD1 _L_(8) /**< \brief I2S signal: SD1 on PA08 mux G */ 933 #define MUX_PA08G_I2S_SD1 _L_(6) 934 #define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) 935 #define PORT_PA08G_I2S_SD1 (_UL_(1) << 8) 936 937 #endif /* _SAMD21G15A_PIO_ */ 938
