1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMC21E18A 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21E18A_PIO_ 31 #define _SAMC21E18A_PIO_ 32 33 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 34 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 35 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 36 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 37 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 38 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 39 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 40 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 41 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 42 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 43 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 44 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 45 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 46 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 47 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 48 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 49 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 50 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 51 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 52 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 53 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 54 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 55 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 56 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 57 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 58 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 59 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 60 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 61 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 62 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 63 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 64 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 65 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 66 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 67 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 68 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 69 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 70 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 71 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 72 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 73 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 74 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 75 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 76 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 77 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 78 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 79 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 80 #define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */ 81 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 82 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 83 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 84 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 85 /* ========== PORT definition for RSTC peripheral ========== */ 86 #define PIN_PA00A_RSTC_EXTWAKE0 _L_(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ 87 #define MUX_PA00A_RSTC_EXTWAKE0 _L_(0) 88 #define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) 89 #define PORT_PA00A_RSTC_EXTWAKE0 (_UL_(1) << 0) 90 #define PIN_PA01A_RSTC_EXTWAKE1 _L_(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ 91 #define MUX_PA01A_RSTC_EXTWAKE1 _L_(0) 92 #define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) 93 #define PORT_PA01A_RSTC_EXTWAKE1 (_UL_(1) << 1) 94 #define PIN_PA02A_RSTC_EXTWAKE2 _L_(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ 95 #define MUX_PA02A_RSTC_EXTWAKE2 _L_(0) 96 #define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) 97 #define PORT_PA02A_RSTC_EXTWAKE2 (_UL_(1) << 2) 98 #define PIN_PA03A_RSTC_EXTWAKE3 _L_(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ 99 #define MUX_PA03A_RSTC_EXTWAKE3 _L_(0) 100 #define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) 101 #define PORT_PA03A_RSTC_EXTWAKE3 (_UL_(1) << 3) 102 #define PIN_PA04A_RSTC_EXTWAKE4 _L_(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ 103 #define MUX_PA04A_RSTC_EXTWAKE4 _L_(0) 104 #define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) 105 #define PORT_PA04A_RSTC_EXTWAKE4 (_UL_(1) << 4) 106 #define PIN_PA05A_RSTC_EXTWAKE5 _L_(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ 107 #define MUX_PA05A_RSTC_EXTWAKE5 _L_(0) 108 #define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) 109 #define PORT_PA05A_RSTC_EXTWAKE5 (_UL_(1) << 5) 110 #define PIN_PA06A_RSTC_EXTWAKE6 _L_(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ 111 #define MUX_PA06A_RSTC_EXTWAKE6 _L_(0) 112 #define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) 113 #define PORT_PA06A_RSTC_EXTWAKE6 (_UL_(1) << 6) 114 #define PIN_PA07A_RSTC_EXTWAKE7 _L_(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ 115 #define MUX_PA07A_RSTC_EXTWAKE7 _L_(0) 116 #define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) 117 #define PORT_PA07A_RSTC_EXTWAKE7 (_UL_(1) << 7) 118 #define PIN_PA08A_RSTC_EXTWAKE8 _L_(8) /**< \brief RSTC signal: EXTWAKE8 on PA08 mux A */ 119 #define MUX_PA08A_RSTC_EXTWAKE8 _L_(0) 120 #define PINMUX_PA08A_RSTC_EXTWAKE8 ((PIN_PA08A_RSTC_EXTWAKE8 << 16) | MUX_PA08A_RSTC_EXTWAKE8) 121 #define PORT_PA08A_RSTC_EXTWAKE8 (_UL_(1) << 8) 122 #define PIN_PA09A_RSTC_EXTWAKE9 _L_(9) /**< \brief RSTC signal: EXTWAKE9 on PA09 mux A */ 123 #define MUX_PA09A_RSTC_EXTWAKE9 _L_(0) 124 #define PINMUX_PA09A_RSTC_EXTWAKE9 ((PIN_PA09A_RSTC_EXTWAKE9 << 16) | MUX_PA09A_RSTC_EXTWAKE9) 125 #define PORT_PA09A_RSTC_EXTWAKE9 (_UL_(1) << 9) 126 #define PIN_PA10A_RSTC_EXTWAKE10 _L_(10) /**< \brief RSTC signal: EXTWAKE10 on PA10 mux A */ 127 #define MUX_PA10A_RSTC_EXTWAKE10 _L_(0) 128 #define PINMUX_PA10A_RSTC_EXTWAKE10 ((PIN_PA10A_RSTC_EXTWAKE10 << 16) | MUX_PA10A_RSTC_EXTWAKE10) 129 #define PORT_PA10A_RSTC_EXTWAKE10 (_UL_(1) << 10) 130 #define PIN_PA11A_RSTC_EXTWAKE11 _L_(11) /**< \brief RSTC signal: EXTWAKE11 on PA11 mux A */ 131 #define MUX_PA11A_RSTC_EXTWAKE11 _L_(0) 132 #define PINMUX_PA11A_RSTC_EXTWAKE11 ((PIN_PA11A_RSTC_EXTWAKE11 << 16) | MUX_PA11A_RSTC_EXTWAKE11) 133 #define PORT_PA11A_RSTC_EXTWAKE11 (_UL_(1) << 11) 134 #define PIN_PA14A_RSTC_EXTWAKE14 _L_(14) /**< \brief RSTC signal: EXTWAKE14 on PA14 mux A */ 135 #define MUX_PA14A_RSTC_EXTWAKE14 _L_(0) 136 #define PINMUX_PA14A_RSTC_EXTWAKE14 ((PIN_PA14A_RSTC_EXTWAKE14 << 16) | MUX_PA14A_RSTC_EXTWAKE14) 137 #define PORT_PA14A_RSTC_EXTWAKE14 (_UL_(1) << 14) 138 #define PIN_PA15A_RSTC_EXTWAKE15 _L_(15) /**< \brief RSTC signal: EXTWAKE15 on PA15 mux A */ 139 #define MUX_PA15A_RSTC_EXTWAKE15 _L_(0) 140 #define PINMUX_PA15A_RSTC_EXTWAKE15 ((PIN_PA15A_RSTC_EXTWAKE15 << 16) | MUX_PA15A_RSTC_EXTWAKE15) 141 #define PORT_PA15A_RSTC_EXTWAKE15 (_UL_(1) << 15) 142 /* ========== PORT definition for GCLK peripheral ========== */ 143 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 144 #define MUX_PA14H_GCLK_IO0 _L_(7) 145 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 146 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 147 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 148 #define MUX_PA27H_GCLK_IO0 _L_(7) 149 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 150 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 151 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 152 #define MUX_PA30H_GCLK_IO0 _L_(7) 153 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 154 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 155 #define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */ 156 #define MUX_PA28H_GCLK_IO0 _L_(7) 157 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) 158 #define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28) 159 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 160 #define MUX_PA15H_GCLK_IO1 _L_(7) 161 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 162 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 163 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 164 #define MUX_PA16H_GCLK_IO2 _L_(7) 165 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 166 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 167 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 168 #define MUX_PA17H_GCLK_IO3 _L_(7) 169 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 170 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 171 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 172 #define MUX_PA10H_GCLK_IO4 _L_(7) 173 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 174 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 175 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 176 #define MUX_PA11H_GCLK_IO5 _L_(7) 177 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 178 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 179 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 180 #define MUX_PA22H_GCLK_IO6 _L_(7) 181 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 182 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 183 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 184 #define MUX_PA23H_GCLK_IO7 _L_(7) 185 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 186 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 187 /* ========== PORT definition for EIC peripheral ========== */ 188 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 189 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 190 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 191 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 192 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 193 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 194 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 195 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 196 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 197 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 198 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 199 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 200 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 201 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 202 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 203 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 204 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 205 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 206 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 207 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 208 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 209 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 210 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 211 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 212 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 213 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 214 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 215 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 216 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 217 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 218 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 219 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 220 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 221 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 222 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 223 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 224 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 225 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 226 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 227 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 228 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 229 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 230 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 231 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 232 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 233 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 234 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 235 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 236 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 237 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 238 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 239 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 240 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 241 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 242 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 243 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 244 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 245 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 246 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 247 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 248 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 249 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 250 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 251 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 252 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 253 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 254 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 255 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 256 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 257 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 258 #define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */ 259 #define MUX_PA28A_EIC_EXTINT8 _L_(0) 260 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) 261 #define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28) 262 #define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */ 263 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 264 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 265 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 266 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 267 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 268 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 269 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 270 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 271 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 272 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 273 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 274 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 275 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 276 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 277 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 278 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 279 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 280 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 281 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 282 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 283 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 284 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 285 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 286 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 287 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 288 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 289 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 290 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 291 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 292 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 293 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 294 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 295 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 296 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 297 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 298 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 299 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 300 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 301 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 302 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 303 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 304 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 305 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 306 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 307 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 308 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 309 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 310 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 311 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 312 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 313 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 314 #define MUX_PA08A_EIC_NMI _L_(0) 315 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 316 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 317 /* ========== PORT definition for SERCOM0 peripheral ========== */ 318 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 319 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 320 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 321 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 322 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 323 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 324 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 325 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 326 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 327 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 328 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 329 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 330 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 331 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 332 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 333 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 334 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 335 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 336 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 337 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 338 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 339 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 340 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 341 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 342 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 343 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 344 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 345 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 346 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 347 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 348 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 349 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 350 /* ========== PORT definition for SERCOM1 peripheral ========== */ 351 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 352 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 353 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 354 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 355 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 356 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 357 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 358 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 359 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 360 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 361 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 362 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 363 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 364 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 365 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 366 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 367 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 368 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 369 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 370 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 371 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 372 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 373 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 374 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 375 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 376 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 377 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 378 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 379 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 380 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 381 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 382 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 383 /* ========== PORT definition for SERCOM2 peripheral ========== */ 384 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 385 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 386 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 387 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 388 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 389 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 390 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 391 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 392 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 393 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 394 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 395 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 396 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 397 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 398 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 399 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 400 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 401 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 402 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 403 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 404 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 405 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 406 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 407 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 408 /* ========== PORT definition for SERCOM3 peripheral ========== */ 409 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 410 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 411 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 412 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 413 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 414 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 415 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 416 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 417 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 418 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 419 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 420 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 421 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 422 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 423 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 424 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 425 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 426 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 427 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 428 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 429 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 430 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 431 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 432 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 433 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 434 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 435 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 436 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 437 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 438 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 439 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 440 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 441 /* ========== PORT definition for CAN0 peripheral ========== */ 442 #define PIN_PA25G_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux G */ 443 #define MUX_PA25G_CAN0_RX _L_(6) 444 #define PINMUX_PA25G_CAN0_RX ((PIN_PA25G_CAN0_RX << 16) | MUX_PA25G_CAN0_RX) 445 #define PORT_PA25G_CAN0_RX (_UL_(1) << 25) 446 #define PIN_PA24G_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux G */ 447 #define MUX_PA24G_CAN0_TX _L_(6) 448 #define PINMUX_PA24G_CAN0_TX ((PIN_PA24G_CAN0_TX << 16) | MUX_PA24G_CAN0_TX) 449 #define PORT_PA24G_CAN0_TX (_UL_(1) << 24) 450 /* ========== PORT definition for TCC0 peripheral ========== */ 451 #define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ 452 #define MUX_PA04E_TCC0_WO0 _L_(4) 453 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) 454 #define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) 455 #define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 456 #define MUX_PA08E_TCC0_WO0 _L_(4) 457 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 458 #define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) 459 #define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ 460 #define MUX_PA05E_TCC0_WO1 _L_(4) 461 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) 462 #define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) 463 #define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 464 #define MUX_PA09E_TCC0_WO1 _L_(4) 465 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 466 #define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) 467 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 468 #define MUX_PA10F_TCC0_WO2 _L_(5) 469 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 470 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 471 #define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 472 #define MUX_PA18F_TCC0_WO2 _L_(5) 473 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 474 #define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) 475 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 476 #define MUX_PA11F_TCC0_WO3 _L_(5) 477 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 478 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 479 #define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 480 #define MUX_PA19F_TCC0_WO3 _L_(5) 481 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 482 #define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) 483 #define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ 484 #define MUX_PA22F_TCC0_WO4 _L_(5) 485 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) 486 #define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) 487 #define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ 488 #define MUX_PA14F_TCC0_WO4 _L_(5) 489 #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) 490 #define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) 491 #define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ 492 #define MUX_PA15F_TCC0_WO5 _L_(5) 493 #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) 494 #define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) 495 #define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ 496 #define MUX_PA23F_TCC0_WO5 _L_(5) 497 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) 498 #define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) 499 #define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ 500 #define MUX_PA16F_TCC0_WO6 _L_(5) 501 #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) 502 #define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) 503 #define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ 504 #define MUX_PA17F_TCC0_WO7 _L_(5) 505 #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) 506 #define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) 507 /* ========== PORT definition for TCC1 peripheral ========== */ 508 #define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 509 #define MUX_PA06E_TCC1_WO0 _L_(4) 510 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 511 #define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6) 512 #define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 513 #define MUX_PA10E_TCC1_WO0 _L_(4) 514 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 515 #define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10) 516 #define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 517 #define MUX_PA30E_TCC1_WO0 _L_(4) 518 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 519 #define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30) 520 #define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 521 #define MUX_PA07E_TCC1_WO1 _L_(4) 522 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 523 #define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7) 524 #define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 525 #define MUX_PA11E_TCC1_WO1 _L_(4) 526 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 527 #define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11) 528 #define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 529 #define MUX_PA31E_TCC1_WO1 _L_(4) 530 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 531 #define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31) 532 #define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */ 533 #define MUX_PA08F_TCC1_WO2 _L_(5) 534 #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) 535 #define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8) 536 #define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 537 #define MUX_PA24F_TCC1_WO2 _L_(5) 538 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 539 #define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24) 540 #define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */ 541 #define MUX_PA09F_TCC1_WO3 _L_(5) 542 #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) 543 #define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9) 544 #define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 545 #define MUX_PA25F_TCC1_WO3 _L_(5) 546 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 547 #define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25) 548 /* ========== PORT definition for TCC2 peripheral ========== */ 549 #define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 550 #define MUX_PA16E_TCC2_WO0 _L_(4) 551 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 552 #define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16) 553 #define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */ 554 #define MUX_PA00E_TCC2_WO0 _L_(4) 555 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) 556 #define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0) 557 #define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 558 #define MUX_PA17E_TCC2_WO1 _L_(4) 559 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 560 #define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17) 561 #define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */ 562 #define MUX_PA01E_TCC2_WO1 _L_(4) 563 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) 564 #define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1) 565 /* ========== PORT definition for TC0 peripheral ========== */ 566 #define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ 567 #define MUX_PA22E_TC0_WO0 _L_(4) 568 #define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) 569 #define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) 570 #define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ 571 #define MUX_PA23E_TC0_WO1 _L_(4) 572 #define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) 573 #define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) 574 /* ========== PORT definition for TC1 peripheral ========== */ 575 #define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ 576 #define MUX_PA24E_TC1_WO0 _L_(4) 577 #define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) 578 #define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) 579 #define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ 580 #define MUX_PA25E_TC1_WO1 _L_(4) 581 #define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) 582 #define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) 583 /* ========== PORT definition for TC4 peripheral ========== */ 584 #define PIN_PA18E_TC4_WO0 _L_(18) /**< \brief TC4 signal: WO0 on PA18 mux E */ 585 #define MUX_PA18E_TC4_WO0 _L_(4) 586 #define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) 587 #define PORT_PA18E_TC4_WO0 (_UL_(1) << 18) 588 #define PIN_PA14E_TC4_WO0 _L_(14) /**< \brief TC4 signal: WO0 on PA14 mux E */ 589 #define MUX_PA14E_TC4_WO0 _L_(4) 590 #define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) 591 #define PORT_PA14E_TC4_WO0 (_UL_(1) << 14) 592 #define PIN_PA19E_TC4_WO1 _L_(19) /**< \brief TC4 signal: WO1 on PA19 mux E */ 593 #define MUX_PA19E_TC4_WO1 _L_(4) 594 #define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) 595 #define PORT_PA19E_TC4_WO1 (_UL_(1) << 19) 596 #define PIN_PA15E_TC4_WO1 _L_(15) /**< \brief TC4 signal: WO1 on PA15 mux E */ 597 #define MUX_PA15E_TC4_WO1 _L_(4) 598 #define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) 599 #define PORT_PA15E_TC4_WO1 (_UL_(1) << 15) 600 /* ========== PORT definition for ADC0 peripheral ========== */ 601 #define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ 602 #define MUX_PA02B_ADC0_AIN0 _L_(1) 603 #define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) 604 #define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) 605 #define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ 606 #define MUX_PA03B_ADC0_AIN1 _L_(1) 607 #define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) 608 #define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) 609 #define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ 610 #define MUX_PA04B_ADC0_AIN4 _L_(1) 611 #define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) 612 #define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) 613 #define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ 614 #define MUX_PA05B_ADC0_AIN5 _L_(1) 615 #define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) 616 #define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) 617 #define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ 618 #define MUX_PA06B_ADC0_AIN6 _L_(1) 619 #define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) 620 #define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) 621 #define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ 622 #define MUX_PA07B_ADC0_AIN7 _L_(1) 623 #define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) 624 #define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) 625 #define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ 626 #define MUX_PA08B_ADC0_AIN8 _L_(1) 627 #define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) 628 #define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) 629 #define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ 630 #define MUX_PA09B_ADC0_AIN9 _L_(1) 631 #define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) 632 #define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) 633 #define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ 634 #define MUX_PA10B_ADC0_AIN10 _L_(1) 635 #define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) 636 #define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) 637 #define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ 638 #define MUX_PA11B_ADC0_AIN11 _L_(1) 639 #define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) 640 #define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) 641 #define PIN_PA03B_ADC0_VREFP _L_(3) /**< \brief ADC0 signal: VREFP on PA03 mux B */ 642 #define MUX_PA03B_ADC0_VREFP _L_(1) 643 #define PINMUX_PA03B_ADC0_VREFP ((PIN_PA03B_ADC0_VREFP << 16) | MUX_PA03B_ADC0_VREFP) 644 #define PORT_PA03B_ADC0_VREFP (_UL_(1) << 3) 645 /* ========== PORT definition for ADC1 peripheral ========== */ 646 #define PIN_PA08B_ADC1_AIN10 _L_(8) /**< \brief ADC1 signal: AIN10 on PA08 mux B */ 647 #define MUX_PA08B_ADC1_AIN10 _L_(1) 648 #define PINMUX_PA08B_ADC1_AIN10 ((PIN_PA08B_ADC1_AIN10 << 16) | MUX_PA08B_ADC1_AIN10) 649 #define PORT_PA08B_ADC1_AIN10 (_UL_(1) << 8) 650 #define PIN_PA09B_ADC1_AIN11 _L_(9) /**< \brief ADC1 signal: AIN11 on PA09 mux B */ 651 #define MUX_PA09B_ADC1_AIN11 _L_(1) 652 #define PINMUX_PA09B_ADC1_AIN11 ((PIN_PA09B_ADC1_AIN11 << 16) | MUX_PA09B_ADC1_AIN11) 653 #define PORT_PA09B_ADC1_AIN11 (_UL_(1) << 9) 654 /* ========== PORT definition for SDADC peripheral ========== */ 655 #define PIN_PA06B_SDADC_INN0 _L_(6) /**< \brief SDADC signal: INN0 on PA06 mux B */ 656 #define MUX_PA06B_SDADC_INN0 _L_(1) 657 #define PINMUX_PA06B_SDADC_INN0 ((PIN_PA06B_SDADC_INN0 << 16) | MUX_PA06B_SDADC_INN0) 658 #define PORT_PA06B_SDADC_INN0 (_UL_(1) << 6) 659 #define PIN_PA07B_SDADC_INP0 _L_(7) /**< \brief SDADC signal: INP0 on PA07 mux B */ 660 #define MUX_PA07B_SDADC_INP0 _L_(1) 661 #define PINMUX_PA07B_SDADC_INP0 ((PIN_PA07B_SDADC_INP0 << 16) | MUX_PA07B_SDADC_INP0) 662 #define PORT_PA07B_SDADC_INP0 (_UL_(1) << 7) 663 #define PIN_PA04B_SDADC_VREFP _L_(4) /**< \brief SDADC signal: VREFP on PA04 mux B */ 664 #define MUX_PA04B_SDADC_VREFP _L_(1) 665 #define PINMUX_PA04B_SDADC_VREFP ((PIN_PA04B_SDADC_VREFP << 16) | MUX_PA04B_SDADC_VREFP) 666 #define PORT_PA04B_SDADC_VREFP (_UL_(1) << 4) 667 /* ========== PORT definition for AC peripheral ========== */ 668 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 669 #define MUX_PA04B_AC_AIN0 _L_(1) 670 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 671 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 672 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 673 #define MUX_PA05B_AC_AIN1 _L_(1) 674 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 675 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 676 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 677 #define MUX_PA06B_AC_AIN2 _L_(1) 678 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 679 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 680 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 681 #define MUX_PA07B_AC_AIN3 _L_(1) 682 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 683 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 684 #define PIN_PA02B_AC_AIN4 _L_(2) /**< \brief AC signal: AIN4 on PA02 mux B */ 685 #define MUX_PA02B_AC_AIN4 _L_(1) 686 #define PINMUX_PA02B_AC_AIN4 ((PIN_PA02B_AC_AIN4 << 16) | MUX_PA02B_AC_AIN4) 687 #define PORT_PA02B_AC_AIN4 (_UL_(1) << 2) 688 #define PIN_PA03B_AC_AIN5 _L_(3) /**< \brief AC signal: AIN5 on PA03 mux B */ 689 #define MUX_PA03B_AC_AIN5 _L_(1) 690 #define PINMUX_PA03B_AC_AIN5 ((PIN_PA03B_AC_AIN5 << 16) | MUX_PA03B_AC_AIN5) 691 #define PORT_PA03B_AC_AIN5 (_UL_(1) << 3) 692 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 693 #define MUX_PA18H_AC_CMP0 _L_(7) 694 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 695 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 696 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 697 #define MUX_PA19H_AC_CMP1 _L_(7) 698 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 699 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 700 #define PIN_PA00H_AC_CMP2 _L_(0) /**< \brief AC signal: CMP2 on PA00 mux H */ 701 #define MUX_PA00H_AC_CMP2 _L_(7) 702 #define PINMUX_PA00H_AC_CMP2 ((PIN_PA00H_AC_CMP2 << 16) | MUX_PA00H_AC_CMP2) 703 #define PORT_PA00H_AC_CMP2 (_UL_(1) << 0) 704 #define PIN_PA24H_AC_CMP2 _L_(24) /**< \brief AC signal: CMP2 on PA24 mux H */ 705 #define MUX_PA24H_AC_CMP2 _L_(7) 706 #define PINMUX_PA24H_AC_CMP2 ((PIN_PA24H_AC_CMP2 << 16) | MUX_PA24H_AC_CMP2) 707 #define PORT_PA24H_AC_CMP2 (_UL_(1) << 24) 708 #define PIN_PA01H_AC_CMP3 _L_(1) /**< \brief AC signal: CMP3 on PA01 mux H */ 709 #define MUX_PA01H_AC_CMP3 _L_(7) 710 #define PINMUX_PA01H_AC_CMP3 ((PIN_PA01H_AC_CMP3 << 16) | MUX_PA01H_AC_CMP3) 711 #define PORT_PA01H_AC_CMP3 (_UL_(1) << 1) 712 #define PIN_PA25H_AC_CMP3 _L_(25) /**< \brief AC signal: CMP3 on PA25 mux H */ 713 #define MUX_PA25H_AC_CMP3 _L_(7) 714 #define PINMUX_PA25H_AC_CMP3 ((PIN_PA25H_AC_CMP3 << 16) | MUX_PA25H_AC_CMP3) 715 #define PORT_PA25H_AC_CMP3 (_UL_(1) << 25) 716 /* ========== PORT definition for DAC peripheral ========== */ 717 #define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */ 718 #define MUX_PA02B_DAC_VOUT _L_(1) 719 #define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) 720 #define PORT_PA02B_DAC_VOUT (_UL_(1) << 2) 721 #define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */ 722 #define MUX_PA03B_DAC_VREFP _L_(1) 723 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) 724 #define PORT_PA03B_DAC_VREFP (_UL_(1) << 3) 725 /* ========== PORT definition for CCL peripheral ========== */ 726 #define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ 727 #define MUX_PA04I_CCL_IN0 _L_(8) 728 #define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) 729 #define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) 730 #define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ 731 #define MUX_PA16I_CCL_IN0 _L_(8) 732 #define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) 733 #define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) 734 #define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ 735 #define MUX_PA05I_CCL_IN1 _L_(8) 736 #define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) 737 #define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) 738 #define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ 739 #define MUX_PA17I_CCL_IN1 _L_(8) 740 #define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) 741 #define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) 742 #define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ 743 #define MUX_PA06I_CCL_IN2 _L_(8) 744 #define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) 745 #define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) 746 #define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ 747 #define MUX_PA18I_CCL_IN2 _L_(8) 748 #define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) 749 #define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) 750 #define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ 751 #define MUX_PA08I_CCL_IN3 _L_(8) 752 #define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) 753 #define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) 754 #define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ 755 #define MUX_PA30I_CCL_IN3 _L_(8) 756 #define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) 757 #define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) 758 #define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ 759 #define MUX_PA09I_CCL_IN4 _L_(8) 760 #define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) 761 #define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) 762 #define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ 763 #define MUX_PA10I_CCL_IN5 _L_(8) 764 #define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) 765 #define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) 766 #define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ 767 #define MUX_PA22I_CCL_IN6 _L_(8) 768 #define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) 769 #define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) 770 #define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ 771 #define MUX_PA23I_CCL_IN7 _L_(8) 772 #define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) 773 #define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) 774 #define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ 775 #define MUX_PA24I_CCL_IN8 _L_(8) 776 #define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) 777 #define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) 778 #define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ 779 #define MUX_PA07I_CCL_OUT0 _L_(8) 780 #define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) 781 #define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) 782 #define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ 783 #define MUX_PA19I_CCL_OUT0 _L_(8) 784 #define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) 785 #define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) 786 #define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ 787 #define MUX_PA11I_CCL_OUT1 _L_(8) 788 #define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) 789 #define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) 790 #define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ 791 #define MUX_PA31I_CCL_OUT1 _L_(8) 792 #define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) 793 #define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) 794 #define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ 795 #define MUX_PA25I_CCL_OUT2 _L_(8) 796 #define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) 797 #define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) 798 799 #endif /* _SAMC21E18A_PIO_ */ 800
