1 /* 2 * Peripheral I/O description for PIC32CX1025SG41080 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2024-08-09T07:05:00Z */ 21 #ifndef _PIC32CX1025SG41080_GPIO_H_ 22 #define _PIC32CX1025SG41080_GPIO_H_ 23 24 /* ======================= Peripheral I/O pin numbers ======================= */ 25 #define PIN_PA00 ( 0) /* Pin Number for PA00 */ 26 #define PIN_PA01 ( 1) /* Pin Number for PA01 */ 27 #define PIN_PA02 ( 2) /* Pin Number for PA02 */ 28 #define PIN_PA03 ( 3) /* Pin Number for PA03 */ 29 #define PIN_PA04 ( 4) /* Pin Number for PA04 */ 30 #define PIN_PA05 ( 5) /* Pin Number for PA05 */ 31 #define PIN_PA06 ( 6) /* Pin Number for PA06 */ 32 #define PIN_PA07 ( 7) /* Pin Number for PA07 */ 33 #define PIN_PA08 ( 8) /* Pin Number for PA08 */ 34 #define PIN_PA09 ( 9) /* Pin Number for PA09 */ 35 #define PIN_PA10 ( 10) /* Pin Number for PA10 */ 36 #define PIN_PA11 ( 11) /* Pin Number for PA11 */ 37 #define PIN_PA12 ( 12) /* Pin Number for PA12 */ 38 #define PIN_PA13 ( 13) /* Pin Number for PA13 */ 39 #define PIN_PA14 ( 14) /* Pin Number for PA14 */ 40 #define PIN_PA15 ( 15) /* Pin Number for PA15 */ 41 #define PIN_PA16 ( 16) /* Pin Number for PA16 */ 42 #define PIN_PA17 ( 17) /* Pin Number for PA17 */ 43 #define PIN_PA18 ( 18) /* Pin Number for PA18 */ 44 #define PIN_PA19 ( 19) /* Pin Number for PA19 */ 45 #define PIN_PA20 ( 20) /* Pin Number for PA20 */ 46 #define PIN_PA21 ( 21) /* Pin Number for PA21 */ 47 #define PIN_PA22 ( 22) /* Pin Number for PA22 */ 48 #define PIN_PA23 ( 23) /* Pin Number for PA23 */ 49 #define PIN_PA24 ( 24) /* Pin Number for PA24 */ 50 #define PIN_PA25 ( 25) /* Pin Number for PA25 */ 51 #define PIN_PA27 ( 27) /* Pin Number for PA27 */ 52 #define PIN_PA30 ( 30) /* Pin Number for PA30 */ 53 #define PIN_PA31 ( 31) /* Pin Number for PA31 */ 54 #define PIN_PB00 ( 32) /* Pin Number for PB00 */ 55 #define PIN_PB01 ( 33) /* Pin Number for PB01 */ 56 #define PIN_PB02 ( 34) /* Pin Number for PB02 */ 57 #define PIN_PB03 ( 35) /* Pin Number for PB03 */ 58 #define PIN_PB04 ( 36) /* Pin Number for PB04 */ 59 #define PIN_PB05 ( 37) /* Pin Number for PB05 */ 60 #define PIN_PB06 ( 38) /* Pin Number for PB06 */ 61 #define PIN_PB07 ( 39) /* Pin Number for PB07 */ 62 #define PIN_PB08 ( 40) /* Pin Number for PB08 */ 63 #define PIN_PB09 ( 41) /* Pin Number for PB09 */ 64 #define PIN_PB10 ( 42) /* Pin Number for PB10 */ 65 #define PIN_PB11 ( 43) /* Pin Number for PB11 */ 66 #define PIN_PB12 ( 44) /* Pin Number for PB12 */ 67 #define PIN_PB13 ( 45) /* Pin Number for PB13 */ 68 #define PIN_PB14 ( 46) /* Pin Number for PB14 */ 69 #define PIN_PB15 ( 47) /* Pin Number for PB15 */ 70 #define PIN_PB16 ( 48) /* Pin Number for PB16 */ 71 #define PIN_PB17 ( 49) /* Pin Number for PB17 */ 72 #define PIN_PB18 ( 50) /* Pin Number for PB18 */ 73 #define PIN_PB19 ( 51) /* Pin Number for PB19 */ 74 #define PIN_PB20 ( 52) /* Pin Number for PB20 */ 75 #define PIN_PB21 ( 53) /* Pin Number for PB21 */ 76 #define PIN_PB22 ( 54) /* Pin Number for PB22 */ 77 #define PIN_PB23 ( 55) /* Pin Number for PB23 */ 78 #define PIN_PB30 ( 62) /* Pin Number for PB30 */ 79 #define PIN_PB31 ( 63) /* Pin Number for PB31 */ 80 #define PIN_PC06 ( 70) /* Pin Number for PC06 */ 81 #define PIN_PC07 ( 71) /* Pin Number for PC07 */ 82 #define PIN_PC12 ( 76) /* Pin Number for PC12 */ 83 #define PIN_PC13 ( 77) /* Pin Number for PC13 */ 84 #define PIN_PC14 ( 78) /* Pin Number for PC14 */ 85 #define PIN_PC15 ( 79) /* Pin Number for PC15 */ 86 #define PIN_PC16 ( 80) /* Pin Number for PC16 */ 87 #define PIN_PC17 ( 81) /* Pin Number for PC17 */ 88 #define PIN_PC27 ( 91) /* Pin Number for PC27 */ 89 #define PIN_PC28 ( 92) /* Pin Number for PC28 */ 90 91 /* ========================== Peripheral I/O masks ========================== */ 92 #define PORT_PA00 (_UINT32_(1) << 0) /* PORT mask for PA00 */ 93 #define PORT_PA01 (_UINT32_(1) << 1) /* PORT mask for PA01 */ 94 #define PORT_PA02 (_UINT32_(1) << 2) /* PORT mask for PA02 */ 95 #define PORT_PA03 (_UINT32_(1) << 3) /* PORT mask for PA03 */ 96 #define PORT_PA04 (_UINT32_(1) << 4) /* PORT mask for PA04 */ 97 #define PORT_PA05 (_UINT32_(1) << 5) /* PORT mask for PA05 */ 98 #define PORT_PA06 (_UINT32_(1) << 6) /* PORT mask for PA06 */ 99 #define PORT_PA07 (_UINT32_(1) << 7) /* PORT mask for PA07 */ 100 #define PORT_PA08 (_UINT32_(1) << 8) /* PORT mask for PA08 */ 101 #define PORT_PA09 (_UINT32_(1) << 9) /* PORT mask for PA09 */ 102 #define PORT_PA10 (_UINT32_(1) << 10) /* PORT mask for PA10 */ 103 #define PORT_PA11 (_UINT32_(1) << 11) /* PORT mask for PA11 */ 104 #define PORT_PA12 (_UINT32_(1) << 12) /* PORT mask for PA12 */ 105 #define PORT_PA13 (_UINT32_(1) << 13) /* PORT mask for PA13 */ 106 #define PORT_PA14 (_UINT32_(1) << 14) /* PORT mask for PA14 */ 107 #define PORT_PA15 (_UINT32_(1) << 15) /* PORT mask for PA15 */ 108 #define PORT_PA16 (_UINT32_(1) << 16) /* PORT mask for PA16 */ 109 #define PORT_PA17 (_UINT32_(1) << 17) /* PORT mask for PA17 */ 110 #define PORT_PA18 (_UINT32_(1) << 18) /* PORT mask for PA18 */ 111 #define PORT_PA19 (_UINT32_(1) << 19) /* PORT mask for PA19 */ 112 #define PORT_PA20 (_UINT32_(1) << 20) /* PORT mask for PA20 */ 113 #define PORT_PA21 (_UINT32_(1) << 21) /* PORT mask for PA21 */ 114 #define PORT_PA22 (_UINT32_(1) << 22) /* PORT mask for PA22 */ 115 #define PORT_PA23 (_UINT32_(1) << 23) /* PORT mask for PA23 */ 116 #define PORT_PA24 (_UINT32_(1) << 24) /* PORT mask for PA24 */ 117 #define PORT_PA25 (_UINT32_(1) << 25) /* PORT mask for PA25 */ 118 #define PORT_PA27 (_UINT32_(1) << 27) /* PORT mask for PA27 */ 119 #define PORT_PA30 (_UINT32_(1) << 30) /* PORT mask for PA30 */ 120 #define PORT_PA31 (_UINT32_(1) << 31) /* PORT mask for PA31 */ 121 #define PORT_PB00 (_UINT32_(1) << 0) /* PORT mask for PB00 */ 122 #define PORT_PB01 (_UINT32_(1) << 1) /* PORT mask for PB01 */ 123 #define PORT_PB02 (_UINT32_(1) << 2) /* PORT mask for PB02 */ 124 #define PORT_PB03 (_UINT32_(1) << 3) /* PORT mask for PB03 */ 125 #define PORT_PB04 (_UINT32_(1) << 4) /* PORT mask for PB04 */ 126 #define PORT_PB05 (_UINT32_(1) << 5) /* PORT mask for PB05 */ 127 #define PORT_PB06 (_UINT32_(1) << 6) /* PORT mask for PB06 */ 128 #define PORT_PB07 (_UINT32_(1) << 7) /* PORT mask for PB07 */ 129 #define PORT_PB08 (_UINT32_(1) << 8) /* PORT mask for PB08 */ 130 #define PORT_PB09 (_UINT32_(1) << 9) /* PORT mask for PB09 */ 131 #define PORT_PB10 (_UINT32_(1) << 10) /* PORT mask for PB10 */ 132 #define PORT_PB11 (_UINT32_(1) << 11) /* PORT mask for PB11 */ 133 #define PORT_PB12 (_UINT32_(1) << 12) /* PORT mask for PB12 */ 134 #define PORT_PB13 (_UINT32_(1) << 13) /* PORT mask for PB13 */ 135 #define PORT_PB14 (_UINT32_(1) << 14) /* PORT mask for PB14 */ 136 #define PORT_PB15 (_UINT32_(1) << 15) /* PORT mask for PB15 */ 137 #define PORT_PB16 (_UINT32_(1) << 16) /* PORT mask for PB16 */ 138 #define PORT_PB17 (_UINT32_(1) << 17) /* PORT mask for PB17 */ 139 #define PORT_PB18 (_UINT32_(1) << 18) /* PORT mask for PB18 */ 140 #define PORT_PB19 (_UINT32_(1) << 19) /* PORT mask for PB19 */ 141 #define PORT_PB20 (_UINT32_(1) << 20) /* PORT mask for PB20 */ 142 #define PORT_PB21 (_UINT32_(1) << 21) /* PORT mask for PB21 */ 143 #define PORT_PB22 (_UINT32_(1) << 22) /* PORT mask for PB22 */ 144 #define PORT_PB23 (_UINT32_(1) << 23) /* PORT mask for PB23 */ 145 #define PORT_PB30 (_UINT32_(1) << 30) /* PORT mask for PB30 */ 146 #define PORT_PB31 (_UINT32_(1) << 31) /* PORT mask for PB31 */ 147 #define PORT_PC06 (_UINT32_(1) << 6) /* PORT mask for PC06 */ 148 #define PORT_PC07 (_UINT32_(1) << 7) /* PORT mask for PC07 */ 149 #define PORT_PC12 (_UINT32_(1) << 12) /* PORT mask for PC12 */ 150 #define PORT_PC13 (_UINT32_(1) << 13) /* PORT mask for PC13 */ 151 #define PORT_PC14 (_UINT32_(1) << 14) /* PORT mask for PC14 */ 152 #define PORT_PC15 (_UINT32_(1) << 15) /* PORT mask for PC15 */ 153 #define PORT_PC16 (_UINT32_(1) << 16) /* PORT mask for PC16 */ 154 #define PORT_PC17 (_UINT32_(1) << 17) /* PORT mask for PC17 */ 155 #define PORT_PC27 (_UINT32_(1) << 27) /* PORT mask for PC27 */ 156 #define PORT_PC28 (_UINT32_(1) << 28) /* PORT mask for PC28 */ 157 158 /* =================== PORT definition for AC peripheral ==================== */ 159 #define PIN_PA04B_AC_AIN0 _UINT32_(4) 160 #define MUX_PA04B_AC_AIN0 _UINT32_(1) 161 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 162 #define PORT_PA04B_AC_AIN0 (_UINT32_(1) << 4) 163 164 #define PIN_PA05B_AC_AIN1 _UINT32_(5) 165 #define MUX_PA05B_AC_AIN1 _UINT32_(1) 166 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 167 #define PORT_PA05B_AC_AIN1 (_UINT32_(1) << 5) 168 169 #define PIN_PA06B_AC_AIN2 _UINT32_(6) 170 #define MUX_PA06B_AC_AIN2 _UINT32_(1) 171 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 172 #define PORT_PA06B_AC_AIN2 (_UINT32_(1) << 6) 173 174 #define PIN_PA07B_AC_AIN3 _UINT32_(7) 175 #define MUX_PA07B_AC_AIN3 _UINT32_(1) 176 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 177 #define PORT_PA07B_AC_AIN3 (_UINT32_(1) << 7) 178 179 #define PIN_PA12M_AC_CMP0 _UINT32_(12) 180 #define MUX_PA12M_AC_CMP0 _UINT32_(12) 181 #define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) 182 #define PORT_PA12M_AC_CMP0 (_UINT32_(1) << 12) 183 184 #define PIN_PA18M_AC_CMP0 _UINT32_(18) 185 #define MUX_PA18M_AC_CMP0 _UINT32_(12) 186 #define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) 187 #define PORT_PA18M_AC_CMP0 (_UINT32_(1) << 18) 188 189 #define PIN_PA13M_AC_CMP1 _UINT32_(13) 190 #define MUX_PA13M_AC_CMP1 _UINT32_(12) 191 #define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) 192 #define PORT_PA13M_AC_CMP1 (_UINT32_(1) << 13) 193 194 #define PIN_PA19M_AC_CMP1 _UINT32_(19) 195 #define MUX_PA19M_AC_CMP1 _UINT32_(12) 196 #define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) 197 #define PORT_PA19M_AC_CMP1 (_UINT32_(1) << 19) 198 199 /* ================== PORT definition for ADC0 peripheral =================== */ 200 #define PIN_PA02B_ADC0_AIN0 _UINT32_(2) 201 #define MUX_PA02B_ADC0_AIN0 _UINT32_(1) 202 #define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) 203 #define PORT_PA02B_ADC0_AIN0 (_UINT32_(1) << 2) 204 205 #define PIN_PA03B_ADC0_AIN1 _UINT32_(3) 206 #define MUX_PA03B_ADC0_AIN1 _UINT32_(1) 207 #define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) 208 #define PORT_PA03B_ADC0_AIN1 (_UINT32_(1) << 3) 209 210 #define PIN_PB08B_ADC0_AIN2 _UINT32_(40) 211 #define MUX_PB08B_ADC0_AIN2 _UINT32_(1) 212 #define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) 213 #define PORT_PB08B_ADC0_AIN2 (_UINT32_(1) << 8) 214 215 #define PIN_PB09B_ADC0_AIN3 _UINT32_(41) 216 #define MUX_PB09B_ADC0_AIN3 _UINT32_(1) 217 #define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) 218 #define PORT_PB09B_ADC0_AIN3 (_UINT32_(1) << 9) 219 220 #define PIN_PA04B_ADC0_AIN4 _UINT32_(4) 221 #define MUX_PA04B_ADC0_AIN4 _UINT32_(1) 222 #define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) 223 #define PORT_PA04B_ADC0_AIN4 (_UINT32_(1) << 4) 224 225 #define PIN_PA05B_ADC0_AIN5 _UINT32_(5) 226 #define MUX_PA05B_ADC0_AIN5 _UINT32_(1) 227 #define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) 228 #define PORT_PA05B_ADC0_AIN5 (_UINT32_(1) << 5) 229 230 #define PIN_PA06B_ADC0_AIN6 _UINT32_(6) 231 #define MUX_PA06B_ADC0_AIN6 _UINT32_(1) 232 #define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) 233 #define PORT_PA06B_ADC0_AIN6 (_UINT32_(1) << 6) 234 235 #define PIN_PA07B_ADC0_AIN7 _UINT32_(7) 236 #define MUX_PA07B_ADC0_AIN7 _UINT32_(1) 237 #define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) 238 #define PORT_PA07B_ADC0_AIN7 (_UINT32_(1) << 7) 239 240 #define PIN_PA08B_ADC0_AIN8 _UINT32_(8) 241 #define MUX_PA08B_ADC0_AIN8 _UINT32_(1) 242 #define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) 243 #define PORT_PA08B_ADC0_AIN8 (_UINT32_(1) << 8) 244 245 #define PIN_PA09B_ADC0_AIN9 _UINT32_(9) 246 #define MUX_PA09B_ADC0_AIN9 _UINT32_(1) 247 #define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) 248 #define PORT_PA09B_ADC0_AIN9 (_UINT32_(1) << 9) 249 250 #define PIN_PA10B_ADC0_AIN10 _UINT32_(10) 251 #define MUX_PA10B_ADC0_AIN10 _UINT32_(1) 252 #define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) 253 #define PORT_PA10B_ADC0_AIN10 (_UINT32_(1) << 10) 254 255 #define PIN_PA11B_ADC0_AIN11 _UINT32_(11) 256 #define MUX_PA11B_ADC0_AIN11 _UINT32_(1) 257 #define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) 258 #define PORT_PA11B_ADC0_AIN11 (_UINT32_(1) << 11) 259 260 #define PIN_PB00B_ADC0_AIN12 _UINT32_(32) 261 #define MUX_PB00B_ADC0_AIN12 _UINT32_(1) 262 #define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) 263 #define PORT_PB00B_ADC0_AIN12 (_UINT32_(1) << 0) 264 265 #define PIN_PB01B_ADC0_AIN13 _UINT32_(33) 266 #define MUX_PB01B_ADC0_AIN13 _UINT32_(1) 267 #define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) 268 #define PORT_PB01B_ADC0_AIN13 (_UINT32_(1) << 1) 269 270 #define PIN_PB02B_ADC0_AIN14 _UINT32_(34) 271 #define MUX_PB02B_ADC0_AIN14 _UINT32_(1) 272 #define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) 273 #define PORT_PB02B_ADC0_AIN14 (_UINT32_(1) << 2) 274 275 #define PIN_PB03B_ADC0_AIN15 _UINT32_(35) 276 #define MUX_PB03B_ADC0_AIN15 _UINT32_(1) 277 #define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) 278 #define PORT_PB03B_ADC0_AIN15 (_UINT32_(1) << 3) 279 280 #define PIN_PA03B_ADC0_VREFA _UINT32_(3) 281 #define MUX_PA03B_ADC0_VREFA _UINT32_(1) 282 #define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) 283 #define PORT_PA03B_ADC0_VREFA (_UINT32_(1) << 3) 284 285 #define PIN_PA04B_ADC0_VREFB _UINT32_(4) 286 #define MUX_PA04B_ADC0_VREFB _UINT32_(1) 287 #define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) 288 #define PORT_PA04B_ADC0_VREFB (_UINT32_(1) << 4) 289 290 #define PIN_PA06B_ADC0_VREFC _UINT32_(6) 291 #define MUX_PA06B_ADC0_VREFC _UINT32_(1) 292 #define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) 293 #define PORT_PA06B_ADC0_VREFC (_UINT32_(1) << 6) 294 295 #define PIN_PA03B_ADC0_X0 _UINT32_(3) 296 #define MUX_PA03B_ADC0_X0 _UINT32_(1) 297 #define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) 298 #define PORT_PA03B_ADC0_X0 (_UINT32_(1) << 3) 299 300 #define PIN_PB08B_ADC0_X1 _UINT32_(40) 301 #define MUX_PB08B_ADC0_X1 _UINT32_(1) 302 #define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) 303 #define PORT_PB08B_ADC0_X1 (_UINT32_(1) << 8) 304 305 #define PIN_PB09B_ADC0_X2 _UINT32_(41) 306 #define MUX_PB09B_ADC0_X2 _UINT32_(1) 307 #define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) 308 #define PORT_PB09B_ADC0_X2 (_UINT32_(1) << 9) 309 310 #define PIN_PA04B_ADC0_X3 _UINT32_(4) 311 #define MUX_PA04B_ADC0_X3 _UINT32_(1) 312 #define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) 313 #define PORT_PA04B_ADC0_X3 (_UINT32_(1) << 4) 314 315 #define PIN_PA06B_ADC0_X4 _UINT32_(6) 316 #define MUX_PA06B_ADC0_X4 _UINT32_(1) 317 #define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) 318 #define PORT_PA06B_ADC0_X4 (_UINT32_(1) << 6) 319 320 #define PIN_PA07B_ADC0_X5 _UINT32_(7) 321 #define MUX_PA07B_ADC0_X5 _UINT32_(1) 322 #define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) 323 #define PORT_PA07B_ADC0_X5 (_UINT32_(1) << 7) 324 325 #define PIN_PA08B_ADC0_X6 _UINT32_(8) 326 #define MUX_PA08B_ADC0_X6 _UINT32_(1) 327 #define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) 328 #define PORT_PA08B_ADC0_X6 (_UINT32_(1) << 8) 329 330 #define PIN_PA09B_ADC0_X7 _UINT32_(9) 331 #define MUX_PA09B_ADC0_X7 _UINT32_(1) 332 #define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) 333 #define PORT_PA09B_ADC0_X7 (_UINT32_(1) << 9) 334 335 #define PIN_PA10B_ADC0_X8 _UINT32_(10) 336 #define MUX_PA10B_ADC0_X8 _UINT32_(1) 337 #define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) 338 #define PORT_PA10B_ADC0_X8 (_UINT32_(1) << 10) 339 340 #define PIN_PA11B_ADC0_X9 _UINT32_(11) 341 #define MUX_PA11B_ADC0_X9 _UINT32_(1) 342 #define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) 343 #define PORT_PA11B_ADC0_X9 (_UINT32_(1) << 11) 344 345 #define PIN_PA16B_ADC0_X10 _UINT32_(16) 346 #define MUX_PA16B_ADC0_X10 _UINT32_(1) 347 #define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) 348 #define PORT_PA16B_ADC0_X10 (_UINT32_(1) << 16) 349 350 #define PIN_PA17B_ADC0_X11 _UINT32_(17) 351 #define MUX_PA17B_ADC0_X11 _UINT32_(1) 352 #define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) 353 #define PORT_PA17B_ADC0_X11 (_UINT32_(1) << 17) 354 355 #define PIN_PA18B_ADC0_X12 _UINT32_(18) 356 #define MUX_PA18B_ADC0_X12 _UINT32_(1) 357 #define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) 358 #define PORT_PA18B_ADC0_X12 (_UINT32_(1) << 18) 359 360 #define PIN_PA19B_ADC0_X13 _UINT32_(19) 361 #define MUX_PA19B_ADC0_X13 _UINT32_(1) 362 #define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) 363 #define PORT_PA19B_ADC0_X13 (_UINT32_(1) << 19) 364 365 #define PIN_PA20B_ADC0_X14 _UINT32_(20) 366 #define MUX_PA20B_ADC0_X14 _UINT32_(1) 367 #define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) 368 #define PORT_PA20B_ADC0_X14 (_UINT32_(1) << 20) 369 370 #define PIN_PA21B_ADC0_X15 _UINT32_(21) 371 #define MUX_PA21B_ADC0_X15 _UINT32_(1) 372 #define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) 373 #define PORT_PA21B_ADC0_X15 (_UINT32_(1) << 21) 374 375 #define PIN_PA22B_ADC0_X16 _UINT32_(22) 376 #define MUX_PA22B_ADC0_X16 _UINT32_(1) 377 #define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) 378 #define PORT_PA22B_ADC0_X16 (_UINT32_(1) << 22) 379 380 #define PIN_PA23B_ADC0_X17 _UINT32_(23) 381 #define MUX_PA23B_ADC0_X17 _UINT32_(1) 382 #define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) 383 #define PORT_PA23B_ADC0_X17 (_UINT32_(1) << 23) 384 385 #define PIN_PA27B_ADC0_X18 _UINT32_(27) 386 #define MUX_PA27B_ADC0_X18 _UINT32_(1) 387 #define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) 388 #define PORT_PA27B_ADC0_X18 (_UINT32_(1) << 27) 389 390 #define PIN_PA30B_ADC0_X19 _UINT32_(30) 391 #define MUX_PA30B_ADC0_X19 _UINT32_(1) 392 #define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) 393 #define PORT_PA30B_ADC0_X19 (_UINT32_(1) << 30) 394 395 #define PIN_PB02B_ADC0_X20 _UINT32_(34) 396 #define MUX_PB02B_ADC0_X20 _UINT32_(1) 397 #define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) 398 #define PORT_PB02B_ADC0_X20 (_UINT32_(1) << 2) 399 400 #define PIN_PB03B_ADC0_X21 _UINT32_(35) 401 #define MUX_PB03B_ADC0_X21 _UINT32_(1) 402 #define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) 403 #define PORT_PB03B_ADC0_X21 (_UINT32_(1) << 3) 404 405 #define PIN_PB04B_ADC0_X22 _UINT32_(36) 406 #define MUX_PB04B_ADC0_X22 _UINT32_(1) 407 #define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) 408 #define PORT_PB04B_ADC0_X22 (_UINT32_(1) << 4) 409 410 #define PIN_PB05B_ADC0_X23 _UINT32_(37) 411 #define MUX_PB05B_ADC0_X23 _UINT32_(1) 412 #define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) 413 #define PORT_PB05B_ADC0_X23 (_UINT32_(1) << 5) 414 415 #define PIN_PB06B_ADC0_X24 _UINT32_(38) 416 #define MUX_PB06B_ADC0_X24 _UINT32_(1) 417 #define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) 418 #define PORT_PB06B_ADC0_X24 (_UINT32_(1) << 6) 419 420 #define PIN_PB07B_ADC0_X25 _UINT32_(39) 421 #define MUX_PB07B_ADC0_X25 _UINT32_(1) 422 #define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) 423 #define PORT_PB07B_ADC0_X25 (_UINT32_(1) << 7) 424 425 #define PIN_PB12B_ADC0_X26 _UINT32_(44) 426 #define MUX_PB12B_ADC0_X26 _UINT32_(1) 427 #define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) 428 #define PORT_PB12B_ADC0_X26 (_UINT32_(1) << 12) 429 430 #define PIN_PB13B_ADC0_X27 _UINT32_(45) 431 #define MUX_PB13B_ADC0_X27 _UINT32_(1) 432 #define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) 433 #define PORT_PB13B_ADC0_X27 (_UINT32_(1) << 13) 434 435 #define PIN_PB14B_ADC0_X28 _UINT32_(46) 436 #define MUX_PB14B_ADC0_X28 _UINT32_(1) 437 #define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) 438 #define PORT_PB14B_ADC0_X28 (_UINT32_(1) << 14) 439 440 #define PIN_PB15B_ADC0_X29 _UINT32_(47) 441 #define MUX_PB15B_ADC0_X29 _UINT32_(1) 442 #define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) 443 #define PORT_PB15B_ADC0_X29 (_UINT32_(1) << 15) 444 445 #define PIN_PB00B_ADC0_X30 _UINT32_(32) 446 #define MUX_PB00B_ADC0_X30 _UINT32_(1) 447 #define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) 448 #define PORT_PB00B_ADC0_X30 (_UINT32_(1) << 0) 449 450 #define PIN_PB01B_ADC0_X31 _UINT32_(33) 451 #define MUX_PB01B_ADC0_X31 _UINT32_(1) 452 #define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) 453 #define PORT_PB01B_ADC0_X31 (_UINT32_(1) << 1) 454 455 #define PIN_PA03B_ADC0_Y0 _UINT32_(3) 456 #define MUX_PA03B_ADC0_Y0 _UINT32_(1) 457 #define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) 458 #define PORT_PA03B_ADC0_Y0 (_UINT32_(1) << 3) 459 460 #define PIN_PB08B_ADC0_Y1 _UINT32_(40) 461 #define MUX_PB08B_ADC0_Y1 _UINT32_(1) 462 #define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) 463 #define PORT_PB08B_ADC0_Y1 (_UINT32_(1) << 8) 464 465 #define PIN_PB09B_ADC0_Y2 _UINT32_(41) 466 #define MUX_PB09B_ADC0_Y2 _UINT32_(1) 467 #define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) 468 #define PORT_PB09B_ADC0_Y2 (_UINT32_(1) << 9) 469 470 #define PIN_PA04B_ADC0_Y3 _UINT32_(4) 471 #define MUX_PA04B_ADC0_Y3 _UINT32_(1) 472 #define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) 473 #define PORT_PA04B_ADC0_Y3 (_UINT32_(1) << 4) 474 475 #define PIN_PA06B_ADC0_Y4 _UINT32_(6) 476 #define MUX_PA06B_ADC0_Y4 _UINT32_(1) 477 #define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) 478 #define PORT_PA06B_ADC0_Y4 (_UINT32_(1) << 6) 479 480 #define PIN_PA07B_ADC0_Y5 _UINT32_(7) 481 #define MUX_PA07B_ADC0_Y5 _UINT32_(1) 482 #define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) 483 #define PORT_PA07B_ADC0_Y5 (_UINT32_(1) << 7) 484 485 #define PIN_PA08B_ADC0_Y6 _UINT32_(8) 486 #define MUX_PA08B_ADC0_Y6 _UINT32_(1) 487 #define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) 488 #define PORT_PA08B_ADC0_Y6 (_UINT32_(1) << 8) 489 490 #define PIN_PA09B_ADC0_Y7 _UINT32_(9) 491 #define MUX_PA09B_ADC0_Y7 _UINT32_(1) 492 #define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) 493 #define PORT_PA09B_ADC0_Y7 (_UINT32_(1) << 9) 494 495 #define PIN_PA10B_ADC0_Y8 _UINT32_(10) 496 #define MUX_PA10B_ADC0_Y8 _UINT32_(1) 497 #define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) 498 #define PORT_PA10B_ADC0_Y8 (_UINT32_(1) << 10) 499 500 #define PIN_PA11B_ADC0_Y9 _UINT32_(11) 501 #define MUX_PA11B_ADC0_Y9 _UINT32_(1) 502 #define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) 503 #define PORT_PA11B_ADC0_Y9 (_UINT32_(1) << 11) 504 505 #define PIN_PA16B_ADC0_Y10 _UINT32_(16) 506 #define MUX_PA16B_ADC0_Y10 _UINT32_(1) 507 #define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) 508 #define PORT_PA16B_ADC0_Y10 (_UINT32_(1) << 16) 509 510 #define PIN_PA17B_ADC0_Y11 _UINT32_(17) 511 #define MUX_PA17B_ADC0_Y11 _UINT32_(1) 512 #define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) 513 #define PORT_PA17B_ADC0_Y11 (_UINT32_(1) << 17) 514 515 #define PIN_PA18B_ADC0_Y12 _UINT32_(18) 516 #define MUX_PA18B_ADC0_Y12 _UINT32_(1) 517 #define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) 518 #define PORT_PA18B_ADC0_Y12 (_UINT32_(1) << 18) 519 520 #define PIN_PA19B_ADC0_Y13 _UINT32_(19) 521 #define MUX_PA19B_ADC0_Y13 _UINT32_(1) 522 #define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) 523 #define PORT_PA19B_ADC0_Y13 (_UINT32_(1) << 19) 524 525 #define PIN_PA20B_ADC0_Y14 _UINT32_(20) 526 #define MUX_PA20B_ADC0_Y14 _UINT32_(1) 527 #define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) 528 #define PORT_PA20B_ADC0_Y14 (_UINT32_(1) << 20) 529 530 #define PIN_PA21B_ADC0_Y15 _UINT32_(21) 531 #define MUX_PA21B_ADC0_Y15 _UINT32_(1) 532 #define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) 533 #define PORT_PA21B_ADC0_Y15 (_UINT32_(1) << 21) 534 535 #define PIN_PA22B_ADC0_Y16 _UINT32_(22) 536 #define MUX_PA22B_ADC0_Y16 _UINT32_(1) 537 #define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) 538 #define PORT_PA22B_ADC0_Y16 (_UINT32_(1) << 22) 539 540 #define PIN_PA23B_ADC0_Y17 _UINT32_(23) 541 #define MUX_PA23B_ADC0_Y17 _UINT32_(1) 542 #define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) 543 #define PORT_PA23B_ADC0_Y17 (_UINT32_(1) << 23) 544 545 #define PIN_PA27B_ADC0_Y18 _UINT32_(27) 546 #define MUX_PA27B_ADC0_Y18 _UINT32_(1) 547 #define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) 548 #define PORT_PA27B_ADC0_Y18 (_UINT32_(1) << 27) 549 550 #define PIN_PA30B_ADC0_Y19 _UINT32_(30) 551 #define MUX_PA30B_ADC0_Y19 _UINT32_(1) 552 #define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) 553 #define PORT_PA30B_ADC0_Y19 (_UINT32_(1) << 30) 554 555 #define PIN_PB02B_ADC0_Y20 _UINT32_(34) 556 #define MUX_PB02B_ADC0_Y20 _UINT32_(1) 557 #define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) 558 #define PORT_PB02B_ADC0_Y20 (_UINT32_(1) << 2) 559 560 #define PIN_PB03B_ADC0_Y21 _UINT32_(35) 561 #define MUX_PB03B_ADC0_Y21 _UINT32_(1) 562 #define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) 563 #define PORT_PB03B_ADC0_Y21 (_UINT32_(1) << 3) 564 565 #define PIN_PB04B_ADC0_Y22 _UINT32_(36) 566 #define MUX_PB04B_ADC0_Y22 _UINT32_(1) 567 #define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) 568 #define PORT_PB04B_ADC0_Y22 (_UINT32_(1) << 4) 569 570 #define PIN_PB05B_ADC0_Y23 _UINT32_(37) 571 #define MUX_PB05B_ADC0_Y23 _UINT32_(1) 572 #define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) 573 #define PORT_PB05B_ADC0_Y23 (_UINT32_(1) << 5) 574 575 #define PIN_PB06B_ADC0_Y24 _UINT32_(38) 576 #define MUX_PB06B_ADC0_Y24 _UINT32_(1) 577 #define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) 578 #define PORT_PB06B_ADC0_Y24 (_UINT32_(1) << 6) 579 580 #define PIN_PB07B_ADC0_Y25 _UINT32_(39) 581 #define MUX_PB07B_ADC0_Y25 _UINT32_(1) 582 #define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) 583 #define PORT_PB07B_ADC0_Y25 (_UINT32_(1) << 7) 584 585 #define PIN_PB12B_ADC0_Y26 _UINT32_(44) 586 #define MUX_PB12B_ADC0_Y26 _UINT32_(1) 587 #define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) 588 #define PORT_PB12B_ADC0_Y26 (_UINT32_(1) << 12) 589 590 #define PIN_PB13B_ADC0_Y27 _UINT32_(45) 591 #define MUX_PB13B_ADC0_Y27 _UINT32_(1) 592 #define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) 593 #define PORT_PB13B_ADC0_Y27 (_UINT32_(1) << 13) 594 595 #define PIN_PB14B_ADC0_Y28 _UINT32_(46) 596 #define MUX_PB14B_ADC0_Y28 _UINT32_(1) 597 #define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) 598 #define PORT_PB14B_ADC0_Y28 (_UINT32_(1) << 14) 599 600 #define PIN_PB15B_ADC0_Y29 _UINT32_(47) 601 #define MUX_PB15B_ADC0_Y29 _UINT32_(1) 602 #define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) 603 #define PORT_PB15B_ADC0_Y29 (_UINT32_(1) << 15) 604 605 #define PIN_PB00B_ADC0_Y30 _UINT32_(32) 606 #define MUX_PB00B_ADC0_Y30 _UINT32_(1) 607 #define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) 608 #define PORT_PB00B_ADC0_Y30 (_UINT32_(1) << 0) 609 610 #define PIN_PB01B_ADC0_Y31 _UINT32_(33) 611 #define MUX_PB01B_ADC0_Y31 _UINT32_(1) 612 #define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) 613 #define PORT_PB01B_ADC0_Y31 (_UINT32_(1) << 1) 614 615 /* ================== PORT definition for ADC1 peripheral =================== */ 616 #define PIN_PB08B_ADC1_AIN0 _UINT32_(40) 617 #define MUX_PB08B_ADC1_AIN0 _UINT32_(1) 618 #define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) 619 #define PORT_PB08B_ADC1_AIN0 (_UINT32_(1) << 8) 620 621 #define PIN_PB09B_ADC1_AIN1 _UINT32_(41) 622 #define MUX_PB09B_ADC1_AIN1 _UINT32_(1) 623 #define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) 624 #define PORT_PB09B_ADC1_AIN1 (_UINT32_(1) << 9) 625 626 #define PIN_PA08B_ADC1_AIN2 _UINT32_(8) 627 #define MUX_PA08B_ADC1_AIN2 _UINT32_(1) 628 #define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) 629 #define PORT_PA08B_ADC1_AIN2 (_UINT32_(1) << 8) 630 631 #define PIN_PA09B_ADC1_AIN3 _UINT32_(9) 632 #define MUX_PA09B_ADC1_AIN3 _UINT32_(1) 633 #define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) 634 #define PORT_PA09B_ADC1_AIN3 (_UINT32_(1) << 9) 635 636 #define PIN_PB04B_ADC1_AIN6 _UINT32_(36) 637 #define MUX_PB04B_ADC1_AIN6 _UINT32_(1) 638 #define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) 639 #define PORT_PB04B_ADC1_AIN6 (_UINT32_(1) << 4) 640 641 #define PIN_PB05B_ADC1_AIN7 _UINT32_(37) 642 #define MUX_PB05B_ADC1_AIN7 _UINT32_(1) 643 #define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) 644 #define PORT_PB05B_ADC1_AIN7 (_UINT32_(1) << 5) 645 646 #define PIN_PB06B_ADC1_AIN8 _UINT32_(38) 647 #define MUX_PB06B_ADC1_AIN8 _UINT32_(1) 648 #define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) 649 #define PORT_PB06B_ADC1_AIN8 (_UINT32_(1) << 6) 650 651 #define PIN_PB07B_ADC1_AIN9 _UINT32_(39) 652 #define MUX_PB07B_ADC1_AIN9 _UINT32_(1) 653 #define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) 654 #define PORT_PB07B_ADC1_AIN9 (_UINT32_(1) << 7) 655 656 /* ================== PORT definition for CAN0 peripheral =================== */ 657 #define PIN_PA23I_CAN0_RX _UINT32_(23) 658 #define MUX_PA23I_CAN0_RX _UINT32_(8) 659 #define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) 660 #define PORT_PA23I_CAN0_RX (_UINT32_(1) << 23) 661 662 #define PIN_PA25I_CAN0_RX _UINT32_(25) 663 #define MUX_PA25I_CAN0_RX _UINT32_(8) 664 #define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) 665 #define PORT_PA25I_CAN0_RX (_UINT32_(1) << 25) 666 667 #define PIN_PA22I_CAN0_TX _UINT32_(22) 668 #define MUX_PA22I_CAN0_TX _UINT32_(8) 669 #define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) 670 #define PORT_PA22I_CAN0_TX (_UINT32_(1) << 22) 671 672 #define PIN_PA24I_CAN0_TX _UINT32_(24) 673 #define MUX_PA24I_CAN0_TX _UINT32_(8) 674 #define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) 675 #define PORT_PA24I_CAN0_TX (_UINT32_(1) << 24) 676 677 /* ================== PORT definition for CAN1 peripheral =================== */ 678 #define PIN_PB13H_CAN1_RX _UINT32_(45) 679 #define MUX_PB13H_CAN1_RX _UINT32_(7) 680 #define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) 681 #define PORT_PB13H_CAN1_RX (_UINT32_(1) << 13) 682 683 #define PIN_PB15H_CAN1_RX _UINT32_(47) 684 #define MUX_PB15H_CAN1_RX _UINT32_(7) 685 #define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) 686 #define PORT_PB15H_CAN1_RX (_UINT32_(1) << 15) 687 688 #define PIN_PB12H_CAN1_TX _UINT32_(44) 689 #define MUX_PB12H_CAN1_TX _UINT32_(7) 690 #define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) 691 #define PORT_PB12H_CAN1_TX (_UINT32_(1) << 12) 692 693 #define PIN_PB14H_CAN1_TX _UINT32_(46) 694 #define MUX_PB14H_CAN1_TX _UINT32_(7) 695 #define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) 696 #define PORT_PB14H_CAN1_TX (_UINT32_(1) << 14) 697 698 /* =================== PORT definition for CCL peripheral =================== */ 699 #define PIN_PA04N_CCL_IN0 _UINT32_(4) 700 #define MUX_PA04N_CCL_IN0 _UINT32_(13) 701 #define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) 702 #define PORT_PA04N_CCL_IN0 (_UINT32_(1) << 4) 703 704 #define PIN_PA16N_CCL_IN0 _UINT32_(16) 705 #define MUX_PA16N_CCL_IN0 _UINT32_(13) 706 #define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) 707 #define PORT_PA16N_CCL_IN0 (_UINT32_(1) << 16) 708 709 #define PIN_PB22N_CCL_IN0 _UINT32_(54) 710 #define MUX_PB22N_CCL_IN0 _UINT32_(13) 711 #define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) 712 #define PORT_PB22N_CCL_IN0 (_UINT32_(1) << 22) 713 714 #define PIN_PA05N_CCL_IN1 _UINT32_(5) 715 #define MUX_PA05N_CCL_IN1 _UINT32_(13) 716 #define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) 717 #define PORT_PA05N_CCL_IN1 (_UINT32_(1) << 5) 718 719 #define PIN_PA17N_CCL_IN1 _UINT32_(17) 720 #define MUX_PA17N_CCL_IN1 _UINT32_(13) 721 #define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) 722 #define PORT_PA17N_CCL_IN1 (_UINT32_(1) << 17) 723 724 #define PIN_PB00N_CCL_IN1 _UINT32_(32) 725 #define MUX_PB00N_CCL_IN1 _UINT32_(13) 726 #define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) 727 #define PORT_PB00N_CCL_IN1 (_UINT32_(1) << 0) 728 729 #define PIN_PA06N_CCL_IN2 _UINT32_(6) 730 #define MUX_PA06N_CCL_IN2 _UINT32_(13) 731 #define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) 732 #define PORT_PA06N_CCL_IN2 (_UINT32_(1) << 6) 733 734 #define PIN_PA18N_CCL_IN2 _UINT32_(18) 735 #define MUX_PA18N_CCL_IN2 _UINT32_(13) 736 #define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) 737 #define PORT_PA18N_CCL_IN2 (_UINT32_(1) << 18) 738 739 #define PIN_PB01N_CCL_IN2 _UINT32_(33) 740 #define MUX_PB01N_CCL_IN2 _UINT32_(13) 741 #define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) 742 #define PORT_PB01N_CCL_IN2 (_UINT32_(1) << 1) 743 744 #define PIN_PA08N_CCL_IN3 _UINT32_(8) 745 #define MUX_PA08N_CCL_IN3 _UINT32_(13) 746 #define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) 747 #define PORT_PA08N_CCL_IN3 (_UINT32_(1) << 8) 748 749 #define PIN_PA30N_CCL_IN3 _UINT32_(30) 750 #define MUX_PA30N_CCL_IN3 _UINT32_(13) 751 #define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) 752 #define PORT_PA30N_CCL_IN3 (_UINT32_(1) << 30) 753 754 #define PIN_PA09N_CCL_IN4 _UINT32_(9) 755 #define MUX_PA09N_CCL_IN4 _UINT32_(13) 756 #define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) 757 #define PORT_PA09N_CCL_IN4 (_UINT32_(1) << 9) 758 759 #define PIN_PC27N_CCL_IN4 _UINT32_(91) 760 #define MUX_PC27N_CCL_IN4 _UINT32_(13) 761 #define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) 762 #define PORT_PC27N_CCL_IN4 (_UINT32_(1) << 27) 763 764 #define PIN_PA10N_CCL_IN5 _UINT32_(10) 765 #define MUX_PA10N_CCL_IN5 _UINT32_(13) 766 #define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) 767 #define PORT_PA10N_CCL_IN5 (_UINT32_(1) << 10) 768 769 #define PIN_PC28N_CCL_IN5 _UINT32_(92) 770 #define MUX_PC28N_CCL_IN5 _UINT32_(13) 771 #define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) 772 #define PORT_PC28N_CCL_IN5 (_UINT32_(1) << 28) 773 774 #define PIN_PA22N_CCL_IN6 _UINT32_(22) 775 #define MUX_PA22N_CCL_IN6 _UINT32_(13) 776 #define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) 777 #define PORT_PA22N_CCL_IN6 (_UINT32_(1) << 22) 778 779 #define PIN_PB06N_CCL_IN6 _UINT32_(38) 780 #define MUX_PB06N_CCL_IN6 _UINT32_(13) 781 #define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) 782 #define PORT_PB06N_CCL_IN6 (_UINT32_(1) << 6) 783 784 #define PIN_PA23N_CCL_IN7 _UINT32_(23) 785 #define MUX_PA23N_CCL_IN7 _UINT32_(13) 786 #define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) 787 #define PORT_PA23N_CCL_IN7 (_UINT32_(1) << 23) 788 789 #define PIN_PB07N_CCL_IN7 _UINT32_(39) 790 #define MUX_PB07N_CCL_IN7 _UINT32_(13) 791 #define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) 792 #define PORT_PB07N_CCL_IN7 (_UINT32_(1) << 7) 793 794 #define PIN_PA24N_CCL_IN8 _UINT32_(24) 795 #define MUX_PA24N_CCL_IN8 _UINT32_(13) 796 #define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) 797 #define PORT_PA24N_CCL_IN8 (_UINT32_(1) << 24) 798 799 #define PIN_PB08N_CCL_IN8 _UINT32_(40) 800 #define MUX_PB08N_CCL_IN8 _UINT32_(13) 801 #define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) 802 #define PORT_PB08N_CCL_IN8 (_UINT32_(1) << 8) 803 804 #define PIN_PB14N_CCL_IN9 _UINT32_(46) 805 #define MUX_PB14N_CCL_IN9 _UINT32_(13) 806 #define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) 807 #define PORT_PB14N_CCL_IN9 (_UINT32_(1) << 14) 808 809 #define PIN_PB15N_CCL_IN10 _UINT32_(47) 810 #define MUX_PB15N_CCL_IN10 _UINT32_(13) 811 #define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) 812 #define PORT_PB15N_CCL_IN10 (_UINT32_(1) << 15) 813 814 #define PIN_PB10N_CCL_IN11 _UINT32_(42) 815 #define MUX_PB10N_CCL_IN11 _UINT32_(13) 816 #define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) 817 #define PORT_PB10N_CCL_IN11 (_UINT32_(1) << 10) 818 819 #define PIN_PB16N_CCL_IN11 _UINT32_(48) 820 #define MUX_PB16N_CCL_IN11 _UINT32_(13) 821 #define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) 822 #define PORT_PB16N_CCL_IN11 (_UINT32_(1) << 16) 823 824 #define PIN_PA07N_CCL_OUT0 _UINT32_(7) 825 #define MUX_PA07N_CCL_OUT0 _UINT32_(13) 826 #define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) 827 #define PORT_PA07N_CCL_OUT0 (_UINT32_(1) << 7) 828 829 #define PIN_PA19N_CCL_OUT0 _UINT32_(19) 830 #define MUX_PA19N_CCL_OUT0 _UINT32_(13) 831 #define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) 832 #define PORT_PA19N_CCL_OUT0 (_UINT32_(1) << 19) 833 834 #define PIN_PB02N_CCL_OUT0 _UINT32_(34) 835 #define MUX_PB02N_CCL_OUT0 _UINT32_(13) 836 #define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) 837 #define PORT_PB02N_CCL_OUT0 (_UINT32_(1) << 2) 838 839 #define PIN_PB23N_CCL_OUT0 _UINT32_(55) 840 #define MUX_PB23N_CCL_OUT0 _UINT32_(13) 841 #define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) 842 #define PORT_PB23N_CCL_OUT0 (_UINT32_(1) << 23) 843 844 #define PIN_PA11N_CCL_OUT1 _UINT32_(11) 845 #define MUX_PA11N_CCL_OUT1 _UINT32_(13) 846 #define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) 847 #define PORT_PA11N_CCL_OUT1 (_UINT32_(1) << 11) 848 849 #define PIN_PA31N_CCL_OUT1 _UINT32_(31) 850 #define MUX_PA31N_CCL_OUT1 _UINT32_(13) 851 #define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) 852 #define PORT_PA31N_CCL_OUT1 (_UINT32_(1) << 31) 853 854 #define PIN_PB11N_CCL_OUT1 _UINT32_(43) 855 #define MUX_PB11N_CCL_OUT1 _UINT32_(13) 856 #define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) 857 #define PORT_PB11N_CCL_OUT1 (_UINT32_(1) << 11) 858 859 #define PIN_PA25N_CCL_OUT2 _UINT32_(25) 860 #define MUX_PA25N_CCL_OUT2 _UINT32_(13) 861 #define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) 862 #define PORT_PA25N_CCL_OUT2 (_UINT32_(1) << 25) 863 864 #define PIN_PB09N_CCL_OUT2 _UINT32_(41) 865 #define MUX_PB09N_CCL_OUT2 _UINT32_(13) 866 #define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) 867 #define PORT_PB09N_CCL_OUT2 (_UINT32_(1) << 9) 868 869 #define PIN_PB17N_CCL_OUT3 _UINT32_(49) 870 #define MUX_PB17N_CCL_OUT3 _UINT32_(13) 871 #define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) 872 #define PORT_PB17N_CCL_OUT3 (_UINT32_(1) << 17) 873 874 /* =================== PORT definition for DAC peripheral =================== */ 875 #define PIN_PA02B_DAC_VOUT0 _UINT32_(2) 876 #define MUX_PA02B_DAC_VOUT0 _UINT32_(1) 877 #define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) 878 #define PORT_PA02B_DAC_VOUT0 (_UINT32_(1) << 2) 879 880 #define PIN_PA05B_DAC_VOUT1 _UINT32_(5) 881 #define MUX_PA05B_DAC_VOUT1 _UINT32_(1) 882 #define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) 883 #define PORT_PA05B_DAC_VOUT1 (_UINT32_(1) << 5) 884 885 /* =================== PORT definition for EIC peripheral =================== */ 886 #define PIN_PA00A_EIC_EXTINT0 _UINT32_(0) 887 #define MUX_PA00A_EIC_EXTINT0 _UINT32_(0) 888 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 889 #define PORT_PA00A_EIC_EXTINT0 (_UINT32_(1) << 0) 890 #define PIN_PA00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA00 External Interrupt Line */ 891 892 #define PIN_PA16A_EIC_EXTINT0 _UINT32_(16) 893 #define MUX_PA16A_EIC_EXTINT0 _UINT32_(0) 894 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 895 #define PORT_PA16A_EIC_EXTINT0 (_UINT32_(1) << 16) 896 #define PIN_PA16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PA16 External Interrupt Line */ 897 898 #define PIN_PB00A_EIC_EXTINT0 _UINT32_(32) 899 #define MUX_PB00A_EIC_EXTINT0 _UINT32_(0) 900 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) 901 #define PORT_PB00A_EIC_EXTINT0 (_UINT32_(1) << 0) 902 #define PIN_PB00A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB00 External Interrupt Line */ 903 904 #define PIN_PB16A_EIC_EXTINT0 _UINT32_(48) 905 #define MUX_PB16A_EIC_EXTINT0 _UINT32_(0) 906 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) 907 #define PORT_PB16A_EIC_EXTINT0 (_UINT32_(1) << 16) 908 #define PIN_PB16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PB16 External Interrupt Line */ 909 910 #define PIN_PC16A_EIC_EXTINT0 _UINT32_(80) 911 #define MUX_PC16A_EIC_EXTINT0 _UINT32_(0) 912 #define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) 913 #define PORT_PC16A_EIC_EXTINT0 (_UINT32_(1) << 16) 914 #define PIN_PC16A_EIC_EXTINT_NUM _UINT32_(0) /* EIC signal: PIN_PC16 External Interrupt Line */ 915 916 #define PIN_PA01A_EIC_EXTINT1 _UINT32_(1) 917 #define MUX_PA01A_EIC_EXTINT1 _UINT32_(0) 918 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 919 #define PORT_PA01A_EIC_EXTINT1 (_UINT32_(1) << 1) 920 #define PIN_PA01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA01 External Interrupt Line */ 921 922 #define PIN_PA17A_EIC_EXTINT1 _UINT32_(17) 923 #define MUX_PA17A_EIC_EXTINT1 _UINT32_(0) 924 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 925 #define PORT_PA17A_EIC_EXTINT1 (_UINT32_(1) << 17) 926 #define PIN_PA17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PA17 External Interrupt Line */ 927 928 #define PIN_PB01A_EIC_EXTINT1 _UINT32_(33) 929 #define MUX_PB01A_EIC_EXTINT1 _UINT32_(0) 930 #define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) 931 #define PORT_PB01A_EIC_EXTINT1 (_UINT32_(1) << 1) 932 #define PIN_PB01A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB01 External Interrupt Line */ 933 934 #define PIN_PB17A_EIC_EXTINT1 _UINT32_(49) 935 #define MUX_PB17A_EIC_EXTINT1 _UINT32_(0) 936 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) 937 #define PORT_PB17A_EIC_EXTINT1 (_UINT32_(1) << 17) 938 #define PIN_PB17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PB17 External Interrupt Line */ 939 940 #define PIN_PC17A_EIC_EXTINT1 _UINT32_(81) 941 #define MUX_PC17A_EIC_EXTINT1 _UINT32_(0) 942 #define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) 943 #define PORT_PC17A_EIC_EXTINT1 (_UINT32_(1) << 17) 944 #define PIN_PC17A_EIC_EXTINT_NUM _UINT32_(1) /* EIC signal: PIN_PC17 External Interrupt Line */ 945 946 #define PIN_PA02A_EIC_EXTINT2 _UINT32_(2) 947 #define MUX_PA02A_EIC_EXTINT2 _UINT32_(0) 948 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 949 #define PORT_PA02A_EIC_EXTINT2 (_UINT32_(1) << 2) 950 #define PIN_PA02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA02 External Interrupt Line */ 951 952 #define PIN_PA18A_EIC_EXTINT2 _UINT32_(18) 953 #define MUX_PA18A_EIC_EXTINT2 _UINT32_(0) 954 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 955 #define PORT_PA18A_EIC_EXTINT2 (_UINT32_(1) << 18) 956 #define PIN_PA18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PA18 External Interrupt Line */ 957 958 #define PIN_PB02A_EIC_EXTINT2 _UINT32_(34) 959 #define MUX_PB02A_EIC_EXTINT2 _UINT32_(0) 960 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 961 #define PORT_PB02A_EIC_EXTINT2 (_UINT32_(1) << 2) 962 #define PIN_PB02A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB02 External Interrupt Line */ 963 964 #define PIN_PB18A_EIC_EXTINT2 _UINT32_(50) 965 #define MUX_PB18A_EIC_EXTINT2 _UINT32_(0) 966 #define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) 967 #define PORT_PB18A_EIC_EXTINT2 (_UINT32_(1) << 18) 968 #define PIN_PB18A_EIC_EXTINT_NUM _UINT32_(2) /* EIC signal: PIN_PB18 External Interrupt Line */ 969 970 #define PIN_PA03A_EIC_EXTINT3 _UINT32_(3) 971 #define MUX_PA03A_EIC_EXTINT3 _UINT32_(0) 972 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 973 #define PORT_PA03A_EIC_EXTINT3 (_UINT32_(1) << 3) 974 #define PIN_PA03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA03 External Interrupt Line */ 975 976 #define PIN_PA19A_EIC_EXTINT3 _UINT32_(19) 977 #define MUX_PA19A_EIC_EXTINT3 _UINT32_(0) 978 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 979 #define PORT_PA19A_EIC_EXTINT3 (_UINT32_(1) << 19) 980 #define PIN_PA19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PA19 External Interrupt Line */ 981 982 #define PIN_PB03A_EIC_EXTINT3 _UINT32_(35) 983 #define MUX_PB03A_EIC_EXTINT3 _UINT32_(0) 984 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 985 #define PORT_PB03A_EIC_EXTINT3 (_UINT32_(1) << 3) 986 #define PIN_PB03A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB03 External Interrupt Line */ 987 988 #define PIN_PB19A_EIC_EXTINT3 _UINT32_(51) 989 #define MUX_PB19A_EIC_EXTINT3 _UINT32_(0) 990 #define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) 991 #define PORT_PB19A_EIC_EXTINT3 (_UINT32_(1) << 19) 992 #define PIN_PB19A_EIC_EXTINT_NUM _UINT32_(3) /* EIC signal: PIN_PB19 External Interrupt Line */ 993 994 #define PIN_PA04A_EIC_EXTINT4 _UINT32_(4) 995 #define MUX_PA04A_EIC_EXTINT4 _UINT32_(0) 996 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 997 #define PORT_PA04A_EIC_EXTINT4 (_UINT32_(1) << 4) 998 #define PIN_PA04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA04 External Interrupt Line */ 999 1000 #define PIN_PA20A_EIC_EXTINT4 _UINT32_(20) 1001 #define MUX_PA20A_EIC_EXTINT4 _UINT32_(0) 1002 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 1003 #define PORT_PA20A_EIC_EXTINT4 (_UINT32_(1) << 20) 1004 #define PIN_PA20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PA20 External Interrupt Line */ 1005 1006 #define PIN_PB04A_EIC_EXTINT4 _UINT32_(36) 1007 #define MUX_PB04A_EIC_EXTINT4 _UINT32_(0) 1008 #define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) 1009 #define PORT_PB04A_EIC_EXTINT4 (_UINT32_(1) << 4) 1010 #define PIN_PB04A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB04 External Interrupt Line */ 1011 1012 #define PIN_PB20A_EIC_EXTINT4 _UINT32_(52) 1013 #define MUX_PB20A_EIC_EXTINT4 _UINT32_(0) 1014 #define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) 1015 #define PORT_PB20A_EIC_EXTINT4 (_UINT32_(1) << 20) 1016 #define PIN_PB20A_EIC_EXTINT_NUM _UINT32_(4) /* EIC signal: PIN_PB20 External Interrupt Line */ 1017 1018 #define PIN_PA05A_EIC_EXTINT5 _UINT32_(5) 1019 #define MUX_PA05A_EIC_EXTINT5 _UINT32_(0) 1020 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 1021 #define PORT_PA05A_EIC_EXTINT5 (_UINT32_(1) << 5) 1022 #define PIN_PA05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA05 External Interrupt Line */ 1023 1024 #define PIN_PA21A_EIC_EXTINT5 _UINT32_(21) 1025 #define MUX_PA21A_EIC_EXTINT5 _UINT32_(0) 1026 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 1027 #define PORT_PA21A_EIC_EXTINT5 (_UINT32_(1) << 21) 1028 #define PIN_PA21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PA21 External Interrupt Line */ 1029 1030 #define PIN_PB05A_EIC_EXTINT5 _UINT32_(37) 1031 #define MUX_PB05A_EIC_EXTINT5 _UINT32_(0) 1032 #define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) 1033 #define PORT_PB05A_EIC_EXTINT5 (_UINT32_(1) << 5) 1034 #define PIN_PB05A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB05 External Interrupt Line */ 1035 1036 #define PIN_PB21A_EIC_EXTINT5 _UINT32_(53) 1037 #define MUX_PB21A_EIC_EXTINT5 _UINT32_(0) 1038 #define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) 1039 #define PORT_PB21A_EIC_EXTINT5 (_UINT32_(1) << 21) 1040 #define PIN_PB21A_EIC_EXTINT_NUM _UINT32_(5) /* EIC signal: PIN_PB21 External Interrupt Line */ 1041 1042 #define PIN_PA06A_EIC_EXTINT6 _UINT32_(6) 1043 #define MUX_PA06A_EIC_EXTINT6 _UINT32_(0) 1044 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 1045 #define PORT_PA06A_EIC_EXTINT6 (_UINT32_(1) << 6) 1046 #define PIN_PA06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA06 External Interrupt Line */ 1047 1048 #define PIN_PA22A_EIC_EXTINT6 _UINT32_(22) 1049 #define MUX_PA22A_EIC_EXTINT6 _UINT32_(0) 1050 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 1051 #define PORT_PA22A_EIC_EXTINT6 (_UINT32_(1) << 22) 1052 #define PIN_PA22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PA22 External Interrupt Line */ 1053 1054 #define PIN_PB06A_EIC_EXTINT6 _UINT32_(38) 1055 #define MUX_PB06A_EIC_EXTINT6 _UINT32_(0) 1056 #define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) 1057 #define PORT_PB06A_EIC_EXTINT6 (_UINT32_(1) << 6) 1058 #define PIN_PB06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB06 External Interrupt Line */ 1059 1060 #define PIN_PB22A_EIC_EXTINT6 _UINT32_(54) 1061 #define MUX_PB22A_EIC_EXTINT6 _UINT32_(0) 1062 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 1063 #define PORT_PB22A_EIC_EXTINT6 (_UINT32_(1) << 22) 1064 #define PIN_PB22A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PB22 External Interrupt Line */ 1065 1066 #define PIN_PC06A_EIC_EXTINT6 _UINT32_(70) 1067 #define MUX_PC06A_EIC_EXTINT6 _UINT32_(0) 1068 #define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) 1069 #define PORT_PC06A_EIC_EXTINT6 (_UINT32_(1) << 6) 1070 #define PIN_PC06A_EIC_EXTINT_NUM _UINT32_(6) /* EIC signal: PIN_PC06 External Interrupt Line */ 1071 1072 #define PIN_PA07A_EIC_EXTINT7 _UINT32_(7) 1073 #define MUX_PA07A_EIC_EXTINT7 _UINT32_(0) 1074 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 1075 #define PORT_PA07A_EIC_EXTINT7 (_UINT32_(1) << 7) 1076 #define PIN_PA07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA07 External Interrupt Line */ 1077 1078 #define PIN_PA23A_EIC_EXTINT7 _UINT32_(23) 1079 #define MUX_PA23A_EIC_EXTINT7 _UINT32_(0) 1080 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 1081 #define PORT_PA23A_EIC_EXTINT7 (_UINT32_(1) << 23) 1082 #define PIN_PA23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PA23 External Interrupt Line */ 1083 1084 #define PIN_PB07A_EIC_EXTINT7 _UINT32_(39) 1085 #define MUX_PB07A_EIC_EXTINT7 _UINT32_(0) 1086 #define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) 1087 #define PORT_PB07A_EIC_EXTINT7 (_UINT32_(1) << 7) 1088 #define PIN_PB07A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB07 External Interrupt Line */ 1089 1090 #define PIN_PB23A_EIC_EXTINT7 _UINT32_(55) 1091 #define MUX_PB23A_EIC_EXTINT7 _UINT32_(0) 1092 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 1093 #define PORT_PB23A_EIC_EXTINT7 (_UINT32_(1) << 23) 1094 #define PIN_PB23A_EIC_EXTINT_NUM _UINT32_(7) /* EIC signal: PIN_PB23 External Interrupt Line */ 1095 1096 #define PIN_PA24A_EIC_EXTINT8 _UINT32_(24) 1097 #define MUX_PA24A_EIC_EXTINT8 _UINT32_(0) 1098 #define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) 1099 #define PORT_PA24A_EIC_EXTINT8 (_UINT32_(1) << 24) 1100 #define PIN_PA24A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PA24 External Interrupt Line */ 1101 1102 #define PIN_PB08A_EIC_EXTINT8 _UINT32_(40) 1103 #define MUX_PB08A_EIC_EXTINT8 _UINT32_(0) 1104 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 1105 #define PORT_PB08A_EIC_EXTINT8 (_UINT32_(1) << 8) 1106 #define PIN_PB08A_EIC_EXTINT_NUM _UINT32_(8) /* EIC signal: PIN_PB08 External Interrupt Line */ 1107 1108 #define PIN_PA09A_EIC_EXTINT9 _UINT32_(9) 1109 #define MUX_PA09A_EIC_EXTINT9 _UINT32_(0) 1110 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 1111 #define PORT_PA09A_EIC_EXTINT9 (_UINT32_(1) << 9) 1112 #define PIN_PA09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA09 External Interrupt Line */ 1113 1114 #define PIN_PA25A_EIC_EXTINT9 _UINT32_(25) 1115 #define MUX_PA25A_EIC_EXTINT9 _UINT32_(0) 1116 #define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) 1117 #define PORT_PA25A_EIC_EXTINT9 (_UINT32_(1) << 25) 1118 #define PIN_PA25A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PA25 External Interrupt Line */ 1119 1120 #define PIN_PB09A_EIC_EXTINT9 _UINT32_(41) 1121 #define MUX_PB09A_EIC_EXTINT9 _UINT32_(0) 1122 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 1123 #define PORT_PB09A_EIC_EXTINT9 (_UINT32_(1) << 9) 1124 #define PIN_PB09A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PB09 External Interrupt Line */ 1125 1126 #define PIN_PC07A_EIC_EXTINT9 _UINT32_(71) 1127 #define MUX_PC07A_EIC_EXTINT9 _UINT32_(0) 1128 #define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) 1129 #define PORT_PC07A_EIC_EXTINT9 (_UINT32_(1) << 7) 1130 #define PIN_PC07A_EIC_EXTINT_NUM _UINT32_(9) /* EIC signal: PIN_PC07 External Interrupt Line */ 1131 1132 #define PIN_PA10A_EIC_EXTINT10 _UINT32_(10) 1133 #define MUX_PA10A_EIC_EXTINT10 _UINT32_(0) 1134 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 1135 #define PORT_PA10A_EIC_EXTINT10 (_UINT32_(1) << 10) 1136 #define PIN_PA10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PA10 External Interrupt Line */ 1137 1138 #define PIN_PB10A_EIC_EXTINT10 _UINT32_(42) 1139 #define MUX_PB10A_EIC_EXTINT10 _UINT32_(0) 1140 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 1141 #define PORT_PB10A_EIC_EXTINT10 (_UINT32_(1) << 10) 1142 #define PIN_PB10A_EIC_EXTINT_NUM _UINT32_(10) /* EIC signal: PIN_PB10 External Interrupt Line */ 1143 1144 #define PIN_PA11A_EIC_EXTINT11 _UINT32_(11) 1145 #define MUX_PA11A_EIC_EXTINT11 _UINT32_(0) 1146 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 1147 #define PORT_PA11A_EIC_EXTINT11 (_UINT32_(1) << 11) 1148 #define PIN_PA11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA11 External Interrupt Line */ 1149 1150 #define PIN_PA27A_EIC_EXTINT11 _UINT32_(27) 1151 #define MUX_PA27A_EIC_EXTINT11 _UINT32_(0) 1152 #define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) 1153 #define PORT_PA27A_EIC_EXTINT11 (_UINT32_(1) << 27) 1154 #define PIN_PA27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PA27 External Interrupt Line */ 1155 1156 #define PIN_PB11A_EIC_EXTINT11 _UINT32_(43) 1157 #define MUX_PB11A_EIC_EXTINT11 _UINT32_(0) 1158 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 1159 #define PORT_PB11A_EIC_EXTINT11 (_UINT32_(1) << 11) 1160 #define PIN_PB11A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PB11 External Interrupt Line */ 1161 1162 #define PIN_PC27A_EIC_EXTINT11 _UINT32_(91) 1163 #define MUX_PC27A_EIC_EXTINT11 _UINT32_(0) 1164 #define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) 1165 #define PORT_PC27A_EIC_EXTINT11 (_UINT32_(1) << 27) 1166 #define PIN_PC27A_EIC_EXTINT_NUM _UINT32_(11) /* EIC signal: PIN_PC27 External Interrupt Line */ 1167 1168 #define PIN_PA12A_EIC_EXTINT12 _UINT32_(12) 1169 #define MUX_PA12A_EIC_EXTINT12 _UINT32_(0) 1170 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 1171 #define PORT_PA12A_EIC_EXTINT12 (_UINT32_(1) << 12) 1172 #define PIN_PA12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PA12 External Interrupt Line */ 1173 1174 #define PIN_PB12A_EIC_EXTINT12 _UINT32_(44) 1175 #define MUX_PB12A_EIC_EXTINT12 _UINT32_(0) 1176 #define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) 1177 #define PORT_PB12A_EIC_EXTINT12 (_UINT32_(1) << 12) 1178 #define PIN_PB12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PB12 External Interrupt Line */ 1179 1180 #define PIN_PC12A_EIC_EXTINT12 _UINT32_(76) 1181 #define MUX_PC12A_EIC_EXTINT12 _UINT32_(0) 1182 #define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) 1183 #define PORT_PC12A_EIC_EXTINT12 (_UINT32_(1) << 12) 1184 #define PIN_PC12A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PC12 External Interrupt Line */ 1185 1186 #define PIN_PC28A_EIC_EXTINT12 _UINT32_(92) 1187 #define MUX_PC28A_EIC_EXTINT12 _UINT32_(0) 1188 #define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) 1189 #define PORT_PC28A_EIC_EXTINT12 (_UINT32_(1) << 28) 1190 #define PIN_PC28A_EIC_EXTINT_NUM _UINT32_(12) /* EIC signal: PIN_PC28 External Interrupt Line */ 1191 1192 #define PIN_PA13A_EIC_EXTINT13 _UINT32_(13) 1193 #define MUX_PA13A_EIC_EXTINT13 _UINT32_(0) 1194 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 1195 #define PORT_PA13A_EIC_EXTINT13 (_UINT32_(1) << 13) 1196 #define PIN_PA13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PA13 External Interrupt Line */ 1197 1198 #define PIN_PB13A_EIC_EXTINT13 _UINT32_(45) 1199 #define MUX_PB13A_EIC_EXTINT13 _UINT32_(0) 1200 #define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) 1201 #define PORT_PB13A_EIC_EXTINT13 (_UINT32_(1) << 13) 1202 #define PIN_PB13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PB13 External Interrupt Line */ 1203 1204 #define PIN_PC13A_EIC_EXTINT13 _UINT32_(77) 1205 #define MUX_PC13A_EIC_EXTINT13 _UINT32_(0) 1206 #define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) 1207 #define PORT_PC13A_EIC_EXTINT13 (_UINT32_(1) << 13) 1208 #define PIN_PC13A_EIC_EXTINT_NUM _UINT32_(13) /* EIC signal: PIN_PC13 External Interrupt Line */ 1209 1210 #define PIN_PA30A_EIC_EXTINT14 _UINT32_(30) 1211 #define MUX_PA30A_EIC_EXTINT14 _UINT32_(0) 1212 #define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) 1213 #define PORT_PA30A_EIC_EXTINT14 (_UINT32_(1) << 30) 1214 #define PIN_PA30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA30 External Interrupt Line */ 1215 1216 #define PIN_PB14A_EIC_EXTINT14 _UINT32_(46) 1217 #define MUX_PB14A_EIC_EXTINT14 _UINT32_(0) 1218 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) 1219 #define PORT_PB14A_EIC_EXTINT14 (_UINT32_(1) << 14) 1220 #define PIN_PB14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB14 External Interrupt Line */ 1221 1222 #define PIN_PB30A_EIC_EXTINT14 _UINT32_(62) 1223 #define MUX_PB30A_EIC_EXTINT14 _UINT32_(0) 1224 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) 1225 #define PORT_PB30A_EIC_EXTINT14 (_UINT32_(1) << 30) 1226 #define PIN_PB30A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PB30 External Interrupt Line */ 1227 1228 #define PIN_PC14A_EIC_EXTINT14 _UINT32_(78) 1229 #define MUX_PC14A_EIC_EXTINT14 _UINT32_(0) 1230 #define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) 1231 #define PORT_PC14A_EIC_EXTINT14 (_UINT32_(1) << 14) 1232 #define PIN_PC14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PC14 External Interrupt Line */ 1233 1234 #define PIN_PA14A_EIC_EXTINT14 _UINT32_(14) 1235 #define MUX_PA14A_EIC_EXTINT14 _UINT32_(0) 1236 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 1237 #define PORT_PA14A_EIC_EXTINT14 (_UINT32_(1) << 14) 1238 #define PIN_PA14A_EIC_EXTINT_NUM _UINT32_(14) /* EIC signal: PIN_PA14 External Interrupt Line */ 1239 1240 #define PIN_PA15A_EIC_EXTINT15 _UINT32_(15) 1241 #define MUX_PA15A_EIC_EXTINT15 _UINT32_(0) 1242 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 1243 #define PORT_PA15A_EIC_EXTINT15 (_UINT32_(1) << 15) 1244 #define PIN_PA15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA15 External Interrupt Line */ 1245 1246 #define PIN_PA31A_EIC_EXTINT15 _UINT32_(31) 1247 #define MUX_PA31A_EIC_EXTINT15 _UINT32_(0) 1248 #define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) 1249 #define PORT_PA31A_EIC_EXTINT15 (_UINT32_(1) << 31) 1250 #define PIN_PA31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PA31 External Interrupt Line */ 1251 1252 #define PIN_PB15A_EIC_EXTINT15 _UINT32_(47) 1253 #define MUX_PB15A_EIC_EXTINT15 _UINT32_(0) 1254 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) 1255 #define PORT_PB15A_EIC_EXTINT15 (_UINT32_(1) << 15) 1256 #define PIN_PB15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB15 External Interrupt Line */ 1257 1258 #define PIN_PB31A_EIC_EXTINT15 _UINT32_(63) 1259 #define MUX_PB31A_EIC_EXTINT15 _UINT32_(0) 1260 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) 1261 #define PORT_PB31A_EIC_EXTINT15 (_UINT32_(1) << 31) 1262 #define PIN_PB31A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PB31 External Interrupt Line */ 1263 1264 #define PIN_PC15A_EIC_EXTINT15 _UINT32_(79) 1265 #define MUX_PC15A_EIC_EXTINT15 _UINT32_(0) 1266 #define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) 1267 #define PORT_PC15A_EIC_EXTINT15 (_UINT32_(1) << 15) 1268 #define PIN_PC15A_EIC_EXTINT_NUM _UINT32_(15) /* EIC signal: PIN_PC15 External Interrupt Line */ 1269 1270 #define PIN_PA08A_EIC_NMI _UINT32_(8) 1271 #define MUX_PA08A_EIC_NMI _UINT32_(0) 1272 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 1273 #define PORT_PA08A_EIC_NMI (_UINT32_(1) << 8) 1274 1275 /* ================== PORT definition for GCLK peripheral =================== */ 1276 #define PIN_PA30M_GCLK_IO0 _UINT32_(30) 1277 #define MUX_PA30M_GCLK_IO0 _UINT32_(12) 1278 #define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) 1279 #define PORT_PA30M_GCLK_IO0 (_UINT32_(1) << 30) 1280 1281 #define PIN_PB14M_GCLK_IO0 _UINT32_(46) 1282 #define MUX_PB14M_GCLK_IO0 _UINT32_(12) 1283 #define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) 1284 #define PORT_PB14M_GCLK_IO0 (_UINT32_(1) << 14) 1285 1286 #define PIN_PA14M_GCLK_IO0 _UINT32_(14) 1287 #define MUX_PA14M_GCLK_IO0 _UINT32_(12) 1288 #define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) 1289 #define PORT_PA14M_GCLK_IO0 (_UINT32_(1) << 14) 1290 1291 #define PIN_PB22M_GCLK_IO0 _UINT32_(54) 1292 #define MUX_PB22M_GCLK_IO0 _UINT32_(12) 1293 #define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) 1294 #define PORT_PB22M_GCLK_IO0 (_UINT32_(1) << 22) 1295 1296 #define PIN_PB15M_GCLK_IO1 _UINT32_(47) 1297 #define MUX_PB15M_GCLK_IO1 _UINT32_(12) 1298 #define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) 1299 #define PORT_PB15M_GCLK_IO1 (_UINT32_(1) << 15) 1300 1301 #define PIN_PA15M_GCLK_IO1 _UINT32_(15) 1302 #define MUX_PA15M_GCLK_IO1 _UINT32_(12) 1303 #define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) 1304 #define PORT_PA15M_GCLK_IO1 (_UINT32_(1) << 15) 1305 1306 #define PIN_PB23M_GCLK_IO1 _UINT32_(55) 1307 #define MUX_PB23M_GCLK_IO1 _UINT32_(12) 1308 #define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) 1309 #define PORT_PB23M_GCLK_IO1 (_UINT32_(1) << 23) 1310 1311 #define PIN_PA27M_GCLK_IO1 _UINT32_(27) 1312 #define MUX_PA27M_GCLK_IO1 _UINT32_(12) 1313 #define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) 1314 #define PORT_PA27M_GCLK_IO1 (_UINT32_(1) << 27) 1315 1316 #define PIN_PA16M_GCLK_IO2 _UINT32_(16) 1317 #define MUX_PA16M_GCLK_IO2 _UINT32_(12) 1318 #define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) 1319 #define PORT_PA16M_GCLK_IO2 (_UINT32_(1) << 16) 1320 1321 #define PIN_PB16M_GCLK_IO2 _UINT32_(48) 1322 #define MUX_PB16M_GCLK_IO2 _UINT32_(12) 1323 #define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) 1324 #define PORT_PB16M_GCLK_IO2 (_UINT32_(1) << 16) 1325 1326 #define PIN_PA17M_GCLK_IO3 _UINT32_(17) 1327 #define MUX_PA17M_GCLK_IO3 _UINT32_(12) 1328 #define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) 1329 #define PORT_PA17M_GCLK_IO3 (_UINT32_(1) << 17) 1330 1331 #define PIN_PB17M_GCLK_IO3 _UINT32_(49) 1332 #define MUX_PB17M_GCLK_IO3 _UINT32_(12) 1333 #define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) 1334 #define PORT_PB17M_GCLK_IO3 (_UINT32_(1) << 17) 1335 1336 #define PIN_PA10M_GCLK_IO4 _UINT32_(10) 1337 #define MUX_PA10M_GCLK_IO4 _UINT32_(12) 1338 #define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) 1339 #define PORT_PA10M_GCLK_IO4 (_UINT32_(1) << 10) 1340 1341 #define PIN_PB10M_GCLK_IO4 _UINT32_(42) 1342 #define MUX_PB10M_GCLK_IO4 _UINT32_(12) 1343 #define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) 1344 #define PORT_PB10M_GCLK_IO4 (_UINT32_(1) << 10) 1345 1346 #define PIN_PB18M_GCLK_IO4 _UINT32_(50) 1347 #define MUX_PB18M_GCLK_IO4 _UINT32_(12) 1348 #define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) 1349 #define PORT_PB18M_GCLK_IO4 (_UINT32_(1) << 18) 1350 1351 #define PIN_PA11M_GCLK_IO5 _UINT32_(11) 1352 #define MUX_PA11M_GCLK_IO5 _UINT32_(12) 1353 #define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) 1354 #define PORT_PA11M_GCLK_IO5 (_UINT32_(1) << 11) 1355 1356 #define PIN_PB11M_GCLK_IO5 _UINT32_(43) 1357 #define MUX_PB11M_GCLK_IO5 _UINT32_(12) 1358 #define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) 1359 #define PORT_PB11M_GCLK_IO5 (_UINT32_(1) << 11) 1360 1361 #define PIN_PB19M_GCLK_IO5 _UINT32_(51) 1362 #define MUX_PB19M_GCLK_IO5 _UINT32_(12) 1363 #define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) 1364 #define PORT_PB19M_GCLK_IO5 (_UINT32_(1) << 19) 1365 1366 #define PIN_PB12M_GCLK_IO6 _UINT32_(44) 1367 #define MUX_PB12M_GCLK_IO6 _UINT32_(12) 1368 #define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) 1369 #define PORT_PB12M_GCLK_IO6 (_UINT32_(1) << 12) 1370 1371 #define PIN_PB20M_GCLK_IO6 _UINT32_(52) 1372 #define MUX_PB20M_GCLK_IO6 _UINT32_(12) 1373 #define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) 1374 #define PORT_PB20M_GCLK_IO6 (_UINT32_(1) << 20) 1375 1376 #define PIN_PB13M_GCLK_IO7 _UINT32_(45) 1377 #define MUX_PB13M_GCLK_IO7 _UINT32_(12) 1378 #define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) 1379 #define PORT_PB13M_GCLK_IO7 (_UINT32_(1) << 13) 1380 1381 #define PIN_PB21M_GCLK_IO7 _UINT32_(53) 1382 #define MUX_PB21M_GCLK_IO7 _UINT32_(12) 1383 #define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) 1384 #define PORT_PB21M_GCLK_IO7 (_UINT32_(1) << 21) 1385 1386 /* ================== PORT definition for GMAC peripheral =================== */ 1387 #define PIN_PA16L_GMAC_GCRS _UINT32_(16) 1388 #define MUX_PA16L_GMAC_GCRS _UINT32_(11) 1389 #define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) 1390 #define PORT_PA16L_GMAC_GCRS (_UINT32_(1) << 16) 1391 1392 #define PIN_PA20L_GMAC_GMDC _UINT32_(20) 1393 #define MUX_PA20L_GMAC_GMDC _UINT32_(11) 1394 #define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) 1395 #define PORT_PA20L_GMAC_GMDC (_UINT32_(1) << 20) 1396 1397 #define PIN_PB14L_GMAC_GMDC _UINT32_(46) 1398 #define MUX_PB14L_GMAC_GMDC _UINT32_(11) 1399 #define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) 1400 #define PORT_PB14L_GMAC_GMDC (_UINT32_(1) << 14) 1401 1402 #define PIN_PA21L_GMAC_GMDIO _UINT32_(21) 1403 #define MUX_PA21L_GMAC_GMDIO _UINT32_(11) 1404 #define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) 1405 #define PORT_PA21L_GMAC_GMDIO (_UINT32_(1) << 21) 1406 1407 #define PIN_PB15L_GMAC_GMDIO _UINT32_(47) 1408 #define MUX_PB15L_GMAC_GMDIO _UINT32_(11) 1409 #define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) 1410 #define PORT_PB15L_GMAC_GMDIO (_UINT32_(1) << 15) 1411 1412 #define PIN_PC12L_GMAC_GMDIO _UINT32_(76) 1413 #define MUX_PC12L_GMAC_GMDIO _UINT32_(11) 1414 #define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) 1415 #define PORT_PC12L_GMAC_GMDIO (_UINT32_(1) << 12) 1416 1417 #define PIN_PA13L_GMAC_GRX0 _UINT32_(13) 1418 #define MUX_PA13L_GMAC_GRX0 _UINT32_(11) 1419 #define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) 1420 #define PORT_PA13L_GMAC_GRX0 (_UINT32_(1) << 13) 1421 1422 #define PIN_PA12L_GMAC_GRX1 _UINT32_(12) 1423 #define MUX_PA12L_GMAC_GRX1 _UINT32_(11) 1424 #define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) 1425 #define PORT_PA12L_GMAC_GRX1 (_UINT32_(1) << 12) 1426 1427 #define PIN_PC15L_GMAC_GRX2 _UINT32_(79) 1428 #define MUX_PC15L_GMAC_GRX2 _UINT32_(11) 1429 #define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) 1430 #define PORT_PC15L_GMAC_GRX2 (_UINT32_(1) << 15) 1431 1432 #define PIN_PC14L_GMAC_GRX3 _UINT32_(78) 1433 #define MUX_PC14L_GMAC_GRX3 _UINT32_(11) 1434 #define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) 1435 #define PORT_PC14L_GMAC_GRX3 (_UINT32_(1) << 14) 1436 1437 #define PIN_PA15L_GMAC_GRXER _UINT32_(15) 1438 #define MUX_PA15L_GMAC_GRXER _UINT32_(11) 1439 #define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) 1440 #define PORT_PA15L_GMAC_GRXER (_UINT32_(1) << 15) 1441 1442 #define PIN_PA18L_GMAC_GTX0 _UINT32_(18) 1443 #define MUX_PA18L_GMAC_GTX0 _UINT32_(11) 1444 #define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) 1445 #define PORT_PA18L_GMAC_GTX0 (_UINT32_(1) << 18) 1446 1447 #define PIN_PA19L_GMAC_GTX1 _UINT32_(19) 1448 #define MUX_PA19L_GMAC_GTX1 _UINT32_(11) 1449 #define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) 1450 #define PORT_PA19L_GMAC_GTX1 (_UINT32_(1) << 19) 1451 1452 #define PIN_PC16L_GMAC_GTX2 _UINT32_(80) 1453 #define MUX_PC16L_GMAC_GTX2 _UINT32_(11) 1454 #define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) 1455 #define PORT_PC16L_GMAC_GTX2 (_UINT32_(1) << 16) 1456 1457 #define PIN_PC17L_GMAC_GTX3 _UINT32_(81) 1458 #define MUX_PC17L_GMAC_GTX3 _UINT32_(11) 1459 #define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) 1460 #define PORT_PC17L_GMAC_GTX3 (_UINT32_(1) << 17) 1461 1462 #define PIN_PA14L_GMAC_GTXCK _UINT32_(14) 1463 #define MUX_PA14L_GMAC_GTXCK _UINT32_(11) 1464 #define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) 1465 #define PORT_PA14L_GMAC_GTXCK (_UINT32_(1) << 14) 1466 1467 #define PIN_PA17L_GMAC_GTXEN _UINT32_(17) 1468 #define MUX_PA17L_GMAC_GTXEN _UINT32_(11) 1469 #define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) 1470 #define PORT_PA17L_GMAC_GTXEN (_UINT32_(1) << 17) 1471 1472 /* =================== PORT definition for I2S peripheral =================== */ 1473 #define PIN_PA09J_I2S_FS0 _UINT32_(9) 1474 #define MUX_PA09J_I2S_FS0 _UINT32_(9) 1475 #define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) 1476 #define PORT_PA09J_I2S_FS0 (_UINT32_(1) << 9) 1477 1478 #define PIN_PA20J_I2S_FS0 _UINT32_(20) 1479 #define MUX_PA20J_I2S_FS0 _UINT32_(9) 1480 #define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) 1481 #define PORT_PA20J_I2S_FS0 (_UINT32_(1) << 20) 1482 1483 #define PIN_PA23J_I2S_FS1 _UINT32_(23) 1484 #define MUX_PA23J_I2S_FS1 _UINT32_(9) 1485 #define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) 1486 #define PORT_PA23J_I2S_FS1 (_UINT32_(1) << 23) 1487 1488 #define PIN_PB11J_I2S_FS1 _UINT32_(43) 1489 #define MUX_PB11J_I2S_FS1 _UINT32_(9) 1490 #define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) 1491 #define PORT_PB11J_I2S_FS1 (_UINT32_(1) << 11) 1492 1493 #define PIN_PA08J_I2S_MCK0 _UINT32_(8) 1494 #define MUX_PA08J_I2S_MCK0 _UINT32_(9) 1495 #define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) 1496 #define PORT_PA08J_I2S_MCK0 (_UINT32_(1) << 8) 1497 1498 #define PIN_PB17J_I2S_MCK0 _UINT32_(49) 1499 #define MUX_PB17J_I2S_MCK0 _UINT32_(9) 1500 #define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) 1501 #define PORT_PB17J_I2S_MCK0 (_UINT32_(1) << 17) 1502 1503 #define PIN_PB13J_I2S_MCK1 _UINT32_(45) 1504 #define MUX_PB13J_I2S_MCK1 _UINT32_(9) 1505 #define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) 1506 #define PORT_PB13J_I2S_MCK1 (_UINT32_(1) << 13) 1507 1508 #define PIN_PA10J_I2S_SCK0 _UINT32_(10) 1509 #define MUX_PA10J_I2S_SCK0 _UINT32_(9) 1510 #define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) 1511 #define PORT_PA10J_I2S_SCK0 (_UINT32_(1) << 10) 1512 1513 #define PIN_PB16J_I2S_SCK0 _UINT32_(48) 1514 #define MUX_PB16J_I2S_SCK0 _UINT32_(9) 1515 #define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) 1516 #define PORT_PB16J_I2S_SCK0 (_UINT32_(1) << 16) 1517 1518 #define PIN_PB12J_I2S_SCK1 _UINT32_(44) 1519 #define MUX_PB12J_I2S_SCK1 _UINT32_(9) 1520 #define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) 1521 #define PORT_PB12J_I2S_SCK1 (_UINT32_(1) << 12) 1522 1523 #define PIN_PA22J_I2S_SDI _UINT32_(22) 1524 #define MUX_PA22J_I2S_SDI _UINT32_(9) 1525 #define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) 1526 #define PORT_PA22J_I2S_SDI (_UINT32_(1) << 22) 1527 1528 #define PIN_PB10J_I2S_SDI _UINT32_(42) 1529 #define MUX_PB10J_I2S_SDI _UINT32_(9) 1530 #define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) 1531 #define PORT_PB10J_I2S_SDI (_UINT32_(1) << 10) 1532 1533 #define PIN_PA11J_I2S_SDO _UINT32_(11) 1534 #define MUX_PA11J_I2S_SDO _UINT32_(9) 1535 #define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) 1536 #define PORT_PA11J_I2S_SDO (_UINT32_(1) << 11) 1537 1538 #define PIN_PA21J_I2S_SDO _UINT32_(21) 1539 #define MUX_PA21J_I2S_SDO _UINT32_(9) 1540 #define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) 1541 #define PORT_PA21J_I2S_SDO (_UINT32_(1) << 21) 1542 1543 /* =================== PORT definition for PCC peripheral =================== */ 1544 #define PIN_PA14K_PCC_CLK _UINT32_(14) 1545 #define MUX_PA14K_PCC_CLK _UINT32_(10) 1546 #define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) 1547 #define PORT_PA14K_PCC_CLK (_UINT32_(1) << 14) 1548 1549 #define PIN_PA16K_PCC_DATA0 _UINT32_(16) 1550 #define MUX_PA16K_PCC_DATA0 _UINT32_(10) 1551 #define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) 1552 #define PORT_PA16K_PCC_DATA0 (_UINT32_(1) << 16) 1553 1554 #define PIN_PA17K_PCC_DATA1 _UINT32_(17) 1555 #define MUX_PA17K_PCC_DATA1 _UINT32_(10) 1556 #define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) 1557 #define PORT_PA17K_PCC_DATA1 (_UINT32_(1) << 17) 1558 1559 #define PIN_PA18K_PCC_DATA2 _UINT32_(18) 1560 #define MUX_PA18K_PCC_DATA2 _UINT32_(10) 1561 #define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) 1562 #define PORT_PA18K_PCC_DATA2 (_UINT32_(1) << 18) 1563 1564 #define PIN_PA19K_PCC_DATA3 _UINT32_(19) 1565 #define MUX_PA19K_PCC_DATA3 _UINT32_(10) 1566 #define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) 1567 #define PORT_PA19K_PCC_DATA3 (_UINT32_(1) << 19) 1568 1569 #define PIN_PA20K_PCC_DATA4 _UINT32_(20) 1570 #define MUX_PA20K_PCC_DATA4 _UINT32_(10) 1571 #define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) 1572 #define PORT_PA20K_PCC_DATA4 (_UINT32_(1) << 20) 1573 1574 #define PIN_PA21K_PCC_DATA5 _UINT32_(21) 1575 #define MUX_PA21K_PCC_DATA5 _UINT32_(10) 1576 #define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) 1577 #define PORT_PA21K_PCC_DATA5 (_UINT32_(1) << 21) 1578 1579 #define PIN_PA22K_PCC_DATA6 _UINT32_(22) 1580 #define MUX_PA22K_PCC_DATA6 _UINT32_(10) 1581 #define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) 1582 #define PORT_PA22K_PCC_DATA6 (_UINT32_(1) << 22) 1583 1584 #define PIN_PA23K_PCC_DATA7 _UINT32_(23) 1585 #define MUX_PA23K_PCC_DATA7 _UINT32_(10) 1586 #define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) 1587 #define PORT_PA23K_PCC_DATA7 (_UINT32_(1) << 23) 1588 1589 #define PIN_PB14K_PCC_DATA8 _UINT32_(46) 1590 #define MUX_PB14K_PCC_DATA8 _UINT32_(10) 1591 #define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) 1592 #define PORT_PB14K_PCC_DATA8 (_UINT32_(1) << 14) 1593 1594 #define PIN_PB15K_PCC_DATA9 _UINT32_(47) 1595 #define MUX_PB15K_PCC_DATA9 _UINT32_(10) 1596 #define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) 1597 #define PORT_PB15K_PCC_DATA9 (_UINT32_(1) << 15) 1598 1599 #define PIN_PC12K_PCC_DATA10 _UINT32_(76) 1600 #define MUX_PC12K_PCC_DATA10 _UINT32_(10) 1601 #define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) 1602 #define PORT_PC12K_PCC_DATA10 (_UINT32_(1) << 12) 1603 1604 #define PIN_PC13K_PCC_DATA11 _UINT32_(77) 1605 #define MUX_PC13K_PCC_DATA11 _UINT32_(10) 1606 #define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) 1607 #define PORT_PC13K_PCC_DATA11 (_UINT32_(1) << 13) 1608 1609 #define PIN_PC14K_PCC_DATA12 _UINT32_(78) 1610 #define MUX_PC14K_PCC_DATA12 _UINT32_(10) 1611 #define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) 1612 #define PORT_PC14K_PCC_DATA12 (_UINT32_(1) << 14) 1613 1614 #define PIN_PC15K_PCC_DATA13 _UINT32_(79) 1615 #define MUX_PC15K_PCC_DATA13 _UINT32_(10) 1616 #define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) 1617 #define PORT_PC15K_PCC_DATA13 (_UINT32_(1) << 15) 1618 1619 #define PIN_PA12K_PCC_DEN1 _UINT32_(12) 1620 #define MUX_PA12K_PCC_DEN1 _UINT32_(10) 1621 #define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) 1622 #define PORT_PA12K_PCC_DEN1 (_UINT32_(1) << 12) 1623 1624 #define PIN_PA13K_PCC_DEN2 _UINT32_(13) 1625 #define MUX_PA13K_PCC_DEN2 _UINT32_(10) 1626 #define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) 1627 #define PORT_PA13K_PCC_DEN2 (_UINT32_(1) << 13) 1628 1629 /* ================== PORT definition for PDEC peripheral =================== */ 1630 #define PIN_PB18G_PDEC_QDI0 _UINT32_(50) 1631 #define MUX_PB18G_PDEC_QDI0 _UINT32_(6) 1632 #define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) 1633 #define PORT_PB18G_PDEC_QDI0 (_UINT32_(1) << 18) 1634 1635 #define PIN_PB23G_PDEC_QDI0 _UINT32_(55) 1636 #define MUX_PB23G_PDEC_QDI0 _UINT32_(6) 1637 #define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) 1638 #define PORT_PB23G_PDEC_QDI0 (_UINT32_(1) << 23) 1639 1640 #define PIN_PC16G_PDEC_QDI0 _UINT32_(80) 1641 #define MUX_PC16G_PDEC_QDI0 _UINT32_(6) 1642 #define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) 1643 #define PORT_PC16G_PDEC_QDI0 (_UINT32_(1) << 16) 1644 1645 #define PIN_PA24G_PDEC_QDI0 _UINT32_(24) 1646 #define MUX_PA24G_PDEC_QDI0 _UINT32_(6) 1647 #define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) 1648 #define PORT_PA24G_PDEC_QDI0 (_UINT32_(1) << 24) 1649 1650 #define PIN_PB19G_PDEC_QDI1 _UINT32_(51) 1651 #define MUX_PB19G_PDEC_QDI1 _UINT32_(6) 1652 #define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) 1653 #define PORT_PB19G_PDEC_QDI1 (_UINT32_(1) << 19) 1654 1655 #define PIN_PC17G_PDEC_QDI1 _UINT32_(81) 1656 #define MUX_PC17G_PDEC_QDI1 _UINT32_(6) 1657 #define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) 1658 #define PORT_PC17G_PDEC_QDI1 (_UINT32_(1) << 17) 1659 1660 #define PIN_PA25G_PDEC_QDI1 _UINT32_(25) 1661 #define MUX_PA25G_PDEC_QDI1 _UINT32_(6) 1662 #define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) 1663 #define PORT_PA25G_PDEC_QDI1 (_UINT32_(1) << 25) 1664 1665 #define PIN_PB20G_PDEC_QDI2 _UINT32_(52) 1666 #define MUX_PB20G_PDEC_QDI2 _UINT32_(6) 1667 #define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) 1668 #define PORT_PB20G_PDEC_QDI2 (_UINT32_(1) << 20) 1669 1670 #define PIN_PB22G_PDEC_QDI2 _UINT32_(54) 1671 #define MUX_PB22G_PDEC_QDI2 _UINT32_(6) 1672 #define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) 1673 #define PORT_PB22G_PDEC_QDI2 (_UINT32_(1) << 22) 1674 1675 /* ================== PORT definition for QSPI peripheral =================== */ 1676 #define PIN_PB11H_QSPI_CS _UINT32_(43) 1677 #define MUX_PB11H_QSPI_CS _UINT32_(7) 1678 #define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) 1679 #define PORT_PB11H_QSPI_CS (_UINT32_(1) << 11) 1680 1681 #define PIN_PA08H_QSPI_DATA0 _UINT32_(8) 1682 #define MUX_PA08H_QSPI_DATA0 _UINT32_(7) 1683 #define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) 1684 #define PORT_PA08H_QSPI_DATA0 (_UINT32_(1) << 8) 1685 1686 #define PIN_PA09H_QSPI_DATA1 _UINT32_(9) 1687 #define MUX_PA09H_QSPI_DATA1 _UINT32_(7) 1688 #define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) 1689 #define PORT_PA09H_QSPI_DATA1 (_UINT32_(1) << 9) 1690 1691 #define PIN_PA10H_QSPI_DATA2 _UINT32_(10) 1692 #define MUX_PA10H_QSPI_DATA2 _UINT32_(7) 1693 #define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) 1694 #define PORT_PA10H_QSPI_DATA2 (_UINT32_(1) << 10) 1695 1696 #define PIN_PA11H_QSPI_DATA3 _UINT32_(11) 1697 #define MUX_PA11H_QSPI_DATA3 _UINT32_(7) 1698 #define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) 1699 #define PORT_PA11H_QSPI_DATA3 (_UINT32_(1) << 11) 1700 1701 #define PIN_PB10H_QSPI_SCK _UINT32_(42) 1702 #define MUX_PB10H_QSPI_SCK _UINT32_(7) 1703 #define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) 1704 #define PORT_PB10H_QSPI_SCK (_UINT32_(1) << 10) 1705 1706 /* ================== PORT definition for SDHC0 peripheral ================== */ 1707 #define PIN_PA06I_SDHC0_SDCD _UINT32_(6) 1708 #define MUX_PA06I_SDHC0_SDCD _UINT32_(8) 1709 #define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) 1710 #define PORT_PA06I_SDHC0_SDCD (_UINT32_(1) << 6) 1711 1712 #define PIN_PA12I_SDHC0_SDCD _UINT32_(12) 1713 #define MUX_PA12I_SDHC0_SDCD _UINT32_(8) 1714 #define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) 1715 #define PORT_PA12I_SDHC0_SDCD (_UINT32_(1) << 12) 1716 1717 #define PIN_PB12I_SDHC0_SDCD _UINT32_(44) 1718 #define MUX_PB12I_SDHC0_SDCD _UINT32_(8) 1719 #define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) 1720 #define PORT_PB12I_SDHC0_SDCD (_UINT32_(1) << 12) 1721 1722 #define PIN_PC06I_SDHC0_SDCD _UINT32_(70) 1723 #define MUX_PC06I_SDHC0_SDCD _UINT32_(8) 1724 #define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) 1725 #define PORT_PC06I_SDHC0_SDCD (_UINT32_(1) << 6) 1726 1727 #define PIN_PB11I_SDHC0_SDCK _UINT32_(43) 1728 #define MUX_PB11I_SDHC0_SDCK _UINT32_(8) 1729 #define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) 1730 #define PORT_PB11I_SDHC0_SDCK (_UINT32_(1) << 11) 1731 1732 #define PIN_PA08I_SDHC0_SDCMD _UINT32_(8) 1733 #define MUX_PA08I_SDHC0_SDCMD _UINT32_(8) 1734 #define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) 1735 #define PORT_PA08I_SDHC0_SDCMD (_UINT32_(1) << 8) 1736 1737 #define PIN_PA09I_SDHC0_SDDAT0 _UINT32_(9) 1738 #define MUX_PA09I_SDHC0_SDDAT0 _UINT32_(8) 1739 #define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) 1740 #define PORT_PA09I_SDHC0_SDDAT0 (_UINT32_(1) << 9) 1741 1742 #define PIN_PA10I_SDHC0_SDDAT1 _UINT32_(10) 1743 #define MUX_PA10I_SDHC0_SDDAT1 _UINT32_(8) 1744 #define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) 1745 #define PORT_PA10I_SDHC0_SDDAT1 (_UINT32_(1) << 10) 1746 1747 #define PIN_PA11I_SDHC0_SDDAT2 _UINT32_(11) 1748 #define MUX_PA11I_SDHC0_SDDAT2 _UINT32_(8) 1749 #define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) 1750 #define PORT_PA11I_SDHC0_SDDAT2 (_UINT32_(1) << 11) 1751 1752 #define PIN_PB10I_SDHC0_SDDAT3 _UINT32_(42) 1753 #define MUX_PB10I_SDHC0_SDDAT3 _UINT32_(8) 1754 #define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) 1755 #define PORT_PB10I_SDHC0_SDDAT3 (_UINT32_(1) << 10) 1756 1757 #define PIN_PA07I_SDHC0_SDWP _UINT32_(7) 1758 #define MUX_PA07I_SDHC0_SDWP _UINT32_(8) 1759 #define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) 1760 #define PORT_PA07I_SDHC0_SDWP (_UINT32_(1) << 7) 1761 1762 #define PIN_PA13I_SDHC0_SDWP _UINT32_(13) 1763 #define MUX_PA13I_SDHC0_SDWP _UINT32_(8) 1764 #define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) 1765 #define PORT_PA13I_SDHC0_SDWP (_UINT32_(1) << 13) 1766 1767 #define PIN_PB13I_SDHC0_SDWP _UINT32_(45) 1768 #define MUX_PB13I_SDHC0_SDWP _UINT32_(8) 1769 #define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) 1770 #define PORT_PB13I_SDHC0_SDWP (_UINT32_(1) << 13) 1771 1772 #define PIN_PC07I_SDHC0_SDWP _UINT32_(71) 1773 #define MUX_PC07I_SDHC0_SDWP _UINT32_(8) 1774 #define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) 1775 #define PORT_PC07I_SDHC0_SDWP (_UINT32_(1) << 7) 1776 1777 /* ================== PORT definition for SDHC1 peripheral ================== */ 1778 #define PIN_PB16I_SDHC1_SDCD _UINT32_(48) 1779 #define MUX_PB16I_SDHC1_SDCD _UINT32_(8) 1780 #define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) 1781 #define PORT_PB16I_SDHC1_SDCD (_UINT32_(1) << 16) 1782 1783 #define PIN_PA21I_SDHC1_SDCK _UINT32_(21) 1784 #define MUX_PA21I_SDHC1_SDCK _UINT32_(8) 1785 #define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) 1786 #define PORT_PA21I_SDHC1_SDCK (_UINT32_(1) << 21) 1787 1788 #define PIN_PA20I_SDHC1_SDCMD _UINT32_(20) 1789 #define MUX_PA20I_SDHC1_SDCMD _UINT32_(8) 1790 #define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) 1791 #define PORT_PA20I_SDHC1_SDCMD (_UINT32_(1) << 20) 1792 1793 #define PIN_PB18I_SDHC1_SDDAT0 _UINT32_(50) 1794 #define MUX_PB18I_SDHC1_SDDAT0 _UINT32_(8) 1795 #define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) 1796 #define PORT_PB18I_SDHC1_SDDAT0 (_UINT32_(1) << 18) 1797 1798 #define PIN_PB19I_SDHC1_SDDAT1 _UINT32_(51) 1799 #define MUX_PB19I_SDHC1_SDDAT1 _UINT32_(8) 1800 #define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) 1801 #define PORT_PB19I_SDHC1_SDDAT1 (_UINT32_(1) << 19) 1802 1803 #define PIN_PB20I_SDHC1_SDDAT2 _UINT32_(52) 1804 #define MUX_PB20I_SDHC1_SDDAT2 _UINT32_(8) 1805 #define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) 1806 #define PORT_PB20I_SDHC1_SDDAT2 (_UINT32_(1) << 20) 1807 1808 #define PIN_PB21I_SDHC1_SDDAT3 _UINT32_(53) 1809 #define MUX_PB21I_SDHC1_SDDAT3 _UINT32_(8) 1810 #define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) 1811 #define PORT_PB21I_SDHC1_SDDAT3 (_UINT32_(1) << 21) 1812 1813 #define PIN_PB17I_SDHC1_SDWP _UINT32_(49) 1814 #define MUX_PB17I_SDHC1_SDWP _UINT32_(8) 1815 #define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) 1816 #define PORT_PB17I_SDHC1_SDWP (_UINT32_(1) << 17) 1817 1818 /* ================= PORT definition for SERCOM0 peripheral ================= */ 1819 #define PIN_PA04D_SERCOM0_PAD0 _UINT32_(4) 1820 #define MUX_PA04D_SERCOM0_PAD0 _UINT32_(3) 1821 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 1822 #define PORT_PA04D_SERCOM0_PAD0 (_UINT32_(1) << 4) 1823 1824 #define PIN_PC17D_SERCOM0_PAD0 _UINT32_(81) 1825 #define MUX_PC17D_SERCOM0_PAD0 _UINT32_(3) 1826 #define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) 1827 #define PORT_PC17D_SERCOM0_PAD0 (_UINT32_(1) << 17) 1828 1829 #define PIN_PA08C_SERCOM0_PAD0 _UINT32_(8) 1830 #define MUX_PA08C_SERCOM0_PAD0 _UINT32_(2) 1831 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 1832 #define PORT_PA08C_SERCOM0_PAD0 (_UINT32_(1) << 8) 1833 1834 #define PIN_PA05D_SERCOM0_PAD1 _UINT32_(5) 1835 #define MUX_PA05D_SERCOM0_PAD1 _UINT32_(3) 1836 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 1837 #define PORT_PA05D_SERCOM0_PAD1 (_UINT32_(1) << 5) 1838 1839 #define PIN_PC16D_SERCOM0_PAD1 _UINT32_(80) 1840 #define MUX_PC16D_SERCOM0_PAD1 _UINT32_(3) 1841 #define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) 1842 #define PORT_PC16D_SERCOM0_PAD1 (_UINT32_(1) << 16) 1843 1844 #define PIN_PA09C_SERCOM0_PAD1 _UINT32_(9) 1845 #define MUX_PA09C_SERCOM0_PAD1 _UINT32_(2) 1846 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 1847 #define PORT_PA09C_SERCOM0_PAD1 (_UINT32_(1) << 9) 1848 1849 #define PIN_PA06D_SERCOM0_PAD2 _UINT32_(6) 1850 #define MUX_PA06D_SERCOM0_PAD2 _UINT32_(3) 1851 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 1852 #define PORT_PA06D_SERCOM0_PAD2 (_UINT32_(1) << 6) 1853 1854 #define PIN_PA10C_SERCOM0_PAD2 _UINT32_(10) 1855 #define MUX_PA10C_SERCOM0_PAD2 _UINT32_(2) 1856 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 1857 #define PORT_PA10C_SERCOM0_PAD2 (_UINT32_(1) << 10) 1858 1859 #define PIN_PA07D_SERCOM0_PAD3 _UINT32_(7) 1860 #define MUX_PA07D_SERCOM0_PAD3 _UINT32_(3) 1861 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 1862 #define PORT_PA07D_SERCOM0_PAD3 (_UINT32_(1) << 7) 1863 1864 #define PIN_PA11C_SERCOM0_PAD3 _UINT32_(11) 1865 #define MUX_PA11C_SERCOM0_PAD3 _UINT32_(2) 1866 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 1867 #define PORT_PA11C_SERCOM0_PAD3 (_UINT32_(1) << 11) 1868 1869 /* ================= PORT definition for SERCOM1 peripheral ================= */ 1870 #define PIN_PA00D_SERCOM1_PAD0 _UINT32_(0) 1871 #define MUX_PA00D_SERCOM1_PAD0 _UINT32_(3) 1872 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 1873 #define PORT_PA00D_SERCOM1_PAD0 (_UINT32_(1) << 0) 1874 1875 #define PIN_PA16C_SERCOM1_PAD0 _UINT32_(16) 1876 #define MUX_PA16C_SERCOM1_PAD0 _UINT32_(2) 1877 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 1878 #define PORT_PA16C_SERCOM1_PAD0 (_UINT32_(1) << 16) 1879 1880 #define PIN_PC27C_SERCOM1_PAD0 _UINT32_(91) 1881 #define MUX_PC27C_SERCOM1_PAD0 _UINT32_(2) 1882 #define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) 1883 #define PORT_PC27C_SERCOM1_PAD0 (_UINT32_(1) << 27) 1884 1885 #define PIN_PA01D_SERCOM1_PAD1 _UINT32_(1) 1886 #define MUX_PA01D_SERCOM1_PAD1 _UINT32_(3) 1887 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 1888 #define PORT_PA01D_SERCOM1_PAD1 (_UINT32_(1) << 1) 1889 1890 #define PIN_PA17C_SERCOM1_PAD1 _UINT32_(17) 1891 #define MUX_PA17C_SERCOM1_PAD1 _UINT32_(2) 1892 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 1893 #define PORT_PA17C_SERCOM1_PAD1 (_UINT32_(1) << 17) 1894 1895 #define PIN_PC28C_SERCOM1_PAD1 _UINT32_(92) 1896 #define MUX_PC28C_SERCOM1_PAD1 _UINT32_(2) 1897 #define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) 1898 #define PORT_PC28C_SERCOM1_PAD1 (_UINT32_(1) << 28) 1899 1900 #define PIN_PA30D_SERCOM1_PAD2 _UINT32_(30) 1901 #define MUX_PA30D_SERCOM1_PAD2 _UINT32_(3) 1902 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 1903 #define PORT_PA30D_SERCOM1_PAD2 (_UINT32_(1) << 30) 1904 1905 #define PIN_PA18C_SERCOM1_PAD2 _UINT32_(18) 1906 #define MUX_PA18C_SERCOM1_PAD2 _UINT32_(2) 1907 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 1908 #define PORT_PA18C_SERCOM1_PAD2 (_UINT32_(1) << 18) 1909 1910 #define PIN_PB22C_SERCOM1_PAD2 _UINT32_(54) 1911 #define MUX_PB22C_SERCOM1_PAD2 _UINT32_(2) 1912 #define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) 1913 #define PORT_PB22C_SERCOM1_PAD2 (_UINT32_(1) << 22) 1914 1915 #define PIN_PA31D_SERCOM1_PAD3 _UINT32_(31) 1916 #define MUX_PA31D_SERCOM1_PAD3 _UINT32_(3) 1917 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 1918 #define PORT_PA31D_SERCOM1_PAD3 (_UINT32_(1) << 31) 1919 1920 #define PIN_PA19C_SERCOM1_PAD3 _UINT32_(19) 1921 #define MUX_PA19C_SERCOM1_PAD3 _UINT32_(2) 1922 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 1923 #define PORT_PA19C_SERCOM1_PAD3 (_UINT32_(1) << 19) 1924 1925 #define PIN_PB23C_SERCOM1_PAD3 _UINT32_(55) 1926 #define MUX_PB23C_SERCOM1_PAD3 _UINT32_(2) 1927 #define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) 1928 #define PORT_PB23C_SERCOM1_PAD3 (_UINT32_(1) << 23) 1929 1930 /* ================= PORT definition for SERCOM2 peripheral ================= */ 1931 #define PIN_PA09D_SERCOM2_PAD0 _UINT32_(9) 1932 #define MUX_PA09D_SERCOM2_PAD0 _UINT32_(3) 1933 #define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) 1934 #define PORT_PA09D_SERCOM2_PAD0 (_UINT32_(1) << 9) 1935 1936 #define PIN_PA12C_SERCOM2_PAD0 _UINT32_(12) 1937 #define MUX_PA12C_SERCOM2_PAD0 _UINT32_(2) 1938 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 1939 #define PORT_PA12C_SERCOM2_PAD0 (_UINT32_(1) << 12) 1940 1941 #define PIN_PA08D_SERCOM2_PAD1 _UINT32_(8) 1942 #define MUX_PA08D_SERCOM2_PAD1 _UINT32_(3) 1943 #define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) 1944 #define PORT_PA08D_SERCOM2_PAD1 (_UINT32_(1) << 8) 1945 1946 #define PIN_PA13C_SERCOM2_PAD1 _UINT32_(13) 1947 #define MUX_PA13C_SERCOM2_PAD1 _UINT32_(2) 1948 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 1949 #define PORT_PA13C_SERCOM2_PAD1 (_UINT32_(1) << 13) 1950 1951 #define PIN_PA10D_SERCOM2_PAD2 _UINT32_(10) 1952 #define MUX_PA10D_SERCOM2_PAD2 _UINT32_(3) 1953 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 1954 #define PORT_PA10D_SERCOM2_PAD2 (_UINT32_(1) << 10) 1955 1956 #define PIN_PA14C_SERCOM2_PAD2 _UINT32_(14) 1957 #define MUX_PA14C_SERCOM2_PAD2 _UINT32_(2) 1958 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 1959 #define PORT_PA14C_SERCOM2_PAD2 (_UINT32_(1) << 14) 1960 1961 #define PIN_PA11D_SERCOM2_PAD3 _UINT32_(11) 1962 #define MUX_PA11D_SERCOM2_PAD3 _UINT32_(3) 1963 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 1964 #define PORT_PA11D_SERCOM2_PAD3 (_UINT32_(1) << 11) 1965 1966 #define PIN_PA15C_SERCOM2_PAD3 _UINT32_(15) 1967 #define MUX_PA15C_SERCOM2_PAD3 _UINT32_(2) 1968 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 1969 #define PORT_PA15C_SERCOM2_PAD3 (_UINT32_(1) << 15) 1970 1971 /* ================= PORT definition for SERCOM3 peripheral ================= */ 1972 #define PIN_PA17D_SERCOM3_PAD0 _UINT32_(17) 1973 #define MUX_PA17D_SERCOM3_PAD0 _UINT32_(3) 1974 #define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) 1975 #define PORT_PA17D_SERCOM3_PAD0 (_UINT32_(1) << 17) 1976 1977 #define PIN_PA22C_SERCOM3_PAD0 _UINT32_(22) 1978 #define MUX_PA22C_SERCOM3_PAD0 _UINT32_(2) 1979 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 1980 #define PORT_PA22C_SERCOM3_PAD0 (_UINT32_(1) << 22) 1981 1982 #define PIN_PB20C_SERCOM3_PAD0 _UINT32_(52) 1983 #define MUX_PB20C_SERCOM3_PAD0 _UINT32_(2) 1984 #define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) 1985 #define PORT_PB20C_SERCOM3_PAD0 (_UINT32_(1) << 20) 1986 1987 #define PIN_PA16D_SERCOM3_PAD1 _UINT32_(16) 1988 #define MUX_PA16D_SERCOM3_PAD1 _UINT32_(3) 1989 #define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) 1990 #define PORT_PA16D_SERCOM3_PAD1 (_UINT32_(1) << 16) 1991 1992 #define PIN_PA23C_SERCOM3_PAD1 _UINT32_(23) 1993 #define MUX_PA23C_SERCOM3_PAD1 _UINT32_(2) 1994 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 1995 #define PORT_PA23C_SERCOM3_PAD1 (_UINT32_(1) << 23) 1996 1997 #define PIN_PB21C_SERCOM3_PAD1 _UINT32_(53) 1998 #define MUX_PB21C_SERCOM3_PAD1 _UINT32_(2) 1999 #define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) 2000 #define PORT_PB21C_SERCOM3_PAD1 (_UINT32_(1) << 21) 2001 2002 #define PIN_PA18D_SERCOM3_PAD2 _UINT32_(18) 2003 #define MUX_PA18D_SERCOM3_PAD2 _UINT32_(3) 2004 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 2005 #define PORT_PA18D_SERCOM3_PAD2 (_UINT32_(1) << 18) 2006 2007 #define PIN_PA20D_SERCOM3_PAD2 _UINT32_(20) 2008 #define MUX_PA20D_SERCOM3_PAD2 _UINT32_(3) 2009 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 2010 #define PORT_PA20D_SERCOM3_PAD2 (_UINT32_(1) << 20) 2011 2012 #define PIN_PA24C_SERCOM3_PAD2 _UINT32_(24) 2013 #define MUX_PA24C_SERCOM3_PAD2 _UINT32_(2) 2014 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 2015 #define PORT_PA24C_SERCOM3_PAD2 (_UINT32_(1) << 24) 2016 2017 #define PIN_PA19D_SERCOM3_PAD3 _UINT32_(19) 2018 #define MUX_PA19D_SERCOM3_PAD3 _UINT32_(3) 2019 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 2020 #define PORT_PA19D_SERCOM3_PAD3 (_UINT32_(1) << 19) 2021 2022 #define PIN_PA21D_SERCOM3_PAD3 _UINT32_(21) 2023 #define MUX_PA21D_SERCOM3_PAD3 _UINT32_(3) 2024 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 2025 #define PORT_PA21D_SERCOM3_PAD3 (_UINT32_(1) << 21) 2026 2027 #define PIN_PA25C_SERCOM3_PAD3 _UINT32_(25) 2028 #define MUX_PA25C_SERCOM3_PAD3 _UINT32_(2) 2029 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 2030 #define PORT_PA25C_SERCOM3_PAD3 (_UINT32_(1) << 25) 2031 2032 /* ================= PORT definition for SERCOM4 peripheral ================= */ 2033 #define PIN_PA13D_SERCOM4_PAD0 _UINT32_(13) 2034 #define MUX_PA13D_SERCOM4_PAD0 _UINT32_(3) 2035 #define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) 2036 #define PORT_PA13D_SERCOM4_PAD0 (_UINT32_(1) << 13) 2037 2038 #define PIN_PB08D_SERCOM4_PAD0 _UINT32_(40) 2039 #define MUX_PB08D_SERCOM4_PAD0 _UINT32_(3) 2040 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 2041 #define PORT_PB08D_SERCOM4_PAD0 (_UINT32_(1) << 8) 2042 2043 #define PIN_PB12C_SERCOM4_PAD0 _UINT32_(44) 2044 #define MUX_PB12C_SERCOM4_PAD0 _UINT32_(2) 2045 #define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) 2046 #define PORT_PB12C_SERCOM4_PAD0 (_UINT32_(1) << 12) 2047 2048 #define PIN_PA12D_SERCOM4_PAD1 _UINT32_(12) 2049 #define MUX_PA12D_SERCOM4_PAD1 _UINT32_(3) 2050 #define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) 2051 #define PORT_PA12D_SERCOM4_PAD1 (_UINT32_(1) << 12) 2052 2053 #define PIN_PB09D_SERCOM4_PAD1 _UINT32_(41) 2054 #define MUX_PB09D_SERCOM4_PAD1 _UINT32_(3) 2055 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 2056 #define PORT_PB09D_SERCOM4_PAD1 (_UINT32_(1) << 9) 2057 2058 #define PIN_PB13C_SERCOM4_PAD1 _UINT32_(45) 2059 #define MUX_PB13C_SERCOM4_PAD1 _UINT32_(2) 2060 #define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) 2061 #define PORT_PB13C_SERCOM4_PAD1 (_UINT32_(1) << 13) 2062 2063 #define PIN_PA14D_SERCOM4_PAD2 _UINT32_(14) 2064 #define MUX_PA14D_SERCOM4_PAD2 _UINT32_(3) 2065 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 2066 #define PORT_PA14D_SERCOM4_PAD2 (_UINT32_(1) << 14) 2067 2068 #define PIN_PB10D_SERCOM4_PAD2 _UINT32_(42) 2069 #define MUX_PB10D_SERCOM4_PAD2 _UINT32_(3) 2070 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 2071 #define PORT_PB10D_SERCOM4_PAD2 (_UINT32_(1) << 10) 2072 2073 #define PIN_PB14C_SERCOM4_PAD2 _UINT32_(46) 2074 #define MUX_PB14C_SERCOM4_PAD2 _UINT32_(2) 2075 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) 2076 #define PORT_PB14C_SERCOM4_PAD2 (_UINT32_(1) << 14) 2077 2078 #define PIN_PB11D_SERCOM4_PAD3 _UINT32_(43) 2079 #define MUX_PB11D_SERCOM4_PAD3 _UINT32_(3) 2080 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 2081 #define PORT_PB11D_SERCOM4_PAD3 (_UINT32_(1) << 11) 2082 2083 #define PIN_PA15D_SERCOM4_PAD3 _UINT32_(15) 2084 #define MUX_PA15D_SERCOM4_PAD3 _UINT32_(3) 2085 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 2086 #define PORT_PA15D_SERCOM4_PAD3 (_UINT32_(1) << 15) 2087 2088 #define PIN_PB15C_SERCOM4_PAD3 _UINT32_(47) 2089 #define MUX_PB15C_SERCOM4_PAD3 _UINT32_(2) 2090 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) 2091 #define PORT_PB15C_SERCOM4_PAD3 (_UINT32_(1) << 15) 2092 2093 /* ================= PORT definition for SERCOM5 peripheral ================= */ 2094 #define PIN_PA23D_SERCOM5_PAD0 _UINT32_(23) 2095 #define MUX_PA23D_SERCOM5_PAD0 _UINT32_(3) 2096 #define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) 2097 #define PORT_PA23D_SERCOM5_PAD0 (_UINT32_(1) << 23) 2098 2099 #define PIN_PB02D_SERCOM5_PAD0 _UINT32_(34) 2100 #define MUX_PB02D_SERCOM5_PAD0 _UINT32_(3) 2101 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 2102 #define PORT_PB02D_SERCOM5_PAD0 (_UINT32_(1) << 2) 2103 2104 #define PIN_PB31D_SERCOM5_PAD0 _UINT32_(63) 2105 #define MUX_PB31D_SERCOM5_PAD0 _UINT32_(3) 2106 #define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) 2107 #define PORT_PB31D_SERCOM5_PAD0 (_UINT32_(1) << 31) 2108 2109 #define PIN_PB16C_SERCOM5_PAD0 _UINT32_(48) 2110 #define MUX_PB16C_SERCOM5_PAD0 _UINT32_(2) 2111 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) 2112 #define PORT_PB16C_SERCOM5_PAD0 (_UINT32_(1) << 16) 2113 2114 #define PIN_PA22D_SERCOM5_PAD1 _UINT32_(22) 2115 #define MUX_PA22D_SERCOM5_PAD1 _UINT32_(3) 2116 #define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) 2117 #define PORT_PA22D_SERCOM5_PAD1 (_UINT32_(1) << 22) 2118 2119 #define PIN_PB03D_SERCOM5_PAD1 _UINT32_(35) 2120 #define MUX_PB03D_SERCOM5_PAD1 _UINT32_(3) 2121 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 2122 #define PORT_PB03D_SERCOM5_PAD1 (_UINT32_(1) << 3) 2123 2124 #define PIN_PB30D_SERCOM5_PAD1 _UINT32_(62) 2125 #define MUX_PB30D_SERCOM5_PAD1 _UINT32_(3) 2126 #define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) 2127 #define PORT_PB30D_SERCOM5_PAD1 (_UINT32_(1) << 30) 2128 2129 #define PIN_PB17C_SERCOM5_PAD1 _UINT32_(49) 2130 #define MUX_PB17C_SERCOM5_PAD1 _UINT32_(2) 2131 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) 2132 #define PORT_PB17C_SERCOM5_PAD1 (_UINT32_(1) << 17) 2133 2134 #define PIN_PA24D_SERCOM5_PAD2 _UINT32_(24) 2135 #define MUX_PA24D_SERCOM5_PAD2 _UINT32_(3) 2136 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 2137 #define PORT_PA24D_SERCOM5_PAD2 (_UINT32_(1) << 24) 2138 2139 #define PIN_PB00D_SERCOM5_PAD2 _UINT32_(32) 2140 #define MUX_PB00D_SERCOM5_PAD2 _UINT32_(3) 2141 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) 2142 #define PORT_PB00D_SERCOM5_PAD2 (_UINT32_(1) << 0) 2143 2144 #define PIN_PB22D_SERCOM5_PAD2 _UINT32_(54) 2145 #define MUX_PB22D_SERCOM5_PAD2 _UINT32_(3) 2146 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 2147 #define PORT_PB22D_SERCOM5_PAD2 (_UINT32_(1) << 22) 2148 2149 #define PIN_PA20C_SERCOM5_PAD2 _UINT32_(20) 2150 #define MUX_PA20C_SERCOM5_PAD2 _UINT32_(2) 2151 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 2152 #define PORT_PA20C_SERCOM5_PAD2 (_UINT32_(1) << 20) 2153 2154 #define PIN_PB18C_SERCOM5_PAD2 _UINT32_(50) 2155 #define MUX_PB18C_SERCOM5_PAD2 _UINT32_(2) 2156 #define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) 2157 #define PORT_PB18C_SERCOM5_PAD2 (_UINT32_(1) << 18) 2158 2159 #define PIN_PA25D_SERCOM5_PAD3 _UINT32_(25) 2160 #define MUX_PA25D_SERCOM5_PAD3 _UINT32_(3) 2161 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 2162 #define PORT_PA25D_SERCOM5_PAD3 (_UINT32_(1) << 25) 2163 2164 #define PIN_PB01D_SERCOM5_PAD3 _UINT32_(33) 2165 #define MUX_PB01D_SERCOM5_PAD3 _UINT32_(3) 2166 #define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) 2167 #define PORT_PB01D_SERCOM5_PAD3 (_UINT32_(1) << 1) 2168 2169 #define PIN_PB23D_SERCOM5_PAD3 _UINT32_(55) 2170 #define MUX_PB23D_SERCOM5_PAD3 _UINT32_(3) 2171 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 2172 #define PORT_PB23D_SERCOM5_PAD3 (_UINT32_(1) << 23) 2173 2174 #define PIN_PA21C_SERCOM5_PAD3 _UINT32_(21) 2175 #define MUX_PA21C_SERCOM5_PAD3 _UINT32_(2) 2176 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 2177 #define PORT_PA21C_SERCOM5_PAD3 (_UINT32_(1) << 21) 2178 2179 #define PIN_PB19C_SERCOM5_PAD3 _UINT32_(51) 2180 #define MUX_PB19C_SERCOM5_PAD3 _UINT32_(2) 2181 #define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) 2182 #define PORT_PB19C_SERCOM5_PAD3 (_UINT32_(1) << 19) 2183 2184 /* ================= PORT definition for SERCOM6 peripheral ================= */ 2185 #define PIN_PC13D_SERCOM6_PAD0 _UINT32_(77) 2186 #define MUX_PC13D_SERCOM6_PAD0 _UINT32_(3) 2187 #define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) 2188 #define PORT_PC13D_SERCOM6_PAD0 (_UINT32_(1) << 13) 2189 2190 #define PIN_PC16C_SERCOM6_PAD0 _UINT32_(80) 2191 #define MUX_PC16C_SERCOM6_PAD0 _UINT32_(2) 2192 #define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) 2193 #define PORT_PC16C_SERCOM6_PAD0 (_UINT32_(1) << 16) 2194 2195 #define PIN_PC12D_SERCOM6_PAD1 _UINT32_(76) 2196 #define MUX_PC12D_SERCOM6_PAD1 _UINT32_(3) 2197 #define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) 2198 #define PORT_PC12D_SERCOM6_PAD1 (_UINT32_(1) << 12) 2199 2200 #define PIN_PC17C_SERCOM6_PAD1 _UINT32_(81) 2201 #define MUX_PC17C_SERCOM6_PAD1 _UINT32_(2) 2202 #define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) 2203 #define PORT_PC17C_SERCOM6_PAD1 (_UINT32_(1) << 17) 2204 2205 #define PIN_PC14D_SERCOM6_PAD2 _UINT32_(78) 2206 #define MUX_PC14D_SERCOM6_PAD2 _UINT32_(3) 2207 #define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) 2208 #define PORT_PC14D_SERCOM6_PAD2 (_UINT32_(1) << 14) 2209 2210 #define PIN_PC06C_SERCOM6_PAD2 _UINT32_(70) 2211 #define MUX_PC06C_SERCOM6_PAD2 _UINT32_(2) 2212 #define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) 2213 #define PORT_PC06C_SERCOM6_PAD2 (_UINT32_(1) << 6) 2214 2215 #define PIN_PC15D_SERCOM6_PAD3 _UINT32_(79) 2216 #define MUX_PC15D_SERCOM6_PAD3 _UINT32_(3) 2217 #define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) 2218 #define PORT_PC15D_SERCOM6_PAD3 (_UINT32_(1) << 15) 2219 2220 #define PIN_PC07C_SERCOM6_PAD3 _UINT32_(71) 2221 #define MUX_PC07C_SERCOM6_PAD3 _UINT32_(2) 2222 #define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) 2223 #define PORT_PC07C_SERCOM6_PAD3 (_UINT32_(1) << 7) 2224 2225 /* ================= PORT definition for SERCOM7 peripheral ================= */ 2226 #define PIN_PB21D_SERCOM7_PAD0 _UINT32_(53) 2227 #define MUX_PB21D_SERCOM7_PAD0 _UINT32_(3) 2228 #define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) 2229 #define PORT_PB21D_SERCOM7_PAD0 (_UINT32_(1) << 21) 2230 2231 #define PIN_PB30C_SERCOM7_PAD0 _UINT32_(62) 2232 #define MUX_PB30C_SERCOM7_PAD0 _UINT32_(2) 2233 #define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) 2234 #define PORT_PB30C_SERCOM7_PAD0 (_UINT32_(1) << 30) 2235 2236 #define PIN_PC12C_SERCOM7_PAD0 _UINT32_(76) 2237 #define MUX_PC12C_SERCOM7_PAD0 _UINT32_(2) 2238 #define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) 2239 #define PORT_PC12C_SERCOM7_PAD0 (_UINT32_(1) << 12) 2240 2241 #define PIN_PB20D_SERCOM7_PAD1 _UINT32_(52) 2242 #define MUX_PB20D_SERCOM7_PAD1 _UINT32_(3) 2243 #define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) 2244 #define PORT_PB20D_SERCOM7_PAD1 (_UINT32_(1) << 20) 2245 2246 #define PIN_PB31C_SERCOM7_PAD1 _UINT32_(63) 2247 #define MUX_PB31C_SERCOM7_PAD1 _UINT32_(2) 2248 #define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) 2249 #define PORT_PB31C_SERCOM7_PAD1 (_UINT32_(1) << 31) 2250 2251 #define PIN_PC13C_SERCOM7_PAD1 _UINT32_(77) 2252 #define MUX_PC13C_SERCOM7_PAD1 _UINT32_(2) 2253 #define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) 2254 #define PORT_PC13C_SERCOM7_PAD1 (_UINT32_(1) << 13) 2255 2256 #define PIN_PB18D_SERCOM7_PAD2 _UINT32_(50) 2257 #define MUX_PB18D_SERCOM7_PAD2 _UINT32_(3) 2258 #define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) 2259 #define PORT_PB18D_SERCOM7_PAD2 (_UINT32_(1) << 18) 2260 2261 #define PIN_PC14C_SERCOM7_PAD2 _UINT32_(78) 2262 #define MUX_PC14C_SERCOM7_PAD2 _UINT32_(2) 2263 #define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) 2264 #define PORT_PC14C_SERCOM7_PAD2 (_UINT32_(1) << 14) 2265 2266 #define PIN_PA30C_SERCOM7_PAD2 _UINT32_(30) 2267 #define MUX_PA30C_SERCOM7_PAD2 _UINT32_(2) 2268 #define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) 2269 #define PORT_PA30C_SERCOM7_PAD2 (_UINT32_(1) << 30) 2270 2271 #define PIN_PB19D_SERCOM7_PAD3 _UINT32_(51) 2272 #define MUX_PB19D_SERCOM7_PAD3 _UINT32_(3) 2273 #define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) 2274 #define PORT_PB19D_SERCOM7_PAD3 (_UINT32_(1) << 19) 2275 2276 #define PIN_PC15C_SERCOM7_PAD3 _UINT32_(79) 2277 #define MUX_PC15C_SERCOM7_PAD3 _UINT32_(2) 2278 #define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) 2279 #define PORT_PC15C_SERCOM7_PAD3 (_UINT32_(1) << 15) 2280 2281 #define PIN_PA31C_SERCOM7_PAD3 _UINT32_(31) 2282 #define MUX_PA31C_SERCOM7_PAD3 _UINT32_(2) 2283 #define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) 2284 #define PORT_PA31C_SERCOM7_PAD3 (_UINT32_(1) << 31) 2285 2286 /* =================== PORT definition for TC0 peripheral =================== */ 2287 #define PIN_PA04E_TC0_WO0 _UINT32_(4) 2288 #define MUX_PA04E_TC0_WO0 _UINT32_(4) 2289 #define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) 2290 #define PORT_PA04E_TC0_WO0 (_UINT32_(1) << 4) 2291 2292 #define PIN_PA08E_TC0_WO0 _UINT32_(8) 2293 #define MUX_PA08E_TC0_WO0 _UINT32_(4) 2294 #define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) 2295 #define PORT_PA08E_TC0_WO0 (_UINT32_(1) << 8) 2296 2297 #define PIN_PB30E_TC0_WO0 _UINT32_(62) 2298 #define MUX_PB30E_TC0_WO0 _UINT32_(4) 2299 #define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) 2300 #define PORT_PB30E_TC0_WO0 (_UINT32_(1) << 30) 2301 2302 #define PIN_PA05E_TC0_WO1 _UINT32_(5) 2303 #define MUX_PA05E_TC0_WO1 _UINT32_(4) 2304 #define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) 2305 #define PORT_PA05E_TC0_WO1 (_UINT32_(1) << 5) 2306 2307 #define PIN_PA09E_TC0_WO1 _UINT32_(9) 2308 #define MUX_PA09E_TC0_WO1 _UINT32_(4) 2309 #define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) 2310 #define PORT_PA09E_TC0_WO1 (_UINT32_(1) << 9) 2311 2312 #define PIN_PB31E_TC0_WO1 _UINT32_(63) 2313 #define MUX_PB31E_TC0_WO1 _UINT32_(4) 2314 #define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) 2315 #define PORT_PB31E_TC0_WO1 (_UINT32_(1) << 31) 2316 2317 /* =================== PORT definition for TC1 peripheral =================== */ 2318 #define PIN_PA06E_TC1_WO0 _UINT32_(6) 2319 #define MUX_PA06E_TC1_WO0 _UINT32_(4) 2320 #define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) 2321 #define PORT_PA06E_TC1_WO0 (_UINT32_(1) << 6) 2322 2323 #define PIN_PA10E_TC1_WO0 _UINT32_(10) 2324 #define MUX_PA10E_TC1_WO0 _UINT32_(4) 2325 #define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) 2326 #define PORT_PA10E_TC1_WO0 (_UINT32_(1) << 10) 2327 2328 #define PIN_PA07E_TC1_WO1 _UINT32_(7) 2329 #define MUX_PA07E_TC1_WO1 _UINT32_(4) 2330 #define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) 2331 #define PORT_PA07E_TC1_WO1 (_UINT32_(1) << 7) 2332 2333 #define PIN_PA11E_TC1_WO1 _UINT32_(11) 2334 #define MUX_PA11E_TC1_WO1 _UINT32_(4) 2335 #define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) 2336 #define PORT_PA11E_TC1_WO1 (_UINT32_(1) << 11) 2337 2338 /* =================== PORT definition for TC2 peripheral =================== */ 2339 #define PIN_PA12E_TC2_WO0 _UINT32_(12) 2340 #define MUX_PA12E_TC2_WO0 _UINT32_(4) 2341 #define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) 2342 #define PORT_PA12E_TC2_WO0 (_UINT32_(1) << 12) 2343 2344 #define PIN_PA16E_TC2_WO0 _UINT32_(16) 2345 #define MUX_PA16E_TC2_WO0 _UINT32_(4) 2346 #define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) 2347 #define PORT_PA16E_TC2_WO0 (_UINT32_(1) << 16) 2348 2349 #define PIN_PA00E_TC2_WO0 _UINT32_(0) 2350 #define MUX_PA00E_TC2_WO0 _UINT32_(4) 2351 #define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) 2352 #define PORT_PA00E_TC2_WO0 (_UINT32_(1) << 0) 2353 2354 #define PIN_PA01E_TC2_WO1 _UINT32_(1) 2355 #define MUX_PA01E_TC2_WO1 _UINT32_(4) 2356 #define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) 2357 #define PORT_PA01E_TC2_WO1 (_UINT32_(1) << 1) 2358 2359 #define PIN_PA13E_TC2_WO1 _UINT32_(13) 2360 #define MUX_PA13E_TC2_WO1 _UINT32_(4) 2361 #define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) 2362 #define PORT_PA13E_TC2_WO1 (_UINT32_(1) << 13) 2363 2364 #define PIN_PA17E_TC2_WO1 _UINT32_(17) 2365 #define MUX_PA17E_TC2_WO1 _UINT32_(4) 2366 #define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) 2367 #define PORT_PA17E_TC2_WO1 (_UINT32_(1) << 17) 2368 2369 /* =================== PORT definition for TC3 peripheral =================== */ 2370 #define PIN_PA18E_TC3_WO0 _UINT32_(18) 2371 #define MUX_PA18E_TC3_WO0 _UINT32_(4) 2372 #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) 2373 #define PORT_PA18E_TC3_WO0 (_UINT32_(1) << 18) 2374 2375 #define PIN_PA14E_TC3_WO0 _UINT32_(14) 2376 #define MUX_PA14E_TC3_WO0 _UINT32_(4) 2377 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) 2378 #define PORT_PA14E_TC3_WO0 (_UINT32_(1) << 14) 2379 2380 #define PIN_PA15E_TC3_WO1 _UINT32_(15) 2381 #define MUX_PA15E_TC3_WO1 _UINT32_(4) 2382 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) 2383 #define PORT_PA15E_TC3_WO1 (_UINT32_(1) << 15) 2384 2385 #define PIN_PA19E_TC3_WO1 _UINT32_(19) 2386 #define MUX_PA19E_TC3_WO1 _UINT32_(4) 2387 #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) 2388 #define PORT_PA19E_TC3_WO1 (_UINT32_(1) << 19) 2389 2390 /* =================== PORT definition for TC4 peripheral =================== */ 2391 #define PIN_PA22E_TC4_WO0 _UINT32_(22) 2392 #define MUX_PA22E_TC4_WO0 _UINT32_(4) 2393 #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) 2394 #define PORT_PA22E_TC4_WO0 (_UINT32_(1) << 22) 2395 2396 #define PIN_PB08E_TC4_WO0 _UINT32_(40) 2397 #define MUX_PB08E_TC4_WO0 _UINT32_(4) 2398 #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) 2399 #define PORT_PB08E_TC4_WO0 (_UINT32_(1) << 8) 2400 2401 #define PIN_PB12E_TC4_WO0 _UINT32_(44) 2402 #define MUX_PB12E_TC4_WO0 _UINT32_(4) 2403 #define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) 2404 #define PORT_PB12E_TC4_WO0 (_UINT32_(1) << 12) 2405 2406 #define PIN_PA23E_TC4_WO1 _UINT32_(23) 2407 #define MUX_PA23E_TC4_WO1 _UINT32_(4) 2408 #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) 2409 #define PORT_PA23E_TC4_WO1 (_UINT32_(1) << 23) 2410 2411 #define PIN_PB09E_TC4_WO1 _UINT32_(41) 2412 #define MUX_PB09E_TC4_WO1 _UINT32_(4) 2413 #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) 2414 #define PORT_PB09E_TC4_WO1 (_UINT32_(1) << 9) 2415 2416 #define PIN_PB13E_TC4_WO1 _UINT32_(45) 2417 #define MUX_PB13E_TC4_WO1 _UINT32_(4) 2418 #define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) 2419 #define PORT_PB13E_TC4_WO1 (_UINT32_(1) << 13) 2420 2421 /* =================== PORT definition for TC5 peripheral =================== */ 2422 #define PIN_PA24E_TC5_WO0 _UINT32_(24) 2423 #define MUX_PA24E_TC5_WO0 _UINT32_(4) 2424 #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) 2425 #define PORT_PA24E_TC5_WO0 (_UINT32_(1) << 24) 2426 2427 #define PIN_PB10E_TC5_WO0 _UINT32_(42) 2428 #define MUX_PB10E_TC5_WO0 _UINT32_(4) 2429 #define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) 2430 #define PORT_PB10E_TC5_WO0 (_UINT32_(1) << 10) 2431 2432 #define PIN_PB14E_TC5_WO0 _UINT32_(46) 2433 #define MUX_PB14E_TC5_WO0 _UINT32_(4) 2434 #define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) 2435 #define PORT_PB14E_TC5_WO0 (_UINT32_(1) << 14) 2436 2437 #define PIN_PA25E_TC5_WO1 _UINT32_(25) 2438 #define MUX_PA25E_TC5_WO1 _UINT32_(4) 2439 #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) 2440 #define PORT_PA25E_TC5_WO1 (_UINT32_(1) << 25) 2441 2442 #define PIN_PB11E_TC5_WO1 _UINT32_(43) 2443 #define MUX_PB11E_TC5_WO1 _UINT32_(4) 2444 #define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) 2445 #define PORT_PB11E_TC5_WO1 (_UINT32_(1) << 11) 2446 2447 #define PIN_PB15E_TC5_WO1 _UINT32_(47) 2448 #define MUX_PB15E_TC5_WO1 _UINT32_(4) 2449 #define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) 2450 #define PORT_PB15E_TC5_WO1 (_UINT32_(1) << 15) 2451 2452 /* =================== PORT definition for TC6 peripheral =================== */ 2453 #define PIN_PA30E_TC6_WO0 _UINT32_(30) 2454 #define MUX_PA30E_TC6_WO0 _UINT32_(4) 2455 #define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) 2456 #define PORT_PA30E_TC6_WO0 (_UINT32_(1) << 30) 2457 2458 #define PIN_PB02E_TC6_WO0 _UINT32_(34) 2459 #define MUX_PB02E_TC6_WO0 _UINT32_(4) 2460 #define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) 2461 #define PORT_PB02E_TC6_WO0 (_UINT32_(1) << 2) 2462 2463 #define PIN_PB16E_TC6_WO0 _UINT32_(48) 2464 #define MUX_PB16E_TC6_WO0 _UINT32_(4) 2465 #define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) 2466 #define PORT_PB16E_TC6_WO0 (_UINT32_(1) << 16) 2467 2468 #define PIN_PA31E_TC6_WO1 _UINT32_(31) 2469 #define MUX_PA31E_TC6_WO1 _UINT32_(4) 2470 #define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) 2471 #define PORT_PA31E_TC6_WO1 (_UINT32_(1) << 31) 2472 2473 #define PIN_PB03E_TC6_WO1 _UINT32_(35) 2474 #define MUX_PB03E_TC6_WO1 _UINT32_(4) 2475 #define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) 2476 #define PORT_PB03E_TC6_WO1 (_UINT32_(1) << 3) 2477 2478 #define PIN_PB17E_TC6_WO1 _UINT32_(49) 2479 #define MUX_PB17E_TC6_WO1 _UINT32_(4) 2480 #define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) 2481 #define PORT_PB17E_TC6_WO1 (_UINT32_(1) << 17) 2482 2483 /* =================== PORT definition for TC7 peripheral =================== */ 2484 #define PIN_PA20E_TC7_WO0 _UINT32_(20) 2485 #define MUX_PA20E_TC7_WO0 _UINT32_(4) 2486 #define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) 2487 #define PORT_PA20E_TC7_WO0 (_UINT32_(1) << 20) 2488 2489 #define PIN_PB00E_TC7_WO0 _UINT32_(32) 2490 #define MUX_PB00E_TC7_WO0 _UINT32_(4) 2491 #define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) 2492 #define PORT_PB00E_TC7_WO0 (_UINT32_(1) << 0) 2493 2494 #define PIN_PB22E_TC7_WO0 _UINT32_(54) 2495 #define MUX_PB22E_TC7_WO0 _UINT32_(4) 2496 #define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) 2497 #define PORT_PB22E_TC7_WO0 (_UINT32_(1) << 22) 2498 2499 #define PIN_PA21E_TC7_WO1 _UINT32_(21) 2500 #define MUX_PA21E_TC7_WO1 _UINT32_(4) 2501 #define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) 2502 #define PORT_PA21E_TC7_WO1 (_UINT32_(1) << 21) 2503 2504 #define PIN_PB01E_TC7_WO1 _UINT32_(33) 2505 #define MUX_PB01E_TC7_WO1 _UINT32_(4) 2506 #define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) 2507 #define PORT_PB01E_TC7_WO1 (_UINT32_(1) << 1) 2508 2509 #define PIN_PB23E_TC7_WO1 _UINT32_(55) 2510 #define MUX_PB23E_TC7_WO1 _UINT32_(4) 2511 #define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) 2512 #define PORT_PB23E_TC7_WO1 (_UINT32_(1) << 23) 2513 2514 /* ================== PORT definition for TCC0 peripheral =================== */ 2515 #define PIN_PA20G_TCC0_WO0 _UINT32_(20) 2516 #define MUX_PA20G_TCC0_WO0 _UINT32_(6) 2517 #define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) 2518 #define PORT_PA20G_TCC0_WO0 (_UINT32_(1) << 20) 2519 2520 #define PIN_PB12G_TCC0_WO0 _UINT32_(44) 2521 #define MUX_PB12G_TCC0_WO0 _UINT32_(6) 2522 #define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) 2523 #define PORT_PB12G_TCC0_WO0 (_UINT32_(1) << 12) 2524 2525 #define PIN_PA08F_TCC0_WO0 _UINT32_(8) 2526 #define MUX_PA08F_TCC0_WO0 _UINT32_(5) 2527 #define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) 2528 #define PORT_PA08F_TCC0_WO0 (_UINT32_(1) << 8) 2529 2530 #define PIN_PC16F_TCC0_WO0 _UINT32_(80) 2531 #define MUX_PC16F_TCC0_WO0 _UINT32_(5) 2532 #define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) 2533 #define PORT_PC16F_TCC0_WO0 (_UINT32_(1) << 16) 2534 2535 #define PIN_PA21G_TCC0_WO1 _UINT32_(21) 2536 #define MUX_PA21G_TCC0_WO1 _UINT32_(6) 2537 #define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) 2538 #define PORT_PA21G_TCC0_WO1 (_UINT32_(1) << 21) 2539 2540 #define PIN_PB13G_TCC0_WO1 _UINT32_(45) 2541 #define MUX_PB13G_TCC0_WO1 _UINT32_(6) 2542 #define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) 2543 #define PORT_PB13G_TCC0_WO1 (_UINT32_(1) << 13) 2544 2545 #define PIN_PA09F_TCC0_WO1 _UINT32_(9) 2546 #define MUX_PA09F_TCC0_WO1 _UINT32_(5) 2547 #define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) 2548 #define PORT_PA09F_TCC0_WO1 (_UINT32_(1) << 9) 2549 2550 #define PIN_PC17F_TCC0_WO1 _UINT32_(81) 2551 #define MUX_PC17F_TCC0_WO1 _UINT32_(5) 2552 #define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) 2553 #define PORT_PC17F_TCC0_WO1 (_UINT32_(1) << 17) 2554 2555 #define PIN_PA22G_TCC0_WO2 _UINT32_(22) 2556 #define MUX_PA22G_TCC0_WO2 _UINT32_(6) 2557 #define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) 2558 #define PORT_PA22G_TCC0_WO2 (_UINT32_(1) << 22) 2559 2560 #define PIN_PB14G_TCC0_WO2 _UINT32_(46) 2561 #define MUX_PB14G_TCC0_WO2 _UINT32_(6) 2562 #define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) 2563 #define PORT_PB14G_TCC0_WO2 (_UINT32_(1) << 14) 2564 2565 #define PIN_PA10F_TCC0_WO2 _UINT32_(10) 2566 #define MUX_PA10F_TCC0_WO2 _UINT32_(5) 2567 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 2568 #define PORT_PA10F_TCC0_WO2 (_UINT32_(1) << 10) 2569 2570 #define PIN_PC12F_TCC0_WO2 _UINT32_(76) 2571 #define MUX_PC12F_TCC0_WO2 _UINT32_(5) 2572 #define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) 2573 #define PORT_PC12F_TCC0_WO2 (_UINT32_(1) << 12) 2574 2575 #define PIN_PA23G_TCC0_WO3 _UINT32_(23) 2576 #define MUX_PA23G_TCC0_WO3 _UINT32_(6) 2577 #define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) 2578 #define PORT_PA23G_TCC0_WO3 (_UINT32_(1) << 23) 2579 2580 #define PIN_PB15G_TCC0_WO3 _UINT32_(47) 2581 #define MUX_PB15G_TCC0_WO3 _UINT32_(6) 2582 #define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) 2583 #define PORT_PB15G_TCC0_WO3 (_UINT32_(1) << 15) 2584 2585 #define PIN_PA11F_TCC0_WO3 _UINT32_(11) 2586 #define MUX_PA11F_TCC0_WO3 _UINT32_(5) 2587 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 2588 #define PORT_PA11F_TCC0_WO3 (_UINT32_(1) << 11) 2589 2590 #define PIN_PC13F_TCC0_WO3 _UINT32_(77) 2591 #define MUX_PC13F_TCC0_WO3 _UINT32_(5) 2592 #define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) 2593 #define PORT_PC13F_TCC0_WO3 (_UINT32_(1) << 13) 2594 2595 #define PIN_PA16G_TCC0_WO4 _UINT32_(16) 2596 #define MUX_PA16G_TCC0_WO4 _UINT32_(6) 2597 #define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) 2598 #define PORT_PA16G_TCC0_WO4 (_UINT32_(1) << 16) 2599 2600 #define PIN_PB16G_TCC0_WO4 _UINT32_(48) 2601 #define MUX_PB16G_TCC0_WO4 _UINT32_(6) 2602 #define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) 2603 #define PORT_PB16G_TCC0_WO4 (_UINT32_(1) << 16) 2604 2605 #define PIN_PB10F_TCC0_WO4 _UINT32_(42) 2606 #define MUX_PB10F_TCC0_WO4 _UINT32_(5) 2607 #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) 2608 #define PORT_PB10F_TCC0_WO4 (_UINT32_(1) << 10) 2609 2610 #define PIN_PC14F_TCC0_WO4 _UINT32_(78) 2611 #define MUX_PC14F_TCC0_WO4 _UINT32_(5) 2612 #define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) 2613 #define PORT_PC14F_TCC0_WO4 (_UINT32_(1) << 14) 2614 2615 #define PIN_PA17G_TCC0_WO5 _UINT32_(17) 2616 #define MUX_PA17G_TCC0_WO5 _UINT32_(6) 2617 #define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) 2618 #define PORT_PA17G_TCC0_WO5 (_UINT32_(1) << 17) 2619 2620 #define PIN_PB17G_TCC0_WO5 _UINT32_(49) 2621 #define MUX_PB17G_TCC0_WO5 _UINT32_(6) 2622 #define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) 2623 #define PORT_PB17G_TCC0_WO5 (_UINT32_(1) << 17) 2624 2625 #define PIN_PB11F_TCC0_WO5 _UINT32_(43) 2626 #define MUX_PB11F_TCC0_WO5 _UINT32_(5) 2627 #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) 2628 #define PORT_PB11F_TCC0_WO5 (_UINT32_(1) << 11) 2629 2630 #define PIN_PC15F_TCC0_WO5 _UINT32_(79) 2631 #define MUX_PC15F_TCC0_WO5 _UINT32_(5) 2632 #define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) 2633 #define PORT_PC15F_TCC0_WO5 (_UINT32_(1) << 15) 2634 2635 #define PIN_PA18G_TCC0_WO6 _UINT32_(18) 2636 #define MUX_PA18G_TCC0_WO6 _UINT32_(6) 2637 #define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) 2638 #define PORT_PA18G_TCC0_WO6 (_UINT32_(1) << 18) 2639 2640 #define PIN_PB30G_TCC0_WO6 _UINT32_(62) 2641 #define MUX_PB30G_TCC0_WO6 _UINT32_(6) 2642 #define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) 2643 #define PORT_PB30G_TCC0_WO6 (_UINT32_(1) << 30) 2644 2645 #define PIN_PA12F_TCC0_WO6 _UINT32_(12) 2646 #define MUX_PA12F_TCC0_WO6 _UINT32_(5) 2647 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) 2648 #define PORT_PA12F_TCC0_WO6 (_UINT32_(1) << 12) 2649 2650 #define PIN_PA19G_TCC0_WO7 _UINT32_(19) 2651 #define MUX_PA19G_TCC0_WO7 _UINT32_(6) 2652 #define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) 2653 #define PORT_PA19G_TCC0_WO7 (_UINT32_(1) << 19) 2654 2655 #define PIN_PB31G_TCC0_WO7 _UINT32_(63) 2656 #define MUX_PB31G_TCC0_WO7 _UINT32_(6) 2657 #define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) 2658 #define PORT_PB31G_TCC0_WO7 (_UINT32_(1) << 31) 2659 2660 #define PIN_PA13F_TCC0_WO7 _UINT32_(13) 2661 #define MUX_PA13F_TCC0_WO7 _UINT32_(5) 2662 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) 2663 #define PORT_PA13F_TCC0_WO7 (_UINT32_(1) << 13) 2664 2665 /* ================== PORT definition for TCC1 peripheral =================== */ 2666 #define PIN_PB10G_TCC1_WO0 _UINT32_(42) 2667 #define MUX_PB10G_TCC1_WO0 _UINT32_(6) 2668 #define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) 2669 #define PORT_PB10G_TCC1_WO0 (_UINT32_(1) << 10) 2670 2671 #define PIN_PC14G_TCC1_WO0 _UINT32_(78) 2672 #define MUX_PC14G_TCC1_WO0 _UINT32_(6) 2673 #define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) 2674 #define PORT_PC14G_TCC1_WO0 (_UINT32_(1) << 14) 2675 2676 #define PIN_PA16F_TCC1_WO0 _UINT32_(16) 2677 #define MUX_PA16F_TCC1_WO0 _UINT32_(5) 2678 #define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) 2679 #define PORT_PA16F_TCC1_WO0 (_UINT32_(1) << 16) 2680 2681 #define PIN_PB18F_TCC1_WO0 _UINT32_(50) 2682 #define MUX_PB18F_TCC1_WO0 _UINT32_(5) 2683 #define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) 2684 #define PORT_PB18F_TCC1_WO0 (_UINT32_(1) << 18) 2685 2686 #define PIN_PB11G_TCC1_WO1 _UINT32_(43) 2687 #define MUX_PB11G_TCC1_WO1 _UINT32_(6) 2688 #define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) 2689 #define PORT_PB11G_TCC1_WO1 (_UINT32_(1) << 11) 2690 2691 #define PIN_PC15G_TCC1_WO1 _UINT32_(79) 2692 #define MUX_PC15G_TCC1_WO1 _UINT32_(6) 2693 #define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) 2694 #define PORT_PC15G_TCC1_WO1 (_UINT32_(1) << 15) 2695 2696 #define PIN_PA17F_TCC1_WO1 _UINT32_(17) 2697 #define MUX_PA17F_TCC1_WO1 _UINT32_(5) 2698 #define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) 2699 #define PORT_PA17F_TCC1_WO1 (_UINT32_(1) << 17) 2700 2701 #define PIN_PB19F_TCC1_WO1 _UINT32_(51) 2702 #define MUX_PB19F_TCC1_WO1 _UINT32_(5) 2703 #define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) 2704 #define PORT_PB19F_TCC1_WO1 (_UINT32_(1) << 19) 2705 2706 #define PIN_PA12G_TCC1_WO2 _UINT32_(12) 2707 #define MUX_PA12G_TCC1_WO2 _UINT32_(6) 2708 #define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) 2709 #define PORT_PA12G_TCC1_WO2 (_UINT32_(1) << 12) 2710 2711 #define PIN_PA14G_TCC1_WO2 _UINT32_(14) 2712 #define MUX_PA14G_TCC1_WO2 _UINT32_(6) 2713 #define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) 2714 #define PORT_PA14G_TCC1_WO2 (_UINT32_(1) << 14) 2715 2716 #define PIN_PA18F_TCC1_WO2 _UINT32_(18) 2717 #define MUX_PA18F_TCC1_WO2 _UINT32_(5) 2718 #define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) 2719 #define PORT_PA18F_TCC1_WO2 (_UINT32_(1) << 18) 2720 2721 #define PIN_PB20F_TCC1_WO2 _UINT32_(52) 2722 #define MUX_PB20F_TCC1_WO2 _UINT32_(5) 2723 #define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) 2724 #define PORT_PB20F_TCC1_WO2 (_UINT32_(1) << 20) 2725 2726 #define PIN_PA13G_TCC1_WO3 _UINT32_(13) 2727 #define MUX_PA13G_TCC1_WO3 _UINT32_(6) 2728 #define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) 2729 #define PORT_PA13G_TCC1_WO3 (_UINT32_(1) << 13) 2730 2731 #define PIN_PA15G_TCC1_WO3 _UINT32_(15) 2732 #define MUX_PA15G_TCC1_WO3 _UINT32_(6) 2733 #define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) 2734 #define PORT_PA15G_TCC1_WO3 (_UINT32_(1) << 15) 2735 2736 #define PIN_PA19F_TCC1_WO3 _UINT32_(19) 2737 #define MUX_PA19F_TCC1_WO3 _UINT32_(5) 2738 #define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) 2739 #define PORT_PA19F_TCC1_WO3 (_UINT32_(1) << 19) 2740 2741 #define PIN_PB21F_TCC1_WO3 _UINT32_(53) 2742 #define MUX_PB21F_TCC1_WO3 _UINT32_(5) 2743 #define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) 2744 #define PORT_PB21F_TCC1_WO3 (_UINT32_(1) << 21) 2745 2746 #define PIN_PA08G_TCC1_WO4 _UINT32_(8) 2747 #define MUX_PA08G_TCC1_WO4 _UINT32_(6) 2748 #define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) 2749 #define PORT_PA08G_TCC1_WO4 (_UINT32_(1) << 8) 2750 2751 #define PIN_PA20F_TCC1_WO4 _UINT32_(20) 2752 #define MUX_PA20F_TCC1_WO4 _UINT32_(5) 2753 #define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) 2754 #define PORT_PA20F_TCC1_WO4 (_UINT32_(1) << 20) 2755 2756 #define PIN_PA09G_TCC1_WO5 _UINT32_(9) 2757 #define MUX_PA09G_TCC1_WO5 _UINT32_(6) 2758 #define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) 2759 #define PORT_PA09G_TCC1_WO5 (_UINT32_(1) << 9) 2760 2761 #define PIN_PA21F_TCC1_WO5 _UINT32_(21) 2762 #define MUX_PA21F_TCC1_WO5 _UINT32_(5) 2763 #define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) 2764 #define PORT_PA21F_TCC1_WO5 (_UINT32_(1) << 21) 2765 2766 #define PIN_PA10G_TCC1_WO6 _UINT32_(10) 2767 #define MUX_PA10G_TCC1_WO6 _UINT32_(6) 2768 #define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) 2769 #define PORT_PA10G_TCC1_WO6 (_UINT32_(1) << 10) 2770 2771 #define PIN_PC12G_TCC1_WO6 _UINT32_(76) 2772 #define MUX_PC12G_TCC1_WO6 _UINT32_(6) 2773 #define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) 2774 #define PORT_PC12G_TCC1_WO6 (_UINT32_(1) << 12) 2775 2776 #define PIN_PA22F_TCC1_WO6 _UINT32_(22) 2777 #define MUX_PA22F_TCC1_WO6 _UINT32_(5) 2778 #define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) 2779 #define PORT_PA22F_TCC1_WO6 (_UINT32_(1) << 22) 2780 2781 #define PIN_PA11G_TCC1_WO7 _UINT32_(11) 2782 #define MUX_PA11G_TCC1_WO7 _UINT32_(6) 2783 #define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) 2784 #define PORT_PA11G_TCC1_WO7 (_UINT32_(1) << 11) 2785 2786 #define PIN_PC13G_TCC1_WO7 _UINT32_(77) 2787 #define MUX_PC13G_TCC1_WO7 _UINT32_(6) 2788 #define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) 2789 #define PORT_PC13G_TCC1_WO7 (_UINT32_(1) << 13) 2790 2791 #define PIN_PA23F_TCC1_WO7 _UINT32_(23) 2792 #define MUX_PA23F_TCC1_WO7 _UINT32_(5) 2793 #define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) 2794 #define PORT_PA23F_TCC1_WO7 (_UINT32_(1) << 23) 2795 2796 /* ================== PORT definition for TCC2 peripheral =================== */ 2797 #define PIN_PA14F_TCC2_WO0 _UINT32_(14) 2798 #define MUX_PA14F_TCC2_WO0 _UINT32_(5) 2799 #define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) 2800 #define PORT_PA14F_TCC2_WO0 (_UINT32_(1) << 14) 2801 2802 #define PIN_PA30F_TCC2_WO0 _UINT32_(30) 2803 #define MUX_PA30F_TCC2_WO0 _UINT32_(5) 2804 #define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) 2805 #define PORT_PA30F_TCC2_WO0 (_UINT32_(1) << 30) 2806 2807 #define PIN_PA15F_TCC2_WO1 _UINT32_(15) 2808 #define MUX_PA15F_TCC2_WO1 _UINT32_(5) 2809 #define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) 2810 #define PORT_PA15F_TCC2_WO1 (_UINT32_(1) << 15) 2811 2812 #define PIN_PA31F_TCC2_WO1 _UINT32_(31) 2813 #define MUX_PA31F_TCC2_WO1 _UINT32_(5) 2814 #define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) 2815 #define PORT_PA31F_TCC2_WO1 (_UINT32_(1) << 31) 2816 2817 #define PIN_PA24F_TCC2_WO2 _UINT32_(24) 2818 #define MUX_PA24F_TCC2_WO2 _UINT32_(5) 2819 #define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) 2820 #define PORT_PA24F_TCC2_WO2 (_UINT32_(1) << 24) 2821 2822 #define PIN_PB02F_TCC2_WO2 _UINT32_(34) 2823 #define MUX_PB02F_TCC2_WO2 _UINT32_(5) 2824 #define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) 2825 #define PORT_PB02F_TCC2_WO2 (_UINT32_(1) << 2) 2826 2827 /* ================== PORT definition for TCC3 peripheral =================== */ 2828 #define PIN_PB12F_TCC3_WO0 _UINT32_(44) 2829 #define MUX_PB12F_TCC3_WO0 _UINT32_(5) 2830 #define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) 2831 #define PORT_PB12F_TCC3_WO0 (_UINT32_(1) << 12) 2832 2833 #define PIN_PB16F_TCC3_WO0 _UINT32_(48) 2834 #define MUX_PB16F_TCC3_WO0 _UINT32_(5) 2835 #define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) 2836 #define PORT_PB16F_TCC3_WO0 (_UINT32_(1) << 16) 2837 2838 #define PIN_PB13F_TCC3_WO1 _UINT32_(45) 2839 #define MUX_PB13F_TCC3_WO1 _UINT32_(5) 2840 #define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) 2841 #define PORT_PB13F_TCC3_WO1 (_UINT32_(1) << 13) 2842 2843 #define PIN_PB17F_TCC3_WO1 _UINT32_(49) 2844 #define MUX_PB17F_TCC3_WO1 _UINT32_(5) 2845 #define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) 2846 #define PORT_PB17F_TCC3_WO1 (_UINT32_(1) << 17) 2847 2848 /* ================== PORT definition for TCC4 peripheral =================== */ 2849 #define PIN_PB14F_TCC4_WO0 _UINT32_(46) 2850 #define MUX_PB14F_TCC4_WO0 _UINT32_(5) 2851 #define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) 2852 #define PORT_PB14F_TCC4_WO0 (_UINT32_(1) << 14) 2853 2854 #define PIN_PB30F_TCC4_WO0 _UINT32_(62) 2855 #define MUX_PB30F_TCC4_WO0 _UINT32_(5) 2856 #define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) 2857 #define PORT_PB30F_TCC4_WO0 (_UINT32_(1) << 30) 2858 2859 #define PIN_PB15F_TCC4_WO1 _UINT32_(47) 2860 #define MUX_PB15F_TCC4_WO1 _UINT32_(5) 2861 #define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) 2862 #define PORT_PB15F_TCC4_WO1 (_UINT32_(1) << 15) 2863 2864 #define PIN_PB31F_TCC4_WO1 _UINT32_(63) 2865 #define MUX_PB31F_TCC4_WO1 _UINT32_(5) 2866 #define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) 2867 #define PORT_PB31F_TCC4_WO1 (_UINT32_(1) << 31) 2868 2869 /* =================== PORT definition for USB peripheral =================== */ 2870 #define PIN_PA24H_USB_DM _UINT32_(24) 2871 #define MUX_PA24H_USB_DM _UINT32_(7) 2872 #define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) 2873 #define PORT_PA24H_USB_DM (_UINT32_(1) << 24) 2874 2875 #define PIN_PA25H_USB_DP _UINT32_(25) 2876 #define MUX_PA25H_USB_DP _UINT32_(7) 2877 #define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) 2878 #define PORT_PA25H_USB_DP (_UINT32_(1) << 25) 2879 2880 #define PIN_PA23H_USB_SOF_1KHZ _UINT32_(23) 2881 #define MUX_PA23H_USB_SOF_1KHZ _UINT32_(7) 2882 #define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) 2883 #define PORT_PA23H_USB_SOF_1KHZ (_UINT32_(1) << 23) 2884 2885 #define PIN_PB22H_USB_SOF_1KHZ _UINT32_(54) 2886 #define MUX_PB22H_USB_SOF_1KHZ _UINT32_(7) 2887 #define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) 2888 #define PORT_PB22H_USB_SOF_1KHZ (_UINT32_(1) << 22) 2889 2890 /* ================== PORT definition for TPIU peripheral =================== */ 2891 #define PIN_PC27H_TPIU_TRACECLK _UINT32_(91) 2892 #define MUX_PC27H_TPIU_TRACECLK _UINT32_(7) 2893 #define PINMUX_PC27H_TPIU_TRACECLK ((PIN_PC27H_TPIU_TRACECLK << 16) | MUX_PC27H_TPIU_TRACECLK) 2894 #define PORT_PC27H_TPIU_TRACECLK (_UINT32_(1) << 27) 2895 2896 #define PIN_PC28H_TPIU_TRACED0 _UINT32_(92) 2897 #define MUX_PC28H_TPIU_TRACED0 _UINT32_(7) 2898 #define PINMUX_PC28H_TPIU_TRACED0 ((PIN_PC28H_TPIU_TRACED0 << 16) | MUX_PC28H_TPIU_TRACED0) 2899 #define PORT_PC28H_TPIU_TRACED0 (_UINT32_(1) << 28) 2900 2901 2902 2903 #endif /* _PIC32CX1025SG41080_GPIO_H_ */ 2904 2905
