1 /***************************************************************************//** 2 * \file cyhal_xmc7200_272_bga.h 3 * 4 * \brief 5 * XMC7200 device GPIO HAL header for 272-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_XMC7200_272_BGA_H_ 28 #define _CYHAL_XMC7200_272_BGA_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_xmc7200_272_bga XMC7200 272-BGA 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the XMC7200 272-BGA package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint16_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint16_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint16_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 272-BGA package for the XMC7200 series. */ 52 typedef enum { 53 NC = 0xFFFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 60 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 61 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 62 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 63 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 64 P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 65 66 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 67 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 68 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 69 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 70 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 71 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 72 P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 73 P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 74 75 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 76 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 77 P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 78 P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 79 P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 80 P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 81 P3_6 = CYHAL_GET_GPIO(CYHAL_PORT_3, 6), //!< Port 3 Pin 6 82 P3_7 = CYHAL_GET_GPIO(CYHAL_PORT_3, 7), //!< Port 3 Pin 7 83 84 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 85 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 86 P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2 87 P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3 88 P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4), //!< Port 4 Pin 4 89 90 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 91 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 92 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 93 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 94 P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 95 P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 96 97 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 98 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 99 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 100 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 101 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 102 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 103 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 104 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 105 106 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 107 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 108 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 109 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 110 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 111 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 112 P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 113 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 114 115 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 116 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 117 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 118 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 119 P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 120 121 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 122 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 123 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 124 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 125 126 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 127 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 128 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 129 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 130 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 131 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 132 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 133 P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 134 135 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 136 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 137 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 138 139 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 140 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 141 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 142 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 143 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 144 P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 145 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 146 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 147 148 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 149 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 150 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 151 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 152 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 153 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 154 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 155 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 156 157 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 158 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 159 P14_2 = CYHAL_GET_GPIO(CYHAL_PORT_14, 2), //!< Port 14 Pin 2 160 P14_3 = CYHAL_GET_GPIO(CYHAL_PORT_14, 3), //!< Port 14 Pin 3 161 P14_4 = CYHAL_GET_GPIO(CYHAL_PORT_14, 4), //!< Port 14 Pin 4 162 P14_5 = CYHAL_GET_GPIO(CYHAL_PORT_14, 5), //!< Port 14 Pin 5 163 P14_6 = CYHAL_GET_GPIO(CYHAL_PORT_14, 6), //!< Port 14 Pin 6 164 P14_7 = CYHAL_GET_GPIO(CYHAL_PORT_14, 7), //!< Port 14 Pin 7 165 166 P15_0 = CYHAL_GET_GPIO(CYHAL_PORT_15, 0), //!< Port 15 Pin 0 167 P15_1 = CYHAL_GET_GPIO(CYHAL_PORT_15, 1), //!< Port 15 Pin 1 168 P15_2 = CYHAL_GET_GPIO(CYHAL_PORT_15, 2), //!< Port 15 Pin 2 169 P15_3 = CYHAL_GET_GPIO(CYHAL_PORT_15, 3), //!< Port 15 Pin 3 170 171 P16_0 = CYHAL_GET_GPIO(CYHAL_PORT_16, 0), //!< Port 16 Pin 0 172 P16_1 = CYHAL_GET_GPIO(CYHAL_PORT_16, 1), //!< Port 16 Pin 1 173 P16_2 = CYHAL_GET_GPIO(CYHAL_PORT_16, 2), //!< Port 16 Pin 2 174 P16_3 = CYHAL_GET_GPIO(CYHAL_PORT_16, 3), //!< Port 16 Pin 3 175 P16_4 = CYHAL_GET_GPIO(CYHAL_PORT_16, 4), //!< Port 16 Pin 4 176 P16_5 = CYHAL_GET_GPIO(CYHAL_PORT_16, 5), //!< Port 16 Pin 5 177 P16_6 = CYHAL_GET_GPIO(CYHAL_PORT_16, 6), //!< Port 16 Pin 6 178 P16_7 = CYHAL_GET_GPIO(CYHAL_PORT_16, 7), //!< Port 16 Pin 7 179 180 P17_0 = CYHAL_GET_GPIO(CYHAL_PORT_17, 0), //!< Port 17 Pin 0 181 P17_1 = CYHAL_GET_GPIO(CYHAL_PORT_17, 1), //!< Port 17 Pin 1 182 P17_2 = CYHAL_GET_GPIO(CYHAL_PORT_17, 2), //!< Port 17 Pin 2 183 P17_3 = CYHAL_GET_GPIO(CYHAL_PORT_17, 3), //!< Port 17 Pin 3 184 P17_4 = CYHAL_GET_GPIO(CYHAL_PORT_17, 4), //!< Port 17 Pin 4 185 P17_5 = CYHAL_GET_GPIO(CYHAL_PORT_17, 5), //!< Port 17 Pin 5 186 P17_6 = CYHAL_GET_GPIO(CYHAL_PORT_17, 6), //!< Port 17 Pin 6 187 P17_7 = CYHAL_GET_GPIO(CYHAL_PORT_17, 7), //!< Port 17 Pin 7 188 189 P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0 190 P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1 191 P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2), //!< Port 18 Pin 2 192 P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3), //!< Port 18 Pin 3 193 P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4), //!< Port 18 Pin 4 194 P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5), //!< Port 18 Pin 5 195 P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6), //!< Port 18 Pin 6 196 P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7), //!< Port 18 Pin 7 197 198 P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0 199 P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1 200 P19_2 = CYHAL_GET_GPIO(CYHAL_PORT_19, 2), //!< Port 19 Pin 2 201 P19_3 = CYHAL_GET_GPIO(CYHAL_PORT_19, 3), //!< Port 19 Pin 3 202 P19_4 = CYHAL_GET_GPIO(CYHAL_PORT_19, 4), //!< Port 19 Pin 4 203 204 P20_0 = CYHAL_GET_GPIO(CYHAL_PORT_20, 0), //!< Port 20 Pin 0 205 P20_1 = CYHAL_GET_GPIO(CYHAL_PORT_20, 1), //!< Port 20 Pin 1 206 P20_2 = CYHAL_GET_GPIO(CYHAL_PORT_20, 2), //!< Port 20 Pin 2 207 P20_3 = CYHAL_GET_GPIO(CYHAL_PORT_20, 3), //!< Port 20 Pin 3 208 P20_4 = CYHAL_GET_GPIO(CYHAL_PORT_20, 4), //!< Port 20 Pin 4 209 P20_5 = CYHAL_GET_GPIO(CYHAL_PORT_20, 5), //!< Port 20 Pin 5 210 P20_6 = CYHAL_GET_GPIO(CYHAL_PORT_20, 6), //!< Port 20 Pin 6 211 P20_7 = CYHAL_GET_GPIO(CYHAL_PORT_20, 7), //!< Port 20 Pin 7 212 213 P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0), //!< Port 21 Pin 0 214 P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1), //!< Port 21 Pin 1 215 P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2), //!< Port 21 Pin 2 216 P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3), //!< Port 21 Pin 3 217 P21_4 = CYHAL_GET_GPIO(CYHAL_PORT_21, 4), //!< Port 21 Pin 4 218 P21_5 = CYHAL_GET_GPIO(CYHAL_PORT_21, 5), //!< Port 21 Pin 5 219 P21_6 = CYHAL_GET_GPIO(CYHAL_PORT_21, 6), //!< Port 21 Pin 6 220 P21_7 = CYHAL_GET_GPIO(CYHAL_PORT_21, 7), //!< Port 21 Pin 7 221 222 P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1), //!< Port 22 Pin 1 223 P22_2 = CYHAL_GET_GPIO(CYHAL_PORT_22, 2), //!< Port 22 Pin 2 224 P22_3 = CYHAL_GET_GPIO(CYHAL_PORT_22, 3), //!< Port 22 Pin 3 225 P22_4 = CYHAL_GET_GPIO(CYHAL_PORT_22, 4), //!< Port 22 Pin 4 226 P22_5 = CYHAL_GET_GPIO(CYHAL_PORT_22, 5), //!< Port 22 Pin 5 227 P22_6 = CYHAL_GET_GPIO(CYHAL_PORT_22, 6), //!< Port 22 Pin 6 228 P22_7 = CYHAL_GET_GPIO(CYHAL_PORT_22, 7), //!< Port 22 Pin 7 229 230 P23_0 = CYHAL_GET_GPIO(CYHAL_PORT_23, 0), //!< Port 23 Pin 0 231 P23_1 = CYHAL_GET_GPIO(CYHAL_PORT_23, 1), //!< Port 23 Pin 1 232 P23_2 = CYHAL_GET_GPIO(CYHAL_PORT_23, 2), //!< Port 23 Pin 2 233 P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3), //!< Port 23 Pin 3 234 P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4), //!< Port 23 Pin 4 235 P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5), //!< Port 23 Pin 5 236 P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6), //!< Port 23 Pin 6 237 P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7), //!< Port 23 Pin 7 238 239 P24_0 = CYHAL_GET_GPIO(CYHAL_PORT_24, 0), //!< Port 24 Pin 0 240 P24_1 = CYHAL_GET_GPIO(CYHAL_PORT_24, 1), //!< Port 24 Pin 1 241 P24_2 = CYHAL_GET_GPIO(CYHAL_PORT_24, 2), //!< Port 24 Pin 2 242 P24_3 = CYHAL_GET_GPIO(CYHAL_PORT_24, 3), //!< Port 24 Pin 3 243 P24_4 = CYHAL_GET_GPIO(CYHAL_PORT_24, 4), //!< Port 24 Pin 4 244 245 P25_0 = CYHAL_GET_GPIO(CYHAL_PORT_25, 0), //!< Port 25 Pin 0 246 P25_1 = CYHAL_GET_GPIO(CYHAL_PORT_25, 1), //!< Port 25 Pin 1 247 P25_2 = CYHAL_GET_GPIO(CYHAL_PORT_25, 2), //!< Port 25 Pin 2 248 P25_3 = CYHAL_GET_GPIO(CYHAL_PORT_25, 3), //!< Port 25 Pin 3 249 P25_4 = CYHAL_GET_GPIO(CYHAL_PORT_25, 4), //!< Port 25 Pin 4 250 P25_5 = CYHAL_GET_GPIO(CYHAL_PORT_25, 5), //!< Port 25 Pin 5 251 P25_6 = CYHAL_GET_GPIO(CYHAL_PORT_25, 6), //!< Port 25 Pin 6 252 P25_7 = CYHAL_GET_GPIO(CYHAL_PORT_25, 7), //!< Port 25 Pin 7 253 254 P26_0 = CYHAL_GET_GPIO(CYHAL_PORT_26, 0), //!< Port 26 Pin 0 255 P26_1 = CYHAL_GET_GPIO(CYHAL_PORT_26, 1), //!< Port 26 Pin 1 256 P26_2 = CYHAL_GET_GPIO(CYHAL_PORT_26, 2), //!< Port 26 Pin 2 257 P26_3 = CYHAL_GET_GPIO(CYHAL_PORT_26, 3), //!< Port 26 Pin 3 258 P26_4 = CYHAL_GET_GPIO(CYHAL_PORT_26, 4), //!< Port 26 Pin 4 259 P26_5 = CYHAL_GET_GPIO(CYHAL_PORT_26, 5), //!< Port 26 Pin 5 260 P26_6 = CYHAL_GET_GPIO(CYHAL_PORT_26, 6), //!< Port 26 Pin 6 261 P26_7 = CYHAL_GET_GPIO(CYHAL_PORT_26, 7), //!< Port 26 Pin 7 262 263 P27_0 = CYHAL_GET_GPIO(CYHAL_PORT_27, 0), //!< Port 27 Pin 0 264 P27_1 = CYHAL_GET_GPIO(CYHAL_PORT_27, 1), //!< Port 27 Pin 1 265 P27_2 = CYHAL_GET_GPIO(CYHAL_PORT_27, 2), //!< Port 27 Pin 2 266 P27_3 = CYHAL_GET_GPIO(CYHAL_PORT_27, 3), //!< Port 27 Pin 3 267 P27_4 = CYHAL_GET_GPIO(CYHAL_PORT_27, 4), //!< Port 27 Pin 4 268 P27_5 = CYHAL_GET_GPIO(CYHAL_PORT_27, 5), //!< Port 27 Pin 5 269 P27_6 = CYHAL_GET_GPIO(CYHAL_PORT_27, 6), //!< Port 27 Pin 6 270 P27_7 = CYHAL_GET_GPIO(CYHAL_PORT_27, 7), //!< Port 27 Pin 7 271 272 P28_0 = CYHAL_GET_GPIO(CYHAL_PORT_28, 0), //!< Port 28 Pin 0 273 P28_1 = CYHAL_GET_GPIO(CYHAL_PORT_28, 1), //!< Port 28 Pin 1 274 P28_2 = CYHAL_GET_GPIO(CYHAL_PORT_28, 2), //!< Port 28 Pin 2 275 P28_3 = CYHAL_GET_GPIO(CYHAL_PORT_28, 3), //!< Port 28 Pin 3 276 P28_4 = CYHAL_GET_GPIO(CYHAL_PORT_28, 4), //!< Port 28 Pin 4 277 P28_5 = CYHAL_GET_GPIO(CYHAL_PORT_28, 5), //!< Port 28 Pin 5 278 P28_6 = CYHAL_GET_GPIO(CYHAL_PORT_28, 6), //!< Port 28 Pin 6 279 P28_7 = CYHAL_GET_GPIO(CYHAL_PORT_28, 7), //!< Port 28 Pin 7 280 281 P29_0 = CYHAL_GET_GPIO(CYHAL_PORT_29, 0), //!< Port 29 Pin 0 282 P29_1 = CYHAL_GET_GPIO(CYHAL_PORT_29, 1), //!< Port 29 Pin 1 283 P29_2 = CYHAL_GET_GPIO(CYHAL_PORT_29, 2), //!< Port 29 Pin 2 284 P29_3 = CYHAL_GET_GPIO(CYHAL_PORT_29, 3), //!< Port 29 Pin 3 285 P29_4 = CYHAL_GET_GPIO(CYHAL_PORT_29, 4), //!< Port 29 Pin 4 286 P29_5 = CYHAL_GET_GPIO(CYHAL_PORT_29, 5), //!< Port 29 Pin 5 287 P29_6 = CYHAL_GET_GPIO(CYHAL_PORT_29, 6), //!< Port 29 Pin 6 288 P29_7 = CYHAL_GET_GPIO(CYHAL_PORT_29, 7), //!< Port 29 Pin 7 289 290 P30_0 = CYHAL_GET_GPIO(CYHAL_PORT_30, 0), //!< Port 30 Pin 0 291 P30_1 = CYHAL_GET_GPIO(CYHAL_PORT_30, 1), //!< Port 30 Pin 1 292 P30_2 = CYHAL_GET_GPIO(CYHAL_PORT_30, 2), //!< Port 30 Pin 2 293 P30_3 = CYHAL_GET_GPIO(CYHAL_PORT_30, 3), //!< Port 30 Pin 3 294 295 P31_0 = CYHAL_GET_GPIO(CYHAL_PORT_31, 0), //!< Port 31 Pin 0 296 P31_1 = CYHAL_GET_GPIO(CYHAL_PORT_31, 1), //!< Port 31 Pin 1 297 P31_2 = CYHAL_GET_GPIO(CYHAL_PORT_31, 2), //!< Port 31 Pin 2 298 299 P32_0 = CYHAL_GET_GPIO(CYHAL_PORT_32, 0), //!< Port 32 Pin 0 300 P32_1 = CYHAL_GET_GPIO(CYHAL_PORT_32, 1), //!< Port 32 Pin 1 301 P32_2 = CYHAL_GET_GPIO(CYHAL_PORT_32, 2), //!< Port 32 Pin 2 302 P32_3 = CYHAL_GET_GPIO(CYHAL_PORT_32, 3), //!< Port 32 Pin 3 303 P32_4 = CYHAL_GET_GPIO(CYHAL_PORT_32, 4), //!< Port 32 Pin 4 304 P32_5 = CYHAL_GET_GPIO(CYHAL_PORT_32, 5), //!< Port 32 Pin 5 305 P32_6 = CYHAL_GET_GPIO(CYHAL_PORT_32, 6), //!< Port 32 Pin 6 306 P32_7 = CYHAL_GET_GPIO(CYHAL_PORT_32, 7), //!< Port 32 Pin 7 307 } cyhal_gpio_xmc7200_272_bga_t; 308 309 /** Create generic name for the series/package specific type. */ 310 typedef cyhal_gpio_xmc7200_272_bga_t cyhal_gpio_t; 311 312 /* Connection type definition */ 313 /** Represents an association between a pin and a resource */ 314 typedef struct 315 { 316 uint8_t block_num; //!< The block number of the resource with this connection 317 uint8_t channel_num; //!< The channel number of the block with this connection 318 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 319 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 320 } cyhal_resource_pin_mapping_t; 321 322 /* Pin connections */ 323 /** Indicates that a pin map exists for audioss_clk_i2s_if*/ 324 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ) 325 /** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ 326 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3]; 327 /** Indicates that a pin map exists for audioss_mclk*/ 328 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_MCLK (CY_GPIO_DM_STRONG) 329 /** List of valid pin to peripheral connections for the audioss_mclk signal. */ 330 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3]; 331 /** Indicates that a pin map exists for audioss_rx_sck*/ 332 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 333 /** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ 334 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[3]; 335 /** Indicates that a pin map exists for audioss_rx_sdi*/ 336 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ) 337 /** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ 338 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3]; 339 /** Indicates that a pin map exists for audioss_rx_ws*/ 340 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF) 341 /** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ 342 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3]; 343 /** Indicates that a pin map exists for audioss_tx_sck*/ 344 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 345 /** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ 346 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3]; 347 /** Indicates that a pin map exists for audioss_tx_sdo*/ 348 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF) 349 /** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ 350 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[3]; 351 /** Indicates that a pin map exists for audioss_tx_ws*/ 352 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF) 353 /** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ 354 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[3]; 355 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 356 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 357 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 358 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[21]; 359 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 360 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 361 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 362 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[21]; 363 /** Indicates that a pin map exists for cpuss_cal_sup_nz*/ 364 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ (CY_GPIO_DM_STRONG_IN_OFF) 365 /** List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. */ 366 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3]; 367 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 368 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 369 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 370 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 371 /** Indicates that a pin map exists for cpuss_fault_out*/ 372 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 373 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 374 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8]; 375 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 376 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 377 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 378 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 379 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 380 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 381 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 382 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 383 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 384 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 385 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 386 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 387 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 388 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 389 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 390 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 391 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 392 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 393 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 394 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 395 /** Indicates that a pin map exists for cpuss_trace_clock*/ 396 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 397 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 398 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2]; 399 /** Indicates that a pin map exists for cpuss_trace_data*/ 400 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 401 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 402 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 403 /** Indicates that a pin map exists for eth_eth_tsu_timer_cmp_val*/ 404 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_ETH_TSU_TIMER_CMP_VAL (CY_GPIO_DM_STRONG_IN_OFF) 405 /** List of valid pin to peripheral connections for the eth_eth_tsu_timer_cmp_val signal. */ 406 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[2]; 407 /** Indicates that a pin map exists for eth_mdc*/ 408 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDC (CY_GPIO_DM_STRONG_IN_OFF) 409 /** List of valid pin to peripheral connections for the eth_mdc signal. */ 410 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[2]; 411 /** Indicates that a pin map exists for eth_mdio*/ 412 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDIO (CY_GPIO_DM_STRONG_IN_OFF) 413 /** List of valid pin to peripheral connections for the eth_mdio signal. */ 414 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[2]; 415 /** Indicates that a pin map exists for eth_ref_clk*/ 416 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_REF_CLK (CY_GPIO_DM_HIGHZ) 417 /** List of valid pin to peripheral connections for the eth_ref_clk signal. */ 418 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[2]; 419 /** Indicates that a pin map exists for eth_rx_clk*/ 420 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CLK (CY_GPIO_DM_HIGHZ) 421 /** List of valid pin to peripheral connections for the eth_rx_clk signal. */ 422 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[2]; 423 /** Indicates that a pin map exists for eth_rx_ctl*/ 424 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CTL (CY_GPIO_DM_HIGHZ) 425 /** List of valid pin to peripheral connections for the eth_rx_ctl signal. */ 426 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[2]; 427 /** Indicates that a pin map exists for eth_rx_er*/ 428 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_ER (CY_GPIO_DM_HIGHZ) 429 /** List of valid pin to peripheral connections for the eth_rx_er signal. */ 430 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1]; 431 /** Indicates that a pin map exists for eth_rxd*/ 432 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RXD (CY_GPIO_DM_HIGHZ) 433 /** List of valid pin to peripheral connections for the eth_rxd signal. */ 434 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[8]; 435 /** Indicates that a pin map exists for eth_tx_clk*/ 436 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CLK (CY_GPIO_DM_STRONG_IN_OFF) 437 /** List of valid pin to peripheral connections for the eth_tx_clk signal. */ 438 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[2]; 439 /** Indicates that a pin map exists for eth_tx_ctl*/ 440 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CTL (CY_GPIO_DM_STRONG_IN_OFF) 441 /** List of valid pin to peripheral connections for the eth_tx_ctl signal. */ 442 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[2]; 443 /** Indicates that a pin map exists for eth_tx_er*/ 444 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_ER (CY_GPIO_DM_STRONG) 445 /** List of valid pin to peripheral connections for the eth_tx_er signal. */ 446 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[1]; 447 /** Indicates that a pin map exists for eth_txd*/ 448 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TXD (CY_GPIO_DM_STRONG_IN_OFF) 449 /** List of valid pin to peripheral connections for the eth_txd signal. */ 450 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[8]; 451 /** Indicates that a pin map exists for flexray_rxda*/ 452 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_RXDA (CY_GPIO_DM_HIGHZ) 453 /** List of valid pin to peripheral connections for the flexray_rxda signal. */ 454 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxda[1]; 455 /** Indicates that a pin map exists for flexray_rxdb*/ 456 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_RXDB (CY_GPIO_DM_HIGHZ) 457 /** List of valid pin to peripheral connections for the flexray_rxdb signal. */ 458 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxdb[1]; 459 /** Indicates that a pin map exists for flexray_txda*/ 460 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXDA (CY_GPIO_DM_STRONG) 461 /** List of valid pin to peripheral connections for the flexray_txda signal. */ 462 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txda[1]; 463 /** Indicates that a pin map exists for flexray_txdb*/ 464 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXDB (CY_GPIO_DM_STRONG) 465 /** List of valid pin to peripheral connections for the flexray_txdb signal. */ 466 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txdb[1]; 467 /** Indicates that a pin map exists for flexray_txena_n*/ 468 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXENA_N (CY_GPIO_DM_STRONG) 469 /** List of valid pin to peripheral connections for the flexray_txena_n signal. */ 470 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txena_n[1]; 471 /** Indicates that a pin map exists for flexray_txenb_n*/ 472 #define CYHAL_PIN_MAP_DRIVE_MODE_FLEXRAY_TXENB_N (CY_GPIO_DM_STRONG) 473 /** List of valid pin to peripheral connections for the flexray_txenb_n signal. */ 474 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txenb_n[1]; 475 /** Indicates that a pin map exists for lin_lin_en*/ 476 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 477 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 478 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[38]; 479 /** Indicates that a pin map exists for lin_lin_rx*/ 480 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 481 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 482 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[49]; 483 /** Indicates that a pin map exists for lin_lin_tx*/ 484 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 485 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 486 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[48]; 487 /** Indicates that a pin map exists for pass_sar_ext_mux_en*/ 488 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN (CY_GPIO_DM_STRONG_IN_OFF) 489 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. */ 490 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3]; 491 /** Indicates that a pin map exists for pass_sar_ext_mux_sel*/ 492 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL (CY_GPIO_DM_STRONG_IN_OFF) 493 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. */ 494 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9]; 495 /** Indicates that a pin map exists for pass_sarmux_pads*/ 496 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 497 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 498 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[96]; 499 /** Indicates that a pin map exists for peri_tr_io_input*/ 500 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 501 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 502 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[46]; 503 /** Indicates that a pin map exists for peri_tr_io_output*/ 504 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 505 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 506 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 507 /** Indicates that a pin map exists for scb_i2c_scl*/ 508 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 509 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 510 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[22]; 511 /** Indicates that a pin map exists for scb_i2c_sda*/ 512 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 513 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 514 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21]; 515 /** Indicates that a pin map exists for scb_spi_m_clk*/ 516 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 517 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 518 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[24]; 519 /** Indicates that a pin map exists for scb_spi_m_miso*/ 520 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 521 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 522 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[23]; 523 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 524 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 525 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 526 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[22]; 527 /** Indicates that a pin map exists for scb_spi_m_select0*/ 528 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 529 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 530 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[25]; 531 /** Indicates that a pin map exists for scb_spi_m_select1*/ 532 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 533 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 534 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[21]; 535 /** Indicates that a pin map exists for scb_spi_m_select2*/ 536 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 537 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 538 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[20]; 539 /** Indicates that a pin map exists for scb_spi_m_select3*/ 540 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 541 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 542 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8]; 543 /** Indicates that a pin map exists for scb_spi_s_clk*/ 544 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 545 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 546 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[24]; 547 /** Indicates that a pin map exists for scb_spi_s_miso*/ 548 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 549 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 550 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[23]; 551 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 552 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 553 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 554 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[22]; 555 /** Indicates that a pin map exists for scb_spi_s_select0*/ 556 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 557 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 558 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[25]; 559 /** Indicates that a pin map exists for scb_spi_s_select1*/ 560 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 561 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 562 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[21]; 563 /** Indicates that a pin map exists for scb_spi_s_select2*/ 564 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 565 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 566 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[20]; 567 /** Indicates that a pin map exists for scb_spi_s_select3*/ 568 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 569 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 570 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8]; 571 /** Indicates that a pin map exists for scb_uart_cts*/ 572 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 573 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 574 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[21]; 575 /** Indicates that a pin map exists for scb_uart_rts*/ 576 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 577 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 578 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[20]; 579 /** Indicates that a pin map exists for scb_uart_rx*/ 580 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 581 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 582 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[20]; 583 /** Indicates that a pin map exists for scb_uart_tx*/ 584 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 585 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 586 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19]; 587 /** Indicates that a pin map exists for sdhc_card_cmd*/ 588 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_CMD (CY_GPIO_DM_STRONG) 589 /** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ 590 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2]; 591 /** Indicates that a pin map exists for sdhc_card_dat_3to0*/ 592 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_3TO0 (CY_GPIO_DM_STRONG) 593 /** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ 594 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8]; 595 /** Indicates that a pin map exists for sdhc_card_dat_7to4*/ 596 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_7TO4 (CY_GPIO_DM_STRONG) 597 /** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ 598 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[8]; 599 /** Indicates that a pin map exists for sdhc_card_detect_n*/ 600 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DETECT_N (CY_GPIO_DM_HIGHZ) 601 /** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ 602 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2]; 603 /** Indicates that a pin map exists for sdhc_card_if_pwr_en*/ 604 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_IF_PWR_EN (CY_GPIO_DM_STRONG_IN_OFF) 605 /** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ 606 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; 607 /** Indicates that a pin map exists for sdhc_card_mech_write_prot*/ 608 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_MECH_WRITE_PROT (CY_GPIO_DM_HIGHZ) 609 /** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ 610 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2]; 611 /** Indicates that a pin map exists for sdhc_clk_card*/ 612 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CLK_CARD (CY_GPIO_DM_STRONG) 613 /** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ 614 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2]; 615 /** Indicates that a pin map exists for smif_spi_clk*/ 616 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 617 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 618 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[2]; 619 /** Indicates that a pin map exists for smif_spi_data0*/ 620 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 621 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 622 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[2]; 623 /** Indicates that a pin map exists for smif_spi_data1*/ 624 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 625 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 626 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[2]; 627 /** Indicates that a pin map exists for smif_spi_data2*/ 628 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 629 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 630 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[2]; 631 /** Indicates that a pin map exists for smif_spi_data3*/ 632 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 633 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 634 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[2]; 635 /** Indicates that a pin map exists for smif_spi_data4*/ 636 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG) 637 /** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ 638 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[2]; 639 /** Indicates that a pin map exists for smif_spi_data5*/ 640 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG) 641 /** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ 642 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[2]; 643 /** Indicates that a pin map exists for smif_spi_data6*/ 644 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG) 645 /** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ 646 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[2]; 647 /** Indicates that a pin map exists for smif_spi_data7*/ 648 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG) 649 /** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ 650 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[2]; 651 /** Indicates that a pin map exists for smif_spi_rwds*/ 652 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_RWDS (CY_GPIO_DM_STRONG) 653 /** List of valid pin to peripheral connections for the smif_spi_rwds signal. */ 654 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[2]; 655 /** Indicates that a pin map exists for smif_spi_select0*/ 656 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 657 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 658 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[2]; 659 /** Indicates that a pin map exists for smif_spi_select1*/ 660 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 661 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 662 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[2]; 663 /** Indicates that a pin map exists for tcpwm_line*/ 664 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 665 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 666 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[227]; 667 /** Indicates that a pin map exists for tcpwm_line_compl*/ 668 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 669 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 670 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[227]; 671 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 672 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 673 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 674 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[446]; 675 676 #if defined(__cplusplus) 677 } 678 #endif /* __cplusplus */ 679 680 /** \} group_hal_impl_pin_package */ 681 682 #endif /* _CYHAL_XMC7200_272_BGA_H_ */ 683 684 685 /* [] END OF FILE */ 686
