1 /***************************************************************************//** 2 * \file cyhal_xmc7100_144_teqfp.h 3 * 4 * \brief 5 * XMC7100 device GPIO HAL header for 144-TEQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_XMC7100_144_TEQFP_H_ 28 #define _CYHAL_XMC7100_144_TEQFP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_xmc7100_144_teqfp XMC7100 144-TEQFP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the XMC7100 144-TEQFP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 144-TEQFP package for the XMC7100 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 60 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 61 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 62 63 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 64 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 65 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 66 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 67 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 68 69 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 70 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 71 P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 72 P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 73 P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 74 75 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 76 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 77 78 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 79 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 80 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 81 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 82 P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 83 84 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 85 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 86 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 87 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 88 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 89 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 90 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 91 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 92 93 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 94 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 95 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 96 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 97 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 98 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 99 P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 100 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 101 102 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 103 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 104 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 105 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 106 107 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 108 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 109 110 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 111 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 112 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 113 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 114 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 115 116 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 117 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 118 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 119 120 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 121 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 122 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 123 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 124 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 125 P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 126 127 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 128 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 129 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 130 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 131 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 132 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 133 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 134 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 135 136 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 137 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 138 P14_4 = CYHAL_GET_GPIO(CYHAL_PORT_14, 4), //!< Port 14 Pin 4 139 P14_5 = CYHAL_GET_GPIO(CYHAL_PORT_14, 5), //!< Port 14 Pin 5 140 141 P15_0 = CYHAL_GET_GPIO(CYHAL_PORT_15, 0), //!< Port 15 Pin 0 142 P15_1 = CYHAL_GET_GPIO(CYHAL_PORT_15, 1), //!< Port 15 Pin 1 143 P15_2 = CYHAL_GET_GPIO(CYHAL_PORT_15, 2), //!< Port 15 Pin 2 144 P15_3 = CYHAL_GET_GPIO(CYHAL_PORT_15, 3), //!< Port 15 Pin 3 145 146 P17_0 = CYHAL_GET_GPIO(CYHAL_PORT_17, 0), //!< Port 17 Pin 0 147 P17_1 = CYHAL_GET_GPIO(CYHAL_PORT_17, 1), //!< Port 17 Pin 1 148 P17_2 = CYHAL_GET_GPIO(CYHAL_PORT_17, 2), //!< Port 17 Pin 2 149 P17_3 = CYHAL_GET_GPIO(CYHAL_PORT_17, 3), //!< Port 17 Pin 3 150 P17_4 = CYHAL_GET_GPIO(CYHAL_PORT_17, 4), //!< Port 17 Pin 4 151 152 P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0 153 P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1 154 P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2), //!< Port 18 Pin 2 155 P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3), //!< Port 18 Pin 3 156 P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4), //!< Port 18 Pin 4 157 P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5), //!< Port 18 Pin 5 158 P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6), //!< Port 18 Pin 6 159 P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7), //!< Port 18 Pin 7 160 161 P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0 162 P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1 163 P19_2 = CYHAL_GET_GPIO(CYHAL_PORT_19, 2), //!< Port 19 Pin 2 164 P19_3 = CYHAL_GET_GPIO(CYHAL_PORT_19, 3), //!< Port 19 Pin 3 165 P19_4 = CYHAL_GET_GPIO(CYHAL_PORT_19, 4), //!< Port 19 Pin 4 166 167 P20_0 = CYHAL_GET_GPIO(CYHAL_PORT_20, 0), //!< Port 20 Pin 0 168 P20_1 = CYHAL_GET_GPIO(CYHAL_PORT_20, 1), //!< Port 20 Pin 1 169 P20_2 = CYHAL_GET_GPIO(CYHAL_PORT_20, 2), //!< Port 20 Pin 2 170 P20_3 = CYHAL_GET_GPIO(CYHAL_PORT_20, 3), //!< Port 20 Pin 3 171 172 P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0), //!< Port 21 Pin 0 173 P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1), //!< Port 21 Pin 1 174 P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2), //!< Port 21 Pin 2 175 P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3), //!< Port 21 Pin 3 176 P21_5 = CYHAL_GET_GPIO(CYHAL_PORT_21, 5), //!< Port 21 Pin 5 177 P21_6 = CYHAL_GET_GPIO(CYHAL_PORT_21, 6), //!< Port 21 Pin 6 178 179 P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1), //!< Port 22 Pin 1 180 P22_2 = CYHAL_GET_GPIO(CYHAL_PORT_22, 2), //!< Port 22 Pin 2 181 P22_3 = CYHAL_GET_GPIO(CYHAL_PORT_22, 3), //!< Port 22 Pin 3 182 P22_4 = CYHAL_GET_GPIO(CYHAL_PORT_22, 4), //!< Port 22 Pin 4 183 P22_5 = CYHAL_GET_GPIO(CYHAL_PORT_22, 5), //!< Port 22 Pin 5 184 P22_6 = CYHAL_GET_GPIO(CYHAL_PORT_22, 6), //!< Port 22 Pin 6 185 186 P23_0 = CYHAL_GET_GPIO(CYHAL_PORT_23, 0), //!< Port 23 Pin 0 187 P23_1 = CYHAL_GET_GPIO(CYHAL_PORT_23, 1), //!< Port 23 Pin 1 188 P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3), //!< Port 23 Pin 3 189 P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4), //!< Port 23 Pin 4 190 P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5), //!< Port 23 Pin 5 191 P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6), //!< Port 23 Pin 6 192 P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7), //!< Port 23 Pin 7 193 } cyhal_gpio_xmc7100_144_teqfp_t; 194 195 /** Create generic name for the series/package specific type. */ 196 typedef cyhal_gpio_xmc7100_144_teqfp_t cyhal_gpio_t; 197 198 /* Connection type definition */ 199 /** Represents an association between a pin and a resource */ 200 typedef struct 201 { 202 uint8_t block_num; //!< The block number of the resource with this connection 203 uint8_t channel_num; //!< The channel number of the block with this connection 204 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 205 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 206 } cyhal_resource_pin_mapping_t; 207 208 /* Pin connections */ 209 /** Indicates that a pin map exists for audioss_clk_i2s_if*/ 210 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ) 211 /** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ 212 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3]; 213 /** Indicates that a pin map exists for audioss_mclk*/ 214 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_MCLK (CY_GPIO_DM_STRONG) 215 /** List of valid pin to peripheral connections for the audioss_mclk signal. */ 216 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3]; 217 /** Indicates that a pin map exists for audioss_rx_sck*/ 218 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 219 /** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ 220 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[3]; 221 /** Indicates that a pin map exists for audioss_rx_sdi*/ 222 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ) 223 /** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ 224 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3]; 225 /** Indicates that a pin map exists for audioss_rx_ws*/ 226 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF) 227 /** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ 228 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3]; 229 /** Indicates that a pin map exists for audioss_tx_sck*/ 230 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 231 /** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ 232 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3]; 233 /** Indicates that a pin map exists for audioss_tx_sdo*/ 234 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF) 235 /** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ 236 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[3]; 237 /** Indicates that a pin map exists for audioss_tx_ws*/ 238 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF) 239 /** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ 240 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[3]; 241 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 242 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 243 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 244 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[14]; 245 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 246 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 247 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 248 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[15]; 249 /** Indicates that a pin map exists for cpuss_cal_sup_nz*/ 250 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ (CY_GPIO_DM_STRONG_IN_OFF) 251 /** List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. */ 252 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2]; 253 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 254 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 255 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 256 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 257 /** Indicates that a pin map exists for cpuss_fault_out*/ 258 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 259 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 260 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[7]; 261 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 262 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 263 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 264 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 265 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 266 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 267 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 268 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 269 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 270 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 271 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 272 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 273 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 274 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 275 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 276 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 277 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 278 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 279 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 280 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 281 /** Indicates that a pin map exists for cpuss_trace_clock*/ 282 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 283 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 284 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2]; 285 /** Indicates that a pin map exists for cpuss_trace_data*/ 286 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 287 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 288 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 289 /** Indicates that a pin map exists for eth_eth_tsu_timer_cmp_val*/ 290 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_ETH_TSU_TIMER_CMP_VAL (CY_GPIO_DM_STRONG_IN_OFF) 291 /** List of valid pin to peripheral connections for the eth_eth_tsu_timer_cmp_val signal. */ 292 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[1]; 293 /** Indicates that a pin map exists for eth_mdc*/ 294 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDC (CY_GPIO_DM_STRONG_IN_OFF) 295 /** List of valid pin to peripheral connections for the eth_mdc signal. */ 296 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[1]; 297 /** Indicates that a pin map exists for eth_mdio*/ 298 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_MDIO (CY_GPIO_DM_STRONG_IN_OFF) 299 /** List of valid pin to peripheral connections for the eth_mdio signal. */ 300 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[1]; 301 /** Indicates that a pin map exists for eth_ref_clk*/ 302 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_REF_CLK (CY_GPIO_DM_HIGHZ) 303 /** List of valid pin to peripheral connections for the eth_ref_clk signal. */ 304 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[1]; 305 /** Indicates that a pin map exists for eth_rx_clk*/ 306 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CLK (CY_GPIO_DM_HIGHZ) 307 /** List of valid pin to peripheral connections for the eth_rx_clk signal. */ 308 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[1]; 309 /** Indicates that a pin map exists for eth_rx_ctl*/ 310 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_CTL (CY_GPIO_DM_HIGHZ) 311 /** List of valid pin to peripheral connections for the eth_rx_ctl signal. */ 312 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[1]; 313 /** Indicates that a pin map exists for eth_rx_er*/ 314 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RX_ER (CY_GPIO_DM_HIGHZ) 315 /** List of valid pin to peripheral connections for the eth_rx_er signal. */ 316 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1]; 317 /** Indicates that a pin map exists for eth_rxd*/ 318 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_RXD (CY_GPIO_DM_HIGHZ) 319 /** List of valid pin to peripheral connections for the eth_rxd signal. */ 320 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[4]; 321 /** Indicates that a pin map exists for eth_tx_clk*/ 322 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CLK (CY_GPIO_DM_STRONG_IN_OFF) 323 /** List of valid pin to peripheral connections for the eth_tx_clk signal. */ 324 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[1]; 325 /** Indicates that a pin map exists for eth_tx_ctl*/ 326 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_CTL (CY_GPIO_DM_STRONG_IN_OFF) 327 /** List of valid pin to peripheral connections for the eth_tx_ctl signal. */ 328 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[1]; 329 /** Indicates that a pin map exists for eth_tx_er*/ 330 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TX_ER (CY_GPIO_DM_STRONG) 331 /** List of valid pin to peripheral connections for the eth_tx_er signal. */ 332 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[1]; 333 /** Indicates that a pin map exists for eth_txd*/ 334 #define CYHAL_PIN_MAP_DRIVE_MODE_ETH_TXD (CY_GPIO_DM_STRONG_IN_OFF) 335 /** List of valid pin to peripheral connections for the eth_txd signal. */ 336 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[4]; 337 /** Indicates that a pin map exists for lin_lin_en*/ 338 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 339 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 340 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[17]; 341 /** Indicates that a pin map exists for lin_lin_rx*/ 342 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 343 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 344 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[28]; 345 /** Indicates that a pin map exists for lin_lin_tx*/ 346 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 347 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 348 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[27]; 349 /** Indicates that a pin map exists for pass_sar_ext_mux_en*/ 350 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN (CY_GPIO_DM_STRONG_IN_OFF) 351 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. */ 352 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2]; 353 /** Indicates that a pin map exists for pass_sar_ext_mux_sel*/ 354 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL (CY_GPIO_DM_STRONG_IN_OFF) 355 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. */ 356 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[8]; 357 /** Indicates that a pin map exists for pass_sarmux_pads*/ 358 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 359 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 360 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[52]; 361 /** Indicates that a pin map exists for peri_tr_io_input*/ 362 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 363 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 364 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[25]; 365 /** Indicates that a pin map exists for peri_tr_io_output*/ 366 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 367 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 368 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[5]; 369 /** Indicates that a pin map exists for scb_i2c_scl*/ 370 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 371 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 372 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[15]; 373 /** Indicates that a pin map exists for scb_i2c_sda*/ 374 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 375 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 376 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[18]; 377 /** Indicates that a pin map exists for scb_spi_m_clk*/ 378 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 379 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 380 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16]; 381 /** Indicates that a pin map exists for scb_spi_m_miso*/ 382 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 383 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 384 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[19]; 385 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 386 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 387 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 388 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[19]; 389 /** Indicates that a pin map exists for scb_spi_m_select0*/ 390 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 391 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 392 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[17]; 393 /** Indicates that a pin map exists for scb_spi_m_select1*/ 394 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 395 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 396 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13]; 397 /** Indicates that a pin map exists for scb_spi_m_select2*/ 398 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 399 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 400 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11]; 401 /** Indicates that a pin map exists for scb_spi_m_select3*/ 402 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 403 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 404 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[5]; 405 /** Indicates that a pin map exists for scb_spi_s_clk*/ 406 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 407 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 408 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16]; 409 /** Indicates that a pin map exists for scb_spi_s_miso*/ 410 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 411 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 412 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[19]; 413 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 414 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 415 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 416 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[19]; 417 /** Indicates that a pin map exists for scb_spi_s_select0*/ 418 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 419 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 420 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[17]; 421 /** Indicates that a pin map exists for scb_spi_s_select1*/ 422 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 423 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 424 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13]; 425 /** Indicates that a pin map exists for scb_spi_s_select2*/ 426 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 427 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 428 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11]; 429 /** Indicates that a pin map exists for scb_spi_s_select3*/ 430 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 431 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 432 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[5]; 433 /** Indicates that a pin map exists for scb_uart_cts*/ 434 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 435 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 436 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[14]; 437 /** Indicates that a pin map exists for scb_uart_rts*/ 438 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 439 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 440 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[13]; 441 /** Indicates that a pin map exists for scb_uart_rx*/ 442 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 443 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 444 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[16]; 445 /** Indicates that a pin map exists for scb_uart_tx*/ 446 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 447 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 448 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[16]; 449 /** Indicates that a pin map exists for sdhc_card_cmd*/ 450 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_CMD (CY_GPIO_DM_STRONG) 451 /** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ 452 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; 453 /** Indicates that a pin map exists for sdhc_card_dat_3to0*/ 454 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_3TO0 (CY_GPIO_DM_STRONG) 455 /** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ 456 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; 457 /** Indicates that a pin map exists for sdhc_card_dat_7to4*/ 458 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_7TO4 (CY_GPIO_DM_STRONG) 459 /** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ 460 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4]; 461 /** Indicates that a pin map exists for sdhc_card_detect_n*/ 462 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DETECT_N (CY_GPIO_DM_HIGHZ) 463 /** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ 464 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; 465 /** Indicates that a pin map exists for sdhc_card_if_pwr_en*/ 466 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_IF_PWR_EN (CY_GPIO_DM_STRONG_IN_OFF) 467 /** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ 468 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; 469 /** Indicates that a pin map exists for sdhc_card_mech_write_prot*/ 470 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_MECH_WRITE_PROT (CY_GPIO_DM_HIGHZ) 471 /** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ 472 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; 473 /** Indicates that a pin map exists for sdhc_clk_card*/ 474 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CLK_CARD (CY_GPIO_DM_STRONG) 475 /** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ 476 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; 477 /** Indicates that a pin map exists for smif_spi_clk*/ 478 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 479 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 480 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 481 /** Indicates that a pin map exists for smif_spi_data0*/ 482 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 483 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 484 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 485 /** Indicates that a pin map exists for smif_spi_data1*/ 486 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 487 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 488 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 489 /** Indicates that a pin map exists for smif_spi_data2*/ 490 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 491 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 492 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 493 /** Indicates that a pin map exists for smif_spi_data3*/ 494 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 495 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 496 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 497 /** Indicates that a pin map exists for smif_spi_data4*/ 498 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG) 499 /** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ 500 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; 501 /** Indicates that a pin map exists for smif_spi_data5*/ 502 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG) 503 /** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ 504 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; 505 /** Indicates that a pin map exists for smif_spi_data6*/ 506 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG) 507 /** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ 508 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; 509 /** Indicates that a pin map exists for smif_spi_data7*/ 510 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG) 511 /** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ 512 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; 513 /** Indicates that a pin map exists for smif_spi_rwds*/ 514 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_RWDS (CY_GPIO_DM_STRONG) 515 /** List of valid pin to peripheral connections for the smif_spi_rwds signal. */ 516 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[1]; 517 /** Indicates that a pin map exists for smif_spi_select0*/ 518 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 519 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 520 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 521 /** Indicates that a pin map exists for smif_spi_select1*/ 522 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 523 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 524 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 525 /** Indicates that a pin map exists for tcpwm_line*/ 526 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 527 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 528 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[127]; 529 /** Indicates that a pin map exists for tcpwm_line_compl*/ 530 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 531 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 532 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[128]; 533 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 534 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 535 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 536 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[255]; 537 538 #if defined(__cplusplus) 539 } 540 #endif /* __cplusplus */ 541 542 /** \} group_hal_impl_pin_package */ 543 544 #endif /* _CYHAL_XMC7100_144_TEQFP_H_ */ 545 546 547 /* [] END OF FILE */ 548
