1 /***************************************************************************//** 2 * \file cyhal_tviibe4m_80_lqfp.h 3 * 4 * \brief 5 * TVIIBE4M device GPIO HAL header for 80-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_TVIIBE4M_80_LQFP_H_ 28 #define _CYHAL_TVIIBE4M_80_LQFP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_tviibe4m_80_lqfp TVIIBE4M 80-LQFP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the TVIIBE4M 80-LQFP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 80-LQFP package for the TVIIBE4M series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 60 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 61 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 62 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 63 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 64 65 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 66 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 67 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 68 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 69 70 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 71 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 72 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 73 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 74 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 75 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 76 77 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 78 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 79 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 80 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 81 82 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 83 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 84 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 85 86 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 87 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 88 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 89 90 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 91 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 92 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 93 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 94 95 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 96 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 97 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 98 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 99 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 100 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 101 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 102 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 103 104 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 105 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 106 107 P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0 108 P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1 109 P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2), //!< Port 18 Pin 2 110 P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3), //!< Port 18 Pin 3 111 P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4), //!< Port 18 Pin 4 112 P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5), //!< Port 18 Pin 5 113 P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6), //!< Port 18 Pin 6 114 P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7), //!< Port 18 Pin 7 115 116 P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0 117 P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1 118 119 P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0), //!< Port 21 Pin 0 120 P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1), //!< Port 21 Pin 1 121 P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2), //!< Port 21 Pin 2 122 P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3), //!< Port 21 Pin 3 123 124 P22_0 = CYHAL_GET_GPIO(CYHAL_PORT_22, 0), //!< Port 22 Pin 0 125 P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1), //!< Port 22 Pin 1 126 127 P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3), //!< Port 23 Pin 3 128 P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4), //!< Port 23 Pin 4 129 P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5), //!< Port 23 Pin 5 130 P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6), //!< Port 23 Pin 6 131 P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7), //!< Port 23 Pin 7 132 } cyhal_gpio_tviibe4m_80_lqfp_t; 133 134 /** Create generic name for the series/package specific type. */ 135 typedef cyhal_gpio_tviibe4m_80_lqfp_t cyhal_gpio_t; 136 137 /* Connection type definition */ 138 /** Represents an association between a pin and a resource */ 139 typedef struct 140 { 141 uint8_t block_num; //!< The block number of the resource with this connection 142 uint8_t channel_num; //!< The channel number of the block with this connection 143 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 144 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 145 } cyhal_resource_pin_mapping_t; 146 147 /* Pin connections */ 148 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 149 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 150 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 151 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[9]; 152 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 153 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 154 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 155 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[9]; 156 /** Indicates that a pin map exists for cpuss_cal_sup_nz*/ 157 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ (CY_GPIO_DM_STRONG_IN_OFF) 158 /** List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. */ 159 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2]; 160 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 161 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 162 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 163 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 164 /** Indicates that a pin map exists for cpuss_fault_out*/ 165 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 166 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 167 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[5]; 168 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 169 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 170 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 171 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 172 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 173 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 174 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 175 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 176 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 177 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 178 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 179 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 180 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 181 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 182 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 183 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 184 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 185 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 186 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 187 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 188 /** Indicates that a pin map exists for cpuss_trace_clock*/ 189 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 190 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 191 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 192 /** Indicates that a pin map exists for cpuss_trace_data*/ 193 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 194 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 195 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[6]; 196 /** Indicates that a pin map exists for cxpi_cxpi_en*/ 197 #define CYHAL_PIN_MAP_DRIVE_MODE_CXPI_CXPI_EN (CY_GPIO_DM_STRONG_IN_OFF) 198 /** List of valid pin to peripheral connections for the cxpi_cxpi_en signal. */ 199 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_en[3]; 200 /** Indicates that a pin map exists for cxpi_cxpi_rx*/ 201 #define CYHAL_PIN_MAP_DRIVE_MODE_CXPI_CXPI_RX (CY_GPIO_DM_STRONG_IN_OFF) 202 /** List of valid pin to peripheral connections for the cxpi_cxpi_rx signal. */ 203 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_rx[4]; 204 /** Indicates that a pin map exists for cxpi_cxpi_tx*/ 205 #define CYHAL_PIN_MAP_DRIVE_MODE_CXPI_CXPI_TX (CY_GPIO_DM_STRONG_IN_OFF) 206 /** List of valid pin to peripheral connections for the cxpi_cxpi_tx signal. */ 207 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_tx[3]; 208 /** Indicates that a pin map exists for lin_lin_en*/ 209 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 210 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 211 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[11]; 212 /** Indicates that a pin map exists for lin_lin_rx*/ 213 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 214 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 215 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[13]; 216 /** Indicates that a pin map exists for lin_lin_tx*/ 217 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 218 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 219 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[11]; 220 /** Indicates that a pin map exists for pass_sar_ext_mux_en*/ 221 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN (CY_GPIO_DM_STRONG_IN_OFF) 222 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. */ 223 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2]; 224 /** Indicates that a pin map exists for pass_sar_ext_mux_sel*/ 225 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL (CY_GPIO_DM_STRONG_IN_OFF) 226 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. */ 227 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[4]; 228 /** Indicates that a pin map exists for pass_sarmux_pads*/ 229 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 230 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 231 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[34]; 232 /** Indicates that a pin map exists for peri_tr_io_input*/ 233 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 234 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 235 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[12]; 236 /** Indicates that a pin map exists for peri_tr_io_output*/ 237 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 238 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 239 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2]; 240 /** Indicates that a pin map exists for scb_i2c_scl*/ 241 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 242 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 243 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[7]; 244 /** Indicates that a pin map exists for scb_i2c_sda*/ 245 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 246 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 247 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10]; 248 /** Indicates that a pin map exists for scb_spi_m_clk*/ 249 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 250 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 251 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[6]; 252 /** Indicates that a pin map exists for scb_spi_m_miso*/ 253 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 254 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 255 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[9]; 256 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 257 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 258 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 259 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[9]; 260 /** Indicates that a pin map exists for scb_spi_m_select0*/ 261 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 262 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 263 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[7]; 264 /** Indicates that a pin map exists for scb_spi_m_select1*/ 265 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 266 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 267 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; 268 /** Indicates that a pin map exists for scb_spi_m_select2*/ 269 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 270 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 271 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[7]; 272 /** Indicates that a pin map exists for scb_spi_m_select3*/ 273 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 274 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 275 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3]; 276 /** Indicates that a pin map exists for scb_spi_s_clk*/ 277 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 278 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 279 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[6]; 280 /** Indicates that a pin map exists for scb_spi_s_miso*/ 281 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 282 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 283 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[9]; 284 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 285 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 286 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 287 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[9]; 288 /** Indicates that a pin map exists for scb_spi_s_select0*/ 289 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 290 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 291 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[7]; 292 /** Indicates that a pin map exists for scb_spi_s_select1*/ 293 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 294 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 295 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; 296 /** Indicates that a pin map exists for scb_spi_s_select2*/ 297 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 298 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 299 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[7]; 300 /** Indicates that a pin map exists for scb_spi_s_select3*/ 301 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 302 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 303 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3]; 304 /** Indicates that a pin map exists for scb_uart_cts*/ 305 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 306 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 307 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[7]; 308 /** Indicates that a pin map exists for scb_uart_rts*/ 309 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 310 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 311 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6]; 312 /** Indicates that a pin map exists for scb_uart_rx*/ 313 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 314 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 315 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[9]; 316 /** Indicates that a pin map exists for scb_uart_tx*/ 317 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 318 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 319 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[9]; 320 /** Indicates that a pin map exists for tcpwm_line*/ 321 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 322 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 323 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[67]; 324 /** Indicates that a pin map exists for tcpwm_line_compl*/ 325 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 326 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 327 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[67]; 328 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 329 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 330 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 331 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[126]; 332 333 #if defined(__cplusplus) 334 } 335 #endif /* __cplusplus */ 336 337 /** \} group_hal_impl_pin_package */ 338 339 #endif /* _CYHAL_TVIIBE4M_80_LQFP_H_ */ 340 341 342 /* [] END OF FILE */ 343
