1 /***************************************************************************//** 2 * \file cyhal_tviibe4m_176_lqfp.h 3 * 4 * \brief 5 * TVIIBE4M device GPIO HAL header for 176-LQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_TVIIBE4M_176_LQFP_H_ 28 #define _CYHAL_TVIIBE4M_176_LQFP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_tviibe4m_176_lqfp TVIIBE4M 176-LQFP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the TVIIBE4M 176-LQFP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 176-LQFP package for the TVIIBE4M series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 60 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 61 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 62 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 63 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 64 65 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 66 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 67 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 68 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 69 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 70 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 71 72 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 73 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 74 P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 75 P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 76 P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 77 P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 78 79 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 80 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 81 P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2 82 P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3 83 P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4), //!< Port 4 Pin 4 84 85 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 86 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 87 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 88 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 89 P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 90 P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 91 92 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 93 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 94 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 95 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 96 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 97 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 98 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 99 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 100 101 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 102 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 103 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 104 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 105 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 106 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 107 P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 108 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 109 110 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 111 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 112 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 113 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 114 P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 115 116 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 117 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 118 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 119 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 120 121 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 122 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 123 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 124 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 125 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 126 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 127 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 128 P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 129 130 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 131 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 132 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 133 134 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 135 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 136 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 137 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 138 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 139 P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 140 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 141 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 142 143 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 144 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 145 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 146 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 147 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 148 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 149 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 150 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 151 152 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 153 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 154 P14_2 = CYHAL_GET_GPIO(CYHAL_PORT_14, 2), //!< Port 14 Pin 2 155 P14_3 = CYHAL_GET_GPIO(CYHAL_PORT_14, 3), //!< Port 14 Pin 3 156 P14_4 = CYHAL_GET_GPIO(CYHAL_PORT_14, 4), //!< Port 14 Pin 4 157 P14_5 = CYHAL_GET_GPIO(CYHAL_PORT_14, 5), //!< Port 14 Pin 5 158 P14_6 = CYHAL_GET_GPIO(CYHAL_PORT_14, 6), //!< Port 14 Pin 6 159 P14_7 = CYHAL_GET_GPIO(CYHAL_PORT_14, 7), //!< Port 14 Pin 7 160 161 P15_0 = CYHAL_GET_GPIO(CYHAL_PORT_15, 0), //!< Port 15 Pin 0 162 P15_1 = CYHAL_GET_GPIO(CYHAL_PORT_15, 1), //!< Port 15 Pin 1 163 P15_2 = CYHAL_GET_GPIO(CYHAL_PORT_15, 2), //!< Port 15 Pin 2 164 P15_3 = CYHAL_GET_GPIO(CYHAL_PORT_15, 3), //!< Port 15 Pin 3 165 166 P16_0 = CYHAL_GET_GPIO(CYHAL_PORT_16, 0), //!< Port 16 Pin 0 167 P16_1 = CYHAL_GET_GPIO(CYHAL_PORT_16, 1), //!< Port 16 Pin 1 168 P16_2 = CYHAL_GET_GPIO(CYHAL_PORT_16, 2), //!< Port 16 Pin 2 169 P16_3 = CYHAL_GET_GPIO(CYHAL_PORT_16, 3), //!< Port 16 Pin 3 170 171 P17_0 = CYHAL_GET_GPIO(CYHAL_PORT_17, 0), //!< Port 17 Pin 0 172 P17_1 = CYHAL_GET_GPIO(CYHAL_PORT_17, 1), //!< Port 17 Pin 1 173 P17_2 = CYHAL_GET_GPIO(CYHAL_PORT_17, 2), //!< Port 17 Pin 2 174 P17_3 = CYHAL_GET_GPIO(CYHAL_PORT_17, 3), //!< Port 17 Pin 3 175 P17_4 = CYHAL_GET_GPIO(CYHAL_PORT_17, 4), //!< Port 17 Pin 4 176 P17_5 = CYHAL_GET_GPIO(CYHAL_PORT_17, 5), //!< Port 17 Pin 5 177 P17_6 = CYHAL_GET_GPIO(CYHAL_PORT_17, 6), //!< Port 17 Pin 6 178 P17_7 = CYHAL_GET_GPIO(CYHAL_PORT_17, 7), //!< Port 17 Pin 7 179 180 P18_0 = CYHAL_GET_GPIO(CYHAL_PORT_18, 0), //!< Port 18 Pin 0 181 P18_1 = CYHAL_GET_GPIO(CYHAL_PORT_18, 1), //!< Port 18 Pin 1 182 P18_2 = CYHAL_GET_GPIO(CYHAL_PORT_18, 2), //!< Port 18 Pin 2 183 P18_3 = CYHAL_GET_GPIO(CYHAL_PORT_18, 3), //!< Port 18 Pin 3 184 P18_4 = CYHAL_GET_GPIO(CYHAL_PORT_18, 4), //!< Port 18 Pin 4 185 P18_5 = CYHAL_GET_GPIO(CYHAL_PORT_18, 5), //!< Port 18 Pin 5 186 P18_6 = CYHAL_GET_GPIO(CYHAL_PORT_18, 6), //!< Port 18 Pin 6 187 P18_7 = CYHAL_GET_GPIO(CYHAL_PORT_18, 7), //!< Port 18 Pin 7 188 189 P19_0 = CYHAL_GET_GPIO(CYHAL_PORT_19, 0), //!< Port 19 Pin 0 190 P19_1 = CYHAL_GET_GPIO(CYHAL_PORT_19, 1), //!< Port 19 Pin 1 191 P19_2 = CYHAL_GET_GPIO(CYHAL_PORT_19, 2), //!< Port 19 Pin 2 192 P19_3 = CYHAL_GET_GPIO(CYHAL_PORT_19, 3), //!< Port 19 Pin 3 193 P19_4 = CYHAL_GET_GPIO(CYHAL_PORT_19, 4), //!< Port 19 Pin 4 194 195 P20_0 = CYHAL_GET_GPIO(CYHAL_PORT_20, 0), //!< Port 20 Pin 0 196 P20_1 = CYHAL_GET_GPIO(CYHAL_PORT_20, 1), //!< Port 20 Pin 1 197 P20_2 = CYHAL_GET_GPIO(CYHAL_PORT_20, 2), //!< Port 20 Pin 2 198 P20_3 = CYHAL_GET_GPIO(CYHAL_PORT_20, 3), //!< Port 20 Pin 3 199 P20_4 = CYHAL_GET_GPIO(CYHAL_PORT_20, 4), //!< Port 20 Pin 4 200 P20_5 = CYHAL_GET_GPIO(CYHAL_PORT_20, 5), //!< Port 20 Pin 5 201 P20_6 = CYHAL_GET_GPIO(CYHAL_PORT_20, 6), //!< Port 20 Pin 6 202 P20_7 = CYHAL_GET_GPIO(CYHAL_PORT_20, 7), //!< Port 20 Pin 7 203 204 P21_0 = CYHAL_GET_GPIO(CYHAL_PORT_21, 0), //!< Port 21 Pin 0 205 P21_1 = CYHAL_GET_GPIO(CYHAL_PORT_21, 1), //!< Port 21 Pin 1 206 P21_2 = CYHAL_GET_GPIO(CYHAL_PORT_21, 2), //!< Port 21 Pin 2 207 P21_3 = CYHAL_GET_GPIO(CYHAL_PORT_21, 3), //!< Port 21 Pin 3 208 P21_4 = CYHAL_GET_GPIO(CYHAL_PORT_21, 4), //!< Port 21 Pin 4 209 P21_5 = CYHAL_GET_GPIO(CYHAL_PORT_21, 5), //!< Port 21 Pin 5 210 P21_6 = CYHAL_GET_GPIO(CYHAL_PORT_21, 6), //!< Port 21 Pin 6 211 P21_7 = CYHAL_GET_GPIO(CYHAL_PORT_21, 7), //!< Port 21 Pin 7 212 213 P22_0 = CYHAL_GET_GPIO(CYHAL_PORT_22, 0), //!< Port 22 Pin 0 214 P22_1 = CYHAL_GET_GPIO(CYHAL_PORT_22, 1), //!< Port 22 Pin 1 215 P22_2 = CYHAL_GET_GPIO(CYHAL_PORT_22, 2), //!< Port 22 Pin 2 216 P22_3 = CYHAL_GET_GPIO(CYHAL_PORT_22, 3), //!< Port 22 Pin 3 217 P22_4 = CYHAL_GET_GPIO(CYHAL_PORT_22, 4), //!< Port 22 Pin 4 218 P22_5 = CYHAL_GET_GPIO(CYHAL_PORT_22, 5), //!< Port 22 Pin 5 219 P22_6 = CYHAL_GET_GPIO(CYHAL_PORT_22, 6), //!< Port 22 Pin 6 220 P22_7 = CYHAL_GET_GPIO(CYHAL_PORT_22, 7), //!< Port 22 Pin 7 221 222 P23_0 = CYHAL_GET_GPIO(CYHAL_PORT_23, 0), //!< Port 23 Pin 0 223 P23_1 = CYHAL_GET_GPIO(CYHAL_PORT_23, 1), //!< Port 23 Pin 1 224 P23_2 = CYHAL_GET_GPIO(CYHAL_PORT_23, 2), //!< Port 23 Pin 2 225 P23_3 = CYHAL_GET_GPIO(CYHAL_PORT_23, 3), //!< Port 23 Pin 3 226 P23_4 = CYHAL_GET_GPIO(CYHAL_PORT_23, 4), //!< Port 23 Pin 4 227 P23_5 = CYHAL_GET_GPIO(CYHAL_PORT_23, 5), //!< Port 23 Pin 5 228 P23_6 = CYHAL_GET_GPIO(CYHAL_PORT_23, 6), //!< Port 23 Pin 6 229 P23_7 = CYHAL_GET_GPIO(CYHAL_PORT_23, 7), //!< Port 23 Pin 7 230 } cyhal_gpio_tviibe4m_176_lqfp_t; 231 232 /** Create generic name for the series/package specific type. */ 233 typedef cyhal_gpio_tviibe4m_176_lqfp_t cyhal_gpio_t; 234 235 /* Connection type definition */ 236 /** Represents an association between a pin and a resource */ 237 typedef struct 238 { 239 uint8_t block_num; //!< The block number of the resource with this connection 240 uint8_t channel_num; //!< The channel number of the block with this connection 241 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 242 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 243 } cyhal_resource_pin_mapping_t; 244 245 /* Pin connections */ 246 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 247 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 248 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 249 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[15]; 250 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 251 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 252 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 253 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[15]; 254 /** Indicates that a pin map exists for cpuss_cal_sup_nz*/ 255 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CAL_SUP_NZ (CY_GPIO_DM_STRONG_IN_OFF) 256 /** List of valid pin to peripheral connections for the cpuss_cal_sup_nz signal. */ 257 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3]; 258 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 259 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 260 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 261 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 262 /** Indicates that a pin map exists for cpuss_fault_out*/ 263 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 264 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 265 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8]; 266 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 267 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 268 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 269 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 270 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 271 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 272 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 273 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 274 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 275 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 276 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 277 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 278 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 279 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 280 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 281 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 282 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 283 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 284 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 285 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 286 /** Indicates that a pin map exists for cpuss_trace_clock*/ 287 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 288 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 289 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2]; 290 /** Indicates that a pin map exists for cpuss_trace_data*/ 291 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 292 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 293 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 294 /** Indicates that a pin map exists for cxpi_cxpi_en*/ 295 #define CYHAL_PIN_MAP_DRIVE_MODE_CXPI_CXPI_EN (CY_GPIO_DM_STRONG_IN_OFF) 296 /** List of valid pin to peripheral connections for the cxpi_cxpi_en signal. */ 297 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_en[8]; 298 /** Indicates that a pin map exists for cxpi_cxpi_rx*/ 299 #define CYHAL_PIN_MAP_DRIVE_MODE_CXPI_CXPI_RX (CY_GPIO_DM_STRONG_IN_OFF) 300 /** List of valid pin to peripheral connections for the cxpi_cxpi_rx signal. */ 301 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_rx[8]; 302 /** Indicates that a pin map exists for cxpi_cxpi_tx*/ 303 #define CYHAL_PIN_MAP_DRIVE_MODE_CXPI_CXPI_TX (CY_GPIO_DM_STRONG_IN_OFF) 304 /** List of valid pin to peripheral connections for the cxpi_cxpi_tx signal. */ 305 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cxpi_cxpi_tx[8]; 306 /** Indicates that a pin map exists for lin_lin_en*/ 307 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_EN (CY_GPIO_DM_HIGHZ) 308 /** List of valid pin to peripheral connections for the lin_lin_en signal. */ 309 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[21]; 310 /** Indicates that a pin map exists for lin_lin_rx*/ 311 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_RX (CY_GPIO_DM_HIGHZ) 312 /** List of valid pin to peripheral connections for the lin_lin_rx signal. */ 313 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[21]; 314 /** Indicates that a pin map exists for lin_lin_tx*/ 315 #define CYHAL_PIN_MAP_DRIVE_MODE_LIN_LIN_TX (CY_GPIO_DM_STRONG_IN_OFF) 316 /** List of valid pin to peripheral connections for the lin_lin_tx signal. */ 317 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[21]; 318 /** Indicates that a pin map exists for pass_sar_ext_mux_en*/ 319 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_EN (CY_GPIO_DM_STRONG_IN_OFF) 320 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_en signal. */ 321 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3]; 322 /** Indicates that a pin map exists for pass_sar_ext_mux_sel*/ 323 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_MUX_SEL (CY_GPIO_DM_STRONG_IN_OFF) 324 /** List of valid pin to peripheral connections for the pass_sar_ext_mux_sel signal. */ 325 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9]; 326 /** Indicates that a pin map exists for pass_sarmux_pads*/ 327 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 328 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 329 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[64]; 330 /** Indicates that a pin map exists for peri_tr_io_input*/ 331 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 332 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 333 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[32]; 334 /** Indicates that a pin map exists for peri_tr_io_output*/ 335 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 336 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 337 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 338 /** Indicates that a pin map exists for scb_i2c_scl*/ 339 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 340 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 341 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[17]; 342 /** Indicates that a pin map exists for scb_i2c_sda*/ 343 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 344 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 345 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[17]; 346 /** Indicates that a pin map exists for scb_spi_m_clk*/ 347 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 348 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 349 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16]; 350 /** Indicates that a pin map exists for scb_spi_m_miso*/ 351 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 352 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 353 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[16]; 354 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 355 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 356 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 357 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[16]; 358 /** Indicates that a pin map exists for scb_spi_m_select0*/ 359 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 360 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 361 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16]; 362 /** Indicates that a pin map exists for scb_spi_m_select1*/ 363 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 364 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 365 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[15]; 366 /** Indicates that a pin map exists for scb_spi_m_select2*/ 367 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 368 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 369 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[15]; 370 /** Indicates that a pin map exists for scb_spi_m_select3*/ 371 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 372 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 373 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; 374 /** Indicates that a pin map exists for scb_spi_s_clk*/ 375 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 376 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 377 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16]; 378 /** Indicates that a pin map exists for scb_spi_s_miso*/ 379 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 380 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 381 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[16]; 382 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 383 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 384 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 385 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[16]; 386 /** Indicates that a pin map exists for scb_spi_s_select0*/ 387 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 388 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 389 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16]; 390 /** Indicates that a pin map exists for scb_spi_s_select1*/ 391 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 392 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 393 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[15]; 394 /** Indicates that a pin map exists for scb_spi_s_select2*/ 395 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 396 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 397 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[15]; 398 /** Indicates that a pin map exists for scb_spi_s_select3*/ 399 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 400 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 401 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; 402 /** Indicates that a pin map exists for scb_uart_cts*/ 403 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 404 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 405 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[15]; 406 /** Indicates that a pin map exists for scb_uart_rts*/ 407 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 408 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 409 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[15]; 410 /** Indicates that a pin map exists for scb_uart_rx*/ 411 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 412 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 413 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15]; 414 /** Indicates that a pin map exists for scb_uart_tx*/ 415 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 416 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 417 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[15]; 418 /** Indicates that a pin map exists for tcpwm_line*/ 419 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 420 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 421 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[165]; 422 /** Indicates that a pin map exists for tcpwm_line_compl*/ 423 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 424 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 425 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[165]; 426 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 427 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 428 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 429 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[322]; 430 431 #if defined(__cplusplus) 432 } 433 #endif /* __cplusplus */ 434 435 /** \} group_hal_impl_pin_package */ 436 437 #endif /* _CYHAL_TVIIBE4M_176_LQFP_H_ */ 438 439 440 /* [] END OF FILE */ 441
