1 /***************************************************************************//** 2 * \file cyhal_psoc6_04_80_tqfp.h 3 * 4 * \brief 5 * PSoC6_04 device GPIO HAL header for 80-TQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_PSOC6_04_80_TQFP_H_ 28 #define _CYHAL_PSOC6_04_80_TQFP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_psoc6_04_80_tqfp PSoC6_04 80-TQFP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the PSoC6_04 80-TQFP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 80-TQFP package for the PSoC6_04 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 60 P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 61 62 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 63 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 64 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 65 66 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 67 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 68 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 69 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 70 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 71 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 72 P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 73 P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 74 75 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 76 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 77 78 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 79 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 80 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 81 P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 82 P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 83 84 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 85 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 86 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 87 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 88 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 89 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 90 91 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 92 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 93 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 94 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 95 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 96 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 97 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 98 99 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 100 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 101 102 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 103 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 104 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 105 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 106 P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 107 P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 108 109 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 110 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 111 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 112 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 113 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 114 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 115 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 116 P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 117 118 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 119 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 120 P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 121 P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 122 P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 123 P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 124 P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 125 126 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 127 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 128 } cyhal_gpio_psoc6_04_80_tqfp_t; 129 130 /** Create generic name for the series/package specific type. */ 131 typedef cyhal_gpio_psoc6_04_80_tqfp_t cyhal_gpio_t; 132 133 /* Connection type definition */ 134 /** Represents an association between a pin and a resource */ 135 typedef struct 136 { 137 uint8_t block_num; //!< The block number of the resource with this connection 138 uint8_t channel_num; //!< The channel number of the block with this connection 139 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 140 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 141 } cyhal_resource_pin_mapping_t; 142 143 /* Pin connections */ 144 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 145 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 146 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 147 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; 148 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 149 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 150 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 151 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; 152 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 153 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 154 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 155 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 156 /** Indicates that a pin map exists for cpuss_fault_out*/ 157 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 158 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 159 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[2]; 160 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 161 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 162 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 163 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 164 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 165 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 166 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 167 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 168 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 169 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 170 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 171 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 172 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 173 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 174 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 175 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 176 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 177 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 178 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 179 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 180 /** Indicates that a pin map exists for cpuss_trace_clock*/ 181 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 182 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 183 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 184 /** Indicates that a pin map exists for cpuss_trace_data*/ 185 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 186 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 187 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8]; 188 /** Indicates that a pin map exists for lpcomp_dsi_comp*/ 189 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_DSI_COMP (CY_GPIO_DM_STRONG_IN_OFF) 190 /** List of valid pin to peripheral connections for the lpcomp_dsi_comp signal. */ 191 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp[2]; 192 /** Indicates that a pin map exists for lpcomp_inn_comp*/ 193 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) 194 /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ 195 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2]; 196 /** Indicates that a pin map exists for lpcomp_inp_comp*/ 197 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) 198 /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ 199 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; 200 /** Indicates that a pin map exists for opamp_dsi_ctb_cmp*/ 201 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_DSI_CTB_CMP (CY_GPIO_DM_STRONG_IN_OFF) 202 /** List of valid pin to peripheral connections for the opamp_dsi_ctb_cmp signal. */ 203 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_dsi_ctb_cmp[2]; 204 /** Indicates that a pin map exists for opamp_out_10x*/ 205 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_OUT_10X (CY_GPIO_DM_ANALOG) 206 /** List of valid pin to peripheral connections for the opamp_out_10x signal. */ 207 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_out_10x[2]; 208 /** Indicates that a pin map exists for opamp_vin_m*/ 209 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_M (CY_GPIO_DM_ANALOG) 210 /** List of valid pin to peripheral connections for the opamp_vin_m signal. */ 211 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_m[2]; 212 /** Indicates that a pin map exists for opamp_vin_p0*/ 213 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P0 (CY_GPIO_DM_ANALOG) 214 /** List of valid pin to peripheral connections for the opamp_vin_p0 signal. */ 215 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p0[2]; 216 /** Indicates that a pin map exists for pass_sarmux_pads*/ 217 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 218 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 219 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[16]; 220 /** Indicates that a pin map exists for peri_tr_io_input*/ 221 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 222 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 223 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[24]; 224 /** Indicates that a pin map exists for peri_tr_io_output*/ 225 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 226 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 227 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 228 /** Indicates that a pin map exists for scb_i2c_scl*/ 229 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 230 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 231 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[9]; 232 /** Indicates that a pin map exists for scb_i2c_sda*/ 233 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 234 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 235 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[9]; 236 /** Indicates that a pin map exists for scb_spi_m_clk*/ 237 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 238 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 239 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[7]; 240 /** Indicates that a pin map exists for scb_spi_m_miso*/ 241 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 242 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 243 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[8]; 244 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 245 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 246 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 247 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[8]; 248 /** Indicates that a pin map exists for scb_spi_m_select0*/ 249 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 250 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 251 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[7]; 252 /** Indicates that a pin map exists for scb_spi_m_select1*/ 253 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 254 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 255 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[6]; 256 /** Indicates that a pin map exists for scb_spi_m_select2*/ 257 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 258 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 259 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[6]; 260 /** Indicates that a pin map exists for scb_spi_m_select3*/ 261 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 262 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 263 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3]; 264 /** Indicates that a pin map exists for scb_spi_s_clk*/ 265 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 266 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 267 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[7]; 268 /** Indicates that a pin map exists for scb_spi_s_miso*/ 269 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 270 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 271 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[8]; 272 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 273 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 274 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 275 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[8]; 276 /** Indicates that a pin map exists for scb_spi_s_select0*/ 277 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 278 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 279 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[7]; 280 /** Indicates that a pin map exists for scb_spi_s_select1*/ 281 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 282 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 283 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[6]; 284 /** Indicates that a pin map exists for scb_spi_s_select2*/ 285 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 286 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 287 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[6]; 288 /** Indicates that a pin map exists for scb_spi_s_select3*/ 289 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 290 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 291 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3]; 292 /** Indicates that a pin map exists for scb_uart_cts*/ 293 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 294 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 295 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; 296 /** Indicates that a pin map exists for scb_uart_rts*/ 297 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 298 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 299 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6]; 300 /** Indicates that a pin map exists for scb_uart_rx*/ 301 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 302 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 303 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8]; 304 /** Indicates that a pin map exists for scb_uart_tx*/ 305 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 306 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 307 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[8]; 308 /** Indicates that a pin map exists for smif_spi_clk*/ 309 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 310 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 311 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 312 /** Indicates that a pin map exists for smif_spi_data0*/ 313 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 314 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 315 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 316 /** Indicates that a pin map exists for smif_spi_data1*/ 317 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 318 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 319 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 320 /** Indicates that a pin map exists for smif_spi_data2*/ 321 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 322 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 323 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 324 /** Indicates that a pin map exists for smif_spi_data3*/ 325 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 326 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 327 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 328 /** Indicates that a pin map exists for smif_spi_select0*/ 329 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 330 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 331 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 332 /** Indicates that a pin map exists for smif_spi_select1*/ 333 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 334 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 335 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 336 /** Indicates that a pin map exists for smif_spi_select2*/ 337 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 338 /** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ 339 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; 340 /** Indicates that a pin map exists for tcpwm_line*/ 341 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 342 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 343 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[53]; 344 /** Indicates that a pin map exists for tcpwm_line_compl*/ 345 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 346 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 347 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[53]; 348 /** Indicates that a pin map exists for tcpwm_tr_one_cnt_in*/ 349 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_ONE_CNT_IN (CY_GPIO_DM_HIGHZ) 350 /** List of valid pin to peripheral connections for the tcpwm_tr_one_cnt_in signal. */ 351 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[62]; 352 /** Indicates that a pin map exists for usb_usb_dm_pad*/ 353 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DM_PAD (CY_GPIO_DM_ANALOG) 354 /** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ 355 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; 356 /** Indicates that a pin map exists for usb_usb_dp_pad*/ 357 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DP_PAD (CY_GPIO_DM_ANALOG) 358 /** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ 359 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; 360 361 #if defined(__cplusplus) 362 } 363 #endif /* __cplusplus */ 364 365 /** \} group_hal_impl_pin_package */ 366 367 #endif /* _CYHAL_PSOC6_04_80_TQFP_H_ */ 368 369 370 /* [] END OF FILE */ 371
