1 /***************************************************************************//** 2 * \file cyhal_psoc6_03_100_tqfp.h 3 * 4 * \brief 5 * PSoC6_03 device GPIO HAL header for 100-TQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_PSOC6_03_100_TQFP_H_ 28 #define _CYHAL_PSOC6_03_100_TQFP_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_psoc6_03_100_tqfp PSoC6_03 100-TQFP 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the PSoC6_03 100-TQFP package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 100-TQFP package for the PSoC6_03 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 60 P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 61 62 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 63 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 64 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 65 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 66 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 67 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 68 P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 69 P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 70 71 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 72 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 73 74 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 75 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 76 P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 77 P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 78 79 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 80 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 81 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 82 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 83 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 84 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 85 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 86 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 87 88 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 89 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 90 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 91 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 92 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 93 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 94 P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 95 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 96 97 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 98 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 99 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 100 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 101 102 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 103 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 104 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 105 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 106 107 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 108 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 109 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 110 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 111 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 112 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 113 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 114 P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 115 116 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 117 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 118 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 119 P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 120 P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 121 P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 122 P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 123 P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 124 125 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 126 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 127 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 128 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 129 130 USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 131 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 132 USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 133 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 134 } cyhal_gpio_psoc6_03_100_tqfp_t; 135 136 /** Create generic name for the series/package specific type. */ 137 typedef cyhal_gpio_psoc6_03_100_tqfp_t cyhal_gpio_t; 138 139 /* Connection type definition */ 140 /** Represents an association between a pin and a resource */ 141 typedef struct 142 { 143 uint8_t block_num; //!< The block number of the resource with this connection 144 uint8_t channel_num; //!< The channel number of the block with this connection 145 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 146 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 147 } cyhal_resource_pin_mapping_t; 148 149 /* Pin connections */ 150 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 151 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 152 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 153 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; 154 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 155 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 156 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 157 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; 158 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 159 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 160 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 161 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 162 /** Indicates that a pin map exists for cpuss_fault_out*/ 163 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 164 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 165 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[2]; 166 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 167 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 168 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 169 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 170 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 171 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 172 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 173 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 174 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 175 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 176 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 177 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 178 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 179 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 180 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 181 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 182 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 183 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 184 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 185 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 186 /** Indicates that a pin map exists for cpuss_trace_clock*/ 187 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 188 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 189 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 190 /** Indicates that a pin map exists for cpuss_trace_data*/ 191 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 192 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 193 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[12]; 194 /** Indicates that a pin map exists for lpcomp_dsi_comp*/ 195 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_DSI_COMP (CY_GPIO_DM_STRONG_IN_OFF) 196 /** List of valid pin to peripheral connections for the lpcomp_dsi_comp signal. */ 197 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp[2]; 198 /** Indicates that a pin map exists for lpcomp_inn_comp*/ 199 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) 200 /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ 201 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2]; 202 /** Indicates that a pin map exists for lpcomp_inp_comp*/ 203 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) 204 /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ 205 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; 206 /** Indicates that a pin map exists for pass_sarmux_pads*/ 207 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 208 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 209 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; 210 /** Indicates that a pin map exists for peri_tr_io_input*/ 211 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 212 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 213 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[26]; 214 /** Indicates that a pin map exists for peri_tr_io_output*/ 215 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 216 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 217 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 218 /** Indicates that a pin map exists for scb_i2c_scl*/ 219 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 220 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 221 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12]; 222 /** Indicates that a pin map exists for scb_i2c_sda*/ 223 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 224 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 225 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12]; 226 /** Indicates that a pin map exists for scb_spi_m_clk*/ 227 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 228 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 229 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9]; 230 /** Indicates that a pin map exists for scb_spi_m_miso*/ 231 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 232 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 233 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11]; 234 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 235 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 236 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 237 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11]; 238 /** Indicates that a pin map exists for scb_spi_m_select0*/ 239 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 240 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 241 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[9]; 242 /** Indicates that a pin map exists for scb_spi_m_select1*/ 243 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 244 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 245 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; 246 /** Indicates that a pin map exists for scb_spi_m_select2*/ 247 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 248 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 249 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[5]; 250 /** Indicates that a pin map exists for scb_spi_m_select3*/ 251 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 252 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 253 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; 254 /** Indicates that a pin map exists for scb_spi_s_clk*/ 255 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 256 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 257 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9]; 258 /** Indicates that a pin map exists for scb_spi_s_miso*/ 259 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 260 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 261 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11]; 262 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 263 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 264 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 265 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11]; 266 /** Indicates that a pin map exists for scb_spi_s_select0*/ 267 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 268 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 269 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[9]; 270 /** Indicates that a pin map exists for scb_spi_s_select1*/ 271 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 272 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 273 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; 274 /** Indicates that a pin map exists for scb_spi_s_select2*/ 275 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 276 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 277 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[5]; 278 /** Indicates that a pin map exists for scb_spi_s_select3*/ 279 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 280 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 281 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; 282 /** Indicates that a pin map exists for scb_uart_cts*/ 283 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 284 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 285 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[8]; 286 /** Indicates that a pin map exists for scb_uart_rts*/ 287 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 288 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 289 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[8]; 290 /** Indicates that a pin map exists for scb_uart_rx*/ 291 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 292 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 293 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[10]; 294 /** Indicates that a pin map exists for scb_uart_tx*/ 295 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 296 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 297 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[10]; 298 /** Indicates that a pin map exists for sdhc_card_cmd*/ 299 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_CMD (CY_GPIO_DM_STRONG) 300 /** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ 301 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; 302 /** Indicates that a pin map exists for sdhc_card_dat_3to0*/ 303 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_3TO0 (CY_GPIO_DM_STRONG) 304 /** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ 305 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; 306 /** Indicates that a pin map exists for sdhc_card_detect_n*/ 307 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DETECT_N (CY_GPIO_DM_HIGHZ) 308 /** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ 309 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; 310 /** Indicates that a pin map exists for sdhc_card_if_pwr_en*/ 311 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_IF_PWR_EN (CY_GPIO_DM_STRONG_IN_OFF) 312 /** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ 313 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; 314 /** Indicates that a pin map exists for sdhc_card_mech_write_prot*/ 315 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_MECH_WRITE_PROT (CY_GPIO_DM_HIGHZ) 316 /** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ 317 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; 318 /** Indicates that a pin map exists for sdhc_clk_card*/ 319 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CLK_CARD (CY_GPIO_DM_STRONG) 320 /** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ 321 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; 322 /** Indicates that a pin map exists for sdhc_io_volt_sel*/ 323 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_IO_VOLT_SEL (CY_GPIO_DM_STRONG_IN_OFF) 324 /** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ 325 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1]; 326 /** Indicates that a pin map exists for smif_spi_clk*/ 327 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 328 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 329 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 330 /** Indicates that a pin map exists for smif_spi_data0*/ 331 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 332 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 333 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 334 /** Indicates that a pin map exists for smif_spi_data1*/ 335 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 336 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 337 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 338 /** Indicates that a pin map exists for smif_spi_data2*/ 339 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 340 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 341 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 342 /** Indicates that a pin map exists for smif_spi_data3*/ 343 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 344 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 345 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 346 /** Indicates that a pin map exists for smif_spi_select0*/ 347 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 348 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 349 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 350 /** Indicates that a pin map exists for smif_spi_select1*/ 351 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 352 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 353 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 354 /** Indicates that a pin map exists for smif_spi_select2*/ 355 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 356 /** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ 357 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; 358 /** Indicates that a pin map exists for tcpwm_line*/ 359 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 360 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 361 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[64]; 362 /** Indicates that a pin map exists for tcpwm_line_compl*/ 363 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 364 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 365 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[64]; 366 /** Indicates that a pin map exists for usb_usb_dm_pad*/ 367 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DM_PAD (CY_GPIO_DM_ANALOG) 368 /** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ 369 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[2]; 370 /** Indicates that a pin map exists for usb_usb_dp_pad*/ 371 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DP_PAD (CY_GPIO_DM_ANALOG) 372 /** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ 373 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[2]; 374 375 #if defined(__cplusplus) 376 } 377 #endif /* __cplusplus */ 378 379 /** \} group_hal_impl_pin_package */ 380 381 #endif /* _CYHAL_PSOC6_03_100_TQFP_H_ */ 382 383 384 /* [] END OF FILE */ 385
