1 /***************************************************************************//** 2 * \file cyhal_psoc6_02_68_qfn.h 3 * 4 * \brief 5 * PSoC6_02 device GPIO HAL header for 68-QFN package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_PSOC6_02_68_QFN_H_ 28 #define _CYHAL_PSOC6_02_68_QFN_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_psoc6_02_68_qfn PSoC6_02 68-QFN 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the PSoC6_02 68-QFN package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 68-QFN package for the PSoC6_02 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 60 P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 61 62 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 63 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 64 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 65 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 66 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 67 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 68 P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 69 P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 70 71 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 72 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 73 74 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 75 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 76 P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 77 P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 78 79 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 80 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 81 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 82 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 83 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 84 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 85 86 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 87 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 88 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 89 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 90 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 91 92 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 93 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 94 95 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 96 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 97 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 98 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 99 100 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 101 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 102 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 103 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 104 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 105 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 106 107 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 108 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 109 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 110 P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 111 P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 112 P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 113 P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 114 P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 115 116 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 117 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 118 119 USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 120 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 121 USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 122 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 123 } cyhal_gpio_psoc6_02_68_qfn_t; 124 125 /** Create generic name for the series/package specific type. */ 126 typedef cyhal_gpio_psoc6_02_68_qfn_t cyhal_gpio_t; 127 128 /* Connection type definition */ 129 /** Represents an association between a pin and a resource */ 130 typedef struct 131 { 132 uint8_t block_num; //!< The block number of the resource with this connection 133 uint8_t channel_num; //!< The channel number of the block with this connection 134 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 135 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 136 } cyhal_resource_pin_mapping_t; 137 138 /* Pin connections */ 139 /** Indicates that a pin map exists for audioss_clk_i2s_if*/ 140 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ) 141 /** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ 142 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3]; 143 /** Indicates that a pin map exists for audioss_pdm_clk*/ 144 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_PDM_CLK (CY_GPIO_DM_STRONG_IN_OFF) 145 /** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ 146 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1]; 147 /** Indicates that a pin map exists for audioss_pdm_data*/ 148 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_PDM_DATA (CY_GPIO_DM_HIGHZ) 149 /** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ 150 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; 151 /** Indicates that a pin map exists for audioss_rx_sck*/ 152 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 153 /** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ 154 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; 155 /** Indicates that a pin map exists for audioss_rx_sdi*/ 156 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ) 157 /** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ 158 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[2]; 159 /** Indicates that a pin map exists for audioss_rx_ws*/ 160 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF) 161 /** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ 162 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; 163 /** Indicates that a pin map exists for audioss_tx_sck*/ 164 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 165 /** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ 166 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3]; 167 /** Indicates that a pin map exists for audioss_tx_sdo*/ 168 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF) 169 /** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ 170 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[2]; 171 /** Indicates that a pin map exists for audioss_tx_ws*/ 172 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF) 173 /** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ 174 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[2]; 175 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 176 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 177 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 178 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 179 /** Indicates that a pin map exists for cpuss_fault_out*/ 180 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 181 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 182 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[1]; 183 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 184 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 185 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 186 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 187 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 188 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 189 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 190 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 191 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 192 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 193 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 194 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 195 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 196 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 197 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 198 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 199 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 200 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 201 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 202 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 203 /** Indicates that a pin map exists for cpuss_trace_clock*/ 204 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 205 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 206 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 207 /** Indicates that a pin map exists for cpuss_trace_data*/ 208 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 209 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 210 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[9]; 211 /** Indicates that a pin map exists for lpcomp_dsi_comp*/ 212 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_DSI_COMP (CY_GPIO_DM_STRONG_IN_OFF) 213 /** List of valid pin to peripheral connections for the lpcomp_dsi_comp signal. */ 214 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp[1]; 215 /** Indicates that a pin map exists for lpcomp_inn_comp*/ 216 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) 217 /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ 218 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2]; 219 /** Indicates that a pin map exists for lpcomp_inp_comp*/ 220 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) 221 /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ 222 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; 223 /** Indicates that a pin map exists for pass_sarmux_pads*/ 224 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 225 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 226 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6]; 227 /** Indicates that a pin map exists for peri_tr_io_input*/ 228 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 229 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 230 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[20]; 231 /** Indicates that a pin map exists for peri_tr_io_output*/ 232 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 233 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 234 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 235 /** Indicates that a pin map exists for scb_i2c_scl*/ 236 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 237 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 238 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12]; 239 /** Indicates that a pin map exists for scb_i2c_sda*/ 240 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 241 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 242 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12]; 243 /** Indicates that a pin map exists for scb_spi_m_clk*/ 244 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 245 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 246 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[10]; 247 /** Indicates that a pin map exists for scb_spi_m_miso*/ 248 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 249 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 250 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11]; 251 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 252 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 253 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 254 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11]; 255 /** Indicates that a pin map exists for scb_spi_m_select0*/ 256 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 257 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 258 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[10]; 259 /** Indicates that a pin map exists for scb_spi_m_select1*/ 260 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 261 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 262 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; 263 /** Indicates that a pin map exists for scb_spi_m_select2*/ 264 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 265 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 266 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4]; 267 /** Indicates that a pin map exists for scb_spi_m_select3*/ 268 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 269 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 270 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[5]; 271 /** Indicates that a pin map exists for scb_spi_s_clk*/ 272 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 273 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 274 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[10]; 275 /** Indicates that a pin map exists for scb_spi_s_miso*/ 276 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 277 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 278 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11]; 279 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 280 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 281 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 282 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11]; 283 /** Indicates that a pin map exists for scb_spi_s_select0*/ 284 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 285 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 286 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[10]; 287 /** Indicates that a pin map exists for scb_spi_s_select1*/ 288 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 289 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 290 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; 291 /** Indicates that a pin map exists for scb_spi_s_select2*/ 292 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 293 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 294 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4]; 295 /** Indicates that a pin map exists for scb_spi_s_select3*/ 296 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 297 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 298 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[5]; 299 /** Indicates that a pin map exists for scb_uart_cts*/ 300 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 301 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 302 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10]; 303 /** Indicates that a pin map exists for scb_uart_rts*/ 304 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 305 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 306 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10]; 307 /** Indicates that a pin map exists for scb_uart_rx*/ 308 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 309 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 310 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11]; 311 /** Indicates that a pin map exists for scb_uart_tx*/ 312 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 313 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 314 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11]; 315 /** Indicates that a pin map exists for sdhc_card_cmd*/ 316 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_CMD (CY_GPIO_DM_STRONG) 317 /** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ 318 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; 319 /** Indicates that a pin map exists for sdhc_card_dat_3to0*/ 320 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_3TO0 (CY_GPIO_DM_STRONG) 321 /** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ 322 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; 323 /** Indicates that a pin map exists for sdhc_card_dat_7to4*/ 324 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_7TO4 (CY_GPIO_DM_STRONG) 325 /** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ 326 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[1]; 327 /** Indicates that a pin map exists for sdhc_card_detect_n*/ 328 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DETECT_N (CY_GPIO_DM_HIGHZ) 329 /** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ 330 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; 331 /** Indicates that a pin map exists for sdhc_card_emmc_reset_n*/ 332 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_EMMC_RESET_N (CY_GPIO_DM_STRONG_IN_OFF) 333 /** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */ 334 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; 335 /** Indicates that a pin map exists for sdhc_card_if_pwr_en*/ 336 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_IF_PWR_EN (CY_GPIO_DM_STRONG_IN_OFF) 337 /** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ 338 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; 339 /** Indicates that a pin map exists for sdhc_card_mech_write_prot*/ 340 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_MECH_WRITE_PROT (CY_GPIO_DM_HIGHZ) 341 /** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ 342 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; 343 /** Indicates that a pin map exists for sdhc_clk_card*/ 344 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CLK_CARD (CY_GPIO_DM_STRONG) 345 /** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ 346 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; 347 /** Indicates that a pin map exists for sdhc_io_volt_sel*/ 348 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_IO_VOLT_SEL (CY_GPIO_DM_STRONG_IN_OFF) 349 /** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ 350 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2]; 351 /** Indicates that a pin map exists for sdhc_led_ctrl*/ 352 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_LED_CTRL (CY_GPIO_DM_STRONG_IN_OFF) 353 /** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */ 354 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; 355 /** Indicates that a pin map exists for smif_spi_clk*/ 356 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 357 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 358 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 359 /** Indicates that a pin map exists for smif_spi_data0*/ 360 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 361 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 362 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 363 /** Indicates that a pin map exists for smif_spi_data1*/ 364 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 365 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 366 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 367 /** Indicates that a pin map exists for smif_spi_data2*/ 368 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 369 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 370 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 371 /** Indicates that a pin map exists for smif_spi_data3*/ 372 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 373 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 374 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 375 /** Indicates that a pin map exists for smif_spi_data4*/ 376 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG) 377 /** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ 378 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; 379 /** Indicates that a pin map exists for smif_spi_data5*/ 380 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG) 381 /** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ 382 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; 383 /** Indicates that a pin map exists for smif_spi_data6*/ 384 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG) 385 /** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ 386 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; 387 /** Indicates that a pin map exists for smif_spi_data7*/ 388 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG) 389 /** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ 390 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; 391 /** Indicates that a pin map exists for smif_spi_select0*/ 392 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 393 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 394 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 395 /** Indicates that a pin map exists for smif_spi_select1*/ 396 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 397 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 398 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 399 /** Indicates that a pin map exists for smif_spi_select2*/ 400 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 401 /** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ 402 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; 403 /** Indicates that a pin map exists for smif_spi_select3*/ 404 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 405 /** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ 406 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; 407 /** Indicates that a pin map exists for tcpwm_line*/ 408 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 409 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 410 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[50]; 411 /** Indicates that a pin map exists for tcpwm_line_compl*/ 412 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 413 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 414 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[52]; 415 /** Indicates that a pin map exists for usb_usb_dm_pad*/ 416 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DM_PAD (CY_GPIO_DM_ANALOG) 417 /** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ 418 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[2]; 419 /** Indicates that a pin map exists for usb_usb_dp_pad*/ 420 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DP_PAD (CY_GPIO_DM_ANALOG) 421 /** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ 422 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[2]; 423 424 #if defined(__cplusplus) 425 } 426 #endif /* __cplusplus */ 427 428 /** \} group_hal_impl_pin_package */ 429 430 #endif /* _CYHAL_PSOC6_02_68_QFN_H_ */ 431 432 433 /* [] END OF FILE */ 434
