1 /***************************************************************************//** 2 * \file cyhal_psoc6_02_124_bga.h 3 * 4 * \brief 5 * PSoC6_02 device GPIO HAL header for 124-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_PSOC6_02_124_BGA_H_ 28 #define _CYHAL_PSOC6_02_124_BGA_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_psoc6_02_124_bga PSoC6_02 124-BGA 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the PSoC6_02 124-BGA package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 124-BGA package for the PSoC6_02 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 60 P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 61 62 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 63 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 64 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 65 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 66 P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 67 P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 68 69 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 70 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 71 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 72 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 73 P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 74 P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 75 P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 76 P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 77 78 P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 79 P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 80 P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 81 P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 82 P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 83 P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 84 85 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 86 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 87 88 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 89 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 90 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 91 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 92 P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 93 P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 94 P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 95 P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 96 97 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 98 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 99 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 100 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 101 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 102 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 103 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 104 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 105 106 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 107 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 108 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 109 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 110 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 111 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 112 P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 113 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 114 115 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 116 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 117 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 118 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 119 P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 120 P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 121 P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 122 P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 123 124 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 125 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 126 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 127 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 128 P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 129 P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 130 P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 131 P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 132 133 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 134 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 135 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 136 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 137 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 138 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 139 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 140 P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 141 142 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 143 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 144 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 145 P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 146 P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 147 P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 148 P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 149 P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 150 151 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 152 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 153 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 154 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 155 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 156 P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 157 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 158 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 159 160 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 161 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 162 P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 163 P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 164 P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 165 P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 166 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 167 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 168 169 USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 170 P14_0 = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 171 USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 172 P14_1 = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 173 } cyhal_gpio_psoc6_02_124_bga_t; 174 175 /** Create generic name for the series/package specific type. */ 176 typedef cyhal_gpio_psoc6_02_124_bga_t cyhal_gpio_t; 177 178 /* Connection type definition */ 179 /** Represents an association between a pin and a resource */ 180 typedef struct 181 { 182 uint8_t block_num; //!< The block number of the resource with this connection 183 uint8_t channel_num; //!< The channel number of the block with this connection 184 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 185 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 186 } cyhal_resource_pin_mapping_t; 187 188 /* Pin connections */ 189 /** Indicates that a pin map exists for audioss_clk_i2s_if*/ 190 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ) 191 /** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ 192 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4]; 193 /** Indicates that a pin map exists for audioss_pdm_clk*/ 194 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_PDM_CLK (CY_GPIO_DM_STRONG_IN_OFF) 195 /** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ 196 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; 197 /** Indicates that a pin map exists for audioss_pdm_data*/ 198 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_PDM_DATA (CY_GPIO_DM_HIGHZ) 199 /** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ 200 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; 201 /** Indicates that a pin map exists for audioss_rx_sck*/ 202 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 203 /** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ 204 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4]; 205 /** Indicates that a pin map exists for audioss_rx_sdi*/ 206 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ) 207 /** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ 208 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[4]; 209 /** Indicates that a pin map exists for audioss_rx_ws*/ 210 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF) 211 /** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ 212 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[4]; 213 /** Indicates that a pin map exists for audioss_tx_sck*/ 214 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 215 /** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ 216 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4]; 217 /** Indicates that a pin map exists for audioss_tx_sdo*/ 218 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF) 219 /** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ 220 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4]; 221 /** Indicates that a pin map exists for audioss_tx_ws*/ 222 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF) 223 /** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ 224 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4]; 225 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 226 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 227 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 228 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 229 /** Indicates that a pin map exists for cpuss_fault_out*/ 230 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 231 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 232 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[2]; 233 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 234 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 235 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 236 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 237 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 238 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 239 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 240 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 241 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 242 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 243 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 244 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 245 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 246 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 247 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 248 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 249 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 250 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 251 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 252 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 253 /** Indicates that a pin map exists for cpuss_trace_clock*/ 254 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 255 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 256 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 257 /** Indicates that a pin map exists for cpuss_trace_data*/ 258 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 259 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 260 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[12]; 261 /** Indicates that a pin map exists for lpcomp_dsi_comp*/ 262 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_DSI_COMP (CY_GPIO_DM_STRONG_IN_OFF) 263 /** List of valid pin to peripheral connections for the lpcomp_dsi_comp signal. */ 264 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp[2]; 265 /** Indicates that a pin map exists for lpcomp_inn_comp*/ 266 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) 267 /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ 268 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2]; 269 /** Indicates that a pin map exists for lpcomp_inp_comp*/ 270 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) 271 /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ 272 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; 273 /** Indicates that a pin map exists for pass_sarmux_pads*/ 274 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 275 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 276 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; 277 /** Indicates that a pin map exists for peri_tr_io_input*/ 278 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 279 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 280 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[28]; 281 /** Indicates that a pin map exists for peri_tr_io_output*/ 282 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 283 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 284 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 285 /** Indicates that a pin map exists for scb_i2c_scl*/ 286 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 287 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 288 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[21]; 289 /** Indicates that a pin map exists for scb_i2c_sda*/ 290 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 291 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 292 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21]; 293 /** Indicates that a pin map exists for scb_spi_m_clk*/ 294 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 295 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 296 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16]; 297 /** Indicates that a pin map exists for scb_spi_m_miso*/ 298 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 299 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 300 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17]; 301 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 302 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 303 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 304 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17]; 305 /** Indicates that a pin map exists for scb_spi_m_select0*/ 306 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 307 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 308 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16]; 309 /** Indicates that a pin map exists for scb_spi_m_select1*/ 310 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 311 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 312 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13]; 313 /** Indicates that a pin map exists for scb_spi_m_select2*/ 314 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 315 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 316 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13]; 317 /** Indicates that a pin map exists for scb_spi_m_select3*/ 318 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 319 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 320 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10]; 321 /** Indicates that a pin map exists for scb_spi_s_clk*/ 322 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 323 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 324 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16]; 325 /** Indicates that a pin map exists for scb_spi_s_miso*/ 326 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 327 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 328 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17]; 329 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 330 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 331 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 332 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17]; 333 /** Indicates that a pin map exists for scb_spi_s_select0*/ 334 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 335 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 336 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16]; 337 /** Indicates that a pin map exists for scb_spi_s_select1*/ 338 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 339 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 340 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13]; 341 /** Indicates that a pin map exists for scb_spi_s_select2*/ 342 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 343 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 344 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13]; 345 /** Indicates that a pin map exists for scb_spi_s_select3*/ 346 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 347 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 348 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10]; 349 /** Indicates that a pin map exists for scb_uart_cts*/ 350 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 351 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 352 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[18]; 353 /** Indicates that a pin map exists for scb_uart_rts*/ 354 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 355 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 356 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[18]; 357 /** Indicates that a pin map exists for scb_uart_rx*/ 358 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 359 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 360 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[19]; 361 /** Indicates that a pin map exists for scb_uart_tx*/ 362 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 363 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 364 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19]; 365 /** Indicates that a pin map exists for sdhc_card_cmd*/ 366 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_CMD (CY_GPIO_DM_STRONG) 367 /** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ 368 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2]; 369 /** Indicates that a pin map exists for sdhc_card_dat_3to0*/ 370 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_3TO0 (CY_GPIO_DM_STRONG) 371 /** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ 372 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8]; 373 /** Indicates that a pin map exists for sdhc_card_dat_7to4*/ 374 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DAT_7TO4 (CY_GPIO_DM_STRONG) 375 /** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ 376 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4]; 377 /** Indicates that a pin map exists for sdhc_card_detect_n*/ 378 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_DETECT_N (CY_GPIO_DM_HIGHZ) 379 /** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ 380 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2]; 381 /** Indicates that a pin map exists for sdhc_card_emmc_reset_n*/ 382 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_EMMC_RESET_N (CY_GPIO_DM_STRONG_IN_OFF) 383 /** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */ 384 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; 385 /** Indicates that a pin map exists for sdhc_card_if_pwr_en*/ 386 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_IF_PWR_EN (CY_GPIO_DM_STRONG_IN_OFF) 387 /** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ 388 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; 389 /** Indicates that a pin map exists for sdhc_card_mech_write_prot*/ 390 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CARD_MECH_WRITE_PROT (CY_GPIO_DM_HIGHZ) 391 /** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ 392 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2]; 393 /** Indicates that a pin map exists for sdhc_clk_card*/ 394 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_CLK_CARD (CY_GPIO_DM_STRONG) 395 /** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ 396 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2]; 397 /** Indicates that a pin map exists for sdhc_io_volt_sel*/ 398 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_IO_VOLT_SEL (CY_GPIO_DM_STRONG_IN_OFF) 399 /** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ 400 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2]; 401 /** Indicates that a pin map exists for sdhc_led_ctrl*/ 402 #define CYHAL_PIN_MAP_DRIVE_MODE_SDHC_LED_CTRL (CY_GPIO_DM_STRONG_IN_OFF) 403 /** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */ 404 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; 405 /** Indicates that a pin map exists for smif_spi_clk*/ 406 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 407 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 408 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 409 /** Indicates that a pin map exists for smif_spi_data0*/ 410 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 411 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 412 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 413 /** Indicates that a pin map exists for smif_spi_data1*/ 414 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 415 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 416 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 417 /** Indicates that a pin map exists for smif_spi_data2*/ 418 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 419 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 420 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 421 /** Indicates that a pin map exists for smif_spi_data3*/ 422 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 423 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 424 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 425 /** Indicates that a pin map exists for smif_spi_data4*/ 426 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG) 427 /** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ 428 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; 429 /** Indicates that a pin map exists for smif_spi_data5*/ 430 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG) 431 /** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ 432 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; 433 /** Indicates that a pin map exists for smif_spi_data6*/ 434 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG) 435 /** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ 436 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; 437 /** Indicates that a pin map exists for smif_spi_data7*/ 438 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG) 439 /** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ 440 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; 441 /** Indicates that a pin map exists for smif_spi_select0*/ 442 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 443 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 444 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 445 /** Indicates that a pin map exists for smif_spi_select1*/ 446 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 447 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 448 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 449 /** Indicates that a pin map exists for smif_spi_select2*/ 450 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 451 /** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ 452 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; 453 /** Indicates that a pin map exists for smif_spi_select3*/ 454 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 455 /** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ 456 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; 457 /** Indicates that a pin map exists for tcpwm_line*/ 458 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 459 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 460 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98]; 461 /** Indicates that a pin map exists for tcpwm_line_compl*/ 462 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 463 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 464 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[98]; 465 /** Indicates that a pin map exists for usb_usb_dm_pad*/ 466 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DM_PAD (CY_GPIO_DM_ANALOG) 467 /** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ 468 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[2]; 469 /** Indicates that a pin map exists for usb_usb_dp_pad*/ 470 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DP_PAD (CY_GPIO_DM_ANALOG) 471 /** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ 472 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[2]; 473 474 #if defined(__cplusplus) 475 } 476 #endif /* __cplusplus */ 477 478 /** \} group_hal_impl_pin_package */ 479 480 #endif /* _CYHAL_PSOC6_02_124_BGA_H_ */ 481 482 483 /* [] END OF FILE */ 484
