1 /***************************************************************************//** 2 * \file cyhal_psoc6_01_43_smt.h 3 * 4 * \brief 5 * PSoC6_01 device GPIO HAL header for 43-SMT package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_PSOC6_01_43_SMT_H_ 28 #define _CYHAL_PSOC6_01_43_SMT_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_psoc6_01_43_smt PSoC6_01 43-SMT 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the PSoC6_01 43-SMT package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 43-SMT package for the PSoC6_01 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 58 P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 59 60 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 61 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 62 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 63 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 64 P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 65 P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 66 P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 67 68 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 69 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 70 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 71 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 72 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 73 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 74 75 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 76 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 77 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 78 79 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 80 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 81 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 82 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 83 P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 84 P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 85 P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 86 87 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 88 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 89 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 90 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 91 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 92 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 93 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 94 95 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 96 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 97 } cyhal_gpio_psoc6_01_43_smt_t; 98 99 /** Create generic name for the series/package specific type. */ 100 typedef cyhal_gpio_psoc6_01_43_smt_t cyhal_gpio_t; 101 102 /* Connection type definition */ 103 /** Represents an association between a pin and a resource */ 104 typedef struct 105 { 106 uint8_t block_num; //!< The block number of the resource with this connection 107 uint8_t channel_num; //!< The channel number of the block with this connection 108 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 109 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 110 } cyhal_resource_pin_mapping_t; 111 112 /* Pin connections */ 113 /** Indicates that a pin map exists for audioss_clk_i2s_if*/ 114 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ) 115 /** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ 116 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; 117 /** Indicates that a pin map exists for audioss_pdm_clk*/ 118 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_PDM_CLK (CY_GPIO_DM_STRONG_IN_OFF) 119 /** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ 120 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1]; 121 /** Indicates that a pin map exists for audioss_pdm_data*/ 122 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_PDM_DATA (CY_GPIO_DM_HIGHZ) 123 /** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ 124 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; 125 /** Indicates that a pin map exists for audioss_rx_sck*/ 126 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 127 /** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ 128 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; 129 /** Indicates that a pin map exists for audioss_rx_sdi*/ 130 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ) 131 /** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ 132 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; 133 /** Indicates that a pin map exists for audioss_rx_ws*/ 134 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF) 135 /** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ 136 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; 137 /** Indicates that a pin map exists for audioss_tx_sck*/ 138 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 139 /** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ 140 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; 141 /** Indicates that a pin map exists for audioss_tx_sdo*/ 142 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF) 143 /** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ 144 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; 145 /** Indicates that a pin map exists for audioss_tx_ws*/ 146 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF) 147 /** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ 148 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; 149 /** Indicates that a pin map exists for bless_ext_lna_rx_ctl_out*/ 150 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_EXT_LNA_RX_CTL_OUT (CY_GPIO_DM_STRONG_IN_OFF) 151 /** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ 152 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; 153 /** Indicates that a pin map exists for bless_ext_pa_lna_chip_en_out*/ 154 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_EXT_PA_LNA_CHIP_EN_OUT (CY_GPIO_DM_STRONG_IN_OFF) 155 /** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ 156 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; 157 /** Indicates that a pin map exists for bless_ext_pa_tx_ctl_out*/ 158 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_EXT_PA_TX_CTL_OUT (CY_GPIO_DM_STRONG_IN_OFF) 159 /** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ 160 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; 161 /** Indicates that a pin map exists for bless_mxd_act_bpktctl*/ 162 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_BPKTCTL (CY_GPIO_DM_STRONG_IN_OFF) 163 /** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ 164 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; 165 /** Indicates that a pin map exists for bless_mxd_act_dbus_rx_en*/ 166 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_DBUS_RX_EN (CY_GPIO_DM_STRONG_IN_OFF) 167 /** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ 168 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; 169 /** Indicates that a pin map exists for bless_mxd_act_dbus_tx_en*/ 170 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_DBUS_TX_EN (CY_GPIO_DM_STRONG_IN_OFF) 171 /** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ 172 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; 173 /** Indicates that a pin map exists for bless_mxd_act_txd_rxd*/ 174 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_TXD_RXD (CY_GPIO_DM_STRONG_IN_OFF) 175 /** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ 176 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; 177 /** Indicates that a pin map exists for bless_mxd_dpslp_act_ldo_en*/ 178 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_ACT_LDO_EN (CY_GPIO_DM_STRONG_IN_OFF) 179 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ 180 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; 181 /** Indicates that a pin map exists for bless_mxd_dpslp_buck_en*/ 182 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_BUCK_EN (CY_GPIO_DM_STRONG_IN_OFF) 183 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ 184 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; 185 /** Indicates that a pin map exists for bless_mxd_dpslp_clk_en*/ 186 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_CLK_EN (CY_GPIO_DM_STRONG_IN_OFF) 187 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ 188 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; 189 /** Indicates that a pin map exists for bless_mxd_dpslp_dig_ldo_en*/ 190 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_DIG_LDO_EN (CY_GPIO_DM_STRONG_IN_OFF) 191 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ 192 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; 193 /** Indicates that a pin map exists for bless_mxd_dpslp_isolate_n*/ 194 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_ISOLATE_N (CY_GPIO_DM_STRONG_IN_OFF) 195 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ 196 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; 197 /** Indicates that a pin map exists for bless_mxd_dpslp_mxd_clk_out*/ 198 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_MXD_CLK_OUT (CY_GPIO_DM_HIGHZ) 199 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ 200 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; 201 /** Indicates that a pin map exists for bless_mxd_dpslp_rcb_clk*/ 202 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RCB_CLK (CY_GPIO_DM_STRONG_IN_OFF) 203 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ 204 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; 205 /** Indicates that a pin map exists for bless_mxd_dpslp_rcb_data*/ 206 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RCB_DATA (CY_GPIO_DM_STRONG_IN_OFF) 207 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ 208 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; 209 /** Indicates that a pin map exists for bless_mxd_dpslp_rcb_le*/ 210 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RCB_LE (CY_GPIO_DM_STRONG_IN_OFF) 211 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ 212 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; 213 /** Indicates that a pin map exists for bless_mxd_dpslp_reset_n*/ 214 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RESET_N (CY_GPIO_DM_STRONG_IN_OFF) 215 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ 216 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; 217 /** Indicates that a pin map exists for bless_mxd_dpslp_ret_ldo_ol_hv*/ 218 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RET_LDO_OL_HV (CY_GPIO_DM_STRONG_IN_OFF) 219 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ 220 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; 221 /** Indicates that a pin map exists for bless_mxd_dpslp_ret_switch_hv*/ 222 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RET_SWITCH_HV (CY_GPIO_DM_STRONG_IN_OFF) 223 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ 224 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; 225 /** Indicates that a pin map exists for bless_mxd_dpslp_xtal_en*/ 226 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_XTAL_EN (CY_GPIO_DM_STRONG_IN_OFF) 227 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ 228 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; 229 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 230 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 231 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 232 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 233 /** Indicates that a pin map exists for cpuss_fault_out*/ 234 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 235 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 236 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[1]; 237 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 238 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 239 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 240 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 241 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 242 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 243 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 244 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 245 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 246 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 247 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 248 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 249 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 250 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 251 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 252 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 253 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 254 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 255 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 256 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 257 /** Indicates that a pin map exists for cpuss_trace_clock*/ 258 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 259 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 260 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 261 /** Indicates that a pin map exists for cpuss_trace_data*/ 262 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 263 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 264 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[9]; 265 /** Indicates that a pin map exists for dac_ctdac_voutsw*/ 266 #define CYHAL_PIN_MAP_DRIVE_MODE_DAC_CTDAC_VOUTSW (CY_GPIO_DM_ANALOG) 267 /** List of valid pin to peripheral connections for the dac_ctdac_voutsw signal. */ 268 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_dac_ctdac_voutsw[1]; 269 /** Indicates that a pin map exists for lpcomp_dsi_comp*/ 270 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_DSI_COMP (CY_GPIO_DM_STRONG_IN_OFF) 271 /** List of valid pin to peripheral connections for the lpcomp_dsi_comp signal. */ 272 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp[1]; 273 /** Indicates that a pin map exists for lpcomp_inn_comp*/ 274 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) 275 /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ 276 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[1]; 277 /** Indicates that a pin map exists for lpcomp_inp_comp*/ 278 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) 279 /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ 280 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; 281 /** Indicates that a pin map exists for opamp_dsi_ctb_cmp*/ 282 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_DSI_CTB_CMP (CY_GPIO_DM_STRONG_IN_OFF) 283 /** List of valid pin to peripheral connections for the opamp_dsi_ctb_cmp signal. */ 284 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_dsi_ctb_cmp[2]; 285 /** Indicates that a pin map exists for opamp_out_10x*/ 286 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_OUT_10X (CY_GPIO_DM_ANALOG) 287 /** List of valid pin to peripheral connections for the opamp_out_10x signal. */ 288 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_out_10x[2]; 289 /** Indicates that a pin map exists for opamp_vin_m*/ 290 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_M (CY_GPIO_DM_ANALOG) 291 /** List of valid pin to peripheral connections for the opamp_vin_m signal. */ 292 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_m[2]; 293 /** Indicates that a pin map exists for opamp_vin_p0*/ 294 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P0 (CY_GPIO_DM_ANALOG) 295 /** List of valid pin to peripheral connections for the opamp_vin_p0 signal. */ 296 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p0[2]; 297 /** Indicates that a pin map exists for opamp_vin_p1*/ 298 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P1 (CY_GPIO_DM_ANALOG) 299 /** List of valid pin to peripheral connections for the opamp_vin_p1 signal. */ 300 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[1]; 301 /** Indicates that a pin map exists for pass_sarmux_pads*/ 302 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 303 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 304 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7]; 305 /** Indicates that a pin map exists for peri_tr_io_input*/ 306 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 307 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 308 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[11]; 309 /** Indicates that a pin map exists for peri_tr_io_output*/ 310 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 311 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 312 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[4]; 313 /** Indicates that a pin map exists for scb_i2c_scl*/ 314 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 315 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 316 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[5]; 317 /** Indicates that a pin map exists for scb_i2c_sda*/ 318 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 319 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 320 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6]; 321 /** Indicates that a pin map exists for scb_spi_m_clk*/ 322 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 323 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 324 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9]; 325 /** Indicates that a pin map exists for scb_spi_m_miso*/ 326 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 327 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 328 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[6]; 329 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 330 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 331 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 332 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[5]; 333 /** Indicates that a pin map exists for scb_spi_m_select0*/ 334 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 335 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 336 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8]; 337 /** Indicates that a pin map exists for scb_spi_m_select1*/ 338 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 339 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 340 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; 341 /** Indicates that a pin map exists for scb_spi_m_select2*/ 342 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 343 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 344 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4]; 345 /** Indicates that a pin map exists for scb_spi_m_select3*/ 346 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 347 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 348 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; 349 /** Indicates that a pin map exists for scb_spi_s_clk*/ 350 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 351 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 352 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9]; 353 /** Indicates that a pin map exists for scb_spi_s_miso*/ 354 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 355 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 356 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[6]; 357 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 358 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 359 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 360 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[5]; 361 /** Indicates that a pin map exists for scb_spi_s_select0*/ 362 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 363 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 364 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8]; 365 /** Indicates that a pin map exists for scb_spi_s_select1*/ 366 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 367 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 368 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; 369 /** Indicates that a pin map exists for scb_spi_s_select2*/ 370 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 371 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 372 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4]; 373 /** Indicates that a pin map exists for scb_spi_s_select3*/ 374 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 375 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 376 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; 377 /** Indicates that a pin map exists for scb_uart_cts*/ 378 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 379 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 380 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; 381 /** Indicates that a pin map exists for scb_uart_rts*/ 382 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 383 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 384 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7]; 385 /** Indicates that a pin map exists for scb_uart_rx*/ 386 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 387 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 388 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[4]; 389 /** Indicates that a pin map exists for scb_uart_tx*/ 390 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 391 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 392 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5]; 393 /** Indicates that a pin map exists for smif_spi_clk*/ 394 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 395 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 396 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 397 /** Indicates that a pin map exists for smif_spi_data0*/ 398 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 399 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 400 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 401 /** Indicates that a pin map exists for smif_spi_data1*/ 402 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 403 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 404 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 405 /** Indicates that a pin map exists for smif_spi_data2*/ 406 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 407 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 408 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 409 /** Indicates that a pin map exists for smif_spi_data3*/ 410 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 411 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 412 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 413 /** Indicates that a pin map exists for smif_spi_data4*/ 414 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG) 415 /** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ 416 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; 417 /** Indicates that a pin map exists for smif_spi_data5*/ 418 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG) 419 /** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ 420 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; 421 /** Indicates that a pin map exists for smif_spi_data6*/ 422 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG) 423 /** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ 424 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; 425 /** Indicates that a pin map exists for smif_spi_data7*/ 426 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG) 427 /** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ 428 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; 429 /** Indicates that a pin map exists for smif_spi_select0*/ 430 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 431 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 432 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 433 /** Indicates that a pin map exists for smif_spi_select1*/ 434 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 435 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 436 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 437 /** Indicates that a pin map exists for smif_spi_select2*/ 438 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 439 /** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ 440 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; 441 /** Indicates that a pin map exists for smif_spi_select3*/ 442 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 443 /** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ 444 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; 445 /** Indicates that a pin map exists for tcpwm_line*/ 446 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 447 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 448 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38]; 449 /** Indicates that a pin map exists for tcpwm_line_compl*/ 450 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 451 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 452 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[34]; 453 /** Indicates that a pin map exists for usb_usb_dm_pad*/ 454 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DM_PAD (CY_GPIO_DM_ANALOG) 455 /** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ 456 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; 457 /** Indicates that a pin map exists for usb_usb_dp_pad*/ 458 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DP_PAD (CY_GPIO_DM_ANALOG) 459 /** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ 460 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; 461 462 #if defined(__cplusplus) 463 } 464 #endif /* __cplusplus */ 465 466 /** \} group_hal_impl_pin_package */ 467 468 #endif /* _CYHAL_PSOC6_01_43_SMT_H_ */ 469 470 471 /* [] END OF FILE */ 472
