1 /***************************************************************************//** 2 * \file cyhal_psoc6_01_116_bga_ble.h 3 * 4 * \brief 5 * PSoC6_01 device GPIO HAL header for 116-BGA-BLE package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_PSOC6_01_116_BGA_BLE_H_ 28 #define _CYHAL_PSOC6_01_116_BGA_BLE_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_psoc6_01_116_bga_ble PSoC6_01 116-BGA-BLE 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the PSoC6_01 116-BGA-BLE package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the 116-BGA-BLE package for the PSoC6_01 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 58 P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 59 P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 60 P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 61 62 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 63 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 64 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 65 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 66 P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 67 P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 68 69 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 70 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 71 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 72 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 73 P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 74 P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 75 P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 76 77 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 78 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 79 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 80 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 81 P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 82 P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 83 P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 84 P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 85 86 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 87 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 88 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 89 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 90 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 91 P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 92 P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 93 P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 94 95 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 96 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 97 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 98 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 99 P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 100 P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 101 P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 102 P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 103 104 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 105 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 106 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 107 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 108 P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 109 P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 110 P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 111 P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 112 113 P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 114 P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 115 P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 116 P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 117 P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 118 P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 119 P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 120 121 P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 122 P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 123 P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 124 P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 125 P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 126 P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 127 P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 128 P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 129 130 P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 131 P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 132 P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 133 P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 134 P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 135 P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 136 P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 137 P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 138 139 P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 140 P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 141 P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 142 P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 143 } cyhal_gpio_psoc6_01_116_bga_ble_t; 144 145 /** Create generic name for the series/package specific type. */ 146 typedef cyhal_gpio_psoc6_01_116_bga_ble_t cyhal_gpio_t; 147 148 /* Connection type definition */ 149 /** Represents an association between a pin and a resource */ 150 typedef struct 151 { 152 uint8_t block_num; //!< The block number of the resource with this connection 153 uint8_t channel_num; //!< The channel number of the block with this connection 154 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 155 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 156 } cyhal_resource_pin_mapping_t; 157 158 /* Pin connections */ 159 /** Indicates that a pin map exists for audioss_clk_i2s_if*/ 160 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_CLK_I2S_IF (CY_GPIO_DM_HIGHZ) 161 /** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ 162 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; 163 /** Indicates that a pin map exists for audioss_pdm_clk*/ 164 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_PDM_CLK (CY_GPIO_DM_STRONG_IN_OFF) 165 /** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ 166 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; 167 /** Indicates that a pin map exists for audioss_pdm_data*/ 168 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_PDM_DATA (CY_GPIO_DM_HIGHZ) 169 /** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ 170 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; 171 /** Indicates that a pin map exists for audioss_rx_sck*/ 172 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 173 /** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ 174 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; 175 /** Indicates that a pin map exists for audioss_rx_sdi*/ 176 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_SDI (CY_GPIO_DM_HIGHZ) 177 /** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ 178 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; 179 /** Indicates that a pin map exists for audioss_rx_ws*/ 180 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_RX_WS (CY_GPIO_DM_STRONG_IN_OFF) 181 /** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ 182 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; 183 /** Indicates that a pin map exists for audioss_tx_sck*/ 184 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SCK (CY_GPIO_DM_STRONG_IN_OFF) 185 /** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ 186 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; 187 /** Indicates that a pin map exists for audioss_tx_sdo*/ 188 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_SDO (CY_GPIO_DM_STRONG_IN_OFF) 189 /** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ 190 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; 191 /** Indicates that a pin map exists for audioss_tx_ws*/ 192 #define CYHAL_PIN_MAP_DRIVE_MODE_AUDIOSS_TX_WS (CY_GPIO_DM_STRONG_IN_OFF) 193 /** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ 194 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; 195 /** Indicates that a pin map exists for bless_ext_lna_rx_ctl_out*/ 196 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_EXT_LNA_RX_CTL_OUT (CY_GPIO_DM_STRONG_IN_OFF) 197 /** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ 198 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; 199 /** Indicates that a pin map exists for bless_ext_pa_lna_chip_en_out*/ 200 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_EXT_PA_LNA_CHIP_EN_OUT (CY_GPIO_DM_STRONG_IN_OFF) 201 /** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ 202 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; 203 /** Indicates that a pin map exists for bless_ext_pa_tx_ctl_out*/ 204 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_EXT_PA_TX_CTL_OUT (CY_GPIO_DM_STRONG_IN_OFF) 205 /** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ 206 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; 207 /** Indicates that a pin map exists for bless_mxd_act_bpktctl*/ 208 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_BPKTCTL (CY_GPIO_DM_STRONG_IN_OFF) 209 /** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ 210 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; 211 /** Indicates that a pin map exists for bless_mxd_act_dbus_rx_en*/ 212 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_DBUS_RX_EN (CY_GPIO_DM_STRONG_IN_OFF) 213 /** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ 214 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; 215 /** Indicates that a pin map exists for bless_mxd_act_dbus_tx_en*/ 216 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_DBUS_TX_EN (CY_GPIO_DM_STRONG_IN_OFF) 217 /** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ 218 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; 219 /** Indicates that a pin map exists for bless_mxd_act_txd_rxd*/ 220 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_ACT_TXD_RXD (CY_GPIO_DM_STRONG_IN_OFF) 221 /** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ 222 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; 223 /** Indicates that a pin map exists for bless_mxd_dpslp_act_ldo_en*/ 224 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_ACT_LDO_EN (CY_GPIO_DM_STRONG_IN_OFF) 225 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ 226 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; 227 /** Indicates that a pin map exists for bless_mxd_dpslp_buck_en*/ 228 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_BUCK_EN (CY_GPIO_DM_STRONG_IN_OFF) 229 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ 230 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; 231 /** Indicates that a pin map exists for bless_mxd_dpslp_clk_en*/ 232 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_CLK_EN (CY_GPIO_DM_STRONG_IN_OFF) 233 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ 234 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; 235 /** Indicates that a pin map exists for bless_mxd_dpslp_dig_ldo_en*/ 236 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_DIG_LDO_EN (CY_GPIO_DM_STRONG_IN_OFF) 237 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ 238 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; 239 /** Indicates that a pin map exists for bless_mxd_dpslp_isolate_n*/ 240 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_ISOLATE_N (CY_GPIO_DM_STRONG_IN_OFF) 241 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ 242 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; 243 /** Indicates that a pin map exists for bless_mxd_dpslp_mxd_clk_out*/ 244 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_MXD_CLK_OUT (CY_GPIO_DM_HIGHZ) 245 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ 246 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; 247 /** Indicates that a pin map exists for bless_mxd_dpslp_rcb_clk*/ 248 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RCB_CLK (CY_GPIO_DM_STRONG_IN_OFF) 249 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ 250 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; 251 /** Indicates that a pin map exists for bless_mxd_dpslp_rcb_data*/ 252 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RCB_DATA (CY_GPIO_DM_STRONG_IN_OFF) 253 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ 254 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; 255 /** Indicates that a pin map exists for bless_mxd_dpslp_rcb_le*/ 256 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RCB_LE (CY_GPIO_DM_STRONG_IN_OFF) 257 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ 258 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; 259 /** Indicates that a pin map exists for bless_mxd_dpslp_reset_n*/ 260 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RESET_N (CY_GPIO_DM_STRONG_IN_OFF) 261 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ 262 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; 263 /** Indicates that a pin map exists for bless_mxd_dpslp_ret_ldo_ol_hv*/ 264 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RET_LDO_OL_HV (CY_GPIO_DM_STRONG_IN_OFF) 265 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ 266 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; 267 /** Indicates that a pin map exists for bless_mxd_dpslp_ret_switch_hv*/ 268 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_RET_SWITCH_HV (CY_GPIO_DM_STRONG_IN_OFF) 269 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ 270 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; 271 /** Indicates that a pin map exists for bless_mxd_dpslp_xtal_en*/ 272 #define CYHAL_PIN_MAP_DRIVE_MODE_BLESS_MXD_DPSLP_XTAL_EN (CY_GPIO_DM_STRONG_IN_OFF) 273 /** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ 274 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; 275 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 276 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 277 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 278 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 279 /** Indicates that a pin map exists for cpuss_fault_out*/ 280 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT_OUT (CY_GPIO_DM_STRONG_IN_OFF) 281 /** List of valid pin to peripheral connections for the cpuss_fault_out signal. */ 282 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[2]; 283 /** Indicates that a pin map exists for cpuss_swj_swclk_tclk*/ 284 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 285 /** List of valid pin to peripheral connections for the cpuss_swj_swclk_tclk signal. */ 286 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1]; 287 /** Indicates that a pin map exists for cpuss_swj_swdio_tms*/ 288 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 289 /** List of valid pin to peripheral connections for the cpuss_swj_swdio_tms signal. */ 290 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1]; 291 /** Indicates that a pin map exists for cpuss_swj_swdoe_tdi*/ 292 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 293 /** List of valid pin to peripheral connections for the cpuss_swj_swdoe_tdi signal. */ 294 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1]; 295 /** Indicates that a pin map exists for cpuss_swj_swo_tdo*/ 296 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 297 /** List of valid pin to peripheral connections for the cpuss_swj_swo_tdo signal. */ 298 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1]; 299 /** Indicates that a pin map exists for cpuss_swj_trstn*/ 300 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_SWJ_TRSTN (CY_GPIO_DM_PULLUP) 301 /** List of valid pin to peripheral connections for the cpuss_swj_trstn signal. */ 302 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1]; 303 /** Indicates that a pin map exists for cpuss_trace_clock*/ 304 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 305 /** List of valid pin to peripheral connections for the cpuss_trace_clock signal. */ 306 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1]; 307 /** Indicates that a pin map exists for cpuss_trace_data*/ 308 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 309 /** List of valid pin to peripheral connections for the cpuss_trace_data signal. */ 310 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[12]; 311 /** Indicates that a pin map exists for dac_ctdac_voutsw*/ 312 #define CYHAL_PIN_MAP_DRIVE_MODE_DAC_CTDAC_VOUTSW (CY_GPIO_DM_ANALOG) 313 /** List of valid pin to peripheral connections for the dac_ctdac_voutsw signal. */ 314 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_dac_ctdac_voutsw[1]; 315 /** Indicates that a pin map exists for lpcomp_dsi_comp*/ 316 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_DSI_COMP (CY_GPIO_DM_STRONG_IN_OFF) 317 /** List of valid pin to peripheral connections for the lpcomp_dsi_comp signal. */ 318 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp[2]; 319 /** Indicates that a pin map exists for lpcomp_inn_comp*/ 320 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) 321 /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ 322 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[1]; 323 /** Indicates that a pin map exists for lpcomp_inp_comp*/ 324 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) 325 /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ 326 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; 327 /** Indicates that a pin map exists for opamp_dsi_ctb_cmp*/ 328 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_DSI_CTB_CMP (CY_GPIO_DM_STRONG_IN_OFF) 329 /** List of valid pin to peripheral connections for the opamp_dsi_ctb_cmp signal. */ 330 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_dsi_ctb_cmp[2]; 331 /** Indicates that a pin map exists for opamp_out_10x*/ 332 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_OUT_10X (CY_GPIO_DM_ANALOG) 333 /** List of valid pin to peripheral connections for the opamp_out_10x signal. */ 334 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_out_10x[2]; 335 /** Indicates that a pin map exists for opamp_vin_m*/ 336 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_M (CY_GPIO_DM_ANALOG) 337 /** List of valid pin to peripheral connections for the opamp_vin_m signal. */ 338 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_m[2]; 339 /** Indicates that a pin map exists for opamp_vin_p0*/ 340 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P0 (CY_GPIO_DM_ANALOG) 341 /** List of valid pin to peripheral connections for the opamp_vin_p0 signal. */ 342 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p0[2]; 343 /** Indicates that a pin map exists for opamp_vin_p1*/ 344 #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P1 (CY_GPIO_DM_ANALOG) 345 /** List of valid pin to peripheral connections for the opamp_vin_p1 signal. */ 346 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[2]; 347 /** Indicates that a pin map exists for pass_sarmux_pads*/ 348 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG) 349 /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ 350 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7]; 351 /** Indicates that a pin map exists for peri_tr_io_input*/ 352 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 353 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 354 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[22]; 355 /** Indicates that a pin map exists for peri_tr_io_output*/ 356 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 357 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 358 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6]; 359 /** Indicates that a pin map exists for scb_i2c_scl*/ 360 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 361 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 362 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; 363 /** Indicates that a pin map exists for scb_i2c_sda*/ 364 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 365 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 366 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; 367 /** Indicates that a pin map exists for scb_spi_m_clk*/ 368 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 369 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 370 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13]; 371 /** Indicates that a pin map exists for scb_spi_m_miso*/ 372 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 373 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 374 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; 375 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 376 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 377 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 378 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; 379 /** Indicates that a pin map exists for scb_spi_m_select0*/ 380 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 381 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 382 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13]; 383 /** Indicates that a pin map exists for scb_spi_m_select1*/ 384 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 385 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 386 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[10]; 387 /** Indicates that a pin map exists for scb_spi_m_select2*/ 388 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 389 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 390 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[10]; 391 /** Indicates that a pin map exists for scb_spi_m_select3*/ 392 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 393 /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ 394 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8]; 395 /** Indicates that a pin map exists for scb_spi_s_clk*/ 396 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 397 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 398 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13]; 399 /** Indicates that a pin map exists for scb_spi_s_miso*/ 400 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 401 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 402 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; 403 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 404 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 405 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 406 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; 407 /** Indicates that a pin map exists for scb_spi_s_select0*/ 408 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 409 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 410 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13]; 411 /** Indicates that a pin map exists for scb_spi_s_select1*/ 412 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 413 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 414 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[10]; 415 /** Indicates that a pin map exists for scb_spi_s_select2*/ 416 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 417 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 418 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[10]; 419 /** Indicates that a pin map exists for scb_spi_s_select3*/ 420 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ) 421 /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ 422 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8]; 423 /** Indicates that a pin map exists for scb_uart_cts*/ 424 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 425 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 426 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11]; 427 /** Indicates that a pin map exists for scb_uart_rts*/ 428 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 429 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 430 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11]; 431 /** Indicates that a pin map exists for scb_uart_rx*/ 432 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 433 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 434 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; 435 /** Indicates that a pin map exists for scb_uart_tx*/ 436 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 437 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 438 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; 439 /** Indicates that a pin map exists for smif_spi_clk*/ 440 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_CLK (CY_GPIO_DM_STRONG) 441 /** List of valid pin to peripheral connections for the smif_spi_clk signal. */ 442 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; 443 /** Indicates that a pin map exists for smif_spi_data0*/ 444 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA0 (CY_GPIO_DM_STRONG) 445 /** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ 446 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; 447 /** Indicates that a pin map exists for smif_spi_data1*/ 448 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA1 (CY_GPIO_DM_STRONG) 449 /** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ 450 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; 451 /** Indicates that a pin map exists for smif_spi_data2*/ 452 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA2 (CY_GPIO_DM_STRONG) 453 /** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ 454 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; 455 /** Indicates that a pin map exists for smif_spi_data3*/ 456 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA3 (CY_GPIO_DM_STRONG) 457 /** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ 458 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; 459 /** Indicates that a pin map exists for smif_spi_data4*/ 460 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA4 (CY_GPIO_DM_STRONG) 461 /** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ 462 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; 463 /** Indicates that a pin map exists for smif_spi_data5*/ 464 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA5 (CY_GPIO_DM_STRONG) 465 /** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ 466 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; 467 /** Indicates that a pin map exists for smif_spi_data6*/ 468 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA6 (CY_GPIO_DM_STRONG) 469 /** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ 470 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; 471 /** Indicates that a pin map exists for smif_spi_data7*/ 472 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_DATA7 (CY_GPIO_DM_STRONG) 473 /** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ 474 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; 475 /** Indicates that a pin map exists for smif_spi_select0*/ 476 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 477 /** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ 478 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; 479 /** Indicates that a pin map exists for smif_spi_select1*/ 480 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 481 /** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ 482 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; 483 /** Indicates that a pin map exists for smif_spi_select2*/ 484 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 485 /** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ 486 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; 487 /** Indicates that a pin map exists for smif_spi_select3*/ 488 #define CYHAL_PIN_MAP_DRIVE_MODE_SMIF_SPI_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF) 489 /** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ 490 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; 491 /** Indicates that a pin map exists for tcpwm_line*/ 492 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 493 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 494 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[78]; 495 /** Indicates that a pin map exists for tcpwm_line_compl*/ 496 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 497 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 498 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[74]; 499 /** Indicates that a pin map exists for usb_usb_dm_pad*/ 500 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DM_PAD (CY_GPIO_DM_ANALOG) 501 /** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ 502 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; 503 /** Indicates that a pin map exists for usb_usb_dp_pad*/ 504 #define CYHAL_PIN_MAP_DRIVE_MODE_USB_USB_DP_PAD (CY_GPIO_DM_ANALOG) 505 /** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ 506 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; 507 508 #if defined(__cplusplus) 509 } 510 #endif /* __cplusplus */ 511 512 /** \} group_hal_impl_pin_package */ 513 514 #endif /* _CYHAL_PSOC6_01_116_BGA_BLE_H_ */ 515 516 517 /* [] END OF FILE */ 518
