1 /***************************************************************************//** 2 * \file cyhal_psc3_vqfn_64.h 3 * 4 * \brief 5 * PSC3 device GPIO HAL header for VQFN-64 package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_PSC3_VQFN_64_H_ 28 #define _CYHAL_PSC3_VQFN_64_H_ 29 30 #include "cyhal_hw_resources.h" 31 32 /** 33 * \addtogroup group_hal_impl_pin_package_psc3_vqfn_64 PSC3 VQFN-64 34 * \ingroup group_hal_impl_pin_package 35 * \{ 36 * Pin definitions and connections specific to the PSC3 VQFN-64 package. 37 */ 38 39 #if defined(__cplusplus) 40 extern "C" { 41 #endif /* __cplusplus */ 42 43 /** Gets a pin definition from the provided port and pin numbers */ 44 #define CYHAL_GET_GPIO(port, pin) ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin))) 45 46 /** Macro that, given a gpio, will extract the pin number */ 47 #define CYHAL_GET_PIN(pin) ((uint8_t)(((uint8_t)pin) & 0x07U)) 48 /** Macro that, given a gpio, will extract the port number */ 49 #define CYHAL_GET_PORT(pin) ((uint8_t)(((uint8_t)pin) >> 3U)) 50 51 /** Definitions for all of the pins that are bonded out on in the VQFN-64 package for the PSC3 series. */ 52 typedef enum { 53 NC = 0xFF, //!< No Connect/Invalid Pin 54 55 P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 56 P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 57 58 P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 59 P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 60 P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 61 P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 62 63 P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 64 P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 65 P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 66 P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 67 68 P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 69 P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 70 P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2 71 P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3 72 P4_4 = CYHAL_GET_GPIO(CYHAL_PORT_4, 4), //!< Port 4 Pin 4 73 P4_5 = CYHAL_GET_GPIO(CYHAL_PORT_4, 5), //!< Port 4 Pin 5 74 P4_6 = CYHAL_GET_GPIO(CYHAL_PORT_4, 6), //!< Port 4 Pin 6 75 P4_7 = CYHAL_GET_GPIO(CYHAL_PORT_4, 7), //!< Port 4 Pin 7 76 77 P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 78 P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 79 P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 80 P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 81 82 P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 83 P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 84 P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 85 P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 86 87 P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 88 P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 89 P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 90 P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 91 P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 92 93 P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 94 P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 95 P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 96 P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 97 98 P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 99 P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 100 P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 101 P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 102 103 AN_A0 = CYHAL_GET_GPIO(NC, 0), //!< AN_A Pin 0 104 AN_A1 = CYHAL_GET_GPIO(NC, 1), //!< AN_A Pin 1 105 AN_A2 = CYHAL_GET_GPIO(NC, 2), //!< AN_A Pin 2 106 AN_A3 = CYHAL_GET_GPIO(NC, 3), //!< AN_A Pin 3 107 AN_A4 = CYHAL_GET_GPIO(NC, 4), //!< AN_A Pin 4 108 AN_A5 = CYHAL_GET_GPIO(NC, 5), //!< AN_A Pin 5 109 AN_A6 = CYHAL_GET_GPIO(NC, 6), //!< AN_A Pin 6 110 AN_A7 = CYHAL_GET_GPIO(NC, 7), //!< AN_A Pin 7 111 112 AN_B0 = CYHAL_GET_GPIO(NC, 8), //!< AN_B Pin 0 113 AN_B1 = CYHAL_GET_GPIO(NC, 9), //!< AN_B Pin 1 114 AN_B2 = CYHAL_GET_GPIO(NC, 10), //!< AN_B Pin 2 115 AN_B3 = CYHAL_GET_GPIO(NC, 11), //!< AN_B Pin 3 116 AN_B4 = CYHAL_GET_GPIO(NC, 12), //!< AN_B Pin 4 117 AN_B5 = CYHAL_GET_GPIO(NC, 13), //!< AN_B Pin 5 118 AN_B6 = CYHAL_GET_GPIO(NC, 14), //!< AN_B Pin 6 119 AN_B7 = CYHAL_GET_GPIO(NC, 15), //!< AN_B Pin 7 120 } cyhal_gpio_psc3_vqfn_64_t; 121 122 /** Create generic name for the series/package specific type. */ 123 typedef cyhal_gpio_psc3_vqfn_64_t cyhal_gpio_t; 124 125 /* Connection type definition */ 126 /** Represents an association between a pin and a resource */ 127 typedef struct 128 { 129 uint8_t block_num; //!< The block number of the resource with this connection 130 uint8_t channel_num; //!< The channel number of the block with this connection 131 cyhal_gpio_t pin; //!< The GPIO pin the connection is with 132 en_hsiom_sel_t hsiom; //!< The HSIOM configuration value 133 } cyhal_resource_pin_mapping_t; 134 135 /* Pin connections */ 136 /** Indicates that a pin map exists for canfd_ttcan_rx*/ 137 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_RX (CY_GPIO_DM_HIGHZ) 138 /** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ 139 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[4]; 140 /** Indicates that a pin map exists for canfd_ttcan_tx*/ 141 #define CYHAL_PIN_MAP_DRIVE_MODE_CANFD_TTCAN_TX (CY_GPIO_DM_STRONG_IN_OFF) 142 /** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ 143 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[4]; 144 /** Indicates that a pin map exists for cpuss_clk_fm_pump*/ 145 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_CLK_FM_PUMP (CY_GPIO_DM_STRONG_IN_OFF) 146 /** List of valid pin to peripheral connections for the cpuss_clk_fm_pump signal. */ 147 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1]; 148 /** Indicates that a pin map exists for cpuss_fault*/ 149 #define CYHAL_PIN_MAP_DRIVE_MODE_CPUSS_FAULT (CY_GPIO_DM_STRONG_IN_OFF) 150 /** List of valid pin to peripheral connections for the cpuss_fault signal. */ 151 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault[2]; 152 /** Indicates that a pin map exists for debug600_clk_swj_swclk_tclk*/ 153 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_CLK_SWJ_SWCLK_TCLK (CY_GPIO_DM_PULLDOWN) 154 /** List of valid pin to peripheral connections for the debug600_clk_swj_swclk_tclk signal. */ 155 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_clk_swj_swclk_tclk[1]; 156 /** Indicates that a pin map exists for debug600_rst_swj_trstn*/ 157 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_RST_SWJ_TRSTN (CY_GPIO_DM_PULLDOWN) 158 /** List of valid pin to peripheral connections for the debug600_rst_swj_trstn signal. */ 159 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_rst_swj_trstn[1]; 160 /** Indicates that a pin map exists for debug600_swj_swdio_tms*/ 161 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWDIO_TMS (CY_GPIO_DM_PULLUP) 162 /** List of valid pin to peripheral connections for the debug600_swj_swdio_tms signal. */ 163 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdio_tms[1]; 164 /** Indicates that a pin map exists for debug600_swj_swdoe_tdi*/ 165 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWDOE_TDI (CY_GPIO_DM_PULLUP) 166 /** List of valid pin to peripheral connections for the debug600_swj_swdoe_tdi signal. */ 167 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdoe_tdi[1]; 168 /** Indicates that a pin map exists for debug600_swj_swo_tdo*/ 169 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_SWJ_SWO_TDO (CY_GPIO_DM_STRONG_IN_OFF) 170 /** List of valid pin to peripheral connections for the debug600_swj_swo_tdo signal. */ 171 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swo_tdo[1]; 172 /** Indicates that a pin map exists for debug600_trace_clock*/ 173 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_TRACE_CLOCK (CY_GPIO_DM_STRONG_IN_OFF) 174 /** List of valid pin to peripheral connections for the debug600_trace_clock signal. */ 175 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_clock[2]; 176 /** Indicates that a pin map exists for debug600_trace_data*/ 177 #define CYHAL_PIN_MAP_DRIVE_MODE_DEBUG600_TRACE_DATA (CY_GPIO_DM_STRONG_IN_OFF) 178 /** List of valid pin to peripheral connections for the debug600_trace_data signal. */ 179 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_data[8]; 180 /** Indicates that a pin map exists for lpcomp_inn_comp*/ 181 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG) 182 /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */ 183 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2]; 184 /** Indicates that a pin map exists for lpcomp_inp_comp*/ 185 #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG) 186 /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */ 187 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2]; 188 /** Indicates that a pin map exists for pass_an_a_pad_aio*/ 189 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_AN_A_PAD_AIO (CY_GPIO_DM_HIGHZ) 190 /** List of valid pin to peripheral connections for the pass_an_a_pad_aio signal. */ 191 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_an_a_pad_aio[8]; 192 /** Indicates that a pin map exists for pass_an_b_pad_aio*/ 193 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_AN_B_PAD_AIO (CY_GPIO_DM_HIGHZ) 194 /** List of valid pin to peripheral connections for the pass_an_b_pad_aio signal. */ 195 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_an_b_pad_aio[8]; 196 /** Indicates that a pin map exists for pass_gpio_00_aio*/ 197 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_GPIO_00_AIO (CY_GPIO_DM_ANALOG) 198 /** List of valid pin to peripheral connections for the pass_gpio_00_aio signal. */ 199 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_gpio_00_aio[1]; 200 /** Indicates that a pin map exists for pass_gpio_01_aio*/ 201 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_GPIO_01_AIO (CY_GPIO_DM_ANALOG) 202 /** List of valid pin to peripheral connections for the pass_gpio_01_aio signal. */ 203 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_gpio_01_aio[1]; 204 /** Indicates that a pin map exists for pass_mcpass_dclk*/ 205 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_MCPASS_DCLK (CY_GPIO_DM_STRONG_IN_OFF) 206 /** List of valid pin to peripheral connections for the pass_mcpass_dclk signal. */ 207 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_mcpass_dclk[2]; 208 /** Indicates that a pin map exists for pass_mcpass_dout*/ 209 #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_MCPASS_DOUT (CY_GPIO_DM_STRONG_IN_OFF) 210 /** List of valid pin to peripheral connections for the pass_mcpass_dout signal. */ 211 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_mcpass_dout[8]; 212 /** Indicates that a pin map exists for peri_tr_io_input*/ 213 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_INPUT (CY_GPIO_DM_HIGHZ) 214 /** List of valid pin to peripheral connections for the peri_tr_io_input signal. */ 215 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[39]; 216 /** Indicates that a pin map exists for peri_tr_io_output*/ 217 #define CYHAL_PIN_MAP_DRIVE_MODE_PERI_TR_IO_OUTPUT (CY_GPIO_DM_HIGHZ) 218 /** List of valid pin to peripheral connections for the peri_tr_io_output signal. */ 219 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[80]; 220 /** Indicates that a pin map exists for scb_i2c_scl*/ 221 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW) 222 /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ 223 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[8]; 224 /** Indicates that a pin map exists for scb_i2c_sda*/ 225 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW) 226 /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ 227 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[8]; 228 /** Indicates that a pin map exists for scb_spi_m_clk*/ 229 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF) 230 /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ 231 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[8]; 232 /** Indicates that a pin map exists for scb_spi_m_miso*/ 233 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ) 234 /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ 235 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[8]; 236 /** Indicates that a pin map exists for scb_spi_m_mosi*/ 237 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF) 238 /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ 239 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[8]; 240 /** Indicates that a pin map exists for scb_spi_m_select0*/ 241 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF) 242 /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ 243 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8]; 244 /** Indicates that a pin map exists for scb_spi_m_select1*/ 245 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF) 246 /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ 247 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[1]; 248 /** Indicates that a pin map exists for scb_spi_m_select2*/ 249 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF) 250 /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ 251 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[1]; 252 /** Indicates that a pin map exists for scb_spi_s_clk*/ 253 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ) 254 /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ 255 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[8]; 256 /** Indicates that a pin map exists for scb_spi_s_miso*/ 257 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF) 258 /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ 259 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[8]; 260 /** Indicates that a pin map exists for scb_spi_s_mosi*/ 261 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ) 262 /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ 263 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[8]; 264 /** Indicates that a pin map exists for scb_spi_s_select0*/ 265 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ) 266 /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ 267 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8]; 268 /** Indicates that a pin map exists for scb_spi_s_select1*/ 269 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ) 270 /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ 271 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[1]; 272 /** Indicates that a pin map exists for scb_spi_s_select2*/ 273 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ) 274 /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ 275 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[1]; 276 /** Indicates that a pin map exists for scb_uart_cts*/ 277 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ) 278 /** List of valid pin to peripheral connections for the scb_uart_cts signal. */ 279 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[8]; 280 /** Indicates that a pin map exists for scb_uart_rts*/ 281 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF) 282 /** List of valid pin to peripheral connections for the scb_uart_rts signal. */ 283 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[8]; 284 /** Indicates that a pin map exists for scb_uart_rx*/ 285 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ) 286 /** List of valid pin to peripheral connections for the scb_uart_rx signal. */ 287 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8]; 288 /** Indicates that a pin map exists for scb_uart_tx*/ 289 #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF) 290 /** List of valid pin to peripheral connections for the scb_uart_tx signal. */ 291 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[8]; 292 /** Indicates that a pin map exists for tcpwm_line*/ 293 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF) 294 /** List of valid pin to peripheral connections for the tcpwm_line signal. */ 295 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[14]; 296 /** Indicates that a pin map exists for tcpwm_line_compl*/ 297 #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF) 298 /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ 299 extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[14]; 300 301 #if defined(__cplusplus) 302 } 303 #endif /* __cplusplus */ 304 305 /** \} group_hal_impl_pin_package */ 306 307 #endif /* _CYHAL_PSC3_VQFN_64_H_ */ 308 309 310 /* [] END OF FILE */ 311
