1 /**
2 ******************************************************************************
3 * @file partition_stm32wba55xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32WBA55xx Device Initial Setup for Secure / Non-Secure Zones
6 * for ARMCM33 based on CMSIS CORE V5.4.0 partition_ARMCM33.h Template.
7 *
8 * This file contains:
9 * - Initialize Security Attribution Unit (SAU) CTRL register
10 * - Setup behavior of Sleep and Exception Handling
11 * - Setup behavior of Floating Point Unit
12 * - Setup Interrupt Target
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
18 * Copyright (c) 2022 STMicroelectronics. All rights reserved.
19 *
20 * SPDX-License-Identifier: Apache-2.0
21 *
22 * Licensed under the Apache License, Version 2.0 (the License); you may
23 * not use this file except in compliance with the License.
24 * You may obtain a copy of the License at
25 *
26 * www.apache.org/licenses/LICENSE-2.0
27 *
28 * Unless required by applicable law or agreed to in writing, software
29 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
30 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
31 * See the License for the specific language governing permissions and
32 * limitations under the License.
33 ******************************************************************************
34 */
35
36 #ifndef PARTITION_STM32WBA55XX_H
37 #define PARTITION_STM32WBA55XX_H
38
39 /*
40 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
41 */
42
43 /*
44 // <e>Initialize Security Attribution Unit (SAU) CTRL register
45 */
46 #define SAU_INIT_CTRL 1
47
48 /*
49 // <q> Enable SAU
50 // <i> Value for SAU->CTRL register bit ENABLE
51 */
52 #define SAU_INIT_CTRL_ENABLE 1
53
54 /*
55 // <o> When SAU is disabled
56 // <0=> All Memory is Secure
57 // <1=> All Memory is Non-Secure
58 // <i> Value for SAU->CTRL register bit ALLNS
59 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
60 */
61 #define SAU_INIT_CTRL_ALLNS 0
62
63 /*
64 // </e>
65 */
66
67 /*
68 // <h>Initialize Security Attribution Unit (SAU) Address Regions
69 // <i>SAU configuration specifies regions to be one of:
70 // <i> - Secure and Non-Secure Callable
71 // <i> - Non-Secure
72 // <i>Note: All memory regions not configured by SAU are Secure
73 */
74 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
75
76 /*
77 // <e>Initialize SAU Region 0
78 // <i> Setup SAU Region 0 memory attributes
79 */
80 #define SAU_INIT_REGION0 1
81
82 /*
83 // <o>Start Address <0-0xFFFFFFE0>
84 */
85 #define SAU_INIT_START0 0x08080000 /* start address of SAU region 0 */
86
87 /*
88 // <o>End Address <0x1F-0xFFFFFFFF>
89 */
90 #define SAU_INIT_END0 0x080FFFFF /* end address of SAU region 0 */
91
92 /*
93 // <o>Region is
94 // <0=>Non-Secure
95 // <1=>Secure, Non-Secure Callable
96 */
97 #define SAU_INIT_NSC0 0
98 /*
99 // </e>
100 */
101
102 /*
103 // <e>Initialize SAU Region 1
104 // <i> Setup SAU Region 1 memory attributes
105 */
106 #define SAU_INIT_REGION1 1
107
108 /*
109 // <o>Start Address <0-0xFFFFFFE0>
110 */
111 #define SAU_INIT_START1 0x0BF88000 /* start address of SAU region 1 */
112
113 /*
114 // <o>End Address <0x1F-0xFFFFFFFF>
115 */
116 #define SAU_INIT_END1 0x0BF97FFF /* end address of SAU region 1 */
117
118 /*
119 // <o>Region is
120 // <0=>Non-Secure
121 // <1=>Secure, Non-Secure Callable
122 */
123 #define SAU_INIT_NSC1 0
124 /*
125 // </e>
126 */
127
128 /*
129 // <e>Initialize SAU Region 2
130 // <i> Setup SAU Region 2 memory attributes
131 */
132 #define SAU_INIT_REGION2 1
133
134 /*
135 // <o>Start Address <0-0xFFFFFFE0>
136 */
137 #define SAU_INIT_START2 0x0C07E000 /* start address of SAU region 2 */
138
139 /*
140 // <o>End Address <0x1F-0xFFFFFFFF>
141 */
142 #define SAU_INIT_END2 0x0C07FFFF /* end address of SAU region 2 */
143
144 /*
145 // <o>Region is
146 // <0=>Non-Secure
147 // <1=>Secure, Non-Secure Callable
148 */
149 #define SAU_INIT_NSC2 1
150 /*
151 // </e>
152 */
153
154 /*
155 // <e>Initialize SAU Region 3
156 // <i> Setup SAU Region 3 memory attributes
157 */
158 #define SAU_INIT_REGION3 1
159
160 /*
161 // <o>Start Address <0-0xFFFFFFE0>
162 */
163 #define SAU_INIT_START3 0x20010000 /* start address of SAU region 3 */
164
165 /*
166 // <o>End Address <0x1F-0xFFFFFFFF>
167 */
168 #define SAU_INIT_END3 0x2001FFFF /* end address of SAU region 3 */
169
170 /*
171 // <o>Region is
172 // <0=>Non-Secure
173 // <1=>Secure, Non-Secure Callable
174 */
175 #define SAU_INIT_NSC3 0
176 /*
177 // </e>
178 */
179
180 /*
181 // <e>Initialize SAU Region 4
182 // <i> Setup SAU Region 4 memory attributes
183 */
184 #define SAU_INIT_REGION4 1
185
186 /*
187 // <o>Start Address <0-0xFFFFFFE0>
188 */
189 #define SAU_INIT_START4 0x40000000 /* start address of SAU region 4 */
190
191 /*
192 // <o>End Address <0x1F-0xFFFFFFFF>
193 */
194 #define SAU_INIT_END4 0x4FFFFFFF /* end address of SAU region 4 */
195
196 /*
197 // <o>Region is
198 // <0=>Non-Secure
199 // <1=>Secure, Non-Secure Callable
200 */
201 #define SAU_INIT_NSC4 0
202 /*
203 // </e>
204 */
205
206 /*
207 // <e>Initialize SAU Region 5
208 // <i> Setup SAU Region 5 memory attributes
209 */
210 #define SAU_INIT_REGION5 0
211
212 /*
213 // <o>Start Address <0-0xFFFFFFE0>
214 */
215 #define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */
216
217 /*
218 // <o>End Address <0x1F-0xFFFFFFFF>
219 */
220 #define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */
221
222 /*
223 // <o>Region is
224 // <0=>Non-Secure
225 // <1=>Secure, Non-Secure Callable
226 */
227 #define SAU_INIT_NSC5 0
228 /*
229 // </e>
230 */
231
232 /*
233 // <e>Initialize SAU Region 6
234 // <i> Setup SAU Region 6 memory attributes
235 */
236 #define SAU_INIT_REGION6 0
237
238 /*
239 // <o>Start Address <0-0xFFFFFFE0>
240 */
241 #define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
242
243 /*
244 // <o>End Address <0x1F-0xFFFFFFFF>
245 */
246 #define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
247
248 /*
249 // <o>Region is
250 // <0=>Non-Secure
251 // <1=>Secure, Non-Secure Callable
252 */
253 #define SAU_INIT_NSC6 0
254 /*
255 // </e>
256 */
257
258 /*
259 // <e>Initialize SAU Region 7
260 // <i> Setup SAU Region 7 memory attributes
261 */
262 #define SAU_INIT_REGION7 0
263
264 /*
265 // <o>Start Address <0-0xFFFFFFE0>
266 */
267 #define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
268
269 /*
270 // <o>End Address <0x1F-0xFFFFFFFF>
271 */
272 #define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
273
274 /*
275 // <o>Region is
276 // <0=>Non-Secure
277 // <1=>Secure, Non-Secure Callable
278 */
279 #define SAU_INIT_NSC7 0
280 /*
281 // </e>
282 */
283
284 /*
285 // </h>
286 */
287
288 /*
289 // <e>Setup behaviour of Sleep and Exception Handling
290 */
291 #define SCB_CSR_AIRCR_INIT 0
292
293 /*
294 // <o> Deep Sleep can be enabled by
295 // <0=>Secure and Non-Secure state
296 // <1=>Secure state only
297 // <i> Value for SCB->CSR register bit DEEPSLEEPS
298 */
299 #define SCB_CSR_DEEPSLEEPS_VAL 0
300
301 /*
302 // <o>System reset request accessible from
303 // <0=> Secure and Non-Secure state
304 // <1=> Secure state only
305 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
306 */
307 #define SCB_AIRCR_SYSRESETREQS_VAL 0
308
309 /*
310 // <o>Priority of Non-Secure exceptions is
311 // <0=> Not altered
312 // <1=> Lowered to 0x04-0x07
313 // <i> Value for SCB->AIRCR register bit PRIS
314 */
315 #define SCB_AIRCR_PRIS_VAL 0
316
317 /*
318 // <o>BusFault, HardFault, and NMI target
319 // <0=> Secure state
320 // <1=> Non-Secure state
321 // <i> Value for SCB->AIRCR register bit BFHFNMINS
322 */
323 #define SCB_AIRCR_BFHFNMINS_VAL 0
324
325 /*
326 // </e>
327 */
328
329 /*
330 // <e>Setup behaviour of Floating Point Unit
331 */
332 #define TZ_FPU_NS_USAGE 1
333
334 /*
335 // <o>Floating Point Unit usage
336 // <0=> Secure state only
337 // <3=> Secure and Non-Secure state
338 // <i> Value for SCB->NSACR register bits CP10, CP11
339 */
340 #define SCB_NSACR_CP10_11_VAL 3
341
342 /*
343 // <o>Treat floating-point registers as Secure
344 // <0=> Disabled
345 // <1=> Enabled
346 // <i> Value for FPU->FPCCR register bit TS
347 */
348 #define FPU_FPCCR_TS_VAL 0
349
350 /*
351 // <o>Clear on return (CLRONRET) accessibility
352 // <0=> Secure and Non-Secure state
353 // <1=> Secure state only
354 // <i> Value for FPU->FPCCR register bit CLRONRETS
355 */
356 #define FPU_FPCCR_CLRONRETS_VAL 0
357
358 /*
359 // <o>Clear floating-point caller saved registers on exception return
360 // <0=> Disabled
361 // <1=> Enabled
362 // <i> Value for FPU->FPCCR register bit CLRONRET
363 */
364 #define FPU_FPCCR_CLRONRET_VAL 1
365
366 /*
367 // </e>
368 */
369
370 /*
371 // <h>Setup Interrupt Target
372 */
373
374 /*
375 // <e>Initialize ITNS 0 (Interrupts 0..31)
376 */
377 #define NVIC_INIT_ITNS0 1
378
379 /*
380 // Interrupts 0..31
381 // <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
382 // <o.1> PVD_IRQn <0=> Secure state <1=> Non-Secure state
383 // <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
384 // <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
385 // <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
386 // <o.5> RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state
387 // <o.6> FLASH_IRQn <0=> Secure state <1=> Non-Secure state
388 // <o.7> FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
389 // <o.8> GTZC_IRQn <0=> Secure state <1=> Non-Secure state
390 // <o.9> RCC_IRQn <0=> Secure state <1=> Non-Secure state
391 // <o.10> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
392 // <o.11> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
393 // <o.12> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
394 // <o.13> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
395 // <o.14> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
396 // <o.15> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
397 // <o.16> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
398 // <o.17> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
399 // <o.18> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
400 // <o.19> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
401 // <o.20> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
402 // <o.21> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
403 // <o.22> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
404 // <o.23> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
405 // <o.24> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
406 // <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
407 // <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
408 // <o.27> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
409 // <o.28> SAES_IRQn <0=> Secure state <1=> Non-Secure state
410 // <o.29> GPDMA_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
411 // <o.30> GPDMA_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
412 // <o.31> GPDMA_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
413 */
414 #define NVIC_INIT_ITNS0_VAL 0x00000000
415
416 /*
417 // </e>
418 */
419
420 /*
421 // <e>Initialize ITNS 1 (Interrupts 32..63)
422 */
423 #define NVIC_INIT_ITNS1 1
424
425 /*
426 // Interrupts 32..63
427 // <o.0> GPDMA_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
428 // <o.1> GPDMA_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
429 // <o.2> GPDMA_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
430 // <o.3> GPDMA_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
431 // <o.4> GPDMA_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
432 // <o.5> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
433 // <o.6> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
434 // <o.7> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
435 // <o.8> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
436 // <o.9> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
437 // <o.10> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
438 // <o.11> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
439 // <o.12> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
440 // <o.13> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
441 // <o.14> USART1_IRQn <0=> Secure state <1=> Non-Secure state
442 // <o.15> USART2_IRQn <0=> Secure state <1=> Non-Secure state
443 // <o.16> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
444 // <o.17> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
445 // <o.18> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
446 // <o.19> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
447 // <o.20> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
448 // <o.21> COMP_IRQn <0=> Secure state <1=> Non-Secure state
449 // <o.22> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
450 // <o.23> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
451 // <o.24> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
452 // <o.25> TSC_IRQn <0=> Secure state <1=> Non-Secure state
453 // <o.26> AES_IRQn <0=> Secure state <1=> Non-Secure state
454 // <o.27> RNG_IRQn <0=> Secure state <1=> Non-Secure state
455 // <o.28> FPU_IRQn <0=> Secure state <1=> Non-Secure state
456 // <o.29> HASH_IRQn <0=> Secure state <1=> Non-Secure state
457 // <o.30> PKA_IRQn <0=> Secure state <1=> Non-Secure state
458 // <o.31> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
459 */
460 #define NVIC_INIT_ITNS1_VAL 0x00000000
461
462 /*
463 // </e>
464 */
465
466 /*
467 // <e>Initialize ITNS 2 (Interrupts 64..95)
468 */
469 #define NVIC_INIT_ITNS2 1
470
471 /*
472 // Interrupts 64..95
473 // <o.0> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
474 // <o.1> ADC4_IRQn <0=> Secure state <1=> Non-Secure state
475 // <o.2> RADIO_IRQn <0=> Secure state <1=> Non-Secure state
476 // <o.3> WKUP_IRQn <0=> Secure state <1=> Non-Secure state
477 // <o.4> HSEM_IRQn <0=> Secure state <1=> Non-Secure state
478 // <o.5> HSEM_S_IRQn <0=> Secure state <1=> Non-Secure state
479 // <o.6> WKUP_S_IRQn <0=> Secure state <1=> Non-Secure state
480 // <o.7> RCC_AUDIOSYNC_IRQn <0=> Secure state <1=> Non-Secure state
481 */
482 #define NVIC_INIT_ITNS2_VAL 0x00000000
483
484 /*
485 // </e>
486 */
487
488 /*
489 // </h>
490 */
491
492 /*
493 max 8 SAU regions.
494 SAU regions are defined in partition.h
495 */
496
497 #define SAU_INIT_REGION(n) \
498 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
499 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
500 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
501 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
502
503 /**
504 \brief Setup a SAU Region
505 \details Writes the region information contained in SAU_Region to the
506 registers SAU_RNR, SAU_RBAR, and SAU_RLAR
507 */
TZ_SAU_Setup(void)508 __STATIC_INLINE void TZ_SAU_Setup (void)
509 {
510
511 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
512
513 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
514 SAU_INIT_REGION(0);
515 #endif
516
517 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
518 SAU_INIT_REGION(1);
519 #endif
520
521 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
522 SAU_INIT_REGION(2);
523 #endif
524
525 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
526 SAU_INIT_REGION(3);
527 #endif
528
529 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
530 SAU_INIT_REGION(4);
531 #endif
532
533 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
534 SAU_INIT_REGION(5);
535 #endif
536
537 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
538 SAU_INIT_REGION(6);
539 #endif
540
541 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
542 SAU_INIT_REGION(7);
543 #endif
544
545 /* repeat this for all possible SAU regions */
546
547 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
548
549
550 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
551 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
552 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
553 #endif
554
555 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
556 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
557 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
558
559 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
560 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
561 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
562 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
563 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
564 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
565 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
566
567 #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
568 defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
569
570 SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
571 ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
572
573 FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
574 ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
575 ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
576 ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
577 #endif
578
579 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
580 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
581 #endif
582
583 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
584 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
585 #endif
586
587 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
588 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
589 #endif
590
591 }
592
593 #endif /* PARTITION_STM32WBA55XX_H */
594
