1 /**
2 ******************************************************************************
3 * @file partition_stm32l552xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32L552xx Device Initial Setup for Secure / Non-Secure Zones
6 * for ARMCM33 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
7 *
8 * This file contains:
9 * - Initialize Security Attribution Unit (SAU) CTRL register
10 * - Setup behavior of Sleep and Exception Handling
11 * - Setup behavior of Floating Point Unit
12 * - Setup Interrupt Target
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2019 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 */
26
27
28 #ifndef PARTITION_STM32L552XX_H
29 #define PARTITION_STM32L552XX_H
30
31 /*
32 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
33 */
34
35 /*
36 // <e>Initialize Security Attribution Unit (SAU) CTRL register
37 */
38 #define SAU_INIT_CTRL 1
39
40 /*
41 // <q> Enable SAU
42 // <i> Value for SAU->CTRL register bit ENABLE
43 */
44 #define SAU_INIT_CTRL_ENABLE 1
45
46 /*
47 // <o> When SAU is disabled
48 // <0=> All Memory is Secure
49 // <1=> All Memory is Non-Secure
50 // <i> Value for SAU->CTRL register bit ALLNS
51 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
52 */
53 #define SAU_INIT_CTRL_ALLNS 0
54
55 /*
56 // </e>
57 */
58
59 /*
60 // <h>Initialize Security Attribution Unit (SAU) Address Regions
61 // <i>SAU configuration specifies regions to be one of:
62 // <i> - Secure and Non-Secure Callable
63 // <i> - Non-Secure
64 // <i>Note: All memory regions not configured by SAU are Secure
65 */
66 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
67
68 /*
69 // <e>Initialize SAU Region 0
70 // <i> Setup SAU Region 0 memory attributes
71 */
72 #define SAU_INIT_REGION0 1
73
74 /*
75 // <o>Start Address <0-0xFFFFFFE0>
76 */
77 #define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */
78
79 /*
80 // <o>End Address <0x1F-0xFFFFFFFF>
81 */
82 #define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */
83
84 /*
85 // <o>Region is
86 // <0=>Non-Secure
87 // <1=>Secure, Non-Secure Callable
88 */
89 #define SAU_INIT_NSC0 1
90 /*
91 // </e>
92 */
93
94 /*
95 // <e>Initialize SAU Region 1
96 // <i> Setup SAU Region 1 memory attributes
97 */
98 #define SAU_INIT_REGION1 1
99
100 /*
101 // <o>Start Address <0-0xFFFFFFE0>
102 */
103 #define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */
104
105 /*
106 // <o>End Address <0x1F-0xFFFFFFFF>
107 */
108 #define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */
109
110 /*
111 // <o>Region is
112 // <0=>Non-Secure
113 // <1=>Secure, Non-Secure Callable
114 */
115 #define SAU_INIT_NSC1 0
116 /*
117 // </e>
118 */
119
120 /*
121 // <e>Initialize SAU Region 2
122 // <i> Setup SAU Region 2 memory attributes
123 */
124 #define SAU_INIT_REGION2 1
125
126 /*
127 // <o>Start Address <0-0xFFFFFFE0>
128 */
129 #define SAU_INIT_START2 0x20018000 /* start address of SAU region 2 */
130
131 /*
132 // <o>End Address <0x1F-0xFFFFFFFF>
133 */
134 #define SAU_INIT_END2 0x2003FFFF /* end address of SAU region 2 */
135
136 /*
137 // <o>Region is
138 // <0=>Non-Secure
139 // <1=>Secure, Non-Secure Callable
140 */
141 #define SAU_INIT_NSC2 0
142 /*
143 // </e>
144 */
145
146 /*
147 // <e>Initialize SAU Region 3
148 // <i> Setup SAU Region 3 memory attributes
149 */
150 #define SAU_INIT_REGION3 1
151
152 /*
153 // <o>Start Address <0-0xFFFFFFE0>
154 */
155 #define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
156
157 /*
158 // <o>End Address <0x1F-0xFFFFFFFF>
159 */
160 #define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
161
162 /*
163 // <o>Region is
164 // <0=>Non-Secure
165 // <1=>Secure, Non-Secure Callable
166 */
167 #define SAU_INIT_NSC3 0
168 /*
169 // </e>
170 */
171
172 /*
173 // <e>Initialize SAU Region 4
174 // <i> Setup SAU Region 4 memory attributes
175 */
176 #define SAU_INIT_REGION4 1
177
178 /*
179 // <o>Start Address <0-0xFFFFFFE0>
180 */
181 #define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
182
183 /*
184 // <o>End Address <0x1F-0xFFFFFFFF>
185 */
186 #define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
187
188 /*
189 // <o>Region is
190 // <0=>Non-Secure
191 // <1=>Secure, Non-Secure Callable
192 */
193 #define SAU_INIT_NSC4 0
194 /*
195 // </e>
196 */
197
198 /*
199 // <e>Initialize SAU Region 5
200 // <i> Setup SAU Region 5 memory attributes
201 */
202 #define SAU_INIT_REGION5 1
203
204 /*
205 // <o>Start Address <0-0xFFFFFFE0>
206 */
207 #define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
208
209 /*
210 // <o>End Address <0x1F-0xFFFFFFFF>
211 */
212 #define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
213
214 /*
215 // <o>Region is
216 // <0=>Non-Secure
217 // <1=>Secure, Non-Secure Callable
218 */
219 #define SAU_INIT_NSC5 0
220 /*
221 // </e>
222 */
223
224 /*
225 // <e>Initialize SAU Region 6
226 // <i> Setup SAU Region 6 memory attributes
227 */
228 #define SAU_INIT_REGION6 0
229
230 /*
231 // <o>Start Address <0-0xFFFFFFE0>
232 */
233 #define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
234
235 /*
236 // <o>End Address <0x1F-0xFFFFFFFF>
237 */
238 #define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
239
240 /*
241 // <o>Region is
242 // <0=>Non-Secure
243 // <1=>Secure, Non-Secure Callable
244 */
245 #define SAU_INIT_NSC6 0
246 /*
247 // </e>
248 */
249
250 /*
251 // <e>Initialize SAU Region 7
252 // <i> Setup SAU Region 7 memory attributes
253 */
254 #define SAU_INIT_REGION7 0
255
256 /*
257 // <o>Start Address <0-0xFFFFFFE0>
258 */
259 #define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
260
261 /*
262 // <o>End Address <0x1F-0xFFFFFFFF>
263 */
264 #define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
265
266 /*
267 // <o>Region is
268 // <0=>Non-Secure
269 // <1=>Secure, Non-Secure Callable
270 */
271 #define SAU_INIT_NSC7 0
272 /*
273 // </e>
274 */
275
276 /*
277 // </h>
278 */
279
280 /*
281 // <e>Setup behaviour of Sleep and Exception Handling
282 */
283 #define SCB_CSR_AIRCR_INIT 0
284
285 /*
286 // <o> Deep Sleep can be enabled by
287 // <0=>Secure and Non-Secure state
288 // <1=>Secure state only
289 // <i> Value for SCB->CSR register bit DEEPSLEEPS
290 */
291 #define SCB_CSR_DEEPSLEEPS_VAL 0
292
293 /*
294 // <o>System reset request accessible from
295 // <0=> Secure and Non-Secure state
296 // <1=> Secure state only
297 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
298 */
299 #define SCB_AIRCR_SYSRESETREQS_VAL 0
300
301 /*
302 // <o>Priority of Non-Secure exceptions is
303 // <0=> Not altered
304 // <1=> Lowered to 0x04-0x07
305 // <i> Value for SCB->AIRCR register bit PRIS
306 */
307 #define SCB_AIRCR_PRIS_VAL 0
308
309 /*
310 // <o>BusFault, HardFault, and NMI target
311 // <0=> Secure state
312 // <1=> Non-Secure state
313 // <i> Value for SCB->AIRCR register bit BFHFNMINS
314 */
315 #define SCB_AIRCR_BFHFNMINS_VAL 0
316
317 /*
318 // </e>
319 */
320
321 /*
322 // <e>Setup behaviour of Floating Point Unit
323 */
324 #define TZ_FPU_NS_USAGE 1
325
326 /*
327 // <o>Floating Point Unit usage
328 // <0=> Secure state only
329 // <3=> Secure and Non-Secure state
330 // <i> Value for SCB->NSACR register bits CP10, CP11
331 */
332 #define SCB_NSACR_CP10_11_VAL 3
333
334 /*
335 // <o>Treat floating-point registers as Secure
336 // <0=> Disabled
337 // <1=> Enabled
338 // <i> Value for FPU->FPCCR register bit TS
339 */
340 #define FPU_FPCCR_TS_VAL 0
341
342 /*
343 // <o>Clear on return (CLRONRET) accessibility
344 // <0=> Secure and Non-Secure state
345 // <1=> Secure state only
346 // <i> Value for FPU->FPCCR register bit CLRONRETS
347 */
348 #define FPU_FPCCR_CLRONRETS_VAL 0
349
350 /*
351 // <o>Clear floating-point caller saved registers on exception return
352 // <0=> Disabled
353 // <1=> Enabled
354 // <i> Value for FPU->FPCCR register bit CLRONRET
355 */
356 #define FPU_FPCCR_CLRONRET_VAL 1
357
358 /*
359 // </e>
360 */
361
362 /*
363 // <h>Setup Interrupt Target
364 */
365
366 /*
367 // <e>Initialize ITNS 0 (Interrupts 0..31)
368 */
369 #define NVIC_INIT_ITNS0 1
370
371 /*
372 // Interrupts 0..31
373 // <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
374 // <o.1> PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state
375 // <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
376 // <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
377 // <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
378 // <o.5> TAMP_S_IRQn <0=> Secure state <1=> Non-Secure state
379 // <o.6> FLASH_IRQn <0=> Secure state <1=> Non-Secure state
380 // <o.7> FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
381 // <o.8> GTZC_IRQn <0=> Secure state <1=> Non-Secure state
382 // <o.9> RCC_IRQn <0=> Secure state <1=> Non-Secure state
383 // <o.10> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
384 // <o.11> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
385 // <o.12> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
386 // <o.13> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
387 // <o.14> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
388 // <o.15> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
389 // <o.16> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
390 // <o.17> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
391 // <o.18> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
392 // <o.19> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
393 // <o.20> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
394 // <o.21> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
395 // <o.22> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
396 // <o.23> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
397 // <o.24> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
398 // <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
399 // <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
400 // <o.27> DMAMUX1_IRQn <0=> Secure state <1=> Non-Secure state
401 // <o.28> DMAMUX1_S_IRQn <0=> Secure state <1=> Non-Secure state
402 // <o.29> DMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
403 // <o.30> DMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
404 // <o.31> DMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
405 */
406 #define NVIC_INIT_ITNS0_VAL 0x00000000
407
408 /*
409 // </e>
410 */
411
412 /*
413 // <e>Initialize ITNS 1 (Interrupts 32..63)
414 */
415 #define NVIC_INIT_ITNS1 1
416
417 /*
418 // Interrupts 32..63
419 // <o.0> DMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
420 // <o.1> DMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
421 // <o.2> DMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
422 // <o.3> DMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
423 // <o.4> DMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
424 // <o.5> ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state
425 // <o.6> DAC_IRQn <0=> Secure state <1=> Non-Secure state
426 // <o.7> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
427 // <o.8> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
428 // <o.9> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
429 // <o.10> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
430 // <o.11> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
431 // <o.12> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
432 // <o.13> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
433 // <o.14> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
434 // <o.15> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
435 // <o.16> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
436 // <o.17> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
437 // <o.18> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
438 // <o.19> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
439 // <o.20> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
440 // <o.21> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
441 // <o.22> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
442 // <o.23> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
443 // <o.24> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
444 // <o.25> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
445 // <o.26> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
446 // <o.27> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
447 // <o.28> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
448 // <o.29> USART1_IRQn <0=> Secure state <1=> Non-Secure state
449 // <o.30> USART2_IRQn <0=> Secure state <1=> Non-Secure state
450 // <o.31> USART3_IRQn <0=> Secure state <1=> Non-Secure state
451 */
452 #define NVIC_INIT_ITNS1_VAL 0x00000000
453
454 /*
455 // </e>
456 */
457
458 /*
459 // <e>Initialize ITNS 2 (Interrupts 64..95)
460 */
461 #define NVIC_INIT_ITNS2 1
462
463 /*
464 // Interrupts 64..95
465 // <o.0> UART4_IRQn <0=> Secure state <1=> Non-Secure state
466 // <o.1> UART5_IRQn <0=> Secure state <1=> Non-Secure state
467 // <o.2> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
468 // <o.3> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
469 // <o.4> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
470 // <o.5> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
471 // <o.6> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
472 // <o.7> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
473 // <o.8> COMP_IRQn <0=> Secure state <1=> Non-Secure state
474 // <o.9> USB_FS_IRQn <0=> Secure state <1=> Non-Secure state
475 // <o.10> CRS_IRQn <0=> Secure state <1=> Non-Secure state
476 // <o.11> FMC_IRQn <0=> Secure state <1=> Non-Secure state
477 // <o.12> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
478 // <o.13> Reserved <0=> Secure state <1=> Non-Secure state
479 // <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
480 // <o.15> Reserved <0=> Secure state <1=> Non-Secure state
481 // <o.16> DMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
482 // <o.17> DMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
483 // <o.18> DMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
484 // <o.19> DMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
485 // <o.20> DMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
486 // <o.21> DMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
487 // <o.22> DMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
488 // <o.23> DMA2_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
489 // <o.24> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
490 // <o.25> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
491 // <o.26> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
492 // <o.27> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
493 // <o.28> TSC_IRQn <0=> Secure state <1=> Non-Secure state
494 // <o.30> RNG_IRQn <0=> Secure state <1=> Non-Secure state
495 // <o.31> FPU_IRQn <0=> Secure state <1=> Non-Secure state
496 */
497 #define NVIC_INIT_ITNS2_VAL 0x00000000
498
499 /*
500 // </e>
501 */
502
503 /*
504 // <e>Initialize ITNS 3 (Interrupts 96..108)
505 */
506 #define NVIC_INIT_ITNS3 1
507
508 /*
509 // Interrupts 96..108
510 // <o.0> HASH_IRQn <0=> Secure state <1=> Non-Secure state
511 // <o.2> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
512 // <o.3> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
513 // <o.4> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
514 // <o.5> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
515 // <o.6> DFSDM1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
516 // <o.7> DFSDM1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state
517 // <o.8> DFSDM1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state
518 // <o.9> DFSDM1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state
519 // <o.10> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
520 // <o.11> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
521 */
522 #define NVIC_INIT_ITNS3_VAL 0x00000000
523
524 /*
525 // </e>
526 */
527
528 /*
529 // </h>
530 */
531
532
533
534 /*
535 max 8 SAU regions.
536 SAU regions are defined in partition.h
537 */
538
539 #define SAU_INIT_REGION(n) \
540 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
541 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
542 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
543 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
544
545 /**
546 \brief Setup a SAU Region
547 \details Writes the region information contained in SAU_Region to the
548 registers SAU_RNR, SAU_RBAR, and SAU_RLAR
549 */
TZ_SAU_Setup(void)550 __STATIC_INLINE void TZ_SAU_Setup (void)
551 {
552
553 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
554
555 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
556 SAU_INIT_REGION(0);
557 #endif
558
559 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
560 SAU_INIT_REGION(1);
561 #endif
562
563 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
564 SAU_INIT_REGION(2);
565 #endif
566
567 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
568 SAU_INIT_REGION(3);
569 #endif
570
571 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
572 SAU_INIT_REGION(4);
573 #endif
574
575 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
576 SAU_INIT_REGION(5);
577 #endif
578
579 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
580 SAU_INIT_REGION(6);
581 #endif
582
583 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
584 SAU_INIT_REGION(7);
585 #endif
586
587 /* repeat this for all possible SAU regions */
588
589 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
590
591
592 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
593 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
594 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
595 #endif
596
597 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
598 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
599 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
600
601 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
602 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
603 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
604 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
605 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
606 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
607 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
608
609 #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
610 defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
611
612 SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
613 ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
614
615 FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
616 ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
617 ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
618 ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
619 #endif
620
621 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
622 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
623 #endif
624
625 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
626 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
627 #endif
628
629 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
630 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
631 #endif
632
633 #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
634 NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
635 #endif
636
637 }
638
639 #endif /* PARTITION_STM32L552XX_H */
640
