1 /**
2 ******************************************************************************
3 * @file partition_stm32h562xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H562xx Device Header File for Initial Setup for Secure /
6 * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
7 * Template.
8 *
9 * This file contains:
10 * - Initialize Security Attribution Unit (SAU) CTRL register
11 * - Setup behavior of Sleep and Exception Handling
12 * - Setup behavior of Floating Point Unit
13 * - Setup Interrupt Target
14 *
15 ******************************************************************************
16 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
17 * Copyright (c) 2023 STMicroelectronics. All rights reserved.
18 *
19 * SPDX-License-Identifier: Apache-2.0
20 *
21 * Licensed under the Apache License, Version 2.0 (the License); you may
22 * not use this file except in compliance with the License.
23 * You may obtain a copy of the License at
24 *
25 * www.apache.org/licenses/LICENSE-2.0
26 *
27 * Unless required by applicable law or agreed to in writing, software
28 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
29 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
30 * See the License for the specific language governing permissions and
31 * limitations under the License.
32 ******************************************************************************
33 */
34
35 #ifndef PARTITION_STM32H562XX_H
36 #define PARTITION_STM32H562XX_H
37
38 /*
39 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
40 */
41
42 /*
43 // <e>Initialize Security Attribution Unit (SAU) CTRL register
44 */
45 #define SAU_INIT_CTRL 1
46
47 /*
48 // <q> Enable SAU
49 // <i> Value for SAU->CTRL register bit ENABLE
50 */
51 #define SAU_INIT_CTRL_ENABLE 0
52
53 /*
54 // <o> When SAU is disabled
55 // <0=> All Memory is Secure
56 // <1=> All Memory is Non-Secure
57 // <i> Value for SAU->CTRL register bit ALLNS
58 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
59 */
60 #define SAU_INIT_CTRL_ALLNS 1
61
62 /*
63 // </e>
64 */
65
66 /*
67 // <h>Initialize Security Attribution Unit (SAU) Address Regions
68 // <i>SAU configuration specifies regions to be one of:
69 // <i> - Secure and Non-Secure Callable
70 // <i> - Non-Secure
71 // <i>Note: All memory regions not configured by SAU are Secure
72 */
73 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
74
75 /*
76 // <e>Initialize SAU Region 0
77 // <i> Setup SAU Region 0 memory attributes
78 */
79 #define SAU_INIT_REGION0 0
80
81 /*
82 // <o>Start Address <0-0xFFFFFFE0>
83 */
84 #define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */
85
86 /*
87 // <o>End Address <0x1F-0xFFFFFFFF>
88 */
89 #define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */
90
91 /*
92 // <o>Region is
93 // <0=>Non-Secure
94 // <1=>Secure, Non-Secure Callable
95 */
96 #define SAU_INIT_NSC0 1
97 /*
98 // </e>
99 */
100
101 /*
102 // <e>Initialize SAU Region 1
103 // <i> Setup SAU Region 1 memory attributes
104 */
105 #define SAU_INIT_REGION1 0
106
107 /*
108 // <o>Start Address <0-0xFFFFFFE0>
109 */
110 #define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */
111
112 /*
113 // <o>End Address <0x1F-0xFFFFFFFF>
114 */
115 #define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */
116
117 /*
118 // <o>Region is
119 // <0=>Non-Secure
120 // <1=>Secure, Non-Secure Callable
121 */
122 #define SAU_INIT_NSC1 0
123 /*
124 // </e>
125 */
126
127 /*
128 // <e>Initialize SAU Region 2
129 // <i> Setup SAU Region 2 memory attributes
130 */
131 #define SAU_INIT_REGION2 0
132
133 /*
134 // <o>Start Address <0-0xFFFFFFE0>
135 */
136 #define SAU_INIT_START2 0x20050000 /* start address of SAU region 2 */
137
138 /*
139 // <o>End Address <0x1F-0xFFFFFFFF>
140 */
141 #define SAU_INIT_END2 0x2009FFFF /* end address of SAU region 2 */
142
143 /*
144 // <o>Region is
145 // <0=>Non-Secure
146 // <1=>Secure, Non-Secure Callable
147 */
148 #define SAU_INIT_NSC2 0
149 /*
150 // </e>
151 */
152
153 /*
154 // <e>Initialize SAU Region 3
155 // <i> Setup SAU Region 3 memory attributes
156 */
157 #define SAU_INIT_REGION3 0
158
159 /*
160 // <o>Start Address <0-0xFFFFFFE0>
161 */
162 #define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
163
164 /*
165 // <o>End Address <0x1F-0xFFFFFFFF>
166 */
167 #define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
168
169 /*
170 // <o>Region is
171 // <0=>Non-Secure
172 // <1=>Secure, Non-Secure Callable
173 */
174 #define SAU_INIT_NSC3 0
175 /*
176 // </e>
177 */
178
179 /*
180 // <e>Initialize SAU Region 4
181 // <i> Setup SAU Region 4 memory attributes
182 */
183 #define SAU_INIT_REGION4 0
184
185 /*
186 // <o>Start Address <0-0xFFFFFFE0>
187 */
188 #define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
189
190 /*
191 // <o>End Address <0x1F-0xFFFFFFFF>
192 */
193 #define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
194
195 /*
196 // <o>Region is
197 // <0=>Non-Secure
198 // <1=>Secure, Non-Secure Callable
199 */
200 #define SAU_INIT_NSC4 0
201 /*
202 // </e>
203 */
204
205 /*
206 // <e>Initialize SAU Region 5
207 // <i> Setup SAU Region 5 memory attributes
208 */
209 #define SAU_INIT_REGION5 0
210
211 /*
212 // <o>Start Address <0-0xFFFFFFE0>
213 */
214 #define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
215
216 /*
217 // <o>End Address <0x1F-0xFFFFFFFF>
218 */
219 #define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
220
221 /*
222 // <o>Region is
223 // <0=>Non-Secure
224 // <1=>Secure, Non-Secure Callable
225 */
226 #define SAU_INIT_NSC5 0
227 /*
228 // </e>
229 */
230
231 /*
232 // <e>Initialize SAU Region 6
233 // <i> Setup SAU Region 6 memory attributes
234 */
235 #define SAU_INIT_REGION6 0
236
237 /*
238 // <o>Start Address <0-0xFFFFFFE0>
239 */
240 #define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
241
242 /*
243 // <o>End Address <0x1F-0xFFFFFFFF>
244 */
245 #define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
246
247 /*
248 // <o>Region is
249 // <0=>Non-Secure
250 // <1=>Secure, Non-Secure Callable
251 */
252 #define SAU_INIT_NSC6 0
253 /*
254 // </e>
255 */
256
257 /*
258 // <e>Initialize SAU Region 7
259 // <i> Setup SAU Region 7 memory attributes
260 */
261 #define SAU_INIT_REGION7 0
262
263 /*
264 // <o>Start Address <0-0xFFFFFFE0>
265 */
266 #define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
267
268 /*
269 // <o>End Address <0x1F-0xFFFFFFFF>
270 */
271 #define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
272
273 /*
274 // <o>Region is
275 // <0=>Non-Secure
276 // <1=>Secure, Non-Secure Callable
277 */
278 #define SAU_INIT_NSC7 0
279 /*
280 // </e>
281 */
282
283 /*
284 // </h>
285 */
286
287 /*
288 // <e>Setup behaviour of Sleep and Exception Handling
289 */
290 #define SCB_CSR_AIRCR_INIT 0
291
292 /*
293 // <o> Deep Sleep can be enabled by
294 // <0=>Secure and Non-Secure state
295 // <1=>Secure state only
296 // <i> Value for SCB->CSR register bit DEEPSLEEPS
297 */
298 #define SCB_CSR_DEEPSLEEPS_VAL 0
299
300 /*
301 // <o>System reset request accessible from
302 // <0=> Secure and Non-Secure state
303 // <1=> Secure state only
304 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
305 */
306 #define SCB_AIRCR_SYSRESETREQS_VAL 0
307
308 /*
309 // <o>Priority of Non-Secure exceptions is
310 // <0=> Not altered
311 // <1=> Lowered to 0x04-0x07
312 // <i> Value for SCB->AIRCR register bit PRIS
313 */
314 #define SCB_AIRCR_PRIS_VAL 0
315
316 /*
317 // <o>BusFault, HardFault, and NMI target
318 // <0=> Secure state
319 // <1=> Non-Secure state
320 // <i> Value for SCB->AIRCR register bit BFHFNMINS
321 */
322 #define SCB_AIRCR_BFHFNMINS_VAL 0
323
324 /*
325 // </e>
326 */
327
328 /*
329 // <e>Setup behaviour of Floating Point Unit
330 */
331 #define TZ_FPU_NS_USAGE 1
332
333 /*
334 // <o>Floating Point Unit usage
335 // <0=> Secure state only
336 // <3=> Secure and Non-Secure state
337 // <i> Value for SCB->NSACR register bits CP10, CP11
338 */
339 #define SCB_NSACR_CP10_11_VAL 3
340
341 /*
342 // <o>Treat floating-point registers as Secure
343 // <0=> Disabled
344 // <1=> Enabled
345 // <i> Value for FPU->FPCCR register bit TS
346 */
347 #define FPU_FPCCR_TS_VAL 0
348
349 /*
350 // <o>Clear on return (CLRONRET) accessibility
351 // <0=> Secure and Non-Secure state
352 // <1=> Secure state only
353 // <i> Value for FPU->FPCCR register bit CLRONRETS
354 */
355 #define FPU_FPCCR_CLRONRETS_VAL 0
356
357 /*
358 // <o>Clear floating-point caller saved registers on exception return
359 // <0=> Disabled
360 // <1=> Enabled
361 // <i> Value for FPU->FPCCR register bit CLRONRET
362 */
363 #define FPU_FPCCR_CLRONRET_VAL 1
364
365 /*
366 // </e>
367 */
368
369 /*
370 // <h>Setup Interrupt Target
371 */
372
373 /*
374 // <e>Initialize ITNS 0 (Interrupts 0..31)
375 */
376 #define NVIC_INIT_ITNS0 1
377
378 /*
379 // Interrupts 0..31
380 // <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
381 // <o.1> PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state
382 // <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
383 // <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
384 // <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
385 // <o.5> RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state
386 // <o.6> FLASH_IRQn <0=> Secure state <1=> Non-Secure state
387 // <o.7> FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
388 // <o.8> GTZC_IRQn <0=> Secure state <1=> Non-Secure state
389 // <o.9> RCC_IRQn <0=> Secure state <1=> Non-Secure state
390 // <o.10> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
391 // <o.11> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
392 // <o.12> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
393 // <o.13> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
394 // <o.14> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
395 // <o.15> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
396 // <o.16> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
397 // <o.17> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
398 // <o.18> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
399 // <o.19> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
400 // <o.20> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
401 // <o.21> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
402 // <o.22> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
403 // <o.23> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
404 // <o.24> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
405 // <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
406 // <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
407 // <o.27> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
408 // <o.28> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
409 // <o.29> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
410 // <o.30> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
411 // <o.31> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
412 */
413 #define NVIC_INIT_ITNS0_VAL 0x00000000
414
415 /*
416 // </e>
417 */
418
419 /*
420 // <e>Initialize ITNS 1 (Interrupts 32..63)
421 */
422 #define NVIC_INIT_ITNS1 1
423
424 /*
425 // Interrupts 32..63
426 // <o.0> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
427 // <o.1> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
428 // <o.2> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
429 // <o.3> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
430 // <o.5> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
431 // <o.6> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
432 // <o.7> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
433 // <o.8> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
434 // <o.9> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
435 // <o.10> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
436 // <o.11> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
437 // <o.12> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
438 // <o.13> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
439 // <o.14> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
440 // <o.15> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
441 // <o.16> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
442 // <o.17> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
443 // <o.18> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
444 // <o.19> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
445 // <o.20> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
446 // <o.21> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
447 // <o.22> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
448 // <o.23> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
449 // <o.24> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
450 // <o.25> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
451 // <o.26> USART1_IRQn <0=> Secure state <1=> Non-Secure state
452 // <o.27> USART2_IRQn <0=> Secure state <1=> Non-Secure state
453 // <o.28> USART3_IRQn <0=> Secure state <1=> Non-Secure state
454 // <o.29> UART4_IRQn <0=> Secure state <1=> Non-Secure state
455 // <o.30> UART5_IRQn <0=> Secure state <1=> Non-Secure state
456 // <o.31> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
457 */
458 #define NVIC_INIT_ITNS1_VAL 0x00000000
459
460 /*
461 // </e>
462 */
463
464 /*
465 // <e>Initialize ITNS 2 (Interrupts 64..95)
466 */
467 #define NVIC_INIT_ITNS2 1
468
469 /*
470 // Interrupts 64..95
471 // <o.0> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
472 // <o.1> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
473 // <o.2> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
474 // <o.3> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
475 // <o.4> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
476 // <o.5> ADC2_IRQn <0=> Secure state <1=> Non-Secure state
477 // <o.6> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
478 // <o.7> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
479 // <o.8> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
480 // <o.9> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
481 // <o.10> USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state
482 // <o.11> CRS_IRQn <0=> Secure state <1=> Non-Secure state
483 // <o.12> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
484 // <o.13> FMC_IRQn <0=> Secure state <1=> Non-Secure state
485 // <o.14> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
486 // <o.15> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
487 // <o.16> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
488 // <o.17> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
489 // <o.18> SPI4_IRQn <0=> Secure state <1=> Non-Secure state
490 // <o.19> SPI5_IRQn <0=> Secure state <1=> Non-Secure state
491 // <o.20> SPI6_IRQn <0=> Secure state <1=> Non-Secure state
492 // <o.21> USART6_IRQn <0=> Secure state <1=> Non-Secure state
493 // <o.22> USART10_IRQn <0=> Secure state <1=> Non-Secure state
494 // <o.23> USART11_IRQn <0=> Secure state <1=> Non-Secure state
495 // <o.24> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
496 // <o.25> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
497 // <o.26> GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
498 // <o.27> GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
499 // <o.28> GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
500 // <o.29> GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
501 // <o.30> GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
502 // <o.31> GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
503 */
504 #define NVIC_INIT_ITNS2_VAL 0x00000000
505
506 /*
507 // </e>
508 */
509
510 /*
511 // <e>Initialize ITNS 3 (Interrupts 96..127)
512 */
513 #define NVIC_INIT_ITNS3 1
514
515 /*
516 // Interrupts 96..127
517 // <o.0> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
518 // <o.1> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
519 // <o.2> UART7_IRQn <0=> Secure state <1=> Non-Secure state
520 // <o.3> UART8_IRQn <0=> Secure state <1=> Non-Secure state
521 // <o.4> UART9_IRQn <0=> Secure state <1=> Non-Secure state
522 // <o.5> UART12_IRQn <0=> Secure state <1=> Non-Secure state
523 // <o.7> FPU_IRQn <0=> Secure state <1=> Non-Secure state
524 // <o.8> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
525 // <o.9> DCACHE_IRQn <0=> Secure state <1=> Non-Secure state
526 // <o.12> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
527 // <o.15> CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
528 // <o.16> FMAC_IRQn <0=> Secure state <1=> Non-Secure state
529 // <o.17> DTS_IRQn <0=> Secure state <1=> Non-Secure state
530 // <o.18> RNG_IRQn <0=> Secure state <1=> Non-Secure state
531 // <o.21> HASH_IRQn <0=> Secure state <1=> Non-Secure state
532 // <o.23> CEC_IRQn <0=> Secure state <1=> Non-Secure state
533 // <o.24> TIM12_IRQn <0=> Secure state <1=> Non-Secure state
534 // <o.25> TIM13_IRQn <0=> Secure state <1=> Non-Secure state
535 // <o.26> TIM14_IRQn <0=> Secure state <1=> Non-Secure state
536 // <o.27> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
537 // <o.28> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
538 // <o.29> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
539 // <o.30> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
540 // <o.31> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
541 */
542 #define NVIC_INIT_ITNS3_VAL 0x00000000
543
544 /*
545 // </e>
546 */
547
548 /*
549 // <e>Initialize ITNS 4 (Interrupts 128..130)
550 */
551 #define NVIC_INIT_ITNS4 1
552
553 /*
554 // Interrupts 128..130
555 // <o.0> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
556 // <o.1> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state
557 // <o.2> LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state
558 */
559 #define NVIC_INIT_ITNS4_VAL 0x00000000
560
561 /*
562 // </e>
563 */
564
565 /*
566 // </h>
567 */
568
569 /*
570 max 8 SAU regions.
571 SAU regions are defined in partition.h
572 */
573
574 #define SAU_INIT_REGION(n) \
575 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
576 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
577 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
578 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
579
580 /**
581 \brief Setup a SAU Region
582 \details Writes the region information contained in SAU_Region to the
583 registers SAU_RNR, SAU_RBAR, and SAU_RLAR
584 */
TZ_SAU_Setup(void)585 __STATIC_INLINE void TZ_SAU_Setup (void)
586 {
587
588 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
589
590 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
591 SAU_INIT_REGION(0);
592 #endif
593
594 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
595 SAU_INIT_REGION(1);
596 #endif
597
598 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
599 SAU_INIT_REGION(2);
600 #endif
601
602 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
603 SAU_INIT_REGION(3);
604 #endif
605
606 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
607 SAU_INIT_REGION(4);
608 #endif
609
610 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
611 SAU_INIT_REGION(5);
612 #endif
613
614 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
615 SAU_INIT_REGION(6);
616 #endif
617
618 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
619 SAU_INIT_REGION(7);
620 #endif
621
622 /* repeat this for all possible SAU regions */
623
624 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
625
626
627 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
628 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
629 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
630 #endif
631
632 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
633 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
634 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
635
636 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
637 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
638 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
639 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
640 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
641 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
642 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
643
644 #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
645 defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
646
647 SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
648 ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
649
650 FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
651 ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
652 ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
653 ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
654 #endif
655
656 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
657 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
658 #endif
659
660 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
661 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
662 #endif
663
664 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
665 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
666 #endif
667
668 #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
669 NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
670 #endif
671
672 #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
673 NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
674 #endif
675
676 }
677
678 #endif /* PARTITION_STM32H562XX_H */
679
