1 /*************************************************************************//**
2 * @file partition_<Device>.h
3 * @brief CMSIS-Core(M) Device Initial Setup for Secure/Non-Secure Zones for
4 * Device <Device>
5 * @version V1.0.0
6 * @date 20. January 2021
7 *****************************************************************************/
8 /*
9 * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
10 *
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26 /* ToDo: rename this file from 'partition_Device.h' to 'partition_<Device>.c according to your device naming */
27
28 #ifndef PARTITION_<Device>_H /* ToDo: Replace '<Device>' with your device name */
29 #define PARTITION_<Device>_H
30
31 /*
32 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
33 */
34
35 /*
36 // <e>Initialize Security Attribution Unit (SAU) CTRL register
37 */
38 #define SAU_INIT_CTRL 1
39
40 /*
41 // <q> Enable SAU
42 // <i> Value for SAU->CTRL register bit ENABLE
43 */
44 #define SAU_INIT_CTRL_ENABLE 1
45
46 /*
47 // <o> When SAU is disabled
48 // <0=> All Memory is Secure
49 // <1=> All Memory is Non-Secure
50 // <i> Value for SAU->CTRL register bit ALLNS
51 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
52 */
53 #define SAU_INIT_CTRL_ALLNS 0
54
55 /*
56 // </e>
57 */
58
59 /*
60 // <h>Initialize Security Attribution Unit (SAU) Address Regions
61 // <i>SAU configuration specifies regions to be one of:
62 // <i> - Secure and Non-Secure Callable
63 // <i> - Non-Secure
64 // <i>Note: All memory regions not configured by SAU are Secure
65 */
66 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
67
68 /*
69 // <e>Initialize SAU Region 0
70 // <i> Setup SAU Region 0 memory attributes
71 */
72 #define SAU_INIT_REGION0 1
73
74 /*
75 // <o>Start Address <0-0xFFFFFFE0>
76 */
77 #define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
78
79 /*
80 // <o>End Address <0x1F-0xFFFFFFFF>
81 */
82 #define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
83
84 /*
85 // <o>Region is
86 // <0=>Non-Secure
87 // <1=>Secure, Non-Secure Callable
88 */
89 #define SAU_INIT_NSC0 1
90 /*
91 // </e>
92 */
93
94 /*
95 // <e>Initialize SAU Region 1
96 // <i> Setup SAU Region 1 memory attributes
97 */
98 #define SAU_INIT_REGION1 1
99
100 /*
101 // <o>Start Address <0-0xFFFFFFE0>
102 */
103 #define SAU_INIT_START1 0x00200000
104
105 /*
106 // <o>End Address <0x1F-0xFFFFFFFF>
107 */
108 #define SAU_INIT_END1 0x003FFFFF
109
110 /*
111 // <o>Region is
112 // <0=>Non-Secure
113 // <1=>Secure, Non-Secure Callable
114 */
115 #define SAU_INIT_NSC1 0
116 /*
117 // </e>
118 */
119
120 /*
121 // <e>Initialize SAU Region 2
122 // <i> Setup SAU Region 2 memory attributes
123 */
124 #define SAU_INIT_REGION2 1
125
126 /*
127 // <o>Start Address <0-0xFFFFFFE0>
128 */
129 #define SAU_INIT_START2 0x20200000
130
131 /*
132 // <o>End Address <0x1F-0xFFFFFFFF>
133 */
134 #define SAU_INIT_END2 0x203FFFFF
135
136 /*
137 // <o>Region is
138 // <0=>Non-Secure
139 // <1=>Secure, Non-Secure Callable
140 */
141 #define SAU_INIT_NSC2 0
142 /*
143 // </e>
144 */
145
146 /*
147 // <e>Initialize SAU Region 3
148 // <i> Setup SAU Region 3 memory attributes
149 */
150 #define SAU_INIT_REGION3 1
151
152 /*
153 // <o>Start Address <0-0xFFFFFFE0>
154 */
155 #define SAU_INIT_START3 0x40000000
156
157 /*
158 // <o>End Address <0x1F-0xFFFFFFFF>
159 */
160 #define SAU_INIT_END3 0x40040000
161
162 /*
163 // <o>Region is
164 // <0=>Non-Secure
165 // <1=>Secure, Non-Secure Callable
166 */
167 #define SAU_INIT_NSC3 0
168 /*
169 // </e>
170 */
171
172 /*
173 // <e>Initialize SAU Region 4
174 // <i> Setup SAU Region 4 memory attributes
175 */
176 #define SAU_INIT_REGION4 0
177
178 /*
179 // <o>Start Address <0-0xFFFFFFE0>
180 */
181 #define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
182
183 /*
184 // <o>End Address <0x1F-0xFFFFFFFF>
185 */
186 #define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
187
188 /*
189 // <o>Region is
190 // <0=>Non-Secure
191 // <1=>Secure, Non-Secure Callable
192 */
193 #define SAU_INIT_NSC4 0
194 /*
195 // </e>
196 */
197
198 /*
199 // <e>Initialize SAU Region 5
200 // <i> Setup SAU Region 5 memory attributes
201 */
202 #define SAU_INIT_REGION5 0
203
204 /*
205 // <o>Start Address <0-0xFFFFFFE0>
206 */
207 #define SAU_INIT_START5 0x00000000
208
209 /*
210 // <o>End Address <0x1F-0xFFFFFFFF>
211 */
212 #define SAU_INIT_END5 0x00000000
213
214 /*
215 // <o>Region is
216 // <0=>Non-Secure
217 // <1=>Secure, Non-Secure Callable
218 */
219 #define SAU_INIT_NSC5 0
220 /*
221 // </e>
222 */
223
224 /*
225 // <e>Initialize SAU Region 6
226 // <i> Setup SAU Region 6 memory attributes
227 */
228 #define SAU_INIT_REGION6 0
229
230 /*
231 // <o>Start Address <0-0xFFFFFFE0>
232 */
233 #define SAU_INIT_START6 0x00000000
234
235 /*
236 // <o>End Address <0x1F-0xFFFFFFFF>
237 */
238 #define SAU_INIT_END6 0x00000000
239
240 /*
241 // <o>Region is
242 // <0=>Non-Secure
243 // <1=>Secure, Non-Secure Callable
244 */
245 #define SAU_INIT_NSC6 0
246 /*
247 // </e>
248 */
249
250 /*
251 // <e>Initialize SAU Region 7
252 // <i> Setup SAU Region 7 memory attributes
253 */
254 #define SAU_INIT_REGION7 0
255
256 /*
257 // <o>Start Address <0-0xFFFFFFE0>
258 */
259 #define SAU_INIT_START7 0x00000000
260
261 /*
262 // <o>End Address <0x1F-0xFFFFFFFF>
263 */
264 #define SAU_INIT_END7 0x00000000
265
266 /*
267 // <o>Region is
268 // <0=>Non-Secure
269 // <1=>Secure, Non-Secure Callable
270 */
271 #define SAU_INIT_NSC7 0
272 /*
273 // </e>
274 */
275
276 /*
277 // </h>
278 */
279
280 /*
281 // <e>Setup behaviour of Sleep and Exception Handling
282 */
283 #define SCB_CSR_AIRCR_INIT 1
284
285 /*
286 // <o> Deep Sleep can be enabled by
287 // <0=>Secure and Non-Secure state
288 // <1=>Secure state only
289 // <i> Value for SCB->CSR register bit DEEPSLEEPS
290 */
291 #define SCB_CSR_DEEPSLEEPS_VAL 1
292
293 /*
294 // <o>System reset request accessible from
295 // <0=> Secure and Non-Secure state
296 // <1=> Secure state only
297 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
298 */
299 #define SCB_AIRCR_SYSRESETREQS_VAL 1
300
301 /*
302 // <o>Priority of Non-Secure exceptions is
303 // <0=> Not altered
304 // <1=> Lowered to 0x80-0xFF
305 // <i> Value for SCB->AIRCR register bit PRIS
306 */
307 #define SCB_AIRCR_PRIS_VAL 1
308
309 /*
310 // <o>BusFault, HardFault, and NMI target
311 // <0=> Secure state
312 // <1=> Non-Secure state
313 // <i> Value for SCB->AIRCR register bit BFHFNMINS
314 */
315 #define SCB_AIRCR_BFHFNMINS_VAL 0
316
317 /*
318 // </e>
319 */
320
321 /*
322 // <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)
323 */
324 #define TZ_FPU_NS_USAGE 1
325
326 /*
327 // <o>Floating Point and Vector Unit usage
328 // <0=> Secure state only
329 // <3=> Secure and Non-Secure state
330 // <i> Value for SCB->NSACR register bits CP10, CP11
331 */
332 #define SCB_NSACR_CP10_11_VAL 3
333
334 /*
335 // <o>Treat floating-point registers as Secure
336 // <0=> Disabled
337 // <1=> Enabled
338 // <i> Value for FPU->FPCCR register bit TS
339 */
340 #define FPU_FPCCR_TS_VAL 0
341
342 /*
343 // <o>Clear on return (CLRONRET) accessibility
344 // <0=> Secure and Non-Secure state
345 // <1=> Secure state only
346 // <i> Value for FPU->FPCCR register bit CLRONRETS
347 */
348 #define FPU_FPCCR_CLRONRETS_VAL 0
349
350 /*
351 // <o>Clear floating-point caller saved registers on exception return
352 // <0=> Disabled
353 // <1=> Enabled
354 // <i> Value for FPU->FPCCR register bit CLRONRET
355 */
356 #define FPU_FPCCR_CLRONRET_VAL 1
357
358 /*
359 // </e>
360 */
361
362 /*
363 // <h>Setup Interrupt Target
364 */
365
366 /*
367 // <e>Initialize ITNS 0 (Interrupts 0..31)
368 */
369 #define NVIC_INIT_ITNS0 1
370
371 /*
372 // Interrupts 0..31
373 // <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
374 // <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
375 // <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
376 // <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
377 // <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
378 // <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
379 // <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
380 // <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
381 // <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
382 // <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
383 // <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
384 // <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
385 // <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
386 // <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
387 // <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
388 // <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
389 // <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
390 // <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
391 // <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
392 // <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
393 // <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
394 // <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
395 // <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
396 // <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
397 // <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
398 // <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
399 // <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
400 // <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
401 // <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
402 // <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
403 // <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
404 // <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
405 */
406 #define NVIC_INIT_ITNS0_VAL 0x00000000
407
408 /*
409 // </e>
410 */
411
412 /*
413 // <e>Initialize ITNS 1 (Interrupts 32..63)
414 */
415 #define NVIC_INIT_ITNS1 1
416
417 /*
418 // Interrupts 32..63
419 // <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
420 // <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
421 // <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
422 // <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
423 // <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
424 // <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
425 // <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
426 // <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
427 // <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
428 // <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
429 // <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
430 // <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
431 // <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
432 // <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
433 // <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
434 // <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
435 // <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
436 // <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
437 // <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
438 // <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
439 // <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
440 // <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
441 // <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
442 // <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
443 // <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
444 // <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
445 // <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
446 // <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
447 // <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
448 // <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
449 // <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
450 // <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
451 */
452 #define NVIC_INIT_ITNS1_VAL 0x00000000
453
454 /*
455 // </e>
456 */
457
458 /*
459 // <e>Initialize ITNS 2 (Interrupts 64..95)
460 */
461 #define NVIC_INIT_ITNS2 0
462
463 /*
464 // Interrupts 64..95
465 // <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
466 // <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
467 // <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
468 // <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
469 // <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
470 // <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
471 // <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
472 // <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
473 // <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
474 // <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
475 // <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
476 // <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
477 // <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
478 // <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
479 // <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
480 // <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
481 // <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
482 // <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
483 // <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
484 // <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
485 // <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
486 // <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
487 // <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
488 // <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
489 // <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
490 // <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
491 // <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
492 // <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
493 // <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
494 // <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
495 // <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
496 // <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
497 */
498 #define NVIC_INIT_ITNS2_VAL 0x00000000
499
500 /*
501 // </e>
502 */
503
504 /*
505 // <e>Initialize ITNS 3 (Interrupts 96..127)
506 */
507 #define NVIC_INIT_ITNS3 0
508
509 /*
510 // Interrupts 96..127
511 // <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
512 // <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
513 // <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
514 // <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
515 // <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
516 // <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
517 // <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
518 // <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
519 // <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
520 // <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
521 // <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
522 // <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
523 // <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
524 // <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
525 // <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
526 // <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
527 // <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
528 // <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
529 // <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
530 // <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
531 // <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
532 // <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
533 // <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
534 // <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
535 // <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
536 // <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
537 // <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
538 // <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
539 // <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
540 // <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
541 // <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
542 // <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
543 */
544 #define NVIC_INIT_ITNS3_VAL 0x00000000
545
546 /*
547 // </e>
548 */
549
550 /*
551 // <e>Initialize ITNS 4 (Interrupts 128..159)
552 */
553 #define NVIC_INIT_ITNS4 0
554
555 /*
556 // Interrupts 128..159
557 // <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
558 // <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
559 // <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
560 // <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
561 // <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
562 // <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
563 // <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
564 // <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
565 // <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
566 // <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
567 // <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
568 // <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
569 // <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
570 // <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
571 // <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
572 // <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
573 // <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
574 // <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
575 // <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
576 // <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
577 // <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
578 // <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
579 // <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
580 // <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
581 // <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
582 // <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
583 // <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
584 // <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
585 // <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
586 // <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
587 // <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
588 // <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
589 */
590 #define NVIC_INIT_ITNS4_VAL 0x00000000
591
592 /*
593 // </e>
594 */
595
596 /*
597 // <e>Initialize ITNS 5 (Interrupts 160..191)
598 */
599 #define NVIC_INIT_ITNS5 0
600
601 /*
602 // Interrupts 160..191
603 // <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
604 // <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
605 // <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
606 // <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
607 // <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
608 // <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
609 // <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
610 // <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
611 // <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
612 // <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
613 // <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
614 // <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
615 // <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
616 // <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
617 // <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
618 // <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
619 // <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
620 // <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
621 // <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
622 // <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
623 // <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
624 // <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
625 // <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
626 // <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
627 // <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
628 // <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
629 // <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
630 // <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
631 // <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
632 // <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
633 // <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
634 // <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
635 */
636 #define NVIC_INIT_ITNS5_VAL 0x00000000
637
638 /*
639 // </e>
640 */
641
642 /*
643 // <e>Initialize ITNS 6 (Interrupts 192..223)
644 */
645 #define NVIC_INIT_ITNS6 0
646
647 /*
648 // Interrupts 192..223
649 // <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
650 // <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
651 // <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
652 // <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
653 // <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
654 // <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
655 // <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
656 // <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
657 // <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
658 // <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
659 // <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
660 // <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
661 // <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
662 // <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
663 // <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
664 // <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
665 // <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
666 // <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
667 // <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
668 // <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
669 // <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
670 // <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
671 // <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
672 // <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
673 // <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
674 // <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
675 // <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
676 // <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
677 // <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
678 // <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
679 // <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
680 // <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
681 */
682 #define NVIC_INIT_ITNS6_VAL 0x00000000
683
684 /*
685 // </e>
686 */
687
688 /*
689 // <e>Initialize ITNS 7 (Interrupts 224..255)
690 */
691 #define NVIC_INIT_ITNS7 0
692
693 /*
694 // Interrupts 224..255
695 // <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
696 // <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
697 // <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
698 // <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
699 // <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
700 // <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
701 // <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
702 // <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
703 // <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
704 // <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
705 // <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
706 // <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
707 // <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
708 // <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
709 // <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
710 // <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
711 // <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
712 // <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
713 // <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
714 // <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
715 // <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
716 // <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
717 // <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
718 // <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
719 // <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
720 // <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
721 // <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
722 // <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
723 // <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
724 // <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
725 // <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
726 // <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
727 */
728 #define NVIC_INIT_ITNS7_VAL 0x00000000
729
730 /*
731 // </e>
732 */
733
734 /*
735 // <e>Initialize ITNS 8 (Interrupts 256..287)
736 */
737 #define NVIC_INIT_ITNS8 0
738
739 /*
740 // Interrupts 256..287
741 // <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
742 // <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
743 // <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
744 // <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
745 // <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
746 // <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
747 // <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
748 // <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
749 // <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
750 // <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
751 // <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
752 // <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
753 // <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
754 // <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
755 // <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
756 // <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
757 // <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
758 // <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
759 // <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
760 // <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
761 // <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
762 // <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
763 // <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
764 // <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
765 // <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
766 // <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
767 // <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
768 // <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
769 // <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
770 // <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
771 // <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
772 // <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
773 */
774 #define NVIC_INIT_ITNS8_VAL 0x00000000
775
776 /*
777 // </e>
778 */
779
780 /*
781 // <e>Initialize ITNS 9 (Interrupts 288..319)
782 */
783 #define NVIC_INIT_ITNS9 0
784
785 /*
786 // Interrupts 288..319
787 // <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
788 // <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
789 // <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
790 // <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
791 // <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
792 // <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
793 // <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
794 // <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
795 // <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
796 // <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
797 // <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
798 // <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
799 // <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
800 // <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
801 // <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
802 // <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
803 // <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
804 // <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
805 // <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
806 // <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
807 // <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
808 // <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
809 // <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
810 // <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
811 // <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
812 // <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
813 // <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
814 // <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
815 // <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
816 // <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
817 // <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
818 // <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
819 */
820 #define NVIC_INIT_ITNS9_VAL 0x00000000
821
822 /*
823 // </e>
824 */
825
826 /*
827 // <e>Initialize ITNS 10 (Interrupts 320..351)
828 */
829 #define NVIC_INIT_ITNS10 0
830
831 /*
832 // Interrupts 320..351
833 // <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
834 // <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
835 // <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
836 // <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
837 // <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
838 // <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
839 // <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
840 // <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
841 // <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
842 // <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
843 // <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
844 // <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
845 // <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
846 // <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
847 // <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
848 // <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
849 // <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
850 // <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
851 // <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
852 // <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
853 // <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
854 // <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
855 // <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
856 // <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
857 // <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
858 // <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
859 // <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
860 // <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
861 // <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
862 // <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
863 // <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
864 // <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
865 */
866 #define NVIC_INIT_ITNS10_VAL 0x00000000
867
868 /*
869 // </e>
870 */
871
872 /*
873 // <e>Initialize ITNS 11 (Interrupts 352..383)
874 */
875 #define NVIC_INIT_ITNS11 0
876
877 /*
878 // Interrupts 352..383
879 // <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
880 // <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
881 // <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
882 // <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
883 // <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
884 // <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
885 // <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
886 // <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
887 // <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
888 // <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
889 // <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
890 // <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
891 // <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
892 // <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
893 // <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
894 // <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
895 // <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
896 // <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
897 // <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
898 // <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
899 // <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
900 // <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
901 // <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
902 // <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
903 // <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
904 // <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
905 // <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
906 // <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
907 // <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
908 // <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
909 // <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
910 // <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
911 */
912 #define NVIC_INIT_ITNS11_VAL 0x00000000
913
914 /*
915 // </e>
916 */
917
918 /*
919 // <e>Initialize ITNS 12 (Interrupts 384..415)
920 */
921 #define NVIC_INIT_ITNS12 0
922
923 /*
924 // Interrupts 384..415
925 // <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
926 // <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
927 // <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
928 // <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
929 // <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
930 // <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
931 // <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
932 // <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
933 // <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
934 // <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
935 // <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
936 // <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
937 // <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
938 // <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
939 // <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
940 // <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
941 // <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
942 // <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
943 // <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
944 // <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
945 // <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
946 // <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
947 // <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
948 // <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
949 // <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
950 // <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
951 // <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
952 // <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
953 // <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
954 // <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
955 // <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
956 // <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
957 */
958 #define NVIC_INIT_ITNS12_VAL 0x00000000
959
960 /*
961 // </e>
962 */
963
964 /*
965 // <e>Initialize ITNS 13 (Interrupts 416..447)
966 */
967 #define NVIC_INIT_ITNS13 0
968
969 /*
970 // Interrupts 416..447
971 // <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
972 // <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
973 // <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
974 // <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
975 // <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
976 // <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
977 // <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
978 // <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
979 // <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
980 // <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
981 // <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
982 // <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
983 // <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
984 // <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
985 // <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
986 // <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
987 // <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
988 // <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
989 // <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
990 // <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
991 // <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
992 // <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
993 // <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
994 // <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
995 // <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
996 // <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
997 // <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
998 // <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
999 // <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
1000 // <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
1001 // <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
1002 // <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
1003 */
1004 #define NVIC_INIT_ITNS13_VAL 0x00000000
1005
1006 /*
1007 // </e>
1008 */
1009
1010 /*
1011 // <e>Initialize ITNS 14 (Interrupts 448..479)
1012 */
1013 #define NVIC_INIT_ITNS14 0
1014
1015 /*
1016 // Interrupts 448..479
1017 // <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
1018 // <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
1019 // <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
1020 // <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
1021 // <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
1022 // <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
1023 // <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
1024 // <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
1025 // <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
1026 // <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
1027 // <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
1028 // <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
1029 // <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
1030 // <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
1031 // <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
1032 // <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
1033 // <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
1034 // <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
1035 // <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
1036 // <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
1037 // <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
1038 // <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
1039 // <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
1040 // <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
1041 // <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
1042 // <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
1043 // <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
1044 // <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
1045 // <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
1046 // <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
1047 // <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
1048 // <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
1049 */
1050 #define NVIC_INIT_ITNS14_VAL 0x00000000
1051
1052 /*
1053 // </e>
1054 */
1055
1056 /*
1057 // <e>Initialize ITNS 15 (Interrupts 480..511)
1058 */
1059 #define NVIC_INIT_ITNS15 0
1060
1061 /*
1062 // Interrupts 480..511
1063 // <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
1064 // <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
1065 // <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
1066 // <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
1067 // <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
1068 // <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
1069 // <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
1070 // <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
1071 // <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
1072 // <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
1073 // <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
1074 // <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
1075 // <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
1076 // <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
1077 // <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
1078 // <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
1079 // <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
1080 // <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
1081 // <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
1082 // <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
1083 // <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
1084 // <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
1085 // <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
1086 // <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
1087 // <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
1088 // <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
1089 // <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
1090 // <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
1091 // <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
1092 // <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
1093 // <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
1094 // <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
1095 */
1096 #define NVIC_INIT_ITNS15_VAL 0x00000000
1097
1098 /*
1099 // </e>
1100 */
1101
1102 /*
1103 // </h>
1104 */
1105
1106
1107
1108 /*
1109 max 128 SAU regions.
1110 SAU regions are defined in partition.h
1111 */
1112
1113 #define SAU_INIT_REGION(n) \
1114 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
1115 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
1116 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
1117 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
1118
1119 /**
1120 \brief Setup a SAU Region
1121 \details Writes the region information contained in SAU_Region to the
1122 registers SAU_RNR, SAU_RBAR, and SAU_RLAR
1123 */
TZ_SAU_Setup(void)1124 __STATIC_INLINE void TZ_SAU_Setup (void)
1125 {
1126
1127 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1128
1129 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
1130 SAU_INIT_REGION(0);
1131 #endif
1132
1133 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
1134 SAU_INIT_REGION(1);
1135 #endif
1136
1137 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
1138 SAU_INIT_REGION(2);
1139 #endif
1140
1141 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
1142 SAU_INIT_REGION(3);
1143 #endif
1144
1145 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
1146 SAU_INIT_REGION(4);
1147 #endif
1148
1149 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
1150 SAU_INIT_REGION(5);
1151 #endif
1152
1153 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
1154 SAU_INIT_REGION(6);
1155 #endif
1156
1157 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
1158 SAU_INIT_REGION(7);
1159 #endif
1160
1161 /* repeat this for all possible SAU regions */
1162
1163 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1164
1165
1166 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
1167 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
1168 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
1169 #endif
1170
1171 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
1172 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
1173 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
1174
1175 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
1176 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
1177 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
1178 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
1179 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
1180 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
1181 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
1182
1183 #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \
1184 (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \
1185 (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))
1186
1187 SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
1188 ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
1189
1190 FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
1191 ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
1192 ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
1193 ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
1194 #endif
1195
1196 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
1197 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
1198 #endif
1199
1200 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
1201 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
1202 #endif
1203
1204 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
1205 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
1206 #endif
1207
1208 #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
1209 NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
1210 #endif
1211
1212 #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
1213 NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
1214 #endif
1215
1216 #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
1217 NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
1218 #endif
1219
1220 #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
1221 NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
1222 #endif
1223
1224 #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
1225 NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
1226 #endif
1227
1228 #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
1229 NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
1230 #endif
1231
1232 #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
1233 NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
1234 #endif
1235
1236 #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
1237 NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
1238 #endif
1239
1240 #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
1241 NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
1242 #endif
1243
1244 #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
1245 NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
1246 #endif
1247
1248 #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
1249 NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
1250 #endif
1251
1252 #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
1253 NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
1254 #endif
1255
1256 #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
1257 NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
1258 #endif
1259
1260 /* repeat this for all possible ITNS elements */
1261
1262 }
1263
1264 #endif /* PARTITION_<Device>_H */
1265
