1 /** 2 * @file otp_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the OTP_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _OTP_REVA_REGS_H_ 27 #define _OTP_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup otp_reva 65 * @defgroup otp_reva_registers OTP_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the OTP_REVA Peripheral Module. 67 * @details One-Time Programmable (OTP) Memory Controller. 68 */ 69 70 /** 71 * @ingroup otp_reva_registers 72 * Structure type to access the OTP_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> OTP_REVA CTRL Register */ 76 __IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> OTP_REVA CLKDIV Register */ 77 __IO uint32_t rdata; /**< <tt>\b 0x08:</tt> OTP_REVA RDATA Register */ 78 __IO uint32_t status; /**< <tt>\b 0x0C:</tt> OTP_REVA STATUS Register */ 79 __R uint32_t rsv_0x10_0x2f[8]; 80 __IO uint32_t wdata; /**< <tt>\b 0x30:</tt> OTP_REVA WDATA Register */ 81 __R uint32_t rsv_0x34_0x3b[2]; 82 __IO uint32_t actrl0; /**< <tt>\b 0x3C:</tt> OTP_REVA ACTRL0 Register */ 83 __IO uint32_t actrl1; /**< <tt>\b 0x40:</tt> OTP_REVA ACTRL1 Register */ 84 } mxc_otp_reva_regs_t; 85 86 /* Register offsets for module OTP_REVA */ 87 /** 88 * @ingroup otp_reva_registers 89 * @defgroup OTP_REVA_Register_Offsets Register Offsets 90 * @brief OTP_REVA Peripheral Register Offsets from the OTP_REVA Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_OTP_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from OTP_REVA Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_OTP_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from OTP_REVA Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_OTP_REVA_RDATA ((uint32_t)0x00000008UL) /**< Offset from OTP_REVA Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_OTP_REVA_STATUS ((uint32_t)0x0000000CUL) /**< Offset from OTP_REVA Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_OTP_REVA_WDATA ((uint32_t)0x00000030UL) /**< Offset from OTP_REVA Base Address: <tt> 0x0030</tt> */ 98 #define MXC_R_OTP_REVA_ACTRL0 ((uint32_t)0x0000003CUL) /**< Offset from OTP_REVA Base Address: <tt> 0x003C</tt> */ 99 #define MXC_R_OTP_REVA_ACTRL1 ((uint32_t)0x00000040UL) /**< Offset from OTP_REVA Base Address: <tt> 0x0040</tt> */ 100 /**@} end of group otp_reva_registers */ 101 102 /** 103 * @ingroup otp_reva_registers 104 * @defgroup OTP_REVA_CTRL OTP_REVA_CTRL 105 * @brief OTP Control Register. 106 * @{ 107 */ 108 #define MXC_F_OTP_REVA_CTRL_ADDR_POS 0 /**< CTRL_ADDR Position */ 109 #define MXC_F_OTP_REVA_CTRL_ADDR ((uint32_t)(0xFFFFUL << MXC_F_OTP_REVA_CTRL_ADDR_POS)) /**< CTRL_ADDR Mask */ 110 111 #define MXC_F_OTP_REVA_CTRL_READ_POS 24 /**< CTRL_READ Position */ 112 #define MXC_F_OTP_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_OTP_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ 113 114 #define MXC_F_OTP_REVA_CTRL_WRITE_POS 25 /**< CTRL_WRITE Position */ 115 #define MXC_F_OTP_REVA_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_OTP_REVA_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */ 116 117 /**@} end of group OTP_REVA_CTRL_Register */ 118 119 /** 120 * @ingroup otp_reva_registers 121 * @defgroup OTP_REVA_CLKDIV OTP_REVA_CLKDIV 122 * @brief OTP Clock Divide Register. 123 * @{ 124 */ 125 #define MXC_F_OTP_REVA_CLKDIV_PCLKDIV_POS 0 /**< CLKDIV_PCLKDIV Position */ 126 #define MXC_F_OTP_REVA_CLKDIV_PCLKDIV ((uint32_t)(0x3FUL << MXC_F_OTP_REVA_CLKDIV_PCLKDIV_POS)) /**< CLKDIV_PCLKDIV Mask */ 127 #define MXC_V_OTP_REVA_CLKDIV_PCLKDIV_DIV2 ((uint32_t)0x1UL) /**< CLKDIV_PCLKDIV_DIV2 Value */ 128 #define MXC_S_OTP_REVA_CLKDIV_PCLKDIV_DIV2 (MXC_V_OTP_REVA_CLKDIV_PCLKDIV_DIV2 << MXC_F_OTP_REVA_CLKDIV_PCLKDIV_POS) /**< CLKDIV_PCLKDIV_DIV2 Setting */ 129 #define MXC_V_OTP_REVA_CLKDIV_PCLKDIV_DIV4 ((uint32_t)0x3UL) /**< CLKDIV_PCLKDIV_DIV4 Value */ 130 #define MXC_S_OTP_REVA_CLKDIV_PCLKDIV_DIV4 (MXC_V_OTP_REVA_CLKDIV_PCLKDIV_DIV4 << MXC_F_OTP_REVA_CLKDIV_PCLKDIV_POS) /**< CLKDIV_PCLKDIV_DIV4 Setting */ 131 #define MXC_V_OTP_REVA_CLKDIV_PCLKDIV_DIV8 ((uint32_t)0x7UL) /**< CLKDIV_PCLKDIV_DIV8 Value */ 132 #define MXC_S_OTP_REVA_CLKDIV_PCLKDIV_DIV8 (MXC_V_OTP_REVA_CLKDIV_PCLKDIV_DIV8 << MXC_F_OTP_REVA_CLKDIV_PCLKDIV_POS) /**< CLKDIV_PCLKDIV_DIV8 Setting */ 133 #define MXC_V_OTP_REVA_CLKDIV_PCLKDIV_DIV16 ((uint32_t)0xFUL) /**< CLKDIV_PCLKDIV_DIV16 Value */ 134 #define MXC_S_OTP_REVA_CLKDIV_PCLKDIV_DIV16 (MXC_V_OTP_REVA_CLKDIV_PCLKDIV_DIV16 << MXC_F_OTP_REVA_CLKDIV_PCLKDIV_POS) /**< CLKDIV_PCLKDIV_DIV16 Setting */ 135 #define MXC_V_OTP_REVA_CLKDIV_PCLKDIV_DIV32 ((uint32_t)0x1FUL) /**< CLKDIV_PCLKDIV_DIV32 Value */ 136 #define MXC_S_OTP_REVA_CLKDIV_PCLKDIV_DIV32 (MXC_V_OTP_REVA_CLKDIV_PCLKDIV_DIV32 << MXC_F_OTP_REVA_CLKDIV_PCLKDIV_POS) /**< CLKDIV_PCLKDIV_DIV32 Setting */ 137 138 #define MXC_F_OTP_REVA_CLKDIV_SPWE_POS 8 /**< CLKDIV_SPWE Position */ 139 #define MXC_F_OTP_REVA_CLKDIV_SPWE ((uint32_t)(0x1UL << MXC_F_OTP_REVA_CLKDIV_SPWE_POS)) /**< CLKDIV_SPWE Mask */ 140 141 #define MXC_F_OTP_REVA_CLKDIV_PD_POS 9 /**< CLKDIV_PD Position */ 142 #define MXC_F_OTP_REVA_CLKDIV_PD ((uint32_t)(0x1UL << MXC_F_OTP_REVA_CLKDIV_PD_POS)) /**< CLKDIV_PD Mask */ 143 144 #define MXC_F_OTP_REVA_CLKDIV_HCLKDIV_POS 16 /**< CLKDIV_HCLKDIV Position */ 145 #define MXC_F_OTP_REVA_CLKDIV_HCLKDIV ((uint32_t)(0x3FUL << MXC_F_OTP_REVA_CLKDIV_HCLKDIV_POS)) /**< CLKDIV_HCLKDIV Mask */ 146 147 /**@} end of group OTP_REVA_CLKDIV_Register */ 148 149 /** 150 * @ingroup otp_reva_registers 151 * @defgroup OTP_REVA_RDATA OTP_REVA_RDATA 152 * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this 153 * register clears the bits in the same positions in GPIO_EN to 0, without 154 * affecting other bits in that register. 155 * @{ 156 */ 157 #define MXC_F_OTP_REVA_RDATA_DATA_POS 0 /**< RDATA_DATA Position */ 158 #define MXC_F_OTP_REVA_RDATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_OTP_REVA_RDATA_DATA_POS)) /**< RDATA_DATA Mask */ 159 160 /**@} end of group OTP_REVA_RDATA_Register */ 161 162 /** 163 * @ingroup otp_reva_registers 164 * @defgroup OTP_REVA_STATUS OTP_REVA_STATUS 165 * @brief OTP Status Register. 166 * @{ 167 */ 168 #define MXC_F_OTP_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ 169 #define MXC_F_OTP_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_OTP_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ 170 171 #define MXC_F_OTP_REVA_STATUS_FAIL_POS 1 /**< STATUS_FAIL Position */ 172 #define MXC_F_OTP_REVA_STATUS_FAIL ((uint32_t)(0x1UL << MXC_F_OTP_REVA_STATUS_FAIL_POS)) /**< STATUS_FAIL Mask */ 173 174 #define MXC_F_OTP_REVA_STATUS_UNLOCK1_POS 8 /**< STATUS_UNLOCK1 Position */ 175 #define MXC_F_OTP_REVA_STATUS_UNLOCK1 ((uint32_t)(0x1UL << MXC_F_OTP_REVA_STATUS_UNLOCK1_POS)) /**< STATUS_UNLOCK1 Mask */ 176 177 #define MXC_F_OTP_REVA_STATUS_UNLOCK3_POS 9 /**< STATUS_UNLOCK3 Position */ 178 #define MXC_F_OTP_REVA_STATUS_UNLOCK3 ((uint32_t)(0x1UL << MXC_F_OTP_REVA_STATUS_UNLOCK3_POS)) /**< STATUS_UNLOCK3 Mask */ 179 180 #define MXC_F_OTP_REVA_STATUS_PWR_RDY_POS 16 /**< STATUS_PWR_RDY Position */ 181 #define MXC_F_OTP_REVA_STATUS_PWR_RDY ((uint32_t)(0x1UL << MXC_F_OTP_REVA_STATUS_PWR_RDY_POS)) /**< STATUS_PWR_RDY Mask */ 182 183 /**@} end of group OTP_REVA_STATUS_Register */ 184 185 /** 186 * @ingroup otp_reva_registers 187 * @defgroup OTP_REVA_WDATA OTP_REVA_WDATA 188 * @brief OTP Write Data Register. 189 * @{ 190 */ 191 #define MXC_F_OTP_REVA_WDATA_DATA_POS 0 /**< WDATA_DATA Position */ 192 #define MXC_F_OTP_REVA_WDATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_OTP_REVA_WDATA_DATA_POS)) /**< WDATA_DATA Mask */ 193 194 /**@} end of group OTP_REVA_WDATA_Register */ 195 196 /** 197 * @ingroup otp_reva_registers 198 * @defgroup OTP_REVA_ACTRL0 OTP_REVA_ACTRL0 199 * @brief Access Control for user block. 200 * @{ 201 */ 202 #define MXC_F_OTP_REVA_ACTRL0_ADATA_POS 0 /**< ACTRL0_ADATA Position */ 203 #define MXC_F_OTP_REVA_ACTRL0_ADATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_OTP_REVA_ACTRL0_ADATA_POS)) /**< ACTRL0_ADATA Mask */ 204 205 /**@} end of group OTP_REVA_ACTRL0_Register */ 206 207 /** 208 * @ingroup otp_reva_registers 209 * @defgroup OTP_REVA_ACTRL1 OTP_REVA_ACTRL1 210 * @brief Access Control for sys and user block. 211 * @{ 212 */ 213 #define MXC_F_OTP_REVA_ACTRL1_ADATA_POS 0 /**< ACTRL1_ADATA Position */ 214 #define MXC_F_OTP_REVA_ACTRL1_ADATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_OTP_REVA_ACTRL1_ADATA_POS)) /**< ACTRL1_ADATA Mask */ 215 216 /**@} end of group OTP_REVA_ACTRL1_Register */ 217 218 #ifdef __cplusplus 219 } 220 #endif 221 222 #endif /* _OTP_REVA_REGS_H_ */ 223
