1 /*
2  * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <stdint.h>
8 #include "spi_flash_defs.h"
9 
10 //MXIC OPI mode needs two bytes of command - 2nd byte is the inversion of the command (1st) byte. S3 HW send LSB first
11  #define MXIC_CMD16(cmd8)   ( (uint8_t)(cmd8) | ((uint8_t)(~(cmd8)) << 8) )
12 
13 #define OPI_CMD_FORMAT_MXIC_STR() {   \
14     .rdid = {              \
15         .mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
16         .cmd_bit_len = 16, \
17         .cmd = MXIC_CMD16(CMD_RDID), \
18         .addr = 0, \
19         .addr_bit_len = 4*8, \
20         .dummy_bit_len = 4, \
21         .data_bit_len = 4 * 8, \
22         .cs_sel = 0x1, \
23         .is_pe = 0, \
24     }, \
25     .rdsr = { \
26         .mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
27         .cmd_bit_len = 16, \
28         .cmd = MXIC_CMD16(CMD_RDSR), \
29         .addr = 0, \
30         .addr_bit_len = 4*8, \
31         .dummy_bit_len = 4, \
32         .data_bit_len = 1 * 8, \
33         .cs_sel = 0x1, \
34         .is_pe = 0, \
35     }, \
36     .wren = { \
37         .mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
38         .cmd_bit_len = 16, \
39         .cmd = MXIC_CMD16(CMD_WREN), \
40         .addr = 0, \
41         .addr_bit_len = 0, \
42         .dummy_bit_len = 0, \
43         .data_bit_len = 0, \
44         .cs_sel = 0x1, \
45         .is_pe = 0, \
46     }, \
47     .se = { \
48         .mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
49         .cmd_bit_len = 16, \
50         .cmd = MXIC_CMD16(CMD_SECTOR_ERASE_4B), \
51         .addr = 0, \
52         .addr_bit_len = 32, \
53         .dummy_bit_len = 0, \
54         .data_bit_len = 0, \
55         .cs_sel = 0x1, \
56         .is_pe = 1, \
57     }, \
58     .be64k = { \
59         .mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
60         .cmd_bit_len = 16, \
61         .cmd = MXIC_CMD16(CMD_LARGE_BLOCK_ERASE_4B), \
62         .addr = 0, \
63         .addr_bit_len = 32, \
64         .dummy_bit_len = 0, \
65         .data_bit_len = 0, \
66         .cs_sel = 0x1, \
67         .is_pe = 1, \
68     }, \
69     .read = { \
70         .mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
71         .cmd_bit_len = 16, \
72         .cmd = MXIC_CMD16(CMD_8READ), \
73         .addr = 0, \
74         .addr_bit_len = 32, \
75         .dummy_bit_len = 20, \
76         .data_bit_len = 0, \
77         .cs_sel = 0x1, \
78         .is_pe = 0, \
79     }, \
80     .pp = { \
81         .mode = ESP_ROM_SPIFLASH_OPI_STR_MODE, \
82         .cmd_bit_len = 16, \
83         .cmd = MXIC_CMD16(CMD_PROGRAM_PAGE_4B), \
84         .addr = 0, \
85         .addr_bit_len = 32, \
86         .dummy_bit_len = 0, \
87         .data_bit_len = 0, \
88         .cs_sel = 0x1, \
89         .is_pe = 1, \
90     }, \
91     .cache_rd_cmd = { \
92         .addr_bit_len = 32, \
93         .dummy_bit_len = 20, \
94         .cmd = MXIC_CMD16(CMD_8READ), \
95         .cmd_bit_len = 16, \
96         .var_dummy_en = 1, \
97     } \
98 }
99 
100 #define OPI_CMD_FORMAT_MXIC_DTR() {   \
101     .rdid = {              \
102         .mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
103         .cmd_bit_len = 16, \
104         .cmd = MXIC_CMD16(CMD_RDID), \
105         .addr = 0, \
106         .addr_bit_len = 4*8, \
107         .dummy_bit_len = 4*2, \
108         .data_bit_len = 4 * 8, \
109         .cs_sel = 0x1, \
110         .is_pe = 0, \
111     }, \
112     .rdsr = { \
113         .mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
114         .cmd_bit_len = 16, \
115         .cmd = MXIC_CMD16(CMD_RDSR), \
116         .addr = 0, \
117         .addr_bit_len = 4*8, \
118         .dummy_bit_len = 4*2, \
119         .data_bit_len = 2 * 8, \
120         .cs_sel = 0x1, \
121         .is_pe = 0, \
122     }, \
123     .wren = { \
124         .mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
125         .cmd_bit_len = 16, \
126         .cmd = MXIC_CMD16(CMD_WREN), \
127         .addr = 0, \
128         .addr_bit_len = 0, \
129         .dummy_bit_len = 0, \
130         .data_bit_len = 0, \
131         .cs_sel = 0x1, \
132         .is_pe = 0, \
133     }, \
134     .se = { \
135         .mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
136         .cmd_bit_len = 16, \
137         .cmd = MXIC_CMD16(CMD_SECTOR_ERASE_4B), \
138         .addr = 0, \
139         .addr_bit_len = 32, \
140         .dummy_bit_len = 0, \
141         .data_bit_len = 0, \
142         .cs_sel = 0x1, \
143         .is_pe = 1, \
144     }, \
145     .be64k = { \
146         .mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
147         .cmd_bit_len = 16, \
148         .cmd = MXIC_CMD16(CMD_LARGE_BLOCK_ERASE_4B), \
149         .addr = 0, \
150         .addr_bit_len = 32, \
151         .dummy_bit_len = 0, \
152         .data_bit_len = 0, \
153         .cs_sel = 0x1, \
154         .is_pe = 1, \
155     }, \
156     .read = { \
157         .mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
158         .cmd_bit_len = 16, \
159         .cmd = MXIC_CMD16(CMD_8DTRD), \
160         .addr = 0, \
161         .addr_bit_len = 32, \
162         .dummy_bit_len = 20*2, \
163         .data_bit_len = 0, \
164         .cs_sel = 0x1, \
165         .is_pe = 0, \
166     }, \
167     .pp = { \
168         .mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE, \
169         .cmd_bit_len = 16, \
170         .cmd = MXIC_CMD16(CMD_PROGRAM_PAGE_4B), \
171         .addr = 0, \
172         .addr_bit_len = 32, \
173         .dummy_bit_len = 0, \
174         .data_bit_len = 0, \
175         .cs_sel = 0x1, \
176         .is_pe = 1, \
177     }, \
178     .cache_rd_cmd = { \
179         .addr_bit_len = 32, \
180         .dummy_bit_len = 20*2, \
181         .cmd = MXIC_CMD16(CMD_8DTRD), \
182         .cmd_bit_len = 16, \
183         .var_dummy_en = 1, \
184     } \
185 }
186