1/*
2 * Copyright 2022-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
14#include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
15#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
17
18/ {
19	chosen {
20		zephyr,entropy = &trng;
21	};
22
23	cpus {
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		cpu0: cpu@0 {
28			compatible = "arm,cortex-m33f";
29			reg = <0>;
30			#address-cells = <1>;
31			#size-cells = <1>;
32			cpu-power-states = <&idle &suspend>;
33
34			mpu: mpu@e000ed90 {
35				compatible = "arm,armv8m-mpu";
36				reg = <0xe000ed90 0x40>;
37			};
38		};
39
40		power-states {
41			/* This is the setting Sleep Mode */
42			idle: idle {
43				compatible = "zephyr,power-state";
44				power-state-name = "runtime-idle";
45				min-residency-us = <0>;
46				exit-latency-us = <0>;
47			};
48			/* This is the setting for Deep-sleep Mode */
49			suspend: suspend {
50				compatible = "nxp,pdcfg-power", "zephyr,power-state";
51				power-state-name = "suspend-to-idle";
52				min-residency-us = <500>;
53				exit-latency-us = <120>;
54				/*
55				 * These values are written to the PDSLEEPCFG
56				 * registers to keep certain blocks such as
57				 * LPOSC, SRAM's, FlexSPI0 SRAM powered on
58				 * during deep sleep mode.
59				 */
60				deep-sleep-config = <0xC800>,
61							<0x80000004>,
62							<0xFFFFFFFF>,
63							<0>;
64			};
65		};
66	};
67};
68
69&sram {
70	#address-cells = <1>;
71	#size-cells = <1>;
72
73	/* RT5XX SRAM partitions are shared
74	 * between code and data. Boards can
75	 * override the reg properties of either sram0 or sram_code nodes to
76	 * change the balance of SRAM allocation.
77	 *
78	 * Note that the sram code region starts at an offset of 0x1B000,
79	 * as the boot ROM will not load code before 0x1C000. The first
80	 * 0x1000 of the image will contain the boot header.
81	 */
82	sram_code: memory@1b000 {
83		compatible = "mmio-sram";
84		reg = <0x1b000 DT_SIZE_K(1428)>;
85	};
86
87	sram0: memory@20180000 {
88		compatible = "mmio-sram";
89		reg = <0x20180000 DT_SIZE_K(3072)>;
90	};
91
92	sram1: memory@40140000 {
93		compatible =  "zephyr,memory-region", "mmio-sram";
94		reg = <0x40140000 DT_SIZE_K(16)>;
95		zephyr,memory-region = "SRAM1";
96		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
97	};
98};
99
100&systick {
101	/*
102	 * RT500 relies by default on the OS Timer for system clock
103	 * implementation, so the SysTick node is not to be enabled.
104	 */
105	status = "disabled";
106};
107
108&peripheral {
109	#address-cells = <1>;
110	#size-cells = <1>;
111	/*
112	 * Note that the offsets here are relative to the base address
113	 * defined in either nxp_rt5xx_ns.dtsi or nxp_rt5xx.dtsi. The base
114	 * addresses differ between non-secure (0x40000000) and secure
115	 * modes (0x50000000).
116	 */
117
118	flexspi: spi@134000 {
119		reg = <0x134000 0x1000>, <0x18000000 DT_SIZE_M(128)>;
120	};
121
122	flexspi2: spi@13c000 {
123		reg = <0x13c000 0x1000>, <0x38000000 DT_SIZE_M(128)>;
124	};
125
126	clkctl0: clkctl@1000 {
127		/* FIXME This chip does NOT have a syscon */
128		compatible = "nxp,lpc-syscon";
129		reg = <0x1000 0x1000>;
130		#clock-cells = <1>;
131	};
132
133	iocon: iocon@4000 {
134		compatible = "nxp,lpc-iocon";
135		reg = <0x4000 0x1000>;
136		pinctrl: pinctrl {
137			compatible = "nxp,rt-iocon-pinctrl";
138		};
139	};
140
141	clkctl1: clkctl@21000 {
142		/* FIXME This chip does NOT have a syscon */
143		compatible = "nxp,lpc-syscon";
144		reg = <0x21000 0x1000>;
145		#clock-cells = <1>;
146	};
147
148	rstctl0: reset@0 {
149		compatible = "nxp,rstctl";
150		reg = <0x0 0x80>;
151		#reset-cells = <1>;
152	};
153
154	rstctl1: reset@20000 {
155		compatible = "nxp,rstctl";
156		reg = <0x20000 0x80>;
157		#reset-cells = <1>;
158	};
159
160	uuid: uuid@2f50 {
161		compatible = "nxp,lpc-uid";
162		reg = <0x2f50 0x10>;
163	};
164
165	gpio: gpio@100000 {
166		compatible = "nxp,lpc-gpio";
167		reg = <0x100000 0x2784>;
168		#address-cells = <1>;
169		#size-cells = <0>;
170
171		gpio0: gpio@0 {
172			compatible = "nxp,lpc-gpio-port";
173			int-source = "pint";
174			gpio-controller;
175			#gpio-cells = <2>;
176			reg = <0>;
177		};
178
179		gpio1: gpio@1 {
180			compatible = "nxp,lpc-gpio-port";
181			int-source = "pint";
182			gpio-controller;
183			#gpio-cells = <2>;
184			reg = <1>;
185		};
186
187		gpio2: gpio@2 {
188			compatible = "nxp,lpc-gpio-port";
189			gpio-controller;
190			#gpio-cells = <2>;
191			reg = <2>;
192		};
193
194		gpio3: gpio@3 {
195			compatible = "nxp,lpc-gpio-port";
196			gpio-controller;
197			#gpio-cells = <2>;
198			reg = <3>;
199		};
200
201		gpio4: gpio@4 {
202			compatible = "nxp,lpc-gpio-port";
203			gpio-controller;
204			#gpio-cells = <2>;
205			reg = <4>;
206		};
207
208		gpio5: gpio@5 {
209			compatible = "nxp,lpc-gpio-port";
210			gpio-controller;
211			#gpio-cells = <2>;
212			reg = <5>;
213		};
214
215		gpio6: gpio@6 {
216			compatible = "nxp,lpc-gpio-port";
217			gpio-controller;
218			#gpio-cells = <2>;
219			reg = <6>;
220		};
221	};
222
223	pint: pint@25000 {
224		compatible = "nxp,pint";
225		reg = <0x25000 0x1000>;
226		interrupt-controller;
227		#interrupt-cells = <1>;
228		#address-cells = <0>;
229		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
230			<35 2>, <36 2>, <37 2>, <38 2>;
231		num-lines = <8>;
232		num-inputs = <64>;
233	};
234
235	flexcomm0: flexcomm@106000 {
236		compatible = "nxp,lpc-flexcomm";
237		reg = <0x106000 0x1000>;
238		interrupts = <14 0>;
239		clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
240		resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
241		status = "disabled";
242	};
243
244	flexcomm1: flexcomm@107000 {
245		compatible = "nxp,lpc-flexcomm";
246		reg = <0x107000 0x1000>;
247		interrupts = <15 0>;
248		clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
249		resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
250		status = "disabled";
251	};
252
253	flexcomm2: flexcomm@108000 {
254		compatible = "nxp,lpc-flexcomm";
255		reg = <0x108000 0x1000>;
256		interrupts = <16 0>;
257		clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
258		resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
259		status = "disabled";
260	};
261
262	flexcomm3: flexcomm@109000 {
263		compatible = "nxp,lpc-flexcomm";
264		reg = <0x109000 0x1000>;
265		interrupts = <17 0>;
266		clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
267		resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
268		status = "disabled";
269	};
270
271	flexcomm4: flexcomm@122000 {
272		compatible = "nxp,lpc-flexcomm";
273		reg = <0x122000 0x1000>;
274		interrupts = <18 0>;
275		clocks = <&clkctl1 MCUX_FLEXCOMM4_CLK>;
276		resets = <&rstctl1 NXP_SYSCON_RESET(0, 12)>;
277		status = "disabled";
278	};
279
280	flexcomm5: flexcomm@123000 {
281		compatible = "nxp,lpc-flexcomm";
282		reg = <0x123000 0x1000>;
283		interrupts = <19 0>;
284		clocks = <&clkctl1 MCUX_FLEXCOMM5_CLK>;
285		resets = <&rstctl1 NXP_SYSCON_RESET(0, 13)>;
286		status = "disabled";
287	};
288
289	flexcomm6: flexcomm@124000 {
290		compatible = "nxp,lpc-flexcomm";
291		reg = <0x124000 0x1000>;
292		interrupts = <43 0>;
293		clocks = <&clkctl1 MCUX_FLEXCOMM6_CLK>;
294		resets = <&rstctl1 NXP_SYSCON_RESET(0, 14)>;
295		status = "disabled";
296	};
297
298	flexcomm7: flexcomm@125000 {
299		compatible = "nxp,lpc-flexcomm";
300		reg = <0x125000 0x1000>;
301		interrupts = <44 0>;
302		clocks = <&clkctl1 MCUX_FLEXCOMM7_CLK>;
303		resets = <&rstctl1 NXP_SYSCON_RESET(0, 15)>;
304		status = "disabled";
305	};
306
307	pmic_i2c: i2c@127000 {
308		compatible = "nxp,lpc-i2c";
309		reg = <0x127000 0x1000>;
310		interrupts = <21 0>;
311		clocks = <&clkctl1 MCUX_PMIC_I2C_CLK>;
312		resets = <&rstctl1 NXP_SYSCON_RESET(0, 23)>;
313		status = "disabled";
314	};
315
316	flexcomm8: flexcomm@209000 {
317		compatible = "nxp,lpc-flexcomm";
318		reg = <0x209000 0x1000>;
319		interrupts = <60 0>;
320		clocks = <&clkctl1 MCUX_FLEXCOMM8_CLK>;
321		resets = <&rstctl1 NXP_SYSCON_RESET(0, 16)>;
322		status = "disabled";
323	};
324
325	flexcomm9: flexcomm@20a000 {
326		compatible = "nxp,lpc-flexcomm";
327		reg = <0x20a000 0x1000>;
328		interrupts = <61 0>;
329		clocks = <&clkctl1 MCUX_FLEXCOMM9_CLK>;
330		resets = <&rstctl1 NXP_SYSCON_RESET(0, 17)>;
331		status = "disabled";
332	};
333
334	flexcomm10: flexcomm@20b000 {
335		compatible = "nxp,lpc-flexcomm";
336		reg = <0x20b000 0x1000>;
337		interrupts = <62 0>;
338		clocks = <&clkctl1 MCUX_FLEXCOMM10_CLK>;
339		resets = <&rstctl1 NXP_SYSCON_RESET(0, 18)>;
340		status = "disabled";
341	};
342
343	flexcomm11: flexcomm@20c000 {
344		compatible = "nxp,lpc-flexcomm";
345		reg = <0x20c000 0x1000>;
346		interrupts = <63 0>;
347		clocks = <&clkctl1 MCUX_FLEXCOMM11_CLK>;
348		resets = <&rstctl1 NXP_SYSCON_RESET(0, 19)>;
349		status = "disabled";
350	};
351
352	flexcomm12: flexcomm@20d000 {
353		compatible = "nxp,lpc-flexcomm";
354		reg = <0x20d000 0x1000>;
355		interrupts = <64 0>;
356		clocks = <&clkctl1 MCUX_FLEXCOMM12_CLK>;
357		resets = <&rstctl1 NXP_SYSCON_RESET(0, 20)>;
358		status = "disabled";
359	};
360
361	flexcomm13: flexcomm@20e000 {
362		compatible = "nxp,lpc-flexcomm";
363		reg = <0x20e000 0x1000>;
364		interrupts = <65 0>;
365		clocks = <&clkctl1 MCUX_FLEXCOMM13_CLK>;
366		resets = <&rstctl1 NXP_SYSCON_RESET(0, 21)>;
367		status = "disabled";
368	};
369
370	lcdif: lcdif@210000 {
371		compatible = "nxp,dcnano-lcdif";
372		reg = <0x210000 0x1000>;
373		interrupts = <69 0>;
374		status = "disabled";
375	};
376
377	usbhs: usbhs@144000 {
378		compatible = "nxp,lpcip3511";
379		reg = <0x144000 0x1000>;
380		interrupts = <50 1>;
381		num-bidir-endpoints = <6>;
382		status = "disabled";
383	};
384
385	hs_lspi: spi@126000 {
386		compatible = "nxp,lpc-spi";
387		reg = <0x126000 0x1000>;
388		interrupts = <20 0>;
389		clocks = <&clkctl1 MCUX_HS_SPI_CLK>;
390		resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>;
391		status = "disabled";
392		#address-cells = <1>;
393		#size-cells = <0>;
394	};
395
396	hs_lspi1: spi@128000 {
397		compatible = "nxp,lpc-spi";
398		reg = <0x128000 0x1000>;
399		interrupts = <66 0>;
400		clocks = <&clkctl1 MCUX_HS_SPI1_CLK>;
401		resets = <&rstctl1 NXP_SYSCON_RESET(0, 24)>;
402		status = "disabled";
403		#address-cells = <1>;
404		#size-cells = <0>;
405	};
406
407	dma0: dma-controller@104000 {
408		compatible = "nxp,lpc-dma";
409		reg = <0x104000 0x1000>;
410		interrupts = <1 0>;
411		dma-channels = <37>;
412		nxp,dma-num-of-otrigs = <4>;
413		nxp,dma-otrig-base-address = <RT595_DMA0_OTRIG_BASE>;
414		nxp,dma-itrig-base-address = <RT595_DMA0_ITRIG_BASE>;
415		status = "disabled";
416		#dma-cells = <1>;
417	};
418
419	dma1: dma-controller@105000 {
420		compatible = "nxp,lpc-dma";
421		reg = <0x105000 0x1000>;
422		interrupts = <54 0>;
423		dma-channels = <37>;
424		nxp,dma-num-of-otrigs = <4>;
425		nxp,dma-otrig-base-address = <RT595_DMA1_OTRIG_BASE>;
426		nxp,dma-itrig-base-address = <RT595_DMA1_ITRIG_BASE>;
427		status = "disabled";
428		#dma-cells = <1>;
429	};
430
431	dmic0: dmic@121000 {
432		#address-cells=<1>;
433		#size-cells=<0>;
434		compatible = "nxp,dmic";
435		reg = <0x121000 0x1000>;
436		interrupts = <25 0>;
437		status = "disabled";
438		clocks = <&clkctl0 MCUX_DMIC_CLK>;
439
440		pdmc0: dmic-channel@0 {
441			reg = <0>;
442			dmas = <&dma0 16>;
443			status = "disabled";
444		};
445
446		pdmc1: dmic-channel@1 {
447			reg = <1>;
448			dmas = <&dma0 17>;
449			status = "disabled";
450		};
451
452		pdmc2: dmic-channel@2 {
453			reg = <2>;
454			dmas = <&dma0 18>;
455			status = "disabled";
456		};
457
458		pdmc3: dmic-channel@3 {
459			reg = <3>;
460			dmas = <&dma0 19>;
461			status = "disabled";
462		};
463
464		pdmc4: dmic-channel@4 {
465			reg = <4>;
466			dmas = <&dma0 20>;
467			status = "disabled";
468		};
469
470		pdmc5: dmic-channel@5 {
471			reg = <5>;
472			dmas = <&dma0 21>;
473			status = "disabled";
474		};
475
476		pdmc6: dmic-channel@6 {
477			reg = <6>;
478			dmas = <&dma0 22>;
479			status = "disabled";
480		};
481
482		pdmc7: dmic-channel@7 {
483			reg = <7>;
484			dmas = <&dma0 23>;
485			status = "disabled";
486		};
487	};
488
489	os_timer: timers@113000 {
490		compatible = "nxp,os-timer";
491		reg = <0x113000 0x1000>;
492		interrupts = <41 0>;
493		status = "disabled";
494	};
495
496	rtc: rtc@30000 {
497		compatible = "nxp,lpc-rtc";
498		reg = <0x30000 0x1000>;
499		interrupts = <32 0>;
500		status = "disabled";
501		rtc_highres: rtc_highres {
502			compatible = "nxp,lpc-rtc-highres";
503			status = "disabled";
504		};
505	};
506
507	trng: random@138000 {
508		compatible = "nxp,kinetis-trng";
509		reg = <0x138000 0x1000>;
510		status = "okay";
511		interrupts = <31 0>;
512	};
513
514	sc_timer: pwm@146000 {
515		compatible = "nxp,sctimer-pwm";
516		reg = <0x146000 0x1000>;
517		interrupts = <12 0>;
518		status = "disabled";
519		prescaler = <8>;
520		#pwm-cells = <3>;
521		clocks = <&clkctl1 MCUX_SCTIMER_CLK>;
522	};
523
524	wwdt0: watchdog@e000 {
525		compatible = "nxp,lpc-wwdt";
526		reg = <0xe000 0x1000>;
527		interrupts = <0 0>;
528		status = "disabled";
529		clk-divider = <1>;
530	};
531
532	wwdt1: watchdog@2e000 {
533		compatible = "nxp,lpc-wwdt";
534		reg = <0x2e000 0x1000>;
535		interrupts = <52 0>;
536		status = "disabled";
537		clk-divider = <1>;
538	};
539
540	usdhc0: usdhc@136000 {
541		compatible = "nxp,imx-usdhc";
542		reg = <0x136000 0x1000>;
543		status = "disabled";
544		interrupts = <45 0>;
545		clocks = <&clkctl1 MCUX_USDHC1_CLK>;
546		max-current-330 = <1020>;
547		max-current-180 = <1020>;
548		max-bus-freq = <208000000>;
549		min-bus-freq = <400000>;
550	};
551
552	usdhc1: usdhc@137000 {
553		compatible = "nxp,imx-usdhc";
554		reg = <0x137000 0x1000>;
555		status = "disabled";
556		interrupts = <46 0>;
557		clocks = <&clkctl1 MCUX_USDHC2_CLK>;
558		max-current-330 = <1020>;
559		max-current-180 = <1020>;
560		max-bus-freq = <208000000>;
561		min-bus-freq = <400000>;
562	};
563
564	lpadc0: adc@13a000 {
565		compatible = "nxp,lpc-lpadc";
566		reg = <0x13a000 0x304>;
567		interrupts = <22 0>;
568		status = "disabled";
569		voltage-ref= <1>;
570		calibration-average = <128>;
571		power-level = <0>;
572		offset-value-a = <10>;
573		offset-value-b = <10>;
574		#io-channel-cells = <1>;
575		clocks = <&clkctl1 MCUX_LPADC1_CLK>;
576	};
577
578	smartdma: dma@27020 {
579		compatible = "nxp,smartdma";
580		reg = <0x27000 0x1000>;
581		program-mem = <0x24100000>;
582		interrupts = <73 0>;
583		status = "disabled";
584		#dma-cells = <0>;
585	};
586
587	ctimer0: ctimer@28000 {
588		compatible = "nxp,lpc-ctimer";
589		reg = <0x28000 0x1000>;
590		interrupts = <10 0>;
591		status = "disabled";
592		clk-source = <1>;
593		clocks = <&clkctl1 MCUX_CTIMER0_CLK>;
594		mode = <0>;
595		input = <0>;
596		prescale = <0>;
597	};
598
599	ctimer1: ctimer@29000 {
600		compatible = "nxp,lpc-ctimer";
601		reg = <0x29000 0x1000>;
602		interrupts = <11 0>;
603		status = "disabled";
604		clk-source = <1>;
605		clocks = <&clkctl1 MCUX_CTIMER1_CLK>;
606		mode = <0>;
607		input = <0>;
608		prescale = <0>;
609	};
610
611	ctimer2: ctimer@2a000 {
612		compatible = "nxp,lpc-ctimer";
613		reg = <0x2a000 0x1000>;
614		interrupts = <39 0>;
615		status = "disabled";
616		clk-source = <1>;
617		clocks = <&clkctl1 MCUX_CTIMER2_CLK>;
618		mode = <0>;
619		input = <0>;
620		prescale = <0>;
621	};
622
623	ctimer3: ctimer@2b000 {
624		compatible = "nxp,lpc-ctimer";
625		reg = <0x2b000 0x1000>;
626		interrupts = <13 0>;
627		status = "disabled";
628		clk-source = <1>;
629		clocks = <&clkctl1 MCUX_CTIMER3_CLK>;
630		mode = <0>;
631		input = <0>;
632		prescale = <0>;
633	};
634
635	ctimer4: ctimer@2c000 {
636		compatible = "nxp,lpc-ctimer";
637		reg = <0x2c000 0x1000>;
638		interrupts = <40 0>;
639		status = "disabled";
640		clk-source = <1>;
641		clocks = <&clkctl1 MCUX_CTIMER4_CLK>;
642		mode = <0>;
643		input = <0>;
644		prescale = <0>;
645	};
646
647	mipi_dsi: mipi_dsi@31000 {
648		compatible = "nxp,mipi-dsi-2l";
649		#address-cells = <1>;
650		#size-cells = <0>;
651		reg = <0x31000 0x1000>;
652		interrupts = <71 0>;
653		clocks = <&clkctl1 MCUX_MIPI_DSI_DPHY_CLK>,
654			<&clkctl1 MCUX_MIPI_DSI_ESC_CLK>,
655			<&clkctl1 MCUX_LCDIF_PIXEL_CLK>;
656		clock-names = "dphy", "esc", "pixel";
657		status = "disabled";
658	};
659
660	i3c0: i3c@36000 {
661		compatible = "nxp,mcux-i3c";
662		reg = <0x36000 0x1000>;
663		interrupts = <49 0>;
664		clocks = <&clkctl1 MCUX_I3C_CLK>;
665		clk-divider = <2>;
666		clk-divider-slow = <1>;
667		clk-divider-tc = <1>;
668		status = "disabled";
669		#address-cells = <3>;
670		#size-cells = <0>;
671	};
672
673	mbox:mbox@110000 {
674		compatible = "nxp,mbox-imx-mu";
675		reg = <0x110000 0x100>;
676		interrupts = <34 0>;
677		rx-channels = <4>;
678		#mbox-cells = <1>;
679		status = "disabled";
680	};
681
682	mrt: mrt@2d000 {
683		compatible = "nxp,mrt";
684		reg = <0x2d000 0x100>;
685		interrupts = <9 0>;
686		num-channels = <4>;
687		num-bits = <24>;
688		clocks = <&clkctl1 MCUX_MRT_CLK>;
689		resets = <&rstctl1 NXP_SYSCON_RESET(2, 8)>;
690		#address-cells = <1>;
691		#size-cells = <0>;
692
693		mrt_channel0: mrt_channel@0 {
694			compatible = "nxp,mrt-channel";
695			reg = <0>;
696			status = "disabled";
697		};
698		mrt_channel1: mrt_channel@1 {
699			compatible = "nxp,mrt-channel";
700			reg = <1>;
701			status = "disabled";
702		};
703		mrt_channel2: mrt_channel@2 {
704			compatible = "nxp,mrt-channel";
705			reg = <2>;
706			status = "disabled";
707		};
708		mrt_channel3: mrt_channel@3 {
709			compatible = "nxp,mrt-channel";
710			reg = <3>;
711			status = "disabled";
712		};
713	};
714};
715
716&flexspi {
717	compatible = "nxp,imx-flexspi";
718	status = "disabled";
719	interrupts = <42 0>;
720	#address-cells = <1>;
721	#size-cells = <0>;
722	clocks = <&clkctl1 MCUX_FLEXSPI_CLK>;
723};
724
725&flexspi2 {
726	compatible = "nxp,imx-flexspi";
727	status = "disabled";
728	interrupts = <42 0>;
729	#address-cells = <1>;
730	#size-cells = <0>;
731	clocks = <&clkctl1 MCUX_FLEXSPI2_CLK>;
732};
733
734&nvic {
735	arm,num-irq-priority-bits = <3>;
736};
737