1/*
2 * Copyright (c) 2020 Lemonbeat GmbH
3 * Copyright 2024 NXP
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <arm/armv8-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14#include <mem.h>
15#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
16
17/ {
18	aliases {
19		watchdog0 = &wwdt0;
20	};
21
22	chosen {
23		zephyr,flash-controller = &iap;
24	};
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu@0 {
31			compatible = "arm,cortex-m33f";
32			reg = <0>;
33			#address-cells = <1>;
34			#size-cells = <1>;
35
36			mpu: mpu@e000ed90 {
37				compatible = "arm,armv8m-mpu";
38				reg = <0xe000ed90 0x40>;
39			};
40		};
41	};
42};
43
44&sram {
45	#address-cells = <1>;
46	#size-cells = <1>;
47
48	sramx: memory@4000000 {
49		compatible = "mmio-sram";
50		reg = <0x4000000 DT_SIZE_K(32)>;
51	};
52
53	sram0: memory@20000000 {
54		compatible = "mmio-sram";
55		reg = <0x20000000 DT_SIZE_K(64)>;
56	};
57
58	sram1: memory@20010000 {
59		compatible = "zephyr,memory-region", "mmio-sram";
60		reg = <0x20010000 DT_SIZE_K(64)>;
61		zephyr,memory-region = "SRAM1";
62	};
63
64	sram2: memory@20020000 {
65		compatible = "zephyr,memory-region", "mmio-sram";
66		reg = <0x20020000 DT_SIZE_K(64)>;
67		zephyr,memory-region = "SRAM2";
68	};
69
70	sram4: memory@20040000 {
71		compatible = "zephyr,memory-region", "mmio-sram";
72		reg = <0x20040000 DT_SIZE_K(16)>;
73		zephyr,memory-region = "SRAM4";
74	};
75
76	usb_sram: memory@40100000 {
77		compatible = "zephyr,memory-region", "mmio-sram";
78		reg = <0x40100000  DT_SIZE_K(16)>;
79		zephyr,memory-region = "USB_SRAM";
80		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
81	};
82};
83
84&peripheral {
85	#address-cells = <1>;
86	#size-cells = <1>;
87
88	syscon: syscon@0 {
89		compatible = "nxp,lpc-syscon";
90		reg = <0x0 0x1000>;
91		#clock-cells = <1>;
92		reset: reset {
93			compatible = "nxp,lpc-syscon-reset";
94			#reset-cells = <1>;
95		};
96	};
97
98	iap: flash-controller@34000 {
99		compatible = "nxp,iap-fmc55";
100		reg = <0x34000 0x1000>;
101		#address-cells = <1>;
102		#size-cells = <1>;
103		status = "disabled";
104
105		flash0: flash@0 {
106			compatible = "soc-nv-flash";
107			reg = <0x0 DT_SIZE_K(512)>;
108			erase-block-size = <512>;
109			write-block-size = <512>;
110		};
111
112		uuid: flash@9fc70 {
113			compatible = "nxp,lpc-uid";
114			reg = <0x9fc70 0x10>;
115		};
116
117		boot_rom: flash@3000000 {
118			compatible = "soc-nv-flash";
119			reg = <0x3000000 DT_SIZE_K(128)>;
120		};
121	};
122
123	iocon: iocon@1000 {
124		compatible = "nxp,lpc-iocon";
125		reg = <0x1000 0x100>;
126		#address-cells = <1>;
127		#size-cells = <1>;
128		ranges = <0x0 0x1000 0x100>;
129		pinctrl: pinctrl {
130			compatible = "nxp,lpc-iocon-pinctrl";
131		};
132	};
133
134	gpio: gpio@8c000 {
135		compatible = "nxp,lpc-gpio";
136		reg = <0x8c000 0x2488>;
137		#address-cells = <1>;
138		#size-cells = <0>;
139
140		gpio0: gpio@0 {
141			compatible = "nxp,lpc-gpio-port";
142			int-source = "pint";
143			gpio-controller;
144			#gpio-cells = <2>;
145			reg = <0>;
146		};
147
148		gpio1: gpio@1 {
149			compatible = "nxp,lpc-gpio-port";
150			int-source = "pint";
151			gpio-controller;
152			#gpio-cells = <2>;
153			reg = <1>;
154		};
155	};
156
157	pint: pint@4000 {
158		compatible = "nxp,pint";
159		reg = <0x4000 0x1000>;
160		interrupt-controller;
161		#interrupt-cells = <1>;
162		#address-cells = <0>;
163		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
164			<32 2>, <33 2>, <34 2>, <35 2>;
165		num-lines = <8>;
166		num-inputs = <64>;
167	};
168
169	dma0: dma-controller@82000 {
170		compatible = "nxp,lpc-dma";
171		reg = <0x82000 0x1000>;
172		interrupts = <1 0>;
173		dma-channels = <23>;
174		status = "disabled";
175		#dma-cells = <1>;
176	};
177
178	dma1: dma-controller@a7000 {
179		compatible = "nxp,lpc-dma";
180		reg = <0xa7000 0x1000>;
181		interrupts = <58 0>;
182		dma-channels = <10>;
183		status = "disabled";
184		#dma-cells = <1>;
185	};
186
187	flexcomm0: flexcomm@86000 {
188		compatible = "nxp,lpc-flexcomm";
189		reg = <0x86000 0x1000>;
190		interrupts = <14 0>;
191		clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
192		resets = <&reset NXP_SYSCON_RESET(1, 11)>;
193		status = "disabled";
194	};
195
196	flexcomm1: flexcomm@87000 {
197		compatible = "nxp,lpc-flexcomm";
198		reg = <0x87000 0x1000>;
199		interrupts = <15 0>;
200		clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
201		resets = <&reset NXP_SYSCON_RESET(1, 12)>;
202		status = "disabled";
203	};
204
205	flexcomm2: flexcomm@88000 {
206		compatible = "nxp,lpc-flexcomm";
207		reg = <0x88000 0x1000>;
208		interrupts = <16 0>;
209		clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
210		resets = <&reset NXP_SYSCON_RESET(1, 13)>;
211		status = "disabled";
212	};
213
214	flexcomm3: flexcomm@89000 {
215		compatible = "nxp,lpc-flexcomm";
216		reg = <0x89000 0x1000>;
217		interrupts = <17 0>;
218		clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
219		resets = <&reset NXP_SYSCON_RESET(1, 14)>;
220		status = "disabled";
221	};
222
223	flexcomm4: flexcomm@8a000 {
224		compatible = "nxp,lpc-flexcomm";
225		reg = <0x8a000 0x1000>;
226		interrupts = <18 0>;
227		clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
228		resets = <&reset NXP_SYSCON_RESET(1, 15)>;
229		status = "disabled";
230	};
231
232	flexcomm5: flexcomm@96000 {
233		compatible = "nxp,lpc-flexcomm";
234		reg = <0x96000 0x1000>;
235		interrupts = <19 0>;
236		clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
237		resets = <&reset NXP_SYSCON_RESET(1, 16)>;
238		status = "disabled";
239	};
240
241	flexcomm6: flexcomm@97000 {
242		compatible = "nxp,lpc-flexcomm";
243		reg = <0x97000 0x1000>;
244		interrupts = <20 0>;
245		clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
246		resets = <&reset NXP_SYSCON_RESET(1, 17)>;
247		status = "disabled";
248	};
249
250	flexcomm7: flexcomm@98000 {
251		compatible = "nxp,lpc-flexcomm";
252		reg = <0x98000 0x1000>;
253		interrupts = <21 0>;
254		clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
255		resets = <&reset NXP_SYSCON_RESET(1, 18)>;
256		status = "disabled";
257	};
258
259	sc_timer: pwm@85000 {
260		compatible = "nxp,sctimer-pwm";
261		reg = <0x85000 0x1000>;
262		interrupts = <12 0>;
263		status = "disabled";
264		clocks = <&syscon MCUX_SCTIMER_CLK>;
265		prescaler = <2>;
266		#pwm-cells = <3>;
267	};
268
269	hs_lspi: spi@9f000 {
270		compatible = "nxp,lpc-spi";
271		/* Enabling cs-gpios below will allow using GPIO CS,
272		 rather than Flexcomm SS */
273		/* cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
274			<&gpio1 1 GPIO_ACTIVE_LOW>,
275			<&gpio1 12 GPIO_ACTIVE_LOW>,
276			<&gpio1 26 GPIO_ACTIVE_LOW>; */
277		reg = <0x9f000 0x1000>;
278		interrupts = <59 0>;
279		clocks = <&syscon MCUX_HS_SPI_CLK>;
280		resets = <&reset NXP_SYSCON_RESET(2, 28)>;
281		status = "disabled";
282		#address-cells = <1>;
283		#size-cells = <0>;
284	};
285
286	rng: rng@3a000 {
287		compatible = "nxp,lpc-rng";
288		reg = <0x3a000 0x1000>;
289		status = "okay";
290	};
291
292	wwdt0: watchdog@c000 {
293		compatible = "nxp,lpc-wwdt";
294		reg = <0xc000 0x1000>;
295		interrupts = <0 0>;
296		status = "disabled";
297		clk-divider = <1>;
298	};
299
300	adc0: adc@a0000 {
301		compatible = "nxp,lpc-lpadc";
302		reg = <0xa0000 0x1000>;
303		interrupts = <22 0>;
304		status = "disabled";
305		clk-divider = <8>;
306		clk-source = <0>;
307		voltage-ref= <1>;
308		calibration-average = <128>;
309		power-level = <0>;
310		offset-value-a = <10>;
311		offset-value-b = <10>;
312		#io-channel-cells = <1>;
313		clocks = <&syscon MCUX_LPADC1_CLK>;
314	};
315
316	usbhs: usbhs@94000 {
317		compatible = "nxp,lpcip3511";
318		reg = <0x94000 0x1000>;
319		interrupts = <47 1>;
320		num-bidir-endpoints = <6>;
321		status = "disabled";
322	};
323};
324
325&nvic {
326	arm,num-irq-priority-bits = <3>;
327};
328