1/*
2 * Copyright (c) 2022 metraTec
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv8-m.dtsi>
8#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <mem.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			compatible = "arm,cortex-m33f";
19			reg = <0>;
20			#address-cells = <1>;
21			#size-cells = <1>;
22
23			mpu: mpu@e000ed90 {
24				compatible = "arm,armv8m-mpu";
25				reg = <0xe000ed90 0x40>;
26				arm,num-mpu-regions = <8>;
27			};
28		};
29	};
30};
31
32&sram {
33	#address-cells = <1>;
34	#size-cells = <1>;
35
36	/* lpc55_0x Memory configurations:
37	 *
38	 * LPC5502:  RAMX: 16K, SRAM0: 32K
39	 * LPC55x04: RAMX: 16K, SRAM0: 32K, SRAM1: 16K
40	 * LPC55x06: RAMX: 16K, SRAM0: 32K, SRAM1: 16K, SRAM2: 16K, SRAM3: 16k
41	 */
42	sramx: memory@4000000 {
43		compatible = "mmio-sram";
44		reg = <0x04000000 DT_SIZE_K(16)>;
45	};
46	sram0: memory@20000000 {
47		compatible = "mmio-sram";
48		reg = <0x20000000 DT_SIZE_K(32)>;
49	};
50	sram1: memory@20008000 {
51		compatible = "mmio-sram";
52		reg = <0x20008000 DT_SIZE_K(16)>;
53	};
54	sram2: memory@2000C000 {
55		compatible = "mmio-sram";
56		reg = <0x2000C000 DT_SIZE_K(16)>;
57	};
58	sram3: memory@20010000 {
59		compatible = "mmio-sram";
60		reg = <0x20010000 DT_SIZE_K(16)>;
61	};
62};
63
64&peripheral {
65	#address-cells = <1>;
66	#size-cells = <1>;
67
68	syscon: syscon@0 {
69		compatible = "nxp,lpc-syscon";
70		reg = <0x0 0x4000>;
71		#clock-cells = <1>;
72	};
73
74	iap: flash-controller@34000 {
75		compatible = "nxp,iap-fmc55";
76		reg = <0x34000 0x18>;
77		status = "disabled";
78		#address-cells = <1>;
79		#size-cells = <1>;
80
81		flash0: flash@0 {
82			compatible = "soc-nv-flash";
83			reg = <0x0 DT_SIZE_K(246)>;
84			erase-block-size = <512>;
85			write-block-size = <512>;
86		};
87
88		flash_reserved: flash@3d800 {
89			compatible = "soc-nv-flash";
90			reg = <0x0003d800 DT_SIZE_K(10)>;
91			status = "disabled";
92		};
93
94		uuid: flash@9fc70 {
95			compatible = "nxp,lpc-uid";
96			reg = <0x3fc70 0x10>;
97		};
98
99		boot_rom: flash@3000000 {
100			compatible = "soc-nv-flash";
101			reg = <0x3000000 DT_SIZE_K(128)>;
102		};
103	};
104
105	iocon: iocon@1000 {
106		compatible = "nxp,lpc-iocon";
107		reg = <0x1000 0x100>;
108		#address-cells = <1>;
109		#size-cells = <1>;
110		ranges = <0x0 0x1000 0x100>;
111		pinctrl: pinctrl {
112			compatible = "nxp,lpc-iocon-pinctrl";
113		};
114	};
115
116	gpio0: gpio@0 {
117		compatible = "nxp,lpc-gpio";
118		reg = <0x8c000 0x2488>;
119		int-source = "pint";
120		gpio-controller;
121		#gpio-cells = <2>;
122		port = <0>;
123	};
124
125	gpio1: gpio@1 {
126		compatible = "nxp,lpc-gpio";
127		reg = <0x8c000 0x2488>;
128		int-source = "pint";
129		gpio-controller;
130		#gpio-cells = <2>;
131		port = <1>;
132	};
133
134	pint: pint@4000 {
135		compatible = "nxp,pint";
136		reg = <0x4000 0x1000>;
137		interrupt-controller;
138		#interrupt-cells = <1>;
139		#address-cells = <0>;
140		interrupts = <4 2>, <5 2>, <6 2>, <7 2>,
141			<32 2>, <33 2>, <34 2>, <35 2>;
142		num-lines = <8>;
143		num-inputs = <64>;
144	};
145
146	flexcomm0: flexcomm@86000 {
147		compatible = "nxp,lpc-flexcomm";
148		reg = <0x86000 0x1000>;
149		interrupts = <14 0>;
150		clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
151		status = "disabled";
152	};
153
154	flexcomm1: flexcomm@87000 {
155		compatible = "nxp,lpc-flexcomm";
156		reg = <0x87000 0x1000>;
157		interrupts = <15 0>;
158		clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
159		status = "disabled";
160	};
161
162	flexcomm2: flexcomm@88000 {
163		compatible = "nxp,lpc-flexcomm";
164		reg = <0x88000 0x1000>;
165		interrupts = <16 0>;
166		clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
167		status = "disabled";
168	};
169
170	flexcomm3: flexcomm@89000 {
171		compatible = "nxp,lpc-flexcomm";
172		reg = <0x89000 0x1000>;
173		interrupts = <17 0>;
174		clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
175		status = "disabled";
176	};
177
178	flexcomm4: flexcomm@8a000 {
179		compatible = "nxp,lpc-flexcomm";
180		reg = <0x8a000 0x1000>;
181		interrupts = <18 0>;
182		clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
183		status = "disabled";
184	};
185
186	flexcomm5: flexcomm@96000 {
187		compatible = "nxp,lpc-flexcomm";
188		reg = <0x96000 0x1000>;
189		interrupts = <19 0>;
190		clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
191		status = "disabled";
192	};
193
194	flexcomm6: flexcomm@97000 {
195		compatible = "nxp,lpc-flexcomm";
196		reg = <0x97000 0x1000>;
197		interrupts = <20 0>;
198		clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
199		status = "disabled";
200	};
201
202	flexcomm7: flexcomm@98000 {
203		compatible = "nxp,lpc-flexcomm";
204		reg = <0x98000 0x1000>;
205		interrupts = <21 0>;
206		clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
207		status = "disabled";
208	};
209
210	hs_lspi: spi@9f000 {
211		compatible = "nxp,lpc-spi";
212		reg = <0x9f000 0x1000>;
213		interrupts = <59 0>;
214		clocks = <&syscon MCUX_HS_SPI_CLK>;
215		status = "disabled";
216		#address-cells = <1>;
217		#size-cells = <0>;
218	};
219
220	can0: can@9d000 {
221		compatible = "nxp,lpc-mcan";
222		reg = <0x9d000 0x1000>;
223		interrupts = <43 0>, <44 0>;
224		clocks = <&syscon MCUX_MCAN_CLK>;
225		bosch,mram-cfg = <0x0 15 15 8 8 0 15 15>;
226		sample-point = <875>;
227		sample-point-data = <875>;
228		status = "disabled";
229	};
230
231	rng: rng@3a000 {
232		compatible = "nxp,lpc-rng";
233		reg = <0x3a000 0x1000>;
234		status = "okay";
235	};
236};
237
238&nvic {
239	arm,num-irq-priority-bits = <3>;
240};
241