1/* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <freq.h> 9#include <arm64/armv8-a.dtsi> 10#include <zephyr/dt-bindings/clock/imx95_clock.h> 11#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a55"; 25 reg = <0>; 26 }; 27 28 cpu@100 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a55"; 31 reg = <0x100>; 32 }; 33 34 cpu@200 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a55"; 37 reg = <0x200>; 38 }; 39 40 cpu@300 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a55"; 43 reg = <0x300>; 44 }; 45 46 cpu@400 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a55"; 49 reg = <0x400>; 50 }; 51 52 cpu@500 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x500>; 56 }; 57 58 }; 59 60 arch_timer: timer { 61 compatible = "arm,armv8-timer"; 62 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL 63 IRQ_DEFAULT_PRIORITY>, 64 <GIC_PPI 14 IRQ_TYPE_LEVEL 65 IRQ_DEFAULT_PRIORITY>, 66 <GIC_PPI 11 IRQ_TYPE_LEVEL 67 IRQ_DEFAULT_PRIORITY>, 68 <GIC_PPI 10 IRQ_TYPE_LEVEL 69 IRQ_DEFAULT_PRIORITY>; 70 }; 71 72 gic: interrupt-controller@48000000 { 73 compatible = "arm,gic-v3", "arm,gic"; 74 reg = <0x48000000 0x10000>, /* GIC Dist */ 75 <0x48060000 0xc0000>; /* GICR (RD_base + SGI_base) */ 76 interrupt-controller; 77 #interrupt-cells = <4>; 78 status = "okay"; 79 }; 80 81 reserved-memory { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 85 scmi_shmem0: memory@445b1000 { 86 compatible = "arm,scmi-shmem"; 87 reg = <0x445b1000 0x80>; 88 }; 89 }; 90 91 firmware { 92 scmi { 93 compatible = "arm,scmi"; 94 shmem = <&scmi_shmem0>; 95 mboxes = <&mu2 0>; 96 mbox-names = "tx"; 97 98 #address-cells = <1>; 99 #size-cells = <0>; 100 101 scmi_clk: protocol@14 { 102 compatible = "arm,scmi-clock"; 103 reg = <0x14>; 104 #clock-cells = <1>; 105 }; 106 107 scmi_iomuxc: protocol@19 { 108 compatible = "arm,scmi-pinctrl"; 109 reg = <0x19>; 110 111 pinctrl: pinctrl { 112 compatible = "nxp,imx95-pinctrl", "nxp,imx93-pinctrl"; 113 }; 114 }; 115 }; 116 }; 117 118 lpuart3: serial@42570000 { 119 compatible = "nxp,imx-lpuart", "nxp,lpuart"; 120 reg = <0x42570000 DT_SIZE_K(64)>; 121 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 122 interrupt-names = "irq_0"; 123 clocks = <&scmi_clk IMX95_CLK_LPUART3>; 124 status = "disabled"; 125 }; 126 127 lpuart4: serial@42580000 { 128 compatible = "nxp,imx-lpuart", "nxp,lpuart"; 129 reg = <0x42580000 DT_SIZE_K(64)>; 130 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 131 interrupt-names = "irq_0"; 132 clocks = <&scmi_clk IMX95_CLK_LPUART4>; 133 status = "disabled"; 134 }; 135 136 lpuart5: serial@42590000 { 137 compatible = "nxp,imx-lpuart", "nxp,lpuart"; 138 reg = <0x42590000 DT_SIZE_K(64)>; 139 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 140 interrupt-names = "irq_0"; 141 clocks = <&scmi_clk IMX95_CLK_LPUART5>; 142 status = "disabled"; 143 }; 144 145 lpuart6: serial@425a0000 { 146 compatible = "nxp,imx-lpuart", "nxp,lpuart"; 147 reg = <0x425a0000 DT_SIZE_K(64)>; 148 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 149 interrupt-names = "irq_0"; 150 clocks = <&scmi_clk IMX95_CLK_LPUART6>; 151 status = "disabled"; 152 }; 153 154 lpuart7: serial@42690000 { 155 compatible = "nxp,imx-lpuart", "nxp,lpuart"; 156 reg = <0x42690000 DT_SIZE_K(64)>; 157 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 158 interrupt-names = "irq_0"; 159 clocks = <&scmi_clk IMX95_CLK_LPUART7>; 160 status = "disabled"; 161 }; 162 163 lpuart8: serial@426a0000 { 164 compatible = "nxp,imx-lpuart", "nxp,lpuart"; 165 reg = <0x426a0000 DT_SIZE_K(64)>; 166 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 167 interrupt-names = "irq_0"; 168 clocks = <&scmi_clk IMX95_CLK_LPUART8>; 169 status = "disabled"; 170 }; 171 172 mu1: mbox@44220000 { 173 compatible = "nxp,mbox-imx-mu"; 174 reg = <0x44220000 DT_SIZE_K(64)>; 175 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 176 rx-channels = <4>; 177 #mbox-cells = <1>; 178 status = "disabled"; 179 }; 180 181 lpuart1: serial@44380000 { 182 compatible = "nxp,imx-lpuart", "nxp,lpuart"; 183 reg = <0x44380000 DT_SIZE_K(64)>; 184 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 185 interrupt-names = "irq_0"; 186 clocks = <&scmi_clk IMX95_CLK_LPUART1>; 187 status = "disabled"; 188 }; 189 190 lpuart2: serial@44390000 { 191 compatible = "nxp,imx-lpuart", "nxp,lpuart"; 192 reg = <0x44390000 DT_SIZE_K(64)>; 193 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 194 interrupt-names = "irq_0"; 195 clocks = <&scmi_clk IMX95_CLK_LPUART2>; 196 status = "disabled"; 197 }; 198 199 mu2: mbox@445b0000 { 200 compatible = "nxp,mbox-imx-mu"; 201 reg = <0x445b0000 DT_SIZE_K(64)>; 202 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 203 rx-channels = <4>; 204 #mbox-cells = <1>; 205 }; 206 207 mu3: mbox@445d0000 { 208 compatible = "nxp,mbox-imx-mu"; 209 reg = <0x445d0000 DT_SIZE_K(64)>; 210 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 211 rx-channels = <4>; 212 #mbox-cells = <1>; 213 status = "disabled"; 214 }; 215 216 mu4: mbox@445f0000 { 217 compatible = "nxp,mbox-imx-mu"; 218 reg = <0x445f0000 DT_SIZE_K(64)>; 219 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 220 rx-channels = <4>; 221 #mbox-cells = <1>; 222 status = "disabled"; 223 }; 224 225 mu5: mbox@44610000 { 226 compatible = "nxp,mbox-imx-mu"; 227 reg = <0x44610000 DT_SIZE_K(64)>; 228 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 229 rx-channels = <4>; 230 #mbox-cells = <1>; 231 status = "disabled"; 232 }; 233 234 mu6: mbox@44630000 { 235 compatible = "nxp,mbox-imx-mu"; 236 reg = <0x44630000 DT_SIZE_K(64)>; 237 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; 238 rx-channels = <4>; 239 #mbox-cells = <1>; 240 status = "disabled"; 241 }; 242}; 243
