1/* 2 * Copyright (c) 2017, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/i2c/i2c.h> 11#include <mem.h> 12#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h> 13 14/ { 15 aliases{ 16 gpio-0 = &gpio0; 17 gpio-1 = &gpio1; 18 mailbox-0 = &mailbox0; 19 }; 20 21 chosen { 22 zephyr,flash-controller = &iap; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 compatible = "arm,cortex-m4f"; 31 reg = <0>; 32 }; 33 34 cpu1: cpu@1 { 35 compatible = "arm,cortex-m0+"; 36 reg = <1>; 37 }; 38 }; 39 40 soc { 41 syscon: syscon@40000000 { 42 compatible = "nxp,lpc-syscon"; 43 reg = <0x40000000 0x4000>; 44 #clock-cells = <1>; 45 reset: reset { 46 compatible = "nxp,lpc-syscon-reset"; 47 #reset-cells = <1>; 48 }; 49 }; 50 51 /* 52 * lpc54xxx Memory configurations: 53 * (note: reference manual says "up to <n>K") 54 * SRAM0 through SRAM3 will be contiguous 55 * 56 * LPC540xx: RAMX: 192K, SRAM0: 64K, SRAM1: 32K, SRAM2: 32K, SRAM3: 32K, USBRAM: 8K 57 * LPC5410x: RAMX: ----, SRAM0: 64K, SRAM1: 32K, USBRAM: 8K @ 0x03400000 58 * LPC5411x: RAMX: 32K, SRAM0: 64K, SRAM1: 64K, SRAM2: 32K 59 * 60 * SRAM0-SRAM3 will be contiguous memory when present. 61 * 62 * The board level or application level device tree can override the memory sizes 63 * to allocate memory to the different cores of the dual-core platforms. 64 */ 65 sram0:memory@20000000 { 66 compatible = "mmio-sram"; 67 reg = <0x20000000 DT_SIZE_K(64)>; 68 }; 69 70 sram1:memory@20010000 { 71 compatible = "zephyr,memory-region", "mmio-sram"; 72 reg = <0x20010000 DT_SIZE_K(64)>; 73 zephyr,memory-region = "SRAM1"; 74 }; 75 76 sram2:memory@20020000 { 77 compatible = "zephyr,memory-region", "mmio-sram"; 78 reg = <0x20020000 DT_SIZE_K(32)>; 79 zephyr,memory-region = "SRAM2"; 80 }; 81 82 /* 83 * LPC54018: 192K @ 0x04000000 84 * LPC540xx: 192K @ 0x04000000 85 * LPC541xx: 32K @ 0x04000000 86 */ 87 sramx:memory@04000000{ 88 compatible = "mmio-sram"; 89 reg = <0x04000000 DT_SIZE_K(32)>; 90 }; 91 92 iap: flash-controller@4009c000 { 93 compatible = "nxp,iap-fmc54"; 94 reg = <0x4009c000 0x18>; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 status = "disabled"; 98 flash0: flash@0 { 99 compatible = "soc-nv-flash"; 100 reg = <0 DT_SIZE_K(256)>; 101 erase-block-size = <256>; 102 write-block-size = <256>; 103 }; 104 }; 105 106 iocon: iocon@40001000 { 107 compatible = "nxp,lpc-iocon"; 108 reg = <0x40001000 0x100>; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0x0 0x40001000 0x100>; 112 pinctrl: pinctrl { 113 compatible = "nxp,lpc-iocon-pinctrl"; 114 }; 115 }; 116 117 gpio: gpio@4008c000 { 118 compatible = "nxp,lpc-gpio"; 119 reg = <0x4008c000 0x2488>; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 123 gpio0: gpio@0 { 124 compatible = "nxp,lpc-gpio-port"; 125 reg = <0>; 126 int-source = "pint"; 127 gpio-controller; 128 #gpio-cells = <2>; 129 }; 130 131 gpio1: gpio@1 { 132 compatible = "nxp,lpc-gpio-port"; 133 reg = <1>; 134 int-source = "pint"; 135 gpio-controller; 136 #gpio-cells = <2>; 137 }; 138 }; 139 140 pint: pint@40004000 { 141 compatible = "nxp,pint"; 142 reg = <0x40004000 0x1000>; 143 interrupt-controller; 144 #interrupt-cells = <1>; 145 #address-cells = <0>; 146 interrupts = <4 2>, <5 2>, <6 2>, <7 2>, 147 <32 2>, <33 2>, <34 2>, <35 2>; 148 num-lines = <8>; 149 num-inputs = <64>; 150 }; 151 152 mailbox0:mailbox@4008b000 { 153 compatible = "nxp,lpc-mailbox"; 154 reg = <0x4008b000 0xEC>; 155 interrupts = <31 0>; 156 status = "disabled"; 157 }; 158 159 flexcomm0: flexcomm@40086000 { 160 compatible = "nxp,lpc-flexcomm"; 161 reg = <0x40086000 0x1000>; 162 interrupts = <14 0>; 163 clocks = <&syscon MCUX_FLEXCOMM0_CLK>; 164 resets = <&reset NXP_SYSCON_RESET(1, 11)>; 165 status = "disabled"; 166 }; 167 168 flexcomm1: flexcomm@40087000 { 169 compatible = "nxp,lpc-flexcomm"; 170 reg = <0x40087000 0x1000>; 171 interrupts = <15 0>; 172 clocks = <&syscon MCUX_FLEXCOMM1_CLK>; 173 resets = <&reset NXP_SYSCON_RESET(1, 12)>; 174 status = "disabled"; 175 }; 176 177 flexcomm2: flexcomm@40088000 { 178 compatible = "nxp,lpc-flexcomm"; 179 reg = <0x40088000 0x1000>; 180 interrupts = <16 0>; 181 clocks = <&syscon MCUX_FLEXCOMM2_CLK>; 182 resets = <&reset NXP_SYSCON_RESET(1, 13)>; 183 status = "disabled"; 184 }; 185 186 flexcomm3: flexcomm@40089000 { 187 compatible = "nxp,lpc-flexcomm"; 188 reg = <0x40089000 0x1000>; 189 interrupts = <17 0>; 190 clocks = <&syscon MCUX_FLEXCOMM3_CLK>; 191 resets = <&reset NXP_SYSCON_RESET(1, 14)>; 192 status = "disabled"; 193 }; 194 195 flexcomm4: flexcomm@4008a000 { 196 compatible = "nxp,lpc-flexcomm"; 197 reg = <0x4008a000 0x1000>; 198 interrupts = <18 0>; 199 clocks = <&syscon MCUX_FLEXCOMM4_CLK>; 200 resets = <&reset NXP_SYSCON_RESET(1, 15)>; 201 status = "disabled"; 202 }; 203 204 flexcomm5: flexcomm@40096000 { 205 compatible = "nxp,lpc-flexcomm"; 206 reg = <0x40096000 0x1000>; 207 interrupts = <19 0>; 208 clocks = <&syscon MCUX_FLEXCOMM5_CLK>; 209 resets = <&reset NXP_SYSCON_RESET(1, 16)>; 210 status = "disabled"; 211 }; 212 213 flexcomm6: flexcomm@40097000 { 214 compatible = "nxp,lpc-flexcomm"; 215 reg = <0x40097000 0x1000>; 216 interrupts = <20 0>; 217 clocks = <&syscon MCUX_FLEXCOMM6_CLK>; 218 resets = <&reset NXP_SYSCON_RESET(1, 17)>; 219 status = "disabled"; 220 }; 221 222 flexcomm7: flexcomm@40098000 { 223 compatible = "nxp,lpc-flexcomm"; 224 reg = <0x40098000 0x1000>; 225 interrupts = <21 0>; 226 clocks = <&syscon MCUX_FLEXCOMM7_CLK>; 227 resets = <&reset NXP_SYSCON_RESET(1, 18)>; 228 status = "disabled"; 229 }; 230 }; 231}; 232 233&nvic { 234 arm,num-irq-priority-bits = <3>; 235}; 236
