1/* 2 * Copyright (c) 2019 SEAL AG 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <zephyr/dt-bindings/adc/adc.h> 9#include <zephyr/dt-bindings/clock/kinetis_sim.h> 10#include <zephyr/dt-bindings/clock/kinetis_mcg.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13 14/ { 15 chosen { 16 zephyr,flash-controller = &ftfe; 17 }; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-m7"; 26 reg = <0>; 27 }; 28 }; 29 30 /* Dummy pinctrl node, filled with pin mux options at board level */ 31 pinctrl: pinctrl { 32 compatible = "nxp,port-pinctrl"; 33 status = "okay"; 34 }; 35 36 soc { 37 mpu: mpu@4000d000 { 38 compatible = "nxp,sysmpu"; 39 reg = <0x4000d000 0x1000>; 40 status = "disabled"; 41 }; 42 43 sim: sim@40047000 { 44 compatible = "nxp,kinetis-sim"; 45 reg = <0x40047000 0x2000>; 46 #clock-cells = <3>; 47 48 core_clk { 49 compatible = "fixed-factor-clock"; 50 clocks = <&mcg KINETIS_MCG_OUT_CLK>; 51 clock-div = <1>; 52 #clock-cells = <0>; 53 }; 54 55 bus_clk { 56 compatible = "fixed-factor-clock"; 57 clocks = <&mcg KINETIS_MCG_OUT_CLK>; 58 clock-div = <2>; 59 #clock-cells = <0>; 60 }; 61 62 flexbus_clk { 63 compatible = "fixed-factor-clock"; 64 clocks = <&mcg KINETIS_MCG_OUT_CLK>; 65 clock-div = <4>; 66 #clock-cells = <0>; 67 }; 68 69 flash_clk { 70 compatible = "fixed-factor-clock"; 71 clocks = <&mcg KINETIS_MCG_OUT_CLK>; 72 clock-div = <10>; 73 #clock-cells = <0>; 74 }; 75 }; 76 77 mcg: clock-controller@40064000 { 78 compatible = "nxp,kinetis-mcg"; 79 reg = <0x40064000 0x1000>; 80 #clock-cells = <1>; 81 }; 82 83 osc: clock-controller@40065000 { 84 compatible = "nxp,kv58-osc"; 85 reg = <0x40065000 0x4>; 86 enable-external-reference; 87 }; 88 89 ftfe: flash-controller@40020000 { 90 compatible = "nxp,kinetis-ftfe"; 91 reg = <0x40020000 0x1000>; 92 interrupts = <18 0>, <19 0>; 93 interrupt-names = "command-complete", "read-collision"; 94 95 #address-cells = <1>; 96 #size-cells = <1>; 97 }; 98 99 adc0: adc@4003b000 { 100 compatible = "nxp,kinetis-adc16"; 101 reg = <0x4003b000 0x1000>; 102 interrupts = <37 0>; 103 status = "disabled"; 104 #io-channel-cells = <1>; 105 }; 106 107 gpioa: gpio@400ff000 { 108 compatible = "nxp,kinetis-gpio"; 109 status = "disabled"; 110 reg = <0x400ff000 0x40>; 111 interrupts = <59 2>; 112 gpio-controller; 113 #gpio-cells = <2>; 114 nxp,kinetis-port = <&porta>; 115 }; 116 117 gpiob: gpio@400ff040 { 118 compatible = "nxp,kinetis-gpio"; 119 status = "disabled"; 120 reg = <0x400ff040 0x40>; 121 interrupts = <60 2>; 122 gpio-controller; 123 #gpio-cells = <2>; 124 nxp,kinetis-port = <&portb>; 125 }; 126 127 gpioc: gpio@400ff080 { 128 compatible = "nxp,kinetis-gpio"; 129 status = "disabled"; 130 reg = <0x400ff080 0x40>; 131 interrupts = <61 2>; 132 gpio-controller; 133 #gpio-cells = <2>; 134 nxp,kinetis-port = <&portc>; 135 }; 136 137 gpiod: gpio@400ff0c0 { 138 compatible = "nxp,kinetis-gpio"; 139 status = "disabled"; 140 reg = <0x400ff0c0 0x40>; 141 interrupts = <62 2>; 142 gpio-controller; 143 #gpio-cells = <2>; 144 nxp,kinetis-port = <&portd>; 145 }; 146 147 gpioe: gpio@400ff100 { 148 compatible = "nxp,kinetis-gpio"; 149 status = "disabled"; 150 reg = <0x400ff100 0x40>; 151 interrupts = <63 2>; 152 gpio-controller; 153 #gpio-cells = <2>; 154 nxp,kinetis-port = <&porte>; 155 }; 156 157 i2c0: i2c@40066000 { 158 compatible = "nxp,kinetis-i2c"; 159 clock-frequency = <I2C_BITRATE_STANDARD>; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 reg = <0x40066000 0x1000>; 163 interrupts = <24 0>; 164 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>; 165 status = "disabled"; 166 }; 167 168 i2c1: i2c@40067000 { 169 compatible = "nxp,kinetis-i2c"; 170 clock-frequency = <I2C_BITRATE_STANDARD>; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 reg = <0x40067000 0x1000>; 174 interrupts = <25 0>; 175 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>; 176 status = "disabled"; 177 }; 178 179 porta: pinmux@40049000 { 180 compatible = "nxp,port-pinmux"; 181 reg = <0x40049000 0x1000>; 182 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; 183 }; 184 185 portb: pinmux@4004a000 { 186 compatible = "nxp,port-pinmux"; 187 reg = <0x4004a000 0x1000>; 188 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; 189 }; 190 191 portc: pinmux@4004b000 { 192 compatible = "nxp,port-pinmux"; 193 reg = <0x4004b000 0x1000>; 194 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; 195 }; 196 197 portd: pinmux@4004c000 { 198 compatible = "nxp,port-pinmux"; 199 reg = <0x4004c000 0x1000>; 200 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>; 201 }; 202 203 porte: pinmux@4004d000 { 204 compatible = "nxp,port-pinmux"; 205 reg = <0x4004d000 0x1000>; 206 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>; 207 }; 208 209 ftm0: ftm@40038000 { 210 compatible = "nxp,ftm"; 211 reg = <0x40038000 0x1000>; 212 interrupts = <42 0>; 213 prescaler = <16>; 214 status = "disabled"; 215 }; 216 217 ftm1: ftm@40039000 { 218 compatible = "nxp,ftm"; 219 reg = <0x40039000 0x1000>; 220 interrupts = <43 0>; 221 prescaler = <16>; 222 status = "disabled"; 223 }; 224 225 ftm2: ftm@4003a000 { 226 compatible = "nxp,ftm"; 227 reg = <0x4003a000 0x1000>; 228 interrupts = <53 0>; 229 prescaler = <16>; 230 status = "disabled"; 231 }; 232 233 ftm3: ftm@40026000 { 234 compatible = "nxp,ftm"; 235 reg = <0x40026000 0x1000>; 236 interrupts = <71 0>; 237 prescaler = <16>; 238 status = "disabled"; 239 }; 240 241 spi0: spi@4002c000 { 242 compatible = "nxp,dspi"; 243 reg = <0x4002c000 0x1000>; 244 interrupts = <26 3>; 245 status = "disabled"; 246 clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x103c 12>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 }; 250 251 spi1: spi@4002d000 { 252 compatible = "nxp,dspi"; 253 reg = <0x4002d000 0x1000>; 254 interrupts = <27 3>; 255 status = "disabled"; 256 clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x103c 13>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 }; 260 261 spi2: spi@400ac000 { 262 compatible = "nxp,dspi"; 263 reg = <0x400ac000 0x1000>; 264 interrupts = <65 3>; 265 status = "disabled"; 266 clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1030 12>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 }; 270 271 uart0: uart@4006a000 { 272 compatible = "nxp,kinetis-uart"; 273 reg = <0x4006a000 0x1000>; 274 interrupts = <31 0>, <32 0>; 275 interrupt-names = "status", "error"; 276 clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1034 10>; 277 status = "disabled"; 278 }; 279 280 uart1: uart@4006b000 { 281 compatible = "nxp,kinetis-uart"; 282 reg = <0x4006b000 0x1000>; 283 interrupts = <33 0>, <34 0>; 284 interrupt-names = "status", "error"; 285 clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1034 11>; 286 status = "disabled"; 287 }; 288 289 uart2: uart@4006c000 { 290 compatible = "nxp,kinetis-uart"; 291 reg = <0x4006c000 0x1000>; 292 interrupts = <35 0>, <36 0>; 293 interrupt-names = "status", "error"; 294 clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1034 12>; 295 status = "disabled"; 296 }; 297 298 uart3: uart@4006d000 { 299 compatible = "nxp,kinetis-uart"; 300 reg = <0x4006d000 0x1000>; 301 interrupts = <44 0>, <45 0>; 302 interrupt-names = "status", "error"; 303 clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1034 13>; 304 status = "disabled"; 305 }; 306 307 uart4: uart@400ea000 { 308 compatible = "nxp,kinetis-uart"; 309 reg = <0x400ea000 0x1000>; 310 interrupts = <46 0>, <47 0>; 311 interrupt-names = "status", "error"; 312 clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1028 10>; 313 status = "disabled"; 314 }; 315 316 uart5: uart@400eb000 { 317 compatible = "nxp,kinetis-uart"; 318 reg = <0x400eb000 0x1000>; 319 interrupts = <28 0>, <29 0>; 320 interrupt-names = "status", "error"; 321 clocks = <&sim KINETIS_SIM_FAST_PERIPHERAL_CLK 0x1028 11>; 322 status = "disabled"; 323 }; 324 }; 325}; 326 327&nvic { 328 arm,num-irq-priority-bits = <4>; 329}; 330
