1/* SPDX-License-Identifier: Apache-2.0 */ 2 3#include <mem.h> 4#include "armv6-m.dtsi" 5#include <zephyr/dt-bindings/adc/adc.h> 6#include <zephyr/dt-bindings/clock/kinetis_sim.h> 7#include <zephyr/dt-bindings/clock/kinetis_mcg.h> 8#include <zephyr/dt-bindings/gpio/gpio.h> 9#include <zephyr/dt-bindings/i2c/i2c.h> 10 11/ { 12 chosen { 13 zephyr,flash-controller = &ftfa; 14 }; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-m0+"; 23 reg = <0>; 24 }; 25 }; 26 27 sram0: memory@1FFFF000 { 28 compatible = "mmio-sram"; 29 reg = <0x1FFFF000 DT_SIZE_K(16)>; 30 }; 31 32 /* Dummy pinctrl node, filled with pin mux options at board level */ 33 pinctrl: pinctrl { 34 compatible = "nxp,kinetis-pinctrl"; 35 status = "okay"; 36 }; 37 38 soc { 39 ftfa: flash-controller@40020000 { 40 compatible = "nxp,kinetis-ftfa"; 41 reg = <0x40020000 0x14>; 42 interrupts = <5 0>; 43 status = "disabled"; 44 45 #address-cells = <1>; 46 #size-cells = <1>; 47 48 flash0: flash@0 { 49 compatible = "soc-nv-flash"; 50 reg = <0 DT_SIZE_K(128)>; 51 erase-block-size = <1024>; 52 write-block-size = <4>; 53 }; 54 }; 55 56 mcg: clock-controller@40064000 { 57 compatible = "nxp,kinetis-mcg"; 58 reg = <0x40064000 0xd>; 59 #clock-cells = <1>; 60 }; 61 62 i2c0: i2c@40066000 { 63 compatible = "nxp,kinetis-i2c"; 64 clock-frequency = <I2C_BITRATE_STANDARD>; 65 #address-cells = <1>; 66 #size-cells = <0>; 67 reg = <0x40066000 0x1000>; 68 interrupts = <8 0>; 69 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>; 70 status = "disabled"; 71 }; 72 73 i2c1: i2c@40067000 { 74 compatible = "nxp,kinetis-i2c"; 75 clock-frequency = <I2C_BITRATE_STANDARD>; 76 #address-cells = <1>; 77 #size-cells = <0>; 78 reg = <0x40067000 0x1000>; 79 interrupts = <9 0>; 80 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>; 81 status = "disabled"; 82 }; 83 84 sim: sim@40047000 { 85 compatible = "nxp,kinetis-sim"; 86 reg = <0x40047000 0x1060>; 87 #clock-cells = <3>; 88 89 core_clk { 90 compatible = "fixed-factor-clock"; 91 clocks = <&mcg KINETIS_MCG_OUT_CLK>; 92 clock-div = <2>; 93 #clock-cells = <0>; 94 }; 95 96 flash_clk { 97 compatible = "fixed-factor-clock"; 98 clocks = <&mcg KINETIS_MCG_OUT_CLK>; 99 clock-div = <2>; 100 #clock-cells = <0>; 101 }; 102 }; 103 104 uart0: uart@4006a000 { 105 compatible = "nxp,kinetis-lpsci"; 106 reg = <0x4006a000 0xc>; 107 interrupts = <12 0>; 108 clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>; 109 110 status = "disabled"; 111 }; 112 113 adc0: adc@4003b000{ 114 compatible = "nxp,kinetis-adc16"; 115 reg = <0x4003b000 0x70>; 116 interrupts = <15 0>; 117 status = "disabled"; 118 #io-channel-cells = <1>; 119 }; 120 121 porta: pinmux@40049000 { 122 compatible = "nxp,kinetis-pinmux"; 123 reg = <0x40049000 0xd0>; 124 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; 125 }; 126 127 portb: pinmux@4004a000 { 128 compatible = "nxp,kinetis-pinmux"; 129 reg = <0x4004a000 0xd0>; 130 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; 131 }; 132 133 portc: pinmux@4004b000 { 134 compatible = "nxp,kinetis-pinmux"; 135 reg = <0x4004b000 0xd0>; 136 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; 137 }; 138 139 portd: pinmux@4004c000 { 140 compatible = "nxp,kinetis-pinmux"; 141 reg = <0x4004c000 0xd0>; 142 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>; 143 }; 144 145 porte: pinmux@4004d000 { 146 compatible = "nxp,kinetis-pinmux"; 147 reg = <0x4004d000 0xd0>; 148 clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>; 149 }; 150 151 gpioa: gpio@400ff000 { 152 compatible = "nxp,kinetis-gpio"; 153 status = "disabled"; 154 reg = <0x400ff000 0x40>; 155 interrupts = <30 2>; 156 gpio-controller; 157 #gpio-cells = <2>; 158 nxp,kinetis-port = <&porta>; 159 }; 160 161 gpiob: gpio@400ff040 { 162 compatible = "nxp,kinetis-gpio"; 163 status = "disabled"; 164 reg = <0x400ff040 0x40>; 165 gpio-controller; 166 #gpio-cells = <2>; 167 nxp,kinetis-port = <&portb>; 168 }; 169 170 gpioc: gpio@400ff080 { 171 compatible = "nxp,kinetis-gpio"; 172 status = "disabled"; 173 reg = <0x400ff080 0x40>; 174 gpio-controller; 175 #gpio-cells = <2>; 176 nxp,kinetis-port = <&portc>; 177 }; 178 179 gpiod: gpio@400ff0c0 { 180 compatible = "nxp,kinetis-gpio"; 181 status = "disabled"; 182 reg = <0x400ff0c0 0x40>; 183 interrupts = <31 2>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 nxp,kinetis-port = <&portd>; 187 }; 188 189 gpioe: gpio@400ff100 { 190 compatible = "nxp,kinetis-gpio"; 191 status = "disabled"; 192 reg = <0x400ff100 0x40>; 193 gpio-controller; 194 #gpio-cells = <2>; 195 nxp,kinetis-port = <&porte>; 196 }; 197 198 usbotg: usbd@40072000 { 199 compatible = "nxp,kinetis-usbd"; 200 reg = <0x40072000 0x1000>; 201 interrupts = <24 1>; 202 interrupt-names = "usb_otg"; 203 num-bidir-endpoints = <16>; 204 status = "disabled"; 205 }; 206 }; 207}; 208 209&nvic { 210 arm,num-irq-priority-bits = <2>; 211}; 212
