1/* 2 * Copyright (c) 2025 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8.1-m.dtsi> 8#include <mem.h> 9#include <freq.h> 10#include <zephyr/dt-bindings/clock/numaker_m55m1x_clock.h> 11#include <zephyr/dt-bindings/reset/numaker_m55m1x_reset.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13 14/ { 15 chosen { 16 zephyr,flash-controller = &fmc; 17 }; 18 19 aliases { 20 rtc = &rtc; 21 }; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-m55"; 30 reg = <0>; 31 }; 32 }; 33 34 sysclk: system-clock { 35 compatible = "fixed-clock"; 36 clock-frequency = <DT_FREQ_M(220)>; 37 #clock-cells = <0>; 38 }; 39 40 soc { 41 scc: system-clock-controller@40001000 { 42 compatible = "nuvoton,numaker-scc"; 43 reg = <0x40001000 0x100>; 44 #clock-cells = <0>; 45 lxt = "enable"; 46 clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_PCLK0DIV(2) | 47 NUMAKER_CLK_PCLKDIV_PCLK1DIV(2) | 48 NUMAKER_CLK_PCLKDIV_PCLK2DIV(2) | 49 NUMAKER_CLK_PCLKDIV_PCLK3DIV(2) | 50 NUMAKER_CLK_PCLKDIV_PCLK4DIV(2))>; 51 core-clock = <DT_FREQ_M(220)>; 52 powerdown-mode = <NUMAKER_PMC_SPD0>; 53 54 pcc: peripheral-clock-controller { 55 compatible = "nuvoton,numaker-pcc"; 56 #clock-cells = <3>; 57 }; 58 }; 59 60 rst: reset-controller@40000000 { 61 compatible = "nuvoton,numaker-rst"; 62 reg = <0x40000000 0x2e0>; 63 #reset-cells = <1>; 64 }; 65 66 fmc: flash-controller@40044000 { 67 compatible = "nuvoton,numaker-fmc"; 68 reg = <0x40044000 0x120>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 72 flash0: flash@100000 { 73 compatible = "soc-nv-flash"; 74 erase-block-size = <8192>; 75 write-block-size = <4>; 76 }; 77 }; 78 79 uart0: serial@4024d000 { 80 compatible = "nuvoton,numaker-uart"; 81 reg = <0x4024d000 0x1000>; 82 interrupts = <75 0>; 83 resets = <&rst NUMAKER_SYS_UART0RST>; 84 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_UARTSEL0_UART0SEL_HIRC 85 NUMAKER_CLK_UARTDIV0_UART0DIV(1)>; 86 status = "disabled"; 87 }; 88 89 uart1: serial@4028d000 { 90 compatible = "nuvoton,numaker-uart"; 91 reg = <0x4028d000 0x1000>; 92 interrupts = <76 0>; 93 resets = <&rst NUMAKER_SYS_UART1RST>; 94 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_UARTSEL0_UART1SEL_HIRC 95 NUMAKER_CLK_UARTDIV0_UART1DIV(1)>; 96 status = "disabled"; 97 }; 98 99 uart2: serial@4024e000 { 100 compatible = "nuvoton,numaker-uart"; 101 reg = <0x4024e000 0x1000>; 102 interrupts = <77 0>; 103 resets = <&rst NUMAKER_SYS_UART2RST>; 104 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_UARTSEL0_UART2SEL_HIRC 105 NUMAKER_CLK_UARTDIV0_UART2DIV(1)>; 106 status = "disabled"; 107 }; 108 109 uart3: serial@4028e000 { 110 compatible = "nuvoton,numaker-uart"; 111 reg = <0x4028e000 0x1000>; 112 interrupts = <78 0>; 113 resets = <&rst NUMAKER_SYS_UART3RST>; 114 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_UARTSEL0_UART3SEL_HIRC 115 NUMAKER_CLK_UARTDIV0_UART3DIV(1)>; 116 status = "disabled"; 117 }; 118 119 uart4: serial@4024f000 { 120 compatible = "nuvoton,numaker-uart"; 121 reg = <0x4024f000 0x1000>; 122 interrupts = <79 0>; 123 resets = <&rst NUMAKER_SYS_UART4RST>; 124 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_UARTSEL0_UART4SEL_HIRC 125 NUMAKER_CLK_UARTDIV0_UART4DIV(1)>; 126 status = "disabled"; 127 }; 128 129 uart5: serial@4028f000 { 130 compatible = "nuvoton,numaker-uart"; 131 reg = <0x4028f000 0x1000>; 132 interrupts = <80 0>; 133 resets = <&rst NUMAKER_SYS_UART5RST>; 134 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_UARTSEL0_UART5SEL_HIRC 135 NUMAKER_CLK_UARTDIV0_UART5DIV(1)>; 136 status = "disabled"; 137 }; 138 139 uart6: serial@40250000 { 140 compatible = "nuvoton,numaker-uart"; 141 reg = <0x40250000 0x1000>; 142 interrupts = <81 0>; 143 resets = <&rst NUMAKER_SYS_UART6RST>; 144 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_UARTSEL0_UART6SEL_HIRC 145 NUMAKER_CLK_UARTDIV0_UART6DIV(1)>; 146 status = "disabled"; 147 }; 148 149 uart7: serial@40290000 { 150 compatible = "nuvoton,numaker-uart"; 151 reg = <0x40290000 0x1000>; 152 interrupts = <82 0>; 153 resets = <&rst NUMAKER_SYS_UART7RST>; 154 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_UARTSEL0_UART7SEL_HIRC 155 NUMAKER_CLK_UARTDIV0_UART7DIV(1)>; 156 status = "disabled"; 157 }; 158 159 uart8: serial@40251000 { 160 compatible = "nuvoton,numaker-uart"; 161 reg = <0x40251000 0x1000>; 162 interrupts = <83 0>; 163 resets = <&rst NUMAKER_SYS_UART8RST>; 164 clocks = <&pcc NUMAKER_UART8_MODULE NUMAKER_CLK_UARTSEL1_UART8SEL_HIRC 165 NUMAKER_CLK_UARTDIV1_UART8DIV(1)>; 166 status = "disabled"; 167 }; 168 169 uart9: serial@40291000 { 170 compatible = "nuvoton,numaker-uart"; 171 reg = <0x40291000 0x1000>; 172 interrupts = <84 0>; 173 resets = <&rst NUMAKER_SYS_UART9RST>; 174 clocks = <&pcc NUMAKER_UART9_MODULE NUMAKER_CLK_UARTSEL1_UART9SEL_HIRC 175 NUMAKER_CLK_UARTDIV1_UART9DIV(1)>; 176 status = "disabled"; 177 }; 178 179 pinctrl: pin-controller@40000080 { 180 compatible = "nuvoton,numaker-pinctrl"; 181 reg = <0x40000080 0x30 182 0x40000300 0x100>; 183 reg-names = "mfos", "mfp"; 184 }; 185 186 gpioa: gpio@40229000 { 187 compatible = "nuvoton,numaker-gpio"; 188 gpio-controller; 189 #gpio-cells = <2>; 190 reg = <0x40229000 0x40>; 191 clocks = <&pcc NUMAKER_GPIOA_MODULE 0 0>; 192 status = "disabled"; 193 interrupts = <20 2>; 194 }; 195 196 gpiob: gpio@40229040 { 197 compatible = "nuvoton,numaker-gpio"; 198 gpio-controller; 199 #gpio-cells = <2>; 200 reg = <0x40229040 0x40>; 201 clocks = <&pcc NUMAKER_GPIOB_MODULE 0 0>; 202 status = "disabled"; 203 interrupts = <21 2>; 204 }; 205 206 gpioc: gpio@40229080 { 207 compatible = "nuvoton,numaker-gpio"; 208 gpio-controller; 209 #gpio-cells = <2>; 210 reg = <0x40229080 0x40>; 211 clocks = <&pcc NUMAKER_GPIOC_MODULE 0 0>; 212 status = "disabled"; 213 interrupts = <22 2>; 214 }; 215 216 gpiod: gpio@402290c0 { 217 compatible = "nuvoton,numaker-gpio"; 218 gpio-controller; 219 #gpio-cells = <2>; 220 reg = <0x402290c0 0x40>; 221 clocks = <&pcc NUMAKER_GPIOD_MODULE 0 0>; 222 status = "disabled"; 223 interrupts = <23 2>; 224 }; 225 226 gpioe: gpio@40229100 { 227 compatible = "nuvoton,numaker-gpio"; 228 gpio-controller; 229 #gpio-cells = <2>; 230 reg = <0x40229100 0x40>; 231 clocks = <&pcc NUMAKER_GPIOE_MODULE 0 0>; 232 status = "disabled"; 233 interrupts = <24 2>; 234 }; 235 236 gpiof: gpio@40229140 { 237 compatible = "nuvoton,numaker-gpio"; 238 gpio-controller; 239 #gpio-cells = <2>; 240 reg = <0x40229140 0x40>; 241 clocks = <&pcc NUMAKER_GPIOF_MODULE 0 0>; 242 status = "disabled"; 243 interrupts = <25 2>; 244 }; 245 246 gpiog: gpio@40229180 { 247 compatible = "nuvoton,numaker-gpio"; 248 gpio-controller; 249 #gpio-cells = <2>; 250 reg = <0x40229180 0x40>; 251 clocks = <&pcc NUMAKER_GPIOG_MODULE 0 0>; 252 status = "disabled"; 253 interrupts = <26 2>; 254 }; 255 256 gpioh: gpio@402291c0 { 257 compatible = "nuvoton,numaker-gpio"; 258 gpio-controller; 259 #gpio-cells = <2>; 260 reg = <0x402291c0 0x40>; 261 clocks = <&pcc NUMAKER_GPIOH_MODULE 0 0>; 262 status = "disabled"; 263 interrupts = <27 2>; 264 }; 265 266 gpioi: gpio@40229200 { 267 compatible = "nuvoton,numaker-gpio"; 268 gpio-controller; 269 #gpio-cells = <2>; 270 reg = <0x40229200 0x40>; 271 clocks = <&pcc NUMAKER_GPIOI_MODULE 0 0>; 272 status = "disabled"; 273 interrupts = <28 2>; 274 }; 275 276 gpioj: gpio@40229240 { 277 compatible = "nuvoton,numaker-gpio"; 278 gpio-controller; 279 #gpio-cells = <2>; 280 reg = <0x40229240 0x40>; 281 clocks = <&pcc NUMAKER_GPIOJ_MODULE 0 0>; 282 status = "disabled"; 283 interrupts = <29 2>; 284 }; 285 286 rtc: rtc@40297000 { 287 compatible = "nuvoton,numaker-rtc"; 288 reg = <0x40297000 0x1000>; 289 interrupts = <6 0>; 290 oscillator = "lxt"; 291 clocks = <&pcc NUMAKER_RTC0_MODULE 0 0>; 292 alarms-count = <1>; 293 }; 294 }; 295}; 296 297&nvic { 298 arm,num-irq-priority-bits = <3>; 299}; 300
