1/* 2 * Copyright (c) 2024 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv8-m.dtsi> 8#include <mem.h> 9#include <freq.h> 10#include <zephyr/dt-bindings/clock/numaker_m2l31x_clock.h> 11#include <zephyr/dt-bindings/reset/numaker_m2l31x_reset.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13#include <zephyr/dt-bindings/i2c/i2c.h> 14#include <zephyr/dt-bindings/adc/adc.h> 15 16/ { 17 chosen { 18 zephyr,flash-controller = &rmc; 19 }; 20 21 aliases { 22 rtc = &rtc; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-m23"; 32 reg = <0>; 33 }; 34 }; 35 36 sysclk: system-clock { 37 compatible = "fixed-clock"; 38 clock-frequency = <DT_FREQ_M(72)>; 39 #clock-cells = <0>; 40 }; 41 42 soc { 43 scc: system-clock-controller@40000200 { 44 compatible = "nuvoton,numaker-scc"; 45 reg = <0x40000200 0x100>; 46 #clock-cells = <0>; 47 lxt = "enable"; 48 clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | 49 NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; 50 core-clock = <DT_FREQ_M(72)>; 51 52 pcc: peripheral-clock-controller { 53 compatible = "nuvoton,numaker-pcc"; 54 #clock-cells = <3>; 55 }; 56 }; 57 58 rst: reset-controller@40000000 { 59 compatible = "nuvoton,numaker-rst"; 60 reg = <0x40000000 0x20>; 61 #reset-cells = <1>; 62 }; 63 64 rmc: flash-controller@4000c000 { 65 compatible = "nuvoton,numaker-rmc"; 66 reg = <0x4000c000 0x1000>; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 70 flash0: flash@0 { 71 compatible = "soc-nv-flash"; 72 erase-block-size = <4096>; 73 write-block-size = <4>; 74 }; 75 }; 76 77 uart0: serial@40070000 { 78 compatible = "nuvoton,numaker-uart"; 79 reg = <0x40070000 0x1000>; 80 interrupts = <36 0>; 81 resets = <&rst NUMAKER_UART0_RST>; 82 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL4_UART0SEL_HIRC 83 NUMAKER_CLK_CLKDIV0_UART0(1)>; 84 status = "disabled"; 85 }; 86 87 uart1: serial@40071000 { 88 compatible = "nuvoton,numaker-uart"; 89 reg = <0x40071000 0x1000>; 90 interrupts = <37 0>; 91 resets = <&rst NUMAKER_UART1_RST>; 92 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL4_UART1SEL_HIRC 93 NUMAKER_CLK_CLKDIV0_UART1(1)>; 94 status = "disabled"; 95 }; 96 97 uart2: serial@40072000 { 98 compatible = "nuvoton,numaker-uart"; 99 reg = <0x40072000 0x1000>; 100 interrupts = <48 0>; 101 resets = <&rst NUMAKER_UART2_RST>; 102 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL4_UART2SEL_HIRC 103 NUMAKER_CLK_CLKDIV4_UART2(1)>; 104 status = "disabled"; 105 }; 106 107 uart3: serial@40073000 { 108 compatible = "nuvoton,numaker-uart"; 109 reg = <0x40073000 0x1000>; 110 interrupts = <49 0>; 111 resets = <&rst NUMAKER_UART3_RST>; 112 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL4_UART3SEL_HIRC 113 NUMAKER_CLK_CLKDIV4_UART3(1)>; 114 status = "disabled"; 115 }; 116 117 uart4: serial@40074000 { 118 compatible = "nuvoton,numaker-uart"; 119 reg = <0x40074000 0x1000>; 120 interrupts = <74 0>; 121 resets = <&rst NUMAKER_UART4_RST>; 122 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL4_UART4SEL_HIRC 123 NUMAKER_CLK_CLKDIV4_UART4(1)>; 124 status = "disabled"; 125 }; 126 127 uart5: serial@40075000 { 128 compatible = "nuvoton,numaker-uart"; 129 reg = <0x40075000 0x1000>; 130 interrupts = <75 0>; 131 resets = <&rst NUMAKER_UART5_RST>; 132 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL4_UART5SEL_HIRC 133 NUMAKER_CLK_CLKDIV4_UART5(1)>; 134 status = "disabled"; 135 }; 136 137 uart6: serial@40076000 { 138 compatible = "nuvoton,numaker-uart"; 139 reg = <0x40076000 0x1000>; 140 interrupts = <102 0>; 141 resets = <&rst NUMAKER_UART6_RST>; 142 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL4_UART6SEL_HIRC 143 NUMAKER_CLK_CLKDIV4_UART6(1)>; 144 status = "disabled"; 145 }; 146 147 uart7: serial@40077000 { 148 compatible = "nuvoton,numaker-uart"; 149 reg = <0x40077000 0x1000>; 150 interrupts = <103 0>; 151 resets = <&rst NUMAKER_UART7_RST>; 152 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL4_UART7SEL_HIRC 153 NUMAKER_CLK_CLKDIV4_UART7(1)>; 154 status = "disabled"; 155 }; 156 157 pinctrl: pin-controller@40000080 { 158 compatible = "nuvoton,numaker-pinctrl"; 159 reg = <0x40000080 0x20 160 0x40000500 0x80>; 161 reg-names = "mfos", "mfp"; 162 }; 163 164 gpioa: gpio@40004000 { 165 compatible = "nuvoton,numaker-gpio"; 166 gpio-controller; 167 #gpio-cells = <2>; 168 reg = <0x40004000 0x40>; 169 clocks = <&pcc NUMAKER_GPA_MODULE 0 0>; 170 status = "disabled"; 171 interrupts = <16 2>; 172 }; 173 174 gpiob: gpio@40004040 { 175 compatible = "nuvoton,numaker-gpio"; 176 gpio-controller; 177 #gpio-cells = <2>; 178 reg = <0x40004040 0x40>; 179 clocks = <&pcc NUMAKER_GPB_MODULE 0 0>; 180 status = "disabled"; 181 interrupts = <17 2>; 182 }; 183 184 gpioc: gpio@40004080 { 185 compatible = "nuvoton,numaker-gpio"; 186 gpio-controller; 187 #gpio-cells = <2>; 188 reg = <0x40004080 0x40>; 189 clocks = <&pcc NUMAKER_GPC_MODULE 0 0>; 190 status = "disabled"; 191 interrupts = <18 2>; 192 }; 193 194 gpiod: gpio@400040c0 { 195 compatible = "nuvoton,numaker-gpio"; 196 gpio-controller; 197 #gpio-cells = <2>; 198 reg = <0x400040c0 0x40>; 199 clocks = <&pcc NUMAKER_GPD_MODULE 0 0>; 200 status = "disabled"; 201 interrupts = <19 2>; 202 }; 203 204 gpioe: gpio@40004100 { 205 compatible = "nuvoton,numaker-gpio"; 206 gpio-controller; 207 #gpio-cells = <2>; 208 reg = <0x40004100 0x40>; 209 clocks = <&pcc NUMAKER_GPE_MODULE 0 0>; 210 status = "disabled"; 211 interrupts = <20 2>; 212 }; 213 214 gpiof: gpio@40004140 { 215 compatible = "nuvoton,numaker-gpio"; 216 gpio-controller; 217 #gpio-cells = <2>; 218 reg = <0x40004140 0x40>; 219 clocks = <&pcc NUMAKER_GPF_MODULE 0 0>; 220 status = "disabled"; 221 interrupts = <21 2>; 222 }; 223 224 spi0: spi@40061000 { 225 compatible = "nuvoton,numaker-spi"; 226 reg = <0x40061000 0x6c>; 227 interrupts = <23 0>; 228 resets = <&rst NUMAKER_SPI0_RST>; 229 clocks = <&pcc NUMAKER_SPI0_MODULE NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC 0>; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 status = "disabled"; 233 }; 234 235 spi1: spi@40062000 { 236 compatible = "nuvoton,numaker-spi"; 237 reg = <0x40062000 0x6c>; 238 interrupts = <51 0>; 239 resets = <&rst NUMAKER_SPI1_RST>; 240 clocks = <&pcc NUMAKER_SPI1_MODULE NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC 0>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 status = "disabled"; 244 }; 245 246 spi2: spi@40063000 { 247 compatible = "nuvoton,numaker-spi"; 248 reg = <0x40063000 0x6c>; 249 interrupts = <52 0>; 250 resets = <&rst NUMAKER_SPI2_RST>; 251 clocks = <&pcc NUMAKER_SPI2_MODULE NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC 0>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 status = "disabled"; 255 }; 256 257 spi3: spi@40064000 { 258 compatible = "nuvoton,numaker-spi"; 259 reg = <0x40064000 0x6c>; 260 interrupts = <62 0>; 261 resets = <&rst NUMAKER_SPI3_RST>; 262 clocks = <&pcc NUMAKER_SPI3_MODULE NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC 0>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 status = "disabled"; 266 }; 267 268 i2c0: i2c@40080000 { 269 compatible = "nuvoton,numaker-i2c"; 270 clock-frequency = <I2C_BITRATE_STANDARD>; 271 reg = <0x40080000 0x1000>; 272 interrupts = <38 0>; 273 resets = <&rst NUMAKER_I2C0_RST>; 274 clocks = <&pcc NUMAKER_I2C0_MODULE 0 0>; 275 status = "disabled"; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 }; 279 280 i2c1: i2c@40081000 { 281 compatible = "nuvoton,numaker-i2c"; 282 clock-frequency = <I2C_BITRATE_STANDARD>; 283 reg = <0x40081000 0x1000>; 284 interrupts = <39 0>; 285 resets = <&rst NUMAKER_I2C1_RST>; 286 clocks = <&pcc NUMAKER_I2C1_MODULE 0 0>; 287 status = "disabled"; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 }; 291 292 i2c2: i2c@40082000 { 293 compatible = "nuvoton,numaker-i2c"; 294 clock-frequency = <I2C_BITRATE_STANDARD>; 295 reg = <0x40082000 0x1000>; 296 interrupts = <82 0>; 297 resets = <&rst NUMAKER_I2C2_RST>; 298 clocks = <&pcc NUMAKER_I2C2_MODULE 0 0>; 299 status = "disabled"; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 }; 303 304 i2c3: i2c@40083000 { 305 compatible = "nuvoton,numaker-i2c"; 306 clock-frequency = <I2C_BITRATE_STANDARD>; 307 reg = <0x40083000 0x1000>; 308 interrupts = <83 0>; 309 resets = <&rst NUMAKER_I2C3_RST>; 310 clocks = <&pcc NUMAKER_I2C3_MODULE 0 0>; 311 status = "disabled"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 }; 315 316 eadc0: eadc@40043000 { 317 compatible = "nuvoton,numaker-adc"; 318 reg = <0x40043000 0xffc>; 319 interrupts = <42 0>; 320 resets = <&rst NUMAKER_EADC0_RST>; 321 clocks = <&pcc NUMAKER_EADC0_MODULE 322 NUMAKER_CLK_CLKSEL0_EADC0SEL_HCLK 323 NUMAKER_CLK_CLKDIV0_EADC0(2)>; 324 channels = <31>; 325 status = "disabled"; 326 #io-channel-cells = <1>; 327 }; 328 329 rtc: rtc@40041000 { 330 compatible = "nuvoton,numaker-rtc"; 331 reg = <0x40041000 0x138>; 332 interrupts = <6 0>; 333 oscillator = "lxt"; 334 clocks = <&pcc NUMAKER_RTC_MODULE 0 0>; 335 alarms-count = <1>; 336 }; 337 338 epwm0: epwm@40058000 { 339 compatible = "nuvoton,numaker-pwm"; 340 reg = <0x40058000 0x37c>; 341 interrupts = <25 0>, <26 0>, <27 0>; 342 interrupt-names = "pair0", "pair1", "pair2"; 343 resets = <&rst NUMAKER_EPWM0_RST>; 344 prescaler = <19>; 345 clocks = <&pcc NUMAKER_EPWM0_MODULE NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0 0>; 346 #pwm-cells = <3>; 347 status = "disabled"; 348 }; 349 350 epwm1: epwm@40059000 { 351 compatible = "nuvoton,numaker-pwm"; 352 reg = <0x40059000 0x37c>; 353 interrupts = <29 0>, <30 0>, <31 0>; 354 interrupt-names = "pair0", "pair1", "pair2"; 355 resets = <&rst NUMAKER_EPWM1_RST>; 356 prescaler = <19>; 357 clocks = <&pcc NUMAKER_EPWM1_MODULE NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1 0>; 358 #pwm-cells = <3>; 359 status = "disabled"; 360 }; 361 362 canfd0: canfd@40020000 { 363 compatible = "nuvoton,numaker-canfd"; 364 reg = <0x40020000 0x200>, <0x40020200 0x1800>; 365 reg-names = "m_can", "message_ram"; 366 interrupts = <112 0>, <113 0>; 367 interrupt-names = "int0", "int1"; 368 resets = <&rst NUMAKER_CANFD0_RST>; 369 clocks = <&pcc NUMAKER_CANFD0_MODULE 370 NUMAKER_CLK_CLKSEL0_CANFD0SEL_HCLK 371 NUMAKER_CLK_CLKDIV5_CANFD0(1)>; 372 bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; 373 status = "disabled"; 374 }; 375 376 canfd1: canfd@40024000 { 377 compatible = "nuvoton,numaker-canfd"; 378 reg = <0x40024000 0x200>, <0x40024200 0x1800>; 379 reg-names = "m_can", "message_ram"; 380 interrupts = <114 0>, <115 0>; 381 interrupt-names = "int0", "int1"; 382 resets = <&rst NUMAKER_CANFD1_RST>; 383 clocks = <&pcc NUMAKER_CANFD1_MODULE 384 NUMAKER_CLK_CLKSEL0_CANFD1SEL_HCLK 385 NUMAKER_CLK_CLKDIV5_CANFD1(1)>; 386 bosch,mram-cfg = <0x0 12 10 3 3 3 3 3>; 387 status = "disabled"; 388 }; 389 390 wwdt: watchdog@40096000 { 391 compatible = "nuvoton,numaker-wwdt"; 392 reg = <0x40096000 0x10>; 393 interrupts = <9 0>; 394 clocks = <&pcc NUMAKER_WWDT_MODULE NUMAKER_CLK_CLKSEL1_WWDTSEL_LIRC 0>; 395 status = "disabled"; 396 }; 397 398 tcpc0: utcpd@400c6000 { 399 compatible = "nuvoton,numaker-tcpc"; 400 reg = <0x400c6000 0x1000>, 401 <0x40043000 0x1000>, 402 <0x40050000 0x1000>; 403 reg-names = "utcpd", "eadc", "timer"; 404 interrupts = <108 0>; 405 interrupt-names = "utcpd"; 406 resets = <&rst NUMAKER_UTCPD0_RST>, 407 <&rst NUMAKER_TMR0_RST>; 408 reset-names = "utcpd", "timer"; 409 clocks = <&pcc NUMAKER_UTCPD0_MODULE 0 0>, 410 <&pcc NUMAKER_TMR0_MODULE NUMAKER_CLK_CLKSEL1_TMR0SEL_HIRC 0>; 411 clock-names = "utcpd", "timer"; 412 status = "disabled"; 413 414 vbus0: vbus0 { 415 compatible = "nuvoton,numaker-vbus"; 416 status = "disabled"; 417 }; 418 419 ppc0: ppc0 { 420 compatible = "nuvoton,numaker-ppc"; 421 status = "disabled"; 422 }; 423 }; 424 }; 425}; 426 427&nvic { 428 arm,num-irq-priority-bits = <2>; 429}; 430
