1 /* 2 * Copyright (c) 2023 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef NATIVE_SIMULATOR_NATIVE_SRC_NSI_CPU0_INTERRUPTS_H 7 #define NATIVE_SIMULATOR_NATIVE_SRC_NSI_CPU0_INTERRUPTS_H 8 9 #define TIMER_TICK_IRQ 0 10 #define OFFLOAD_SW_IRQ 1 11 #define COUNTER_EVENT_IRQ 2 12 13 /* 14 * This interrupt will awake the CPU if IRQs are not locked, 15 * This interrupt does not have an associated status bit or handler 16 */ 17 #define PHONY_WEAK_IRQ 0xFFFE 18 /* 19 * This interrupt will awake the CPU even if IRQs are locked, 20 * This interrupt does not have an associated status bit or handler 21 * (the lock is only ignored when the interrupt is raised from the HW models, 22 * SW threads should not try to use this) 23 */ 24 #define PHONY_HARD_IRQ 0xFFFF 25 26 27 #endif /* NATIVE_SIMULATOR_NATIVE_SRC_NSI_CPU0_INTERRUPTS_H */ 28
