1/* 2 * Copyright (c) 2024 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6#include <zephyr/dt-bindings/memory-attr/memory-attr.h> 7 8/ { 9 reserved-memory { 10 /* The first 64kb are reserved for SecDom. 11 * The next 4kb are reserved for IPC between SecDom and Cellcore. 12 */ 13 14 cpurad_ram0x_region: memory@2f011000 { 15 compatible = "nordic,owned-memory"; 16 reg = <0x2f011000 DT_SIZE_K(4)>; 17 status = "disabled"; 18 nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RWS>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x0 0x2f011000 0x1000>; 22 23 cpusec_cpurad_ipc_shm: memory@0 { 24 reg = <0x0 DT_SIZE_K(2)>; 25 }; 26 27 cpurad_cpusec_ipc_shm: memory@800 { 28 reg = <0x800 DT_SIZE_K(2)>; 29 }; 30 }; 31 32 cpuapp_ram0x_region: memory@2f012000 { 33 compatible = "nordic,owned-memory"; 34 reg = <0x2f012000 DT_SIZE_K(516)>; 35 status = "disabled"; 36 nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>; 37 #address-cells = <1>; 38 #size-cells = <1>; 39 ranges = <0x0 0x2f012000 0x81000>; 40 41 cpusec_cpuapp_ipc_shm: memory@0 { 42 reg = <0x0 DT_SIZE_K(2)>; 43 }; 44 45 cpuapp_cpusec_ipc_shm: memory@800 { 46 reg = <0x800 DT_SIZE_K(2)>; 47 }; 48 49 cpuapp_data: memory@1000 { 50 reg = <0x1000 DT_SIZE_K(512)>; 51 }; 52 }; 53 54 cpuapp_cpurad_ram0x_region: memory@2f0cf000 { 55 compatible = "nordic,owned-memory"; 56 reg = <0x2f0cf000 DT_SIZE_K(4)>; 57 status = "disabled"; 58 nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>, 59 <NRF_OWNER_ID_RADIOCORE NRF_PERM_RW>; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges = <0x0 0x2f0cf000 0x1000>; 63 64 cpuapp_cpurad_ipc_shm: memory@0 { 65 reg = <0x0 DT_SIZE_K(2)>; 66 }; 67 68 cpurad_cpuapp_ipc_shm: memory@800 { 69 reg = <0x800 DT_SIZE_K(2)>; 70 }; 71 }; 72 73 cpuapp_cpucell_ram0x_region: memory@2f0d0000 { 74 compatible = "nordic,owned-memory"; 75 reg = <0x2f0d0000 DT_SIZE_K(36)>; 76 status = "disabled"; 77 nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>, 78 <NRF_OWNER_ID_CELL NRF_PERM_RW>; 79 #address-cells = <1>; 80 #size-cells = <1>; 81 ranges = <0x0 0x2f0d0000 0x9000>; 82 83 /* Control region, with ICmsg buffers. 84 * Size is fixed. 85 */ 86 cpuapp_cpucell_ipc_shm_ctrl: memory@0 { 87 reg = <0x0 0x1000>; 88 }; 89 90 /* TX heap, user defined */ 91 cpuapp_cpucell_ipc_shm_heap: memory@1000 { 92 reg = <0x1000 0x4000>; 93 }; 94 95 /* RX heap, user defined */ 96 cpucell_cpuapp_ipc_shm_heap: memory@5000 { 97 reg = <0x5000 0x4000>; 98 }; 99 }; 100 101 cpuapp_cpusys_ipc_shm: memory@2f88fce0 { 102 reg = <0x2f88fce0 0x80>; 103 }; 104 105 cpusys_cpuapp_ipc_shm: memory@2f88fd60 { 106 reg = <0x2f88fd60 0x80>; 107 }; 108 109 cpurad_cpusys_ipc_shm: memory@2f88fe00 { 110 reg = <0x2f88fe00 0x80>; 111 }; 112 113 cpusys_cpurad_ipc_shm: memory@2f88fe80 { 114 reg = <0x2f88fe80 0x80>; 115 }; 116 117 ram21_region: memory@2f890000 { 118 compatible = "nordic,owned-memory"; 119 status = "disabled"; 120 reg = <0x2f890000 DT_SIZE_K(32)>; 121 nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 ranges = <0x0 0x2f890000 0x8000>; 125 126 dma_fast_region: memory@4000 { 127 compatible = "zephyr,memory-region"; 128 reg = <0x4000 DT_SIZE_K(16)>; 129 status = "disabled"; 130 #memory-region-cells = <0>; 131 zephyr,memory-region = "DMA_RAM21"; 132 zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>; 133 }; 134 }; 135 136 cpuppr_ram3x_region: memory@2fc00000 { 137 compatible = "nordic,owned-memory"; 138 reg = <0x2fc00000 DT_SIZE_K(24)>; 139 status = "disabled"; 140 nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWX>; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 ranges = <0x0 0x2fc00000 0x6000>; 144 145 cpuppr_code_data: memory@0 { 146 reg = <0x0 DT_SIZE_K(22)>; 147 }; 148 149 cpuapp_cpuppr_ipc_shm: memory@5800 { 150 reg = <0x5800 DT_SIZE_K(1)>; 151 }; 152 153 cpuppr_cpuapp_ipc_shm: memory@5c00 { 154 reg = <0x5c00 DT_SIZE_K(1)>; 155 }; 156 }; 157 158 cpuapp_dma_region: memory@2fc06000 { 159 compatible = "nordic,owned-memory", "zephyr,memory-region"; 160 reg = <0x2fc06000 DT_SIZE_K(4)>; 161 status = "disabled"; 162 #memory-region-cells = <0>; 163 nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>; 164 zephyr,memory-region = "DMA_RAM3x_APP"; 165 zephyr,memory-attr = <( DT_MEM_DMA )>; 166 }; 167 168 cpurad_dma_region: memory@2fc07000 { 169 compatible = "nordic,owned-memory", "zephyr,memory-region"; 170 reg = <0x2fc07000 DT_SIZE_K(1)>; 171 status = "disabled"; 172 #memory-region-cells = <0>; 173 nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RW>; 174 zephyr,memory-region = "DMA_RAM3x_RAD"; 175 zephyr,memory-attr = <( DT_MEM_DMA )>; 176 }; 177 }; 178}; 179 180&mram1x { 181 cpurad_rx_partitions: cpurad-rx-partitions { 182 compatible = "nordic,owned-partitions", "fixed-partitions"; 183 status = "disabled"; 184 nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RXS>; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 188 cpurad_slot0_partition: partition@402000 { 189 reg = <0x402000 DT_SIZE_K(256)>; 190 }; 191 }; 192 193 cpuapp_rx_partitions: cpuapp-rx-partitions { 194 compatible = "nordic,owned-partitions", "fixed-partitions"; 195 status = "disabled"; 196 nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 200 cpuapp_slot0_partition: partition@442000 { 201 reg = <0x442000 DT_SIZE_K(1024)>; 202 }; 203 204 cpuppr_code_partition: partition@542000 { 205 reg = <0x542000 DT_SIZE_K(64)>; 206 }; 207 }; 208 209 cpuapp_rw_partitions: cpuapp-rw-partitions { 210 compatible = "nordic,owned-partitions", "fixed-partitions"; 211 status = "disabled"; 212 nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>; 213 #address-cells = <1>; 214 #size-cells = <1>; 215 216 dfu_partition: partition@600000 { 217 reg = <0x600000 DT_SIZE_K(512)>; 218 }; 219 220 storage_partition: partition@680000 { 221 reg = <0x680000 DT_SIZE_K(24)>; 222 }; 223 }; 224}; 225
