1 /* 2 3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef __NRF9160_BITS_H 36 #define __NRF9160_BITS_H 37 38 /*lint ++flb "Enter library region" */ 39 40 /* Peripheral: ATBFUNNEL */ 41 /* Description: ATB funnel module 0 */ 42 43 /* Register: ATBFUNNEL_CTRLREG */ 44 /* Description: The IDFILTER0 register enables the programming of ID filtering for master port 0. */ 45 46 /* Bits 11..8 : Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you can use this setting to minimize switching. 47 When a source has nothing to transmit, then another source is selected irrespective of the minimum number of transactions. 48 The ATB funnel holds for the minimum hold time and one additional transaction. The actual hold time is the register value plus 1. 49 The maximum value that can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved. */ 50 #define ATBFUNNEL_CTRLREG_HT_Pos (8UL) /*!< Position of HT field. */ 51 #define ATBFUNNEL_CTRLREG_HT_Msk (0xFUL << ATBFUNNEL_CTRLREG_HT_Pos) /*!< Bit mask of HT field. */ 52 53 /* Bit 7 : Enable slave port 7. */ 54 #define ATBFUNNEL_CTRLREG_ENS_7_Pos (7UL) /*!< Position of ENS_7 field. */ 55 #define ATBFUNNEL_CTRLREG_ENS_7_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_7_Pos) /*!< Bit mask of ENS_7 field. */ 56 #define ATBFUNNEL_CTRLREG_ENS_7_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */ 57 #define ATBFUNNEL_CTRLREG_ENS_7_Enabled (0x1UL) /*!< Slave port enabled. */ 58 59 /* Bit 6 : Enable slave port 6. */ 60 #define ATBFUNNEL_CTRLREG_ENS_6_Pos (6UL) /*!< Position of ENS_6 field. */ 61 #define ATBFUNNEL_CTRLREG_ENS_6_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_6_Pos) /*!< Bit mask of ENS_6 field. */ 62 #define ATBFUNNEL_CTRLREG_ENS_6_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */ 63 #define ATBFUNNEL_CTRLREG_ENS_6_Enabled (0x1UL) /*!< Slave port enabled. */ 64 65 /* Bit 5 : Enable slave port 5. */ 66 #define ATBFUNNEL_CTRLREG_ENS_5_Pos (5UL) /*!< Position of ENS_5 field. */ 67 #define ATBFUNNEL_CTRLREG_ENS_5_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_5_Pos) /*!< Bit mask of ENS_5 field. */ 68 #define ATBFUNNEL_CTRLREG_ENS_5_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */ 69 #define ATBFUNNEL_CTRLREG_ENS_5_Enabled (0x1UL) /*!< Slave port enabled. */ 70 71 /* Bit 4 : Enable slave port 4. */ 72 #define ATBFUNNEL_CTRLREG_ENS_4_Pos (4UL) /*!< Position of ENS_4 field. */ 73 #define ATBFUNNEL_CTRLREG_ENS_4_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_4_Pos) /*!< Bit mask of ENS_4 field. */ 74 #define ATBFUNNEL_CTRLREG_ENS_4_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */ 75 #define ATBFUNNEL_CTRLREG_ENS_4_Enabled (0x1UL) /*!< Slave port enabled. */ 76 77 /* Bit 3 : Enable slave port 3. */ 78 #define ATBFUNNEL_CTRLREG_ENS_3_Pos (3UL) /*!< Position of ENS_3 field. */ 79 #define ATBFUNNEL_CTRLREG_ENS_3_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_3_Pos) /*!< Bit mask of ENS_3 field. */ 80 #define ATBFUNNEL_CTRLREG_ENS_3_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */ 81 #define ATBFUNNEL_CTRLREG_ENS_3_Enabled (0x1UL) /*!< Slave port enabled. */ 82 83 /* Bit 2 : Enable slave port 2. */ 84 #define ATBFUNNEL_CTRLREG_ENS_2_Pos (2UL) /*!< Position of ENS_2 field. */ 85 #define ATBFUNNEL_CTRLREG_ENS_2_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_2_Pos) /*!< Bit mask of ENS_2 field. */ 86 #define ATBFUNNEL_CTRLREG_ENS_2_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */ 87 #define ATBFUNNEL_CTRLREG_ENS_2_Enabled (0x1UL) /*!< Slave port enabled. */ 88 89 /* Bit 1 : Enable slave port 1. */ 90 #define ATBFUNNEL_CTRLREG_ENS_1_Pos (1UL) /*!< Position of ENS_1 field. */ 91 #define ATBFUNNEL_CTRLREG_ENS_1_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_1_Pos) /*!< Bit mask of ENS_1 field. */ 92 #define ATBFUNNEL_CTRLREG_ENS_1_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */ 93 #define ATBFUNNEL_CTRLREG_ENS_1_Enabled (0x1UL) /*!< Slave port enabled. */ 94 95 /* Bit 0 : Enable slave port 0. */ 96 #define ATBFUNNEL_CTRLREG_ENS_0_Pos (0UL) /*!< Position of ENS_0 field. */ 97 #define ATBFUNNEL_CTRLREG_ENS_0_Msk (0x1UL << ATBFUNNEL_CTRLREG_ENS_0_Pos) /*!< Bit mask of ENS_0 field. */ 98 #define ATBFUNNEL_CTRLREG_ENS_0_Disabled (0x0UL) /*!< Slave port disabled. This excludes the port from the priority selection scheme. */ 99 #define ATBFUNNEL_CTRLREG_ENS_0_Enabled (0x1UL) /*!< Slave port enabled. */ 100 101 /* Register: ATBFUNNEL_PRIORITYCTRLREG */ 102 /* Description: The Priority_Ctrl_Reg register defines the order in which inputs are selected. Each 3-bit field is a priority for each particular slave interface. */ 103 104 /* Bits 23..21 : Priority value of port number 7. */ 105 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Pos (21UL) /*!< Position of PRIPORT7 field. */ 106 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT7_Pos) /*!< Bit mask of PRIPORT7 field. */ 107 108 /* Bits 20..18 : Priority value of port number 6. */ 109 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Pos (18UL) /*!< Position of PRIPORT6 field. */ 110 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT6_Pos) /*!< Bit mask of PRIPORT6 field. */ 111 112 /* Bits 17..15 : Priority value of port number 5. */ 113 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Pos (15UL) /*!< Position of PRIPORT5 field. */ 114 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT5_Pos) /*!< Bit mask of PRIPORT5 field. */ 115 116 /* Bits 14..12 : Priority value of port number 4. */ 117 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Pos (12UL) /*!< Position of PRIPORT4 field. */ 118 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT4_Pos) /*!< Bit mask of PRIPORT4 field. */ 119 120 /* Bits 11..9 : Priority value of port number 3. */ 121 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Pos (9UL) /*!< Position of PRIPORT3 field. */ 122 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT3_Pos) /*!< Bit mask of PRIPORT3 field. */ 123 124 /* Bits 8..6 : Priority value of port number 2. */ 125 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Pos (6UL) /*!< Position of PRIPORT2 field. */ 126 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT2_Pos) /*!< Bit mask of PRIPORT2 field. */ 127 128 /* Bits 5..3 : Priority value of port number 1. */ 129 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Pos (3UL) /*!< Position of PRIPORT1 field. */ 130 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT1_Pos) /*!< Bit mask of PRIPORT1 field. */ 131 132 /* Bits 2..0 : Priority value of port number 0. */ 133 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Pos (0UL) /*!< Position of PRIPORT0 field. */ 134 #define ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Msk (0x7UL << ATBFUNNEL_PRIORITYCTRLREG_PRIPORT0_Pos) /*!< Bit mask of PRIPORT0 field. */ 135 136 /* Register: ATBFUNNEL_ITATBDATA0 */ 137 /* Description: The ITATBDATA0 register performs different functions depending on whether the access is a read or a write. */ 138 139 /* Bit 16 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 140 #define ATBFUNNEL_ITATBDATA0_ATDATA_16_Pos (16UL) /*!< Position of ATDATA_16 field. */ 141 #define ATBFUNNEL_ITATBDATA0_ATDATA_16_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_16_Pos) /*!< Bit mask of ATDATA_16 field. */ 142 #define ATBFUNNEL_ITATBDATA0_ATDATA_16_Low (0x0UL) /*!< Pin is logic 0. */ 143 #define ATBFUNNEL_ITATBDATA0_ATDATA_16_High (0x1UL) /*!< Pin is logic 1. */ 144 145 /* Bit 15 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 146 #define ATBFUNNEL_ITATBDATA0_ATDATA_15_Pos (15UL) /*!< Position of ATDATA_15 field. */ 147 #define ATBFUNNEL_ITATBDATA0_ATDATA_15_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_15_Pos) /*!< Bit mask of ATDATA_15 field. */ 148 #define ATBFUNNEL_ITATBDATA0_ATDATA_15_Low (0x0UL) /*!< Pin is logic 0. */ 149 #define ATBFUNNEL_ITATBDATA0_ATDATA_15_High (0x1UL) /*!< Pin is logic 1. */ 150 151 /* Bit 14 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 152 #define ATBFUNNEL_ITATBDATA0_ATDATA_14_Pos (14UL) /*!< Position of ATDATA_14 field. */ 153 #define ATBFUNNEL_ITATBDATA0_ATDATA_14_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_14_Pos) /*!< Bit mask of ATDATA_14 field. */ 154 #define ATBFUNNEL_ITATBDATA0_ATDATA_14_Low (0x0UL) /*!< Pin is logic 0. */ 155 #define ATBFUNNEL_ITATBDATA0_ATDATA_14_High (0x1UL) /*!< Pin is logic 1. */ 156 157 /* Bit 13 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 158 #define ATBFUNNEL_ITATBDATA0_ATDATA_13_Pos (13UL) /*!< Position of ATDATA_13 field. */ 159 #define ATBFUNNEL_ITATBDATA0_ATDATA_13_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_13_Pos) /*!< Bit mask of ATDATA_13 field. */ 160 #define ATBFUNNEL_ITATBDATA0_ATDATA_13_Low (0x0UL) /*!< Pin is logic 0. */ 161 #define ATBFUNNEL_ITATBDATA0_ATDATA_13_High (0x1UL) /*!< Pin is logic 1. */ 162 163 /* Bit 12 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 164 #define ATBFUNNEL_ITATBDATA0_ATDATA_12_Pos (12UL) /*!< Position of ATDATA_12 field. */ 165 #define ATBFUNNEL_ITATBDATA0_ATDATA_12_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_12_Pos) /*!< Bit mask of ATDATA_12 field. */ 166 #define ATBFUNNEL_ITATBDATA0_ATDATA_12_Low (0x0UL) /*!< Pin is logic 0. */ 167 #define ATBFUNNEL_ITATBDATA0_ATDATA_12_High (0x1UL) /*!< Pin is logic 1. */ 168 169 /* Bit 11 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 170 #define ATBFUNNEL_ITATBDATA0_ATDATA_11_Pos (11UL) /*!< Position of ATDATA_11 field. */ 171 #define ATBFUNNEL_ITATBDATA0_ATDATA_11_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_11_Pos) /*!< Bit mask of ATDATA_11 field. */ 172 #define ATBFUNNEL_ITATBDATA0_ATDATA_11_Low (0x0UL) /*!< Pin is logic 0. */ 173 #define ATBFUNNEL_ITATBDATA0_ATDATA_11_High (0x1UL) /*!< Pin is logic 1. */ 174 175 /* Bit 10 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 176 #define ATBFUNNEL_ITATBDATA0_ATDATA_10_Pos (10UL) /*!< Position of ATDATA_10 field. */ 177 #define ATBFUNNEL_ITATBDATA0_ATDATA_10_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_10_Pos) /*!< Bit mask of ATDATA_10 field. */ 178 #define ATBFUNNEL_ITATBDATA0_ATDATA_10_Low (0x0UL) /*!< Pin is logic 0. */ 179 #define ATBFUNNEL_ITATBDATA0_ATDATA_10_High (0x1UL) /*!< Pin is logic 1. */ 180 181 /* Bit 9 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 182 #define ATBFUNNEL_ITATBDATA0_ATDATA_9_Pos (9UL) /*!< Position of ATDATA_9 field. */ 183 #define ATBFUNNEL_ITATBDATA0_ATDATA_9_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_9_Pos) /*!< Bit mask of ATDATA_9 field. */ 184 #define ATBFUNNEL_ITATBDATA0_ATDATA_9_Low (0x0UL) /*!< Pin is logic 0. */ 185 #define ATBFUNNEL_ITATBDATA0_ATDATA_9_High (0x1UL) /*!< Pin is logic 1. */ 186 187 /* Bit 8 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 188 #define ATBFUNNEL_ITATBDATA0_ATDATA_8_Pos (8UL) /*!< Position of ATDATA_8 field. */ 189 #define ATBFUNNEL_ITATBDATA0_ATDATA_8_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_8_Pos) /*!< Bit mask of ATDATA_8 field. */ 190 #define ATBFUNNEL_ITATBDATA0_ATDATA_8_Low (0x0UL) /*!< Pin is logic 0. */ 191 #define ATBFUNNEL_ITATBDATA0_ATDATA_8_High (0x1UL) /*!< Pin is logic 1. */ 192 193 /* Bit 7 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 194 #define ATBFUNNEL_ITATBDATA0_ATDATA_7_Pos (7UL) /*!< Position of ATDATA_7 field. */ 195 #define ATBFUNNEL_ITATBDATA0_ATDATA_7_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_7_Pos) /*!< Bit mask of ATDATA_7 field. */ 196 #define ATBFUNNEL_ITATBDATA0_ATDATA_7_Low (0x0UL) /*!< Pin is logic 0. */ 197 #define ATBFUNNEL_ITATBDATA0_ATDATA_7_High (0x1UL) /*!< Pin is logic 1. */ 198 199 /* Bit 6 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 200 #define ATBFUNNEL_ITATBDATA0_ATDATA_6_Pos (6UL) /*!< Position of ATDATA_6 field. */ 201 #define ATBFUNNEL_ITATBDATA0_ATDATA_6_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_6_Pos) /*!< Bit mask of ATDATA_6 field. */ 202 #define ATBFUNNEL_ITATBDATA0_ATDATA_6_Low (0x0UL) /*!< Pin is logic 0. */ 203 #define ATBFUNNEL_ITATBDATA0_ATDATA_6_High (0x1UL) /*!< Pin is logic 1. */ 204 205 /* Bit 5 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 206 #define ATBFUNNEL_ITATBDATA0_ATDATA_5_Pos (5UL) /*!< Position of ATDATA_5 field. */ 207 #define ATBFUNNEL_ITATBDATA0_ATDATA_5_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_5_Pos) /*!< Bit mask of ATDATA_5 field. */ 208 #define ATBFUNNEL_ITATBDATA0_ATDATA_5_Low (0x0UL) /*!< Pin is logic 0. */ 209 #define ATBFUNNEL_ITATBDATA0_ATDATA_5_High (0x1UL) /*!< Pin is logic 1. */ 210 211 /* Bit 4 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 212 #define ATBFUNNEL_ITATBDATA0_ATDATA_4_Pos (4UL) /*!< Position of ATDATA_4 field. */ 213 #define ATBFUNNEL_ITATBDATA0_ATDATA_4_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_4_Pos) /*!< Bit mask of ATDATA_4 field. */ 214 #define ATBFUNNEL_ITATBDATA0_ATDATA_4_Low (0x0UL) /*!< Pin is logic 0. */ 215 #define ATBFUNNEL_ITATBDATA0_ATDATA_4_High (0x1UL) /*!< Pin is logic 1. */ 216 217 /* Bit 3 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 218 #define ATBFUNNEL_ITATBDATA0_ATDATA_3_Pos (3UL) /*!< Position of ATDATA_3 field. */ 219 #define ATBFUNNEL_ITATBDATA0_ATDATA_3_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_3_Pos) /*!< Bit mask of ATDATA_3 field. */ 220 #define ATBFUNNEL_ITATBDATA0_ATDATA_3_Low (0x0UL) /*!< Pin is logic 0. */ 221 #define ATBFUNNEL_ITATBDATA0_ATDATA_3_High (0x1UL) /*!< Pin is logic 1. */ 222 223 /* Bit 2 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 224 #define ATBFUNNEL_ITATBDATA0_ATDATA_2_Pos (2UL) /*!< Position of ATDATA_2 field. */ 225 #define ATBFUNNEL_ITATBDATA0_ATDATA_2_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_2_Pos) /*!< Bit mask of ATDATA_2 field. */ 226 #define ATBFUNNEL_ITATBDATA0_ATDATA_2_Low (0x0UL) /*!< Pin is logic 0. */ 227 #define ATBFUNNEL_ITATBDATA0_ATDATA_2_High (0x1UL) /*!< Pin is logic 1. */ 228 229 /* Bit 1 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 230 #define ATBFUNNEL_ITATBDATA0_ATDATA_1_Pos (1UL) /*!< Position of ATDATA_1 field. */ 231 #define ATBFUNNEL_ITATBDATA0_ATDATA_1_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_1_Pos) /*!< Bit mask of ATDATA_1 field. */ 232 #define ATBFUNNEL_ITATBDATA0_ATDATA_1_Low (0x0UL) /*!< Pin is logic 0. */ 233 #define ATBFUNNEL_ITATBDATA0_ATDATA_1_High (0x1UL) /*!< Pin is logic 1. */ 234 235 /* Bit 0 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 236 #define ATBFUNNEL_ITATBDATA0_ATDATA_0_Pos (0UL) /*!< Position of ATDATA_0 field. */ 237 #define ATBFUNNEL_ITATBDATA0_ATDATA_0_Msk (0x1UL << ATBFUNNEL_ITATBDATA0_ATDATA_0_Pos) /*!< Bit mask of ATDATA_0 field. */ 238 #define ATBFUNNEL_ITATBDATA0_ATDATA_0_Low (0x0UL) /*!< Pin is logic 0. */ 239 #define ATBFUNNEL_ITATBDATA0_ATDATA_0_High (0x1UL) /*!< Pin is logic 1. */ 240 241 /* Register: ATBFUNNEL_ITATBCTR2 */ 242 /* Description: The ITATBCTR2 register performs different functions depending on whether the access is a read or a write. */ 243 244 /* Bit 1 : A read access returns the value of afvalidm. 245 A write access outputs the data to atreadys[n], where the value of the CTRLREG at 0x000 defines n. */ 246 #define ATBFUNNEL_ITATBCTR2_AFVALID_Pos (1UL) /*!< Position of AFVALID field. */ 247 #define ATBFUNNEL_ITATBCTR2_AFVALID_Msk (0x1UL << ATBFUNNEL_ITATBCTR2_AFVALID_Pos) /*!< Bit mask of AFVALID field. */ 248 #define ATBFUNNEL_ITATBCTR2_AFVALID_Low (0x0UL) /*!< Pin is logic 0. */ 249 #define ATBFUNNEL_ITATBCTR2_AFVALID_High (0x1UL) /*!< Pin is logic 1. */ 250 251 /* Bit 0 : A read access returns the value of atreadym. 252 A write access outputs the data to afvalids[n], where the value of the CTRLREG at 0x000 defines n. */ 253 #define ATBFUNNEL_ITATBCTR2_ATREADY_Pos (0UL) /*!< Position of ATREADY field. */ 254 #define ATBFUNNEL_ITATBCTR2_ATREADY_Msk (0x1UL << ATBFUNNEL_ITATBCTR2_ATREADY_Pos) /*!< Bit mask of ATREADY field. */ 255 #define ATBFUNNEL_ITATBCTR2_ATREADY_Low (0x0UL) /*!< Pin is logic 0. */ 256 #define ATBFUNNEL_ITATBCTR2_ATREADY_High (0x1UL) /*!< Pin is logic 1. */ 257 258 /* Register: ATBFUNNEL_ITATBCTR1 */ 259 /* Description: The ITATBCTR1 register performs different functions depending on whether the access is a read or a write. */ 260 261 /* Bits 6..0 : A read returns the value of the atids[n] signals, where the value of the Control Register at 0x000 defines n. 262 A write outputs the value to the atidm port. */ 263 #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Pos (0UL) /*!< Position of ATVALIDM0 field. */ 264 #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Msk (0x7FUL << ATBFUNNEL_ITATBCTR1_ATVALIDM0_Pos) /*!< Bit mask of ATVALIDM0 field. */ 265 #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_Low (0x00UL) /*!< Pin is logic 0. */ 266 #define ATBFUNNEL_ITATBCTR1_ATVALIDM0_High (0x01UL) /*!< Pin is logic 1. */ 267 268 /* Register: ATBFUNNEL_ITATBCTR0 */ 269 /* Description: The ITATBCTR0 register performs different functions depending on whether the access is a read or a write. */ 270 271 /* Bits 9..8 : A read returns the value of the atbytess[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. 272 A write outputs the value to atbytesm. */ 273 #define ATBFUNNEL_ITATBCTR0_ATBYTES_Pos (8UL) /*!< Position of ATBYTES field. */ 274 #define ATBFUNNEL_ITATBCTR0_ATBYTES_Msk (0x3UL << ATBFUNNEL_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field. */ 275 #define ATBFUNNEL_ITATBCTR0_ATBYTES_Low (0x0UL) /*!< Pin is logic 0. */ 276 #define ATBFUNNEL_ITATBCTR0_ATBYTES_High (0x1UL) /*!< Pin is logic 1. */ 277 278 /* Bit 2 : A read returns the value of the afreadys[n] signal, where the value of the Ctrl_Reg at 0x000 defines n. 279 A write outputs the value to afreadym. */ 280 #define ATBFUNNEL_ITATBCTR0_AFREADY_Pos (2UL) /*!< Position of AFREADY field. */ 281 #define ATBFUNNEL_ITATBCTR0_AFREADY_Msk (0x1UL << ATBFUNNEL_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ 282 #define ATBFUNNEL_ITATBCTR0_AFREADY_Low (0x0UL) /*!< Pin is logic 0. */ 283 #define ATBFUNNEL_ITATBCTR0_AFREADY_High (0x1UL) /*!< Pin is logic 1. */ 284 285 /* Bit 0 : A read returns the value of the atvalids[n] signal, where the value of the CTRLREG at 0x000 defines n. 286 A write outputs the value to atvalidm. */ 287 #define ATBFUNNEL_ITATBCTR0_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ 288 #define ATBFUNNEL_ITATBCTR0_ATVALID_Msk (0x1UL << ATBFUNNEL_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ 289 #define ATBFUNNEL_ITATBCTR0_ATVALID_Low (0x0UL) /*!< Pin is logic 0. */ 290 #define ATBFUNNEL_ITATBCTR0_ATVALID_High (0x1UL) /*!< Pin is logic 1. */ 291 292 /* Register: ATBFUNNEL_ITCTRL */ 293 /* Description: The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, 294 to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. */ 295 296 /* Bit 0 : Integration Mode Enable. */ 297 #define ATBFUNNEL_ITCTRL_IME_Pos (0UL) /*!< Position of IME field. */ 298 #define ATBFUNNEL_ITCTRL_IME_Msk (0x1UL << ATBFUNNEL_ITCTRL_IME_Pos) /*!< Bit mask of IME field. */ 299 #define ATBFUNNEL_ITCTRL_IME_Disabled (0x0UL) /*!< Integration mode disabled. */ 300 #define ATBFUNNEL_ITCTRL_IME_Enabled (0x1UL) /*!< Integration mode enabled. */ 301 302 /* Register: ATBFUNNEL_CLAIMSET */ 303 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. 304 The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. */ 305 306 /* Bit 3 : Set claim bit 3 and check if bit is implemented or not. */ 307 #define ATBFUNNEL_CLAIMSET_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */ 308 #define ATBFUNNEL_CLAIMSET_BIT_3_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */ 309 #define ATBFUNNEL_CLAIMSET_BIT_3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented. */ 310 #define ATBFUNNEL_CLAIMSET_BIT_3_Implemented (0x1UL) /*!< Claim bit 3 is implemented. */ 311 #define ATBFUNNEL_CLAIMSET_BIT_3_Set (0x1UL) /*!< Set claim bit 3. */ 312 313 /* Bit 2 : Set claim bit 2 and check if bit is implemented or not. */ 314 #define ATBFUNNEL_CLAIMSET_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */ 315 #define ATBFUNNEL_CLAIMSET_BIT_2_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */ 316 #define ATBFUNNEL_CLAIMSET_BIT_2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented. */ 317 #define ATBFUNNEL_CLAIMSET_BIT_2_Implemented (0x1UL) /*!< Claim bit 2 is implemented. */ 318 #define ATBFUNNEL_CLAIMSET_BIT_2_Set (0x1UL) /*!< Set claim bit 2. */ 319 320 /* Bit 1 : Set claim bit 1 and check if bit is implemented or not. */ 321 #define ATBFUNNEL_CLAIMSET_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */ 322 #define ATBFUNNEL_CLAIMSET_BIT_1_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */ 323 #define ATBFUNNEL_CLAIMSET_BIT_1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented. */ 324 #define ATBFUNNEL_CLAIMSET_BIT_1_Implemented (0x1UL) /*!< Claim bit 1 is implemented. */ 325 #define ATBFUNNEL_CLAIMSET_BIT_1_Set (0x1UL) /*!< Set claim bit 1. */ 326 327 /* Bit 0 : Set claim bit 0 and check if bit is implemented or not. */ 328 #define ATBFUNNEL_CLAIMSET_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */ 329 #define ATBFUNNEL_CLAIMSET_BIT_0_Msk (0x1UL << ATBFUNNEL_CLAIMSET_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */ 330 #define ATBFUNNEL_CLAIMSET_BIT_0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented. */ 331 #define ATBFUNNEL_CLAIMSET_BIT_0_Implemented (0x1UL) /*!< Claim bit 0 is implemented. */ 332 #define ATBFUNNEL_CLAIMSET_BIT_0_Set (0x1UL) /*!< Set claim bit 0. */ 333 334 /* Register: ATBFUNNEL_CLAIMCLR */ 335 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. 336 The claim tags have no effect on the operation of the component. 337 The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. */ 338 339 /* Bit 3 : Read or clear claim bit 3. */ 340 #define ATBFUNNEL_CLAIMCLR_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */ 341 #define ATBFUNNEL_CLAIMCLR_BIT_3_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */ 342 #define ATBFUNNEL_CLAIMCLR_BIT_3_Cleared (0x0UL) /*!< Claim bit 3 is not set. */ 343 #define ATBFUNNEL_CLAIMCLR_BIT_3_Set (0x1UL) /*!< Claim bit 3 is set. */ 344 #define ATBFUNNEL_CLAIMCLR_BIT_3_Clear (0x1UL) /*!< Clear claim bit 3. */ 345 346 /* Bit 2 : Read or clear claim bit 2. */ 347 #define ATBFUNNEL_CLAIMCLR_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */ 348 #define ATBFUNNEL_CLAIMCLR_BIT_2_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */ 349 #define ATBFUNNEL_CLAIMCLR_BIT_2_Cleared (0x0UL) /*!< Claim bit 2 is not set. */ 350 #define ATBFUNNEL_CLAIMCLR_BIT_2_Set (0x1UL) /*!< Claim bit 2 is set. */ 351 #define ATBFUNNEL_CLAIMCLR_BIT_2_Clear (0x1UL) /*!< Clear claim bit 2. */ 352 353 /* Bit 1 : Read or clear claim bit 1. */ 354 #define ATBFUNNEL_CLAIMCLR_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */ 355 #define ATBFUNNEL_CLAIMCLR_BIT_1_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */ 356 #define ATBFUNNEL_CLAIMCLR_BIT_1_Cleared (0x0UL) /*!< Claim bit 1 is not set. */ 357 #define ATBFUNNEL_CLAIMCLR_BIT_1_Set (0x1UL) /*!< Claim bit 1 is set. */ 358 #define ATBFUNNEL_CLAIMCLR_BIT_1_Clear (0x1UL) /*!< Clear claim bit 1. */ 359 360 /* Bit 0 : Read or clear claim bit 0. */ 361 #define ATBFUNNEL_CLAIMCLR_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */ 362 #define ATBFUNNEL_CLAIMCLR_BIT_0_Msk (0x1UL << ATBFUNNEL_CLAIMCLR_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */ 363 #define ATBFUNNEL_CLAIMCLR_BIT_0_Cleared (0x0UL) /*!< Claim bit 0 is not set. */ 364 #define ATBFUNNEL_CLAIMCLR_BIT_0_Set (0x1UL) /*!< Claim bit 0 is set. */ 365 #define ATBFUNNEL_CLAIMCLR_BIT_0_Clear (0x1UL) /*!< Clear claim bit 0. */ 366 367 /* Register: ATBFUNNEL_LAR */ 368 /* Description: This is used to enable write access to device registers. */ 369 370 /* Bits 31..0 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. */ 371 #define ATBFUNNEL_LAR_ACCESS_Pos (0UL) /*!< Position of ACCESS field. */ 372 #define ATBFUNNEL_LAR_ACCESS_Msk (0xFFFFFFFFUL << ATBFUNNEL_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field. */ 373 #define ATBFUNNEL_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface. */ 374 375 /* Register: ATBFUNNEL_LSR */ 376 /* Description: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. 377 Accesses to the extended stimulus port registers are not affected by the lock mechanism. 378 This register must always be present although there might not be any lock access control mechanism. 379 The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. 380 For most components this covers all registers except for the Lock Access Register. */ 381 382 /* Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */ 383 #define ATBFUNNEL_LSR_TYPE_Pos (2UL) /*!< Position of TYPE field. */ 384 #define ATBFUNNEL_LSR_TYPE_Msk (0x1UL << ATBFUNNEL_LSR_TYPE_Pos) /*!< Bit mask of TYPE field. */ 385 #define ATBFUNNEL_LSR_TYPE_Bits32 (0x0UL) /*!< This component implements a 32-bit Lock Access Register. */ 386 #define ATBFUNNEL_LSR_TYPE_Bits8 (0x1UL) /*!< This component implements an 8-bit Lock Access Register. */ 387 388 /* Bit 1 : Returns the current status of the Lock. */ 389 #define ATBFUNNEL_LSR_LOCKED_Pos (1UL) /*!< Position of LOCKED field. */ 390 #define ATBFUNNEL_LSR_LOCKED_Msk (0x1UL << ATBFUNNEL_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ 391 #define ATBFUNNEL_LSR_LOCKED_UnLocked (0x0UL) /*!< Write access is allowed to this device. */ 392 #define ATBFUNNEL_LSR_LOCKED_Locked (0x1UL) /*!< Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. */ 393 394 /* Bit 0 : Indicates that a lock control mechanism exists for this device. */ 395 #define ATBFUNNEL_LSR_PRESENT_Pos (0UL) /*!< Position of PRESENT field. */ 396 #define ATBFUNNEL_LSR_PRESENT_Msk (0x1UL << ATBFUNNEL_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ 397 #define ATBFUNNEL_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access Register are ignored. */ 398 #define ATBFUNNEL_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present. */ 399 400 /* Register: ATBFUNNEL_AUTHSTATUS */ 401 /* Description: Indicates the current level of tracing permitted by the system */ 402 403 /* Bits 7..6 : Secure Non-Invasive Debug */ 404 #define ATBFUNNEL_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ 405 #define ATBFUNNEL_AUTHSTATUS_SNID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ 406 #define ATBFUNNEL_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 407 #define ATBFUNNEL_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */ 408 409 /* Bits 5..4 : Secure Invasive Debug */ 410 #define ATBFUNNEL_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ 411 #define ATBFUNNEL_AUTHSTATUS_SID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ 412 #define ATBFUNNEL_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 413 #define ATBFUNNEL_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */ 414 415 /* Bits 3..2 : Non-secure Non-Invasive Debug */ 416 #define ATBFUNNEL_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ 417 #define ATBFUNNEL_AUTHSTATUS_NSNID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ 418 #define ATBFUNNEL_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 419 #define ATBFUNNEL_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */ 420 421 /* Bits 1..0 : Non-secure Invasive Debug */ 422 #define ATBFUNNEL_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ 423 #define ATBFUNNEL_AUTHSTATUS_NSID_Msk (0x3UL << ATBFUNNEL_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ 424 #define ATBFUNNEL_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 425 #define ATBFUNNEL_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */ 426 427 /* Register: ATBFUNNEL_DEVID */ 428 /* Description: Indicates the capabilities of the component. */ 429 430 /* Bits 3..0 : Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. */ 431 #define ATBFUNNEL_DEVID_PORTCOUNT_Pos (0UL) /*!< Position of PORTCOUNT field. */ 432 #define ATBFUNNEL_DEVID_PORTCOUNT_Msk (0xFUL << ATBFUNNEL_DEVID_PORTCOUNT_Pos) /*!< Bit mask of PORTCOUNT field. */ 433 434 /* Register: ATBFUNNEL_DEVTYPE */ 435 /* Description: The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. */ 436 437 /* Bits 7..4 : The sub-type of the component */ 438 #define ATBFUNNEL_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ 439 #define ATBFUNNEL_DEVTYPE_SUB_Msk (0xFUL << ATBFUNNEL_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ 440 #define ATBFUNNEL_DEVTYPE_SUB_Replicator (0x1UL) /*!< This component arbitrates ATB inputs mapping to ATB outputs. */ 441 442 /* Bits 3..0 : The main type of the component */ 443 #define ATBFUNNEL_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ 444 #define ATBFUNNEL_DEVTYPE_MAJOR_Msk (0xFUL << ATBFUNNEL_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ 445 #define ATBFUNNEL_DEVTYPE_MAJOR_InputOutputDevice (0x2UL) /*!< Indicates that this component has ATB inputs and outputs. */ 446 447 448 /* Peripheral: ATBREPLICATOR */ 449 /* Description: ATB Replicator module */ 450 451 /* Register: ATBREPLICATOR_IDFILTER0 */ 452 /* Description: The IDFILTER0 register enables the programming of ID filtering for master port 0. */ 453 454 /* Bit 7 : Enable or disable ID filtering for IDs 0x70_0x7F. */ 455 #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Pos (7UL) /*!< Position of ID0_70_7F field. */ 456 #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_70_7F_Pos) /*!< Bit mask of ID0_70_7F field. */ 457 #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */ 458 #define ATBREPLICATOR_IDFILTER0_ID0_70_7F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 459 460 /* Bit 6 : Enable or disable ID filtering for IDs 0x60_0x6F. */ 461 #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Pos (6UL) /*!< Position of ID0_60_6F field. */ 462 #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_60_6F_Pos) /*!< Bit mask of ID0_60_6F field. */ 463 #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */ 464 #define ATBREPLICATOR_IDFILTER0_ID0_60_6F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 465 466 /* Bit 5 : Enable or disable ID filtering for IDs 0x50_0x5F. */ 467 #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Pos (5UL) /*!< Position of ID0_50_5F field. */ 468 #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_50_5F_Pos) /*!< Bit mask of ID0_50_5F field. */ 469 #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */ 470 #define ATBREPLICATOR_IDFILTER0_ID0_50_5F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 471 472 /* Bit 4 : Enable or disable ID filtering for IDs 0x40_0x4F. */ 473 #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Pos (4UL) /*!< Position of ID0_40_4F field. */ 474 #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_40_4F_Pos) /*!< Bit mask of ID0_40_4F field. */ 475 #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */ 476 #define ATBREPLICATOR_IDFILTER0_ID0_40_4F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 477 478 /* Bit 3 : Enable or disable ID filtering for IDs 0x30_0x3F. */ 479 #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Pos (3UL) /*!< Position of ID0_30_3F field. */ 480 #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_30_3F_Pos) /*!< Bit mask of ID0_30_3F field. */ 481 #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */ 482 #define ATBREPLICATOR_IDFILTER0_ID0_30_3F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 483 484 /* Bit 2 : Enable or disable ID filtering for IDs 0x20_0x2F. */ 485 #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Pos (2UL) /*!< Position of ID0_20_2F field. */ 486 #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_20_2F_Pos) /*!< Bit mask of ID0_20_2F field. */ 487 #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */ 488 #define ATBREPLICATOR_IDFILTER0_ID0_20_2F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 489 490 /* Bit 1 : Enable or disable ID filtering for IDs 0x10_0x1F. */ 491 #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Pos (1UL) /*!< Position of ID0_10_1F field. */ 492 #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_10_1F_Pos) /*!< Bit mask of ID0_10_1F field. */ 493 #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */ 494 #define ATBREPLICATOR_IDFILTER0_ID0_10_1F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 495 496 /* Bit 0 : Enable or disable ID filtering for IDs 0x00_0x0F. */ 497 #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Pos (0UL) /*!< Position of ID0_00_0F field. */ 498 #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Msk (0x1UL << ATBREPLICATOR_IDFILTER0_ID0_00_0F_Pos) /*!< Bit mask of ID0_00_0F field. */ 499 #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 0. */ 500 #define ATBREPLICATOR_IDFILTER0_ID0_00_0F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 501 502 /* Register: ATBREPLICATOR_IDFILTER1 */ 503 /* Description: The IDFILTER1 register enables the programming of ID filtering for master port 1. */ 504 505 /* Bit 7 : Enable or disable ID filtering for IDs 0x70_0x7F. */ 506 #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Pos (7UL) /*!< Position of ID1_70_7F field. */ 507 #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_70_7F_Pos) /*!< Bit mask of ID1_70_7F field. */ 508 #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */ 509 #define ATBREPLICATOR_IDFILTER1_ID1_70_7F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 510 511 /* Bit 6 : Enable or disable ID filtering for IDs 0x60_0x6F. */ 512 #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Pos (6UL) /*!< Position of ID1_60_6F field. */ 513 #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_60_6F_Pos) /*!< Bit mask of ID1_60_6F field. */ 514 #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */ 515 #define ATBREPLICATOR_IDFILTER1_ID1_60_6F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 516 517 /* Bit 5 : Enable or disable ID filtering for IDs 0x50_0x5F. */ 518 #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Pos (5UL) /*!< Position of ID1_50_5F field. */ 519 #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_50_5F_Pos) /*!< Bit mask of ID1_50_5F field. */ 520 #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */ 521 #define ATBREPLICATOR_IDFILTER1_ID1_50_5F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 522 523 /* Bit 4 : Enable or disable ID filtering for IDs 0x40_0x4F. */ 524 #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Pos (4UL) /*!< Position of ID1_40_4F field. */ 525 #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_40_4F_Pos) /*!< Bit mask of ID1_40_4F field. */ 526 #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */ 527 #define ATBREPLICATOR_IDFILTER1_ID1_40_4F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 528 529 /* Bit 3 : Enable or disable ID filtering for IDs 0x30_0x3F. */ 530 #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Pos (3UL) /*!< Position of ID1_30_3F field. */ 531 #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_30_3F_Pos) /*!< Bit mask of ID1_30_3F field. */ 532 #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */ 533 #define ATBREPLICATOR_IDFILTER1_ID1_30_3F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 534 535 /* Bit 2 : Enable or disable ID filtering for IDs 0x20_0x2F. */ 536 #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Pos (2UL) /*!< Position of ID1_20_2F field. */ 537 #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_20_2F_Pos) /*!< Bit mask of ID1_20_2F field. */ 538 #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */ 539 #define ATBREPLICATOR_IDFILTER1_ID1_20_2F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 540 541 /* Bit 1 : Enable or disable ID filtering for IDs 0x10_0x1F. */ 542 #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Pos (1UL) /*!< Position of ID1_10_1F field. */ 543 #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_10_1F_Pos) /*!< Bit mask of ID1_10_1F field. */ 544 #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */ 545 #define ATBREPLICATOR_IDFILTER1_ID1_10_1F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 546 547 /* Bit 0 : Enable or disable ID filtering for IDs 0x00_0x0F. */ 548 #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Pos (0UL) /*!< Position of ID1_00_0F field. */ 549 #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Msk (0x1UL << ATBREPLICATOR_IDFILTER1_ID1_00_0F_Pos) /*!< Bit mask of ID1_00_0F field. */ 550 #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_NotFiltered (0x0UL) /*!< Transactions with these IDs are passed on to ATB master port 1. */ 551 #define ATBREPLICATOR_IDFILTER1_ID1_00_0F_Selected (0x1UL) /*!< Transactions with these IDs are discarded by the replicator. */ 552 553 /* Register: ATBREPLICATOR_ITATBCTR1 */ 554 /* Description: The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in integration mode. */ 555 556 /* Bit 3 : Reads the value of the atvalids input. */ 557 #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Pos (3UL) /*!< Position of ATVALIDS field. */ 558 #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATVALIDS_Pos) /*!< Bit mask of ATVALIDS field. */ 559 #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_Low (0x0UL) /*!< Pin is logic 0. */ 560 #define ATBREPLICATOR_ITATBCTR1_ATVALIDS_High (0x1UL) /*!< Pin is logic 1. */ 561 562 /* Bit 1 : Reads the value of the atreadym1 input. */ 563 #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Pos (1UL) /*!< Position of ATREADYM1 field. */ 564 #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATREADYM1_Pos) /*!< Bit mask of ATREADYM1 field. */ 565 #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_Low (0x0UL) /*!< Pin is logic 0. */ 566 #define ATBREPLICATOR_ITATBCTR1_ATREADYM1_High (0x1UL) /*!< Pin is logic 1. */ 567 568 /* Bit 0 : Reads the value of the atreadym0 input. */ 569 #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Pos (0UL) /*!< Position of ATREADYM0 field. */ 570 #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Msk (0x1UL << ATBREPLICATOR_ITATBCTR1_ATREADYM0_Pos) /*!< Bit mask of ATREADYM0 field. */ 571 #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_Low (0x0UL) /*!< Pin is logic 0. */ 572 #define ATBREPLICATOR_ITATBCTR1_ATREADYM0_High (0x1UL) /*!< Pin is logic 1. */ 573 574 /* Register: ATBREPLICATOR_ITATBCTR0 */ 575 /* Description: The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in integration mode. */ 576 577 /* Bit 3 : Sets the value of the atreadys output. */ 578 #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Pos (3UL) /*!< Position of ATREADYS field. */ 579 #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATREADYS_Pos) /*!< Bit mask of ATREADYS field. */ 580 #define ATBREPLICATOR_ITATBCTR0_ATREADYS_Low (0x0UL) /*!< Pin is logic 0. */ 581 #define ATBREPLICATOR_ITATBCTR0_ATREADYS_High (0x1UL) /*!< Pin is logic 1. */ 582 583 /* Bit 2 : Sets the value of the atvalidm1 output. */ 584 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Pos (2UL) /*!< Position of ATVALIDM1 field. */ 585 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Pos) /*!< Bit mask of ATVALIDM1 field. */ 586 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_Low (0x0UL) /*!< Pin is logic 0. */ 587 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM1_High (0x1UL) /*!< Pin is logic 1. */ 588 589 /* Bit 0 : Sets the value of the atvalidm0 output. */ 590 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Pos (0UL) /*!< Position of ATVALIDM0 field. */ 591 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Msk (0x1UL << ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Pos) /*!< Bit mask of ATVALIDM0 field. */ 592 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_Low (0x0UL) /*!< Pin is logic 0. */ 593 #define ATBREPLICATOR_ITATBCTR0_ATVALIDM0_High (0x1UL) /*!< Pin is logic 1. */ 594 595 /* Register: ATBREPLICATOR_ITCTRL */ 596 /* Description: The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, 597 to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection. */ 598 599 /* Bit 0 : Integration Mode Enable. */ 600 #define ATBREPLICATOR_ITCTRL_IME_Pos (0UL) /*!< Position of IME field. */ 601 #define ATBREPLICATOR_ITCTRL_IME_Msk (0x1UL << ATBREPLICATOR_ITCTRL_IME_Pos) /*!< Bit mask of IME field. */ 602 #define ATBREPLICATOR_ITCTRL_IME_Disabled (0x0UL) /*!< Integration mode disabled. */ 603 #define ATBREPLICATOR_ITCTRL_IME_Enabled (0x1UL) /*!< Integration mode enabled. */ 604 605 /* Register: ATBREPLICATOR_CLAIMSET */ 606 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. 607 The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. */ 608 609 /* Bit 3 : Set claim bit 3 and check if bit is implemented or not. */ 610 #define ATBREPLICATOR_CLAIMSET_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */ 611 #define ATBREPLICATOR_CLAIMSET_BIT_3_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */ 612 #define ATBREPLICATOR_CLAIMSET_BIT_3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented. */ 613 #define ATBREPLICATOR_CLAIMSET_BIT_3_Implemented (0x1UL) /*!< Claim bit 3 is implemented. */ 614 #define ATBREPLICATOR_CLAIMSET_BIT_3_Set (0x1UL) /*!< Set claim bit 3. */ 615 616 /* Bit 2 : Set claim bit 2 and check if bit is implemented or not. */ 617 #define ATBREPLICATOR_CLAIMSET_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */ 618 #define ATBREPLICATOR_CLAIMSET_BIT_2_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */ 619 #define ATBREPLICATOR_CLAIMSET_BIT_2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented. */ 620 #define ATBREPLICATOR_CLAIMSET_BIT_2_Implemented (0x1UL) /*!< Claim bit 2 is implemented. */ 621 #define ATBREPLICATOR_CLAIMSET_BIT_2_Set (0x1UL) /*!< Set claim bit 2. */ 622 623 /* Bit 1 : Set claim bit 1 and check if bit is implemented or not. */ 624 #define ATBREPLICATOR_CLAIMSET_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */ 625 #define ATBREPLICATOR_CLAIMSET_BIT_1_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */ 626 #define ATBREPLICATOR_CLAIMSET_BIT_1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented. */ 627 #define ATBREPLICATOR_CLAIMSET_BIT_1_Implemented (0x1UL) /*!< Claim bit 1 is implemented. */ 628 #define ATBREPLICATOR_CLAIMSET_BIT_1_Set (0x1UL) /*!< Set claim bit 1. */ 629 630 /* Bit 0 : Set claim bit 0 and check if bit is implemented or not. */ 631 #define ATBREPLICATOR_CLAIMSET_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */ 632 #define ATBREPLICATOR_CLAIMSET_BIT_0_Msk (0x1UL << ATBREPLICATOR_CLAIMSET_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */ 633 #define ATBREPLICATOR_CLAIMSET_BIT_0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented. */ 634 #define ATBREPLICATOR_CLAIMSET_BIT_0_Implemented (0x1UL) /*!< Claim bit 0 is implemented. */ 635 #define ATBREPLICATOR_CLAIMSET_BIT_0_Set (0x1UL) /*!< Set claim bit 0. */ 636 637 /* Register: ATBREPLICATOR_CLAIMCLR */ 638 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. 639 The claim tags have no effect on the operation of the component. 640 The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. */ 641 642 /* Bit 3 : Read or clear claim bit 3. */ 643 #define ATBREPLICATOR_CLAIMCLR_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */ 644 #define ATBREPLICATOR_CLAIMCLR_BIT_3_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */ 645 #define ATBREPLICATOR_CLAIMCLR_BIT_3_Cleared (0x0UL) /*!< Claim bit 3 is not set. */ 646 #define ATBREPLICATOR_CLAIMCLR_BIT_3_Set (0x1UL) /*!< Claim bit 3 is set. */ 647 #define ATBREPLICATOR_CLAIMCLR_BIT_3_Clear (0x1UL) /*!< Clear claim bit 3. */ 648 649 /* Bit 2 : Read or clear claim bit 2. */ 650 #define ATBREPLICATOR_CLAIMCLR_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */ 651 #define ATBREPLICATOR_CLAIMCLR_BIT_2_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */ 652 #define ATBREPLICATOR_CLAIMCLR_BIT_2_Cleared (0x0UL) /*!< Claim bit 2 is not set. */ 653 #define ATBREPLICATOR_CLAIMCLR_BIT_2_Set (0x1UL) /*!< Claim bit 2 is set. */ 654 #define ATBREPLICATOR_CLAIMCLR_BIT_2_Clear (0x1UL) /*!< Clear claim bit 2. */ 655 656 /* Bit 1 : Read or clear claim bit 1. */ 657 #define ATBREPLICATOR_CLAIMCLR_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */ 658 #define ATBREPLICATOR_CLAIMCLR_BIT_1_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */ 659 #define ATBREPLICATOR_CLAIMCLR_BIT_1_Cleared (0x0UL) /*!< Claim bit 1 is not set. */ 660 #define ATBREPLICATOR_CLAIMCLR_BIT_1_Set (0x1UL) /*!< Claim bit 1 is set. */ 661 #define ATBREPLICATOR_CLAIMCLR_BIT_1_Clear (0x1UL) /*!< Clear claim bit 1. */ 662 663 /* Bit 0 : Read or clear claim bit 0. */ 664 #define ATBREPLICATOR_CLAIMCLR_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */ 665 #define ATBREPLICATOR_CLAIMCLR_BIT_0_Msk (0x1UL << ATBREPLICATOR_CLAIMCLR_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */ 666 #define ATBREPLICATOR_CLAIMCLR_BIT_0_Cleared (0x0UL) /*!< Claim bit 0 is not set. */ 667 #define ATBREPLICATOR_CLAIMCLR_BIT_0_Set (0x1UL) /*!< Claim bit 0 is set. */ 668 #define ATBREPLICATOR_CLAIMCLR_BIT_0_Clear (0x1UL) /*!< Clear claim bit 0. */ 669 670 /* Register: ATBREPLICATOR_LAR */ 671 /* Description: This is used to enable write access to device registers. */ 672 673 /* Bits 31..0 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. */ 674 #define ATBREPLICATOR_LAR_ACCESS_Pos (0UL) /*!< Position of ACCESS field. */ 675 #define ATBREPLICATOR_LAR_ACCESS_Msk (0xFFFFFFFFUL << ATBREPLICATOR_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field. */ 676 #define ATBREPLICATOR_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface. */ 677 678 /* Register: ATBREPLICATOR_LSR */ 679 /* Description: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. 680 Accesses to the extended stimulus port registers are not affected by the lock mechanism. 681 This register must always be present although there might not be any lock access control mechanism. 682 The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. 683 For most components this covers all registers except for the Lock Access Register. */ 684 685 /* Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */ 686 #define ATBREPLICATOR_LSR_TYPE_Pos (2UL) /*!< Position of TYPE field. */ 687 #define ATBREPLICATOR_LSR_TYPE_Msk (0x1UL << ATBREPLICATOR_LSR_TYPE_Pos) /*!< Bit mask of TYPE field. */ 688 #define ATBREPLICATOR_LSR_TYPE_Bits32 (0x0UL) /*!< This component implements a 32-bit Lock Access Register. */ 689 #define ATBREPLICATOR_LSR_TYPE_Bits8 (0x1UL) /*!< This component implements an 8-bit Lock Access Register. */ 690 691 /* Bit 1 : Returns the current status of the Lock. */ 692 #define ATBREPLICATOR_LSR_LOCKED_Pos (1UL) /*!< Position of LOCKED field. */ 693 #define ATBREPLICATOR_LSR_LOCKED_Msk (0x1UL << ATBREPLICATOR_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ 694 #define ATBREPLICATOR_LSR_LOCKED_UnLocked (0x0UL) /*!< Write access is allowed to this device. */ 695 #define ATBREPLICATOR_LSR_LOCKED_Locked (0x1UL) /*!< Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. */ 696 697 /* Bit 0 : Indicates that a lock control mechanism exists for this device. */ 698 #define ATBREPLICATOR_LSR_PRESENT_Pos (0UL) /*!< Position of PRESENT field. */ 699 #define ATBREPLICATOR_LSR_PRESENT_Msk (0x1UL << ATBREPLICATOR_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ 700 #define ATBREPLICATOR_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access Register are ignored. */ 701 #define ATBREPLICATOR_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present. */ 702 703 /* Register: ATBREPLICATOR_AUTHSTATUS */ 704 /* Description: Indicates the current level of tracing permitted by the system */ 705 706 /* Bits 7..6 : Secure Non-Invasive Debug */ 707 #define ATBREPLICATOR_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ 708 #define ATBREPLICATOR_AUTHSTATUS_SNID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ 709 #define ATBREPLICATOR_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 710 #define ATBREPLICATOR_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */ 711 712 /* Bits 5..4 : Secure Invasive Debug */ 713 #define ATBREPLICATOR_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ 714 #define ATBREPLICATOR_AUTHSTATUS_SID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ 715 #define ATBREPLICATOR_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 716 #define ATBREPLICATOR_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */ 717 718 /* Bits 3..2 : Non-secure Non-Invasive Debug */ 719 #define ATBREPLICATOR_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ 720 #define ATBREPLICATOR_AUTHSTATUS_NSNID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ 721 #define ATBREPLICATOR_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 722 #define ATBREPLICATOR_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */ 723 724 /* Bits 1..0 : Non-secure Invasive Debug */ 725 #define ATBREPLICATOR_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ 726 #define ATBREPLICATOR_AUTHSTATUS_NSID_Msk (0x3UL << ATBREPLICATOR_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ 727 #define ATBREPLICATOR_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 728 #define ATBREPLICATOR_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */ 729 730 /* Register: ATBREPLICATOR_DEVID */ 731 /* Description: Indicates the capabilities of the component. */ 732 733 /* Bits 3..0 : Indicates the number of master ports implemented. */ 734 #define ATBREPLICATOR_DEVID_PORTNUM_Pos (0UL) /*!< Position of PORTNUM field. */ 735 #define ATBREPLICATOR_DEVID_PORTNUM_Msk (0xFUL << ATBREPLICATOR_DEVID_PORTNUM_Pos) /*!< Bit mask of PORTNUM field. */ 736 737 /* Register: ATBREPLICATOR_DEVTYPE */ 738 /* Description: The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. */ 739 740 /* Bits 7..4 : The sub-type of the component */ 741 #define ATBREPLICATOR_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ 742 #define ATBREPLICATOR_DEVTYPE_SUB_Msk (0xFUL << ATBREPLICATOR_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ 743 #define ATBREPLICATOR_DEVTYPE_SUB_Replicator (0x2UL) /*!< Indicates that this component replicates trace from a single source to multiple targets. */ 744 745 /* Bits 3..0 : The main type of the component */ 746 #define ATBREPLICATOR_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ 747 #define ATBREPLICATOR_DEVTYPE_MAJOR_Msk (0xFUL << ATBREPLICATOR_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ 748 #define ATBREPLICATOR_DEVTYPE_MAJOR_InputOutputDevice (0x2UL) /*!< Indicates that this component has ATB inputs and outputs. */ 749 750 751 /* Peripheral: CC_AES */ 752 /* Description: CRYPTOCELL AES engine */ 753 754 /* Register: CC_AES_AES_KEY_0 */ 755 /* Description: Description collection: AES key value to use. 756 The initial AES_KEY_0[0] register holds the least significant bits [31:0] of the key value. */ 757 758 /* Bits 31..0 : AES key value. */ 759 #define CC_AES_AES_KEY_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 760 #define CC_AES_AES_KEY_0_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_KEY_0_VALUE_Pos) /*!< Bit mask of VALUE field. */ 761 762 /* Register: CC_AES_AES_IV_0 */ 763 /* Description: Description collection: AES Initialization Vector (IV) to use. 764 The initial AES_IV_0[0] register holds the least significant bits [31:0] of the IV. */ 765 766 /* Bits 31..0 : AES non-tunneling or first tunnel stage IV value. */ 767 #define CC_AES_AES_IV_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 768 #define CC_AES_AES_IV_0_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_IV_0_VALUE_Pos) /*!< Bit mask of VALUE field. */ 769 770 /* Register: CC_AES_AES_CTR */ 771 /* Description: Description collection: AES counter (CTR) to use. 772 The initial AES_CTR[0] register holds the least significant bits [31:0] of the CTR. */ 773 774 /* Bits 31..0 : AES CTR value. */ 775 #define CC_AES_AES_CTR_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 776 #define CC_AES_AES_CTR_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_CTR_VALUE_Pos) /*!< Bit mask of VALUE field. */ 777 778 /* Register: CC_AES_AES_BUSY */ 779 /* Description: Status register for AES engine activity. */ 780 781 /* Bit 0 : AES engine status. */ 782 #define CC_AES_AES_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 783 #define CC_AES_AES_BUSY_STATUS_Msk (0x1UL << CC_AES_AES_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 784 #define CC_AES_AES_BUSY_STATUS_Idle (0x0UL) /*!< AES engine is idle */ 785 #define CC_AES_AES_BUSY_STATUS_Busy (0x1UL) /*!< AES engine is busy */ 786 787 /* Register: CC_AES_AES_SK */ 788 /* Description: Writing to this address trigger sampling of the HW key to the AES_KEY_0 register */ 789 790 /* Bit 0 : Sample HW key to AES_KEY_0 registers. */ 791 #define CC_AES_AES_SK_AES_SK_Pos (0UL) /*!< Position of AES_SK field. */ 792 #define CC_AES_AES_SK_AES_SK_Msk (0x1UL << CC_AES_AES_SK_AES_SK_Pos) /*!< Bit mask of AES_SK field. */ 793 794 /* Register: CC_AES_AES_CMAC_INIT */ 795 /* Description: Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations. */ 796 797 /* Bit 0 : Generate K1 and K2 for the AES-CMAC operations. */ 798 #define CC_AES_AES_CMAC_INIT_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 799 #define CC_AES_AES_CMAC_INIT_ENABLE_Msk (0x1UL << CC_AES_AES_CMAC_INIT_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 800 #define CC_AES_AES_CMAC_INIT_ENABLE_Enable (0x1UL) /*!< Initialize AES-CMAC operations. */ 801 802 /* Register: CC_AES_AES_REMAINING_BYTES */ 803 /* Description: This register should be set with the amount of remaining bytes until the end of the current AES operation. */ 804 805 /* Bits 31..0 : Remaining bytes util the end of the current AES operation. */ 806 #define CC_AES_AES_REMAINING_BYTES_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 807 #define CC_AES_AES_REMAINING_BYTES_VALUE_Msk (0xFFFFFFFFUL << CC_AES_AES_REMAINING_BYTES_VALUE_Pos) /*!< Bit mask of VALUE field. */ 808 809 /* Register: CC_AES_AES_CONTROL */ 810 /* Description: Control the AES engine behavior. */ 811 812 /* Bit 31 : Using direct access and not the DIN-DOUT DMA interface */ 813 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Pos (31UL) /*!< Position of DIRECT_ACCESS field. */ 814 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Msk (0x1UL << CC_AES_AES_CONTROL_DIRECT_ACCESS_Pos) /*!< Bit mask of DIRECT_ACCESS field. */ 815 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Disable (0x0UL) /*!< Access using the DIN-DOUT DMA interface */ 816 #define CC_AES_AES_CONTROL_DIRECT_ACCESS_Enable (0x1UL) /*!< Access using direct access */ 817 818 /* Bit 29 : This field determines the value that is written to AES_KEY_0, when AES_SK is kicked. */ 819 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Pos (29UL) /*!< Position of AES_XOR_CRYPTOKEY field. */ 820 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Msk (0x1UL << CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Pos) /*!< Bit mask of AES_XOR_CRYPTOKEY field. */ 821 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Disable (0x0UL) /*!< The value that is written to AES_KEY_0 is the value of the HW cryptokey as is. */ 822 #define CC_AES_AES_CONTROL_AES_XOR_CRYPTOKEY_Enable (0x1UL) /*!< The value that is written to AES_KEY_0 is the value of the HW cryptokey XOR with the current value of AES_KEY_0. */ 823 824 /* Bits 13..12 : Set the AES key length. */ 825 #define CC_AES_AES_CONTROL_NK_KEY0_Pos (12UL) /*!< Position of NK_KEY0 field. */ 826 #define CC_AES_AES_CONTROL_NK_KEY0_Msk (0x3UL << CC_AES_AES_CONTROL_NK_KEY0_Pos) /*!< Bit mask of NK_KEY0 field. */ 827 #define CC_AES_AES_CONTROL_NK_KEY0_128Bits (0x0UL) /*!< 128 bits key length */ 828 829 /* Bits 4..2 : Set the AES mode. */ 830 #define CC_AES_AES_CONTROL_MODE_KEY0_Pos (2UL) /*!< Position of MODE_KEY0 field. */ 831 #define CC_AES_AES_CONTROL_MODE_KEY0_Msk (0x7UL << CC_AES_AES_CONTROL_MODE_KEY0_Pos) /*!< Bit mask of MODE_KEY0 field. */ 832 #define CC_AES_AES_CONTROL_MODE_KEY0_ECB (0x0UL) /*!< Electronic codebook mode */ 833 #define CC_AES_AES_CONTROL_MODE_KEY0_CBC (0x1UL) /*!< Cipher block chaining mode */ 834 #define CC_AES_AES_CONTROL_MODE_KEY0_CTR (0x2UL) /*!< Counter mode */ 835 #define CC_AES_AES_CONTROL_MODE_KEY0_CBC_MAC (0x3UL) /*!< Cipher Block Chaining Message Authentication Code */ 836 #define CC_AES_AES_CONTROL_MODE_KEY0_CMAC (0x7UL) /*!< Cipher-based Message Authentication Code */ 837 838 /* Bit 0 : Set AES encrypt or decrypt mode in non-tunneling operations. */ 839 #define CC_AES_AES_CONTROL_DEC_KEY0_Pos (0UL) /*!< Position of DEC_KEY0 field. */ 840 #define CC_AES_AES_CONTROL_DEC_KEY0_Msk (0x1UL << CC_AES_AES_CONTROL_DEC_KEY0_Pos) /*!< Bit mask of DEC_KEY0 field. */ 841 #define CC_AES_AES_CONTROL_DEC_KEY0_Encrypt (0x0UL) /*!< Perform AES encryption */ 842 #define CC_AES_AES_CONTROL_DEC_KEY0_Decrypt (0x1UL) /*!< Perform AES decryption */ 843 844 /* Register: CC_AES_AES_HW_FLAGS */ 845 /* Description: Hardware configuration of the AES engine. Reset value holds the supported features. */ 846 847 /* Bit 12 : If this flag is set, the engine support DFA countermeasures. */ 848 #define CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Pos (12UL) /*!< Position of DFA_CNTRMSR_EXIST field. */ 849 #define CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_Pos) /*!< Bit mask of DFA_CNTRMSR_EXIST field. */ 850 851 /* Bit 11 : If this flag is set, the engine support a second register set for tunneling operations. */ 852 #define CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Pos (11UL) /*!< Position of SECOND_REGS_SET_EXIST field. */ 853 #define CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_Pos) /*!< Bit mask of SECOND_REGS_SET_EXIST field. */ 854 855 /* Bit 10 : If this flag is set, the engine support tunneling operations. */ 856 #define CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Pos (10UL) /*!< Position of AES_TUNNEL_EXIST field. */ 857 #define CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_TUNNEL_EXIST_Pos) /*!< Bit mask of AES_TUNNEL_EXIST field. */ 858 859 /* Bit 9 : If this flag is set, the engine contains the PREV_IV register for faster AES XCBC MAC calculation. */ 860 #define CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Pos (9UL) /*!< Position of AES_SUPPORT_PREV_IV field. */ 861 #define CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_Pos) /*!< Bit mask of AES_SUPPORT_PREV_IV field. */ 862 863 /* Bit 8 : If this flag is set, the engine uses 5 SBOX where each AES round takes 4 cycles. */ 864 #define CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Pos (8UL) /*!< Position of USE_5_SBOXES field. */ 865 #define CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Msk (0x1UL << CC_AES_AES_HW_FLAGS_USE_5_SBOXES_Pos) /*!< Bit mask of USE_5_SBOXES field. */ 866 867 /* Bit 5 : If this flag is set, the engine uses SBOX tables. */ 868 #define CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Pos (5UL) /*!< Position of USE_SBOX_TABLE field. */ 869 #define CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Msk (0x1UL << CC_AES_AES_HW_FLAGS_USE_SBOX_TABLE_Pos) /*!< Bit mask of USE_SBOX_TABLE field. */ 870 871 /* Bit 4 : If this flag is set, the engine only support encrypt operations. */ 872 #define CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Pos (4UL) /*!< Position of ONLY_ENCRYPT field. */ 873 #define CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Msk (0x1UL << CC_AES_AES_HW_FLAGS_ONLY_ENCRYPT_Pos) /*!< Bit mask of ONLY_ENCRYPT field. */ 874 875 /* Bit 3 : If this flag is set, the engine support AES CTR mode. */ 876 #define CC_AES_AES_HW_FLAGS_CTR_EXIST_Pos (3UL) /*!< Position of CTR_EXIST field. */ 877 #define CC_AES_AES_HW_FLAGS_CTR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_CTR_EXIST_Pos) /*!< Bit mask of CTR_EXIST field. */ 878 879 /* Bit 2 : If this flag is set, the engine support DPA countermeasures. */ 880 #define CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Pos (2UL) /*!< Position of DPA_CNTRMSR_EXIST field. */ 881 #define CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Msk (0x1UL << CC_AES_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_Pos) /*!< Bit mask of DPA_CNTRMSR_EXIST field. */ 882 883 /* Bit 1 : If this flag is set, the engine support AES_LARGE_RKEK. */ 884 #define CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Pos (1UL) /*!< Position of AES_LARGE_RKEK field. */ 885 #define CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Msk (0x1UL << CC_AES_AES_HW_FLAGS_AES_LARGE_RKEK_Pos) /*!< Bit mask of AES_LARGE_RKEK field. */ 886 887 /* Bit 0 : If this flag is set, the engine support 192 bits and 256 bits key size. */ 888 #define CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Pos (0UL) /*!< Position of SUPPORT_256_192_KEY field. */ 889 #define CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Msk (0x1UL << CC_AES_AES_HW_FLAGS_SUPPORT_256_192_KEY_Pos) /*!< Bit mask of SUPPORT_256_192_KEY field. */ 890 891 /* Register: CC_AES_AES_CTR_NO_INCREMENT */ 892 /* Description: This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks */ 893 894 /* Bit 0 : This field enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks */ 895 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 896 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Msk (0x1UL << CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 897 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Disable (0x0UL) /*!< Counter always incremented between blocks */ 898 #define CC_AES_AES_CTR_NO_INCREMENT_ENABLE_Enable (0x1UL) /*!< Do not increment counter between blocks */ 899 900 /* Register: CC_AES_AES_SW_RESET */ 901 /* Description: Reset the AES engine. */ 902 903 /* Bit 0 : Writing any value to this address resets the AES engine. The reset takes 4 CPU clock cycles to complete. */ 904 #define CC_AES_AES_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 905 #define CC_AES_AES_SW_RESET_RESET_Msk (0x1UL << CC_AES_AES_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 906 #define CC_AES_AES_SW_RESET_RESET_Enable (0x1UL) /*!< Reset AES engine. */ 907 908 /* Register: CC_AES_AES_CMAC_SIZE0_KICK */ 909 /* Description: Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register. */ 910 911 /* Bit 0 : Force AES CMAC operation with size 0. */ 912 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 913 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Msk (0x1UL << CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 914 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Disable (0x0UL) /*!< Normal AES CMAC operation */ 915 #define CC_AES_AES_CMAC_SIZE0_KICK_ENABLE_Enable (0x1UL) /*!< Force CMAC operation with size 0 */ 916 917 918 /* Peripheral: CC_AHB */ 919 /* Description: CRYPTOCELL AHB interface */ 920 921 /* Register: CC_AHB_AHBM_SINGLES */ 922 /* Description: This register forces the AHB transactions from CRYPTOCELL master to be always singles. */ 923 924 /* Bit 0 : Force AHB singles */ 925 #define CC_AHB_AHBM_SINGLES_AHB_SINGLES_Pos (0UL) /*!< Position of AHB_SINGLES field. */ 926 #define CC_AHB_AHBM_SINGLES_AHB_SINGLES_Msk (0x1UL << CC_AHB_AHBM_SINGLES_AHB_SINGLES_Pos) /*!< Bit mask of AHB_SINGLES field. */ 927 928 /* Register: CC_AHB_AHBM_HPROT */ 929 /* Description: This register holds the AHB HPROT value */ 930 931 /* Bits 3..0 : The AHB HPROT value */ 932 #define CC_AHB_AHBM_HPROT_AHB_HPROT_Pos (0UL) /*!< Position of AHB_HPROT field. */ 933 #define CC_AHB_AHBM_HPROT_AHB_HPROT_Msk (0xFUL << CC_AHB_AHBM_HPROT_AHB_HPROT_Pos) /*!< Bit mask of AHB_HPROT field. */ 934 935 /* Register: CC_AHB_AHBM_HMASTLOCK */ 936 /* Description: This register holds AHB HMASTLOCK value */ 937 938 /* Bit 0 : The AHB HMASTLOCK value. */ 939 #define CC_AHB_AHBM_HMASTLOCK_AHB_HMASTLOCK_Pos (0UL) /*!< Position of AHB_HMASTLOCK field. */ 940 #define CC_AHB_AHBM_HMASTLOCK_AHB_HMASTLOCK_Msk (0x1UL << CC_AHB_AHBM_HMASTLOCK_AHB_HMASTLOCK_Pos) /*!< Bit mask of AHB_HMASTLOCK field. */ 941 942 /* Register: CC_AHB_AHBM_HNONSEC */ 943 /* Description: This register holds AHB HNONSEC value */ 944 945 /* Bit 1 : The AHB HNONSEC value for read transaction. */ 946 #define CC_AHB_AHBM_HNONSEC_AHB_READ_HNONSEC_Pos (1UL) /*!< Position of AHB_READ_HNONSEC field. */ 947 #define CC_AHB_AHBM_HNONSEC_AHB_READ_HNONSEC_Msk (0x1UL << CC_AHB_AHBM_HNONSEC_AHB_READ_HNONSEC_Pos) /*!< Bit mask of AHB_READ_HNONSEC field. */ 948 949 /* Bit 0 : The AHB HNONSEC value for write transaction. */ 950 #define CC_AHB_AHBM_HNONSEC_AHB_WRITE_HNONSEC_Pos (0UL) /*!< Position of AHB_WRITE_HNONSEC field. */ 951 #define CC_AHB_AHBM_HNONSEC_AHB_WRITE_HNONSEC_Msk (0x1UL << CC_AHB_AHBM_HNONSEC_AHB_WRITE_HNONSEC_Pos) /*!< Bit mask of AHB_WRITE_HNONSEC field. */ 952 953 954 /* Peripheral: CC_CHACHA */ 955 /* Description: CRYPTOCELL CHACHA engine */ 956 957 /* Register: CC_CHACHA_CHACHA_CONTROL */ 958 /* Description: Control the CHACHA engine behavior. */ 959 960 /* Bit 10 : Use 96 bits Initialization Vector (IV) */ 961 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Pos (10UL) /*!< Position of USE_IV_96BIT field. */ 962 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Pos) /*!< Bit mask of USE_IV_96BIT field. */ 963 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Disable (0x0UL) /*!< Use default size IV of 64 bit */ 964 #define CC_CHACHA_CHACHA_CONTROL_USE_IV_96BIT_Enable (0x1UL) /*!< The IV is 96 bits */ 965 966 /* Bit 9 : Reset block counter for new messages */ 967 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Pos (9UL) /*!< Position of RESET_BLOCK_CNT field. */ 968 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Pos) /*!< Bit mask of RESET_BLOCK_CNT field. */ 969 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Disable (0x0UL) /*!< Use current block counter value */ 970 #define CC_CHACHA_CHACHA_CONTROL_RESET_BLOCK_CNT_Enable (0x1UL) /*!< Reset block counter value to zero */ 971 972 /* Bits 5..4 : Set number of permutation rounds, default value is 20. */ 973 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Pos (4UL) /*!< Position of NUM_OF_ROUNDS field. */ 974 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Msk (0x3UL << CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Pos) /*!< Bit mask of NUM_OF_ROUNDS field. */ 975 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_Default (0x0UL) /*!< Use 20 rounds of rotation (default) */ 976 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_12Rounds (0x1UL) /*!< Use 12 rounds of rotation */ 977 #define CC_CHACHA_CHACHA_CONTROL_NUM_OF_ROUNDS_8Rounds (0x2UL) /*!< Use 8 rounds of rotation */ 978 979 /* Bit 3 : Key length selection. */ 980 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Pos (3UL) /*!< Position of KEY_LEN field. */ 981 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_KEY_LEN_Pos) /*!< Bit mask of KEY_LEN field. */ 982 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_256Bits (0x0UL) /*!< Use 256 bits key length */ 983 #define CC_CHACHA_CHACHA_CONTROL_KEY_LEN_128Bits (0x1UL) /*!< Use 128 bits key length */ 984 985 /* Bit 2 : Generate the key to use in Poly1305 message authentication code calculation. */ 986 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Pos (2UL) /*!< Position of GEN_KEY_POLY1305 field. */ 987 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Pos) /*!< Bit mask of GEN_KEY_POLY1305 field. */ 988 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Disable (0x0UL) /*!< Do not generate Poly1305 key */ 989 #define CC_CHACHA_CHACHA_CONTROL_GEN_KEY_POLY1305_Enable (0x1UL) /*!< Generate Poly1305 key */ 990 991 /* Bit 1 : Perform initialization for a new message */ 992 #define CC_CHACHA_CHACHA_CONTROL_INIT_Pos (1UL) /*!< Position of INIT field. */ 993 #define CC_CHACHA_CHACHA_CONTROL_INIT_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_INIT_Pos) /*!< Bit mask of INIT field. */ 994 #define CC_CHACHA_CHACHA_CONTROL_INIT_Disable (0x0UL) /*!< Message already initialized */ 995 #define CC_CHACHA_CHACHA_CONTROL_INIT_Enable (0x1UL) /*!< Initialize new message */ 996 997 /* Bit 0 : Run engine in ChaCha or Salsa mode */ 998 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Pos (0UL) /*!< Position of CHACHA_OR_SALSA field. */ 999 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Msk (0x1UL << CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Pos) /*!< Bit mask of CHACHA_OR_SALSA field. */ 1000 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_ChaCha (0x0UL) /*!< Run engine in ChaCha mode */ 1001 #define CC_CHACHA_CHACHA_CONTROL_CHACHA_OR_SALSA_Salsa (0x1UL) /*!< Run engine in Salsa mode */ 1002 1003 /* Register: CC_CHACHA_CHACHA_VERSION */ 1004 /* Description: CHACHA engine HW version */ 1005 1006 /* Bits 31..0 : */ 1007 #define CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Pos (0UL) /*!< Position of CHACHA_VERSION field. */ 1008 #define CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_VERSION_CHACHA_VERSION_Pos) /*!< Bit mask of CHACHA_VERSION field. */ 1009 1010 /* Register: CC_CHACHA_CHACHA_KEY */ 1011 /* Description: Description collection: CHACHA key value to use. The initial CHACHA_KEY[0] register holds the least significant bits [31:0] of the key value. */ 1012 1013 /* Bits 31..0 : CHACHA key value. */ 1014 #define CC_CHACHA_CHACHA_KEY_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 1015 #define CC_CHACHA_CHACHA_KEY_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_KEY_VALUE_Pos) /*!< Bit mask of VALUE field. */ 1016 1017 /* Register: CC_CHACHA_CHACHA_IV */ 1018 /* Description: Description collection: CHACHA Initialization Vector (IV) to use. The IV is also known as the nonce. */ 1019 1020 /* Bits 31..0 : CHACHA IV value. */ 1021 #define CC_CHACHA_CHACHA_IV_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 1022 #define CC_CHACHA_CHACHA_IV_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_IV_VALUE_Pos) /*!< Bit mask of VALUE field. */ 1023 1024 /* Register: CC_CHACHA_CHACHA_BUSY */ 1025 /* Description: Status register for CHACHA engine activity. */ 1026 1027 /* Bit 0 : CHACHA engine status. */ 1028 #define CC_CHACHA_CHACHA_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1029 #define CC_CHACHA_CHACHA_BUSY_STATUS_Msk (0x1UL << CC_CHACHA_CHACHA_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1030 #define CC_CHACHA_CHACHA_BUSY_STATUS_Idle (0x0UL) /*!< CHACHA engine is idle */ 1031 #define CC_CHACHA_CHACHA_BUSY_STATUS_Busy (0x1UL) /*!< CHACHA engine is busy */ 1032 1033 /* Register: CC_CHACHA_CHACHA_HW_FLAGS */ 1034 /* Description: Hardware configuration of the CHACHA engine. Reset value holds the supported features. */ 1035 1036 /* Bit 2 : If this flag is set, the next matrix calculated when the current one is written to data output path. */ 1037 #define CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Pos (2UL) /*!< Position of FAST_CHACHA field. */ 1038 #define CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_FAST_CHACHA_Pos) /*!< Bit mask of FAST_CHACHA field. */ 1039 1040 /* Bit 1 : If this flag is set, the engine include Salsa support */ 1041 #define CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Pos (1UL) /*!< Position of SALSA_EXISTS field. */ 1042 #define CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_SALSA_EXISTS_Pos) /*!< Bit mask of SALSA_EXISTS field. */ 1043 1044 /* Bit 0 : If this flag is set, the engine include ChaCha support */ 1045 #define CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Pos (0UL) /*!< Position of CHACHA_EXISTS field. */ 1046 #define CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Msk (0x1UL << CC_CHACHA_CHACHA_HW_FLAGS_CHACHA_EXISTS_Pos) /*!< Bit mask of CHACHA_EXISTS field. */ 1047 1048 /* Register: CC_CHACHA_CHACHA_BLOCK_CNT_LSB */ 1049 /* Description: Store the LSB value of the block counter, in order to support suspend/resume of operation */ 1050 1051 /* Bits 31..0 : This register holds the ChaCha block counter bits [31:0] and must be read and written during respectively suspend and resume operations. */ 1052 #define CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 1053 #define CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_BLOCK_CNT_LSB_VALUE_Pos) /*!< Bit mask of VALUE field. */ 1054 1055 /* Register: CC_CHACHA_CHACHA_BLOCK_CNT_MSB */ 1056 /* Description: Store the MSB value of the block counter, in order to support suspend/resume of operation */ 1057 1058 /* Bits 31..0 : This register holds the ChaCha block counter bits [63:32] and must be read and written during respectively suspend and resume operations. */ 1059 #define CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 1060 #define CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_BLOCK_CNT_MSB_VALUE_Pos) /*!< Bit mask of VALUE field. */ 1061 1062 /* Register: CC_CHACHA_CHACHA_SW_RESET */ 1063 /* Description: Reset the CHACHA engine. */ 1064 1065 /* Bit 0 : Writing any value to this address resets the CHACHA engine. The reset takes 4 CPU clock cycles to complete. */ 1066 #define CC_CHACHA_CHACHA_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 1067 #define CC_CHACHA_CHACHA_SW_RESET_RESET_Msk (0x1UL << CC_CHACHA_CHACHA_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 1068 #define CC_CHACHA_CHACHA_SW_RESET_RESET_Enable (0x1UL) /*!< Reset CHACHA engine. */ 1069 1070 /* Register: CC_CHACHA_CHACHA_POLY1305_KEY */ 1071 /* Description: Description collection: The auto-generated key to use in Poly1305 MAC calculation. The initial CHACHA_POLY1305_KEY[0] register holds the least significant bits [31:0] of the key value. */ 1072 1073 /* Bits 31..0 : Poly1305 key value. */ 1074 #define CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 1075 #define CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Msk (0xFFFFFFFFUL << CC_CHACHA_CHACHA_POLY1305_KEY_VALUE_Pos) /*!< Bit mask of VALUE field. */ 1076 1077 /* Register: CC_CHACHA_CHACHA_ENDIANNESS */ 1078 /* Description: CHACHA engine data order configuration. */ 1079 1080 /* Bit 4 : Change the byte order of the output data. */ 1081 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Pos (4UL) /*!< Position of CHACHA_DOUT_BYTE_ORDER field. */ 1082 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Pos) /*!< Bit mask of CHACHA_DOUT_BYTE_ORDER field. */ 1083 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Default (0x0UL) /*!< Use default byte order within each output word, where bytes are ordered as follows: B0, B1, B2, B3. */ 1084 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_BYTE_ORDER_Reverse (0x1UL) /*!< Reverse the byte order within each output word, where bytes are re-ordered as follows: B3, B2, B1, B0. */ 1085 1086 /* Bit 3 : Change the word order of the output data. */ 1087 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Pos (3UL) /*!< Position of CHACHA_DOUT_WORD_ORDER field. */ 1088 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Pos) /*!< Bit mask of CHACHA_DOUT_WORD_ORDER field. */ 1089 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Default (0x0UL) /*!< Uses default word order for 128-bits output, where words are ordered as follows: w0, w1, w2, w3. */ 1090 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DOUT_WORD_ORDER_Reverse (0x1UL) /*!< Reverse the word order for 128-bits output, where words are re-ordered as follows: w3, w2, w1, w0. */ 1091 1092 /* Bit 2 : Change the quarter of a matrix order in the engine. */ 1093 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Pos (2UL) /*!< Position of CHACHA_CORE_MATRIX_LBE_ORDER field. */ 1094 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Pos) /*!< Bit mask of CHACHA_CORE_MATRIX_LBE_ORDER field. */ 1095 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Default (0x0UL) /*!< Use default quarter of matrix order, where quarters are ordered as follows: q0, q1, q2, q3. Each quarter represents a 128-bits section of the matrix. */ 1096 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_CORE_MATRIX_LBE_ORDER_Reverse (0x1UL) /*!< Reverse the order of matrix quarters, where quarters are re-ordered as follows: q3, q2, q1, q0. Each quarter represents a 128-bits section of the matrix. */ 1097 1098 /* Bit 1 : Change the byte order of the input data. */ 1099 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Pos (1UL) /*!< Position of CHACHA_DIN_BYTE_ORDER field. */ 1100 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Pos) /*!< Bit mask of CHACHA_DIN_BYTE_ORDER field. */ 1101 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Default (0x0UL) /*!< Use default byte order within each input word, where bytes are ordered as follows: B0, B1, B2, B3. */ 1102 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_BYTE_ORDER_Reverse (0x1UL) /*!< Reverse the byte order within each input word, where bytes are re-ordered as follows: B3, B2, B1, B0. */ 1103 1104 /* Bit 0 : Change the word order of the input data. */ 1105 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Pos (0UL) /*!< Position of CHACHA_DIN_WORD_ORDER field. */ 1106 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Msk (0x1UL << CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Pos) /*!< Bit mask of CHACHA_DIN_WORD_ORDER field. */ 1107 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Default (0x0UL) /*!< Use default word order for 128-bits input, where words are ordered as follows: w0, w1, w2, w3. */ 1108 #define CC_CHACHA_CHACHA_ENDIANNESS_CHACHA_DIN_WORD_ORDER_Reverse (0x1UL) /*!< Reverses the word order for 128-bits input, where words are re-ordered as follows: w3, w2, w1, w0. */ 1109 1110 /* Register: CC_CHACHA_CHACHA_DEBUG */ 1111 /* Description: Debug register for the CHACHA engine */ 1112 1113 /* Bits 1..0 : Reflects the debug state of the CHACHA FSM. */ 1114 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Pos (0UL) /*!< Position of FSM_STATE field. */ 1115 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Msk (0x3UL << CC_CHACHA_CHACHA_DEBUG_FSM_STATE_Pos) /*!< Bit mask of FSM_STATE field. */ 1116 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_IDLE_STATE (0x0UL) /*!< CHACHA FSM is in idle state */ 1117 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_INIT_STATE (0x1UL) /*!< CHACHA FSM is in init state */ 1118 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_ROUNDS_STATE (0x2UL) /*!< CHACHA FSM is in rounds state */ 1119 #define CC_CHACHA_CHACHA_DEBUG_FSM_STATE_FINAL_STATE (0x3UL) /*!< CHACHA FSM is in final state */ 1120 1121 1122 /* Peripheral: CC_CTL */ 1123 /* Description: CRYPTOCELL CTL interface */ 1124 1125 /* Register: CC_CTL_CRYPTO_CTL */ 1126 /* Description: Defines the cryptographic flow. */ 1127 1128 /* Bits 4..0 : Configure the cryptographic engine mode. */ 1129 #define CC_CTL_CRYPTO_CTL_MODE_Pos (0UL) /*!< Position of MODE field. */ 1130 #define CC_CTL_CRYPTO_CTL_MODE_Msk (0x1FUL << CC_CTL_CRYPTO_CTL_MODE_Pos) /*!< Bit mask of MODE field. */ 1131 #define CC_CTL_CRYPTO_CTL_MODE_Bypass (0x00UL) /*!< Bypass cryptographic engine */ 1132 #define CC_CTL_CRYPTO_CTL_MODE_AESActive (0x01UL) /*!< Use AES engine */ 1133 #define CC_CTL_CRYPTO_CTL_MODE_AESToHashActive (0x02UL) /*!< Pipe AES engine output to HASH engine input */ 1134 #define CC_CTL_CRYPTO_CTL_MODE_AESAndHashActive (0x03UL) /*!< Process input using both AES and HASH engine in parallell */ 1135 #define CC_CTL_CRYPTO_CTL_MODE_HashActive (0x07UL) /*!< Use HASH engine */ 1136 #define CC_CTL_CRYPTO_CTL_MODE_AESMACAndBypassActive (0x09UL) /*!< Calculate AES MAC and bypass */ 1137 #define CC_CTL_CRYPTO_CTL_MODE_AESToHashAndDOUTActive (0x0AUL) /*!< Pipe AES engine output to HASH engine input. The resulting digest output is piped to DOUT buffer. */ 1138 #define CC_CTL_CRYPTO_CTL_MODE_ChaChaActive (0x10UL) /*!< Use CHACHA engine */ 1139 1140 /* Register: CC_CTL_CRYPTO_BUSY */ 1141 /* Description: Status register for cryptographic cores engine activity. */ 1142 1143 /* Bit 0 : Cryptographic core engines status. */ 1144 #define CC_CTL_CRYPTO_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1145 #define CC_CTL_CRYPTO_BUSY_STATUS_Msk (0x1UL << CC_CTL_CRYPTO_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1146 #define CC_CTL_CRYPTO_BUSY_STATUS_Idle (0x0UL) /*!< Cryptographic core engines are idle */ 1147 #define CC_CTL_CRYPTO_BUSY_STATUS_Busy (0x1UL) /*!< Cryptographic core engines are busy */ 1148 1149 /* Register: CC_CTL_HASH_BUSY */ 1150 /* Description: Status register for HASH engine activity. */ 1151 1152 /* Bit 0 : Hash engine status. */ 1153 #define CC_CTL_HASH_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1154 #define CC_CTL_HASH_BUSY_STATUS_Msk (0x1UL << CC_CTL_HASH_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1155 #define CC_CTL_HASH_BUSY_STATUS_Idle (0x0UL) /*!< HASH engine is idle */ 1156 #define CC_CTL_HASH_BUSY_STATUS_Busy (0x1UL) /*!< HASH engine is busy */ 1157 1158 /* Register: CC_CTL_CONTEXT_ID */ 1159 /* Description: A general-purpose read/write register. */ 1160 1161 /* Bits 7..0 : Context ID */ 1162 #define CC_CTL_CONTEXT_ID_CONTEXT_ID_Pos (0UL) /*!< Position of CONTEXT_ID field. */ 1163 #define CC_CTL_CONTEXT_ID_CONTEXT_ID_Msk (0xFFUL << CC_CTL_CONTEXT_ID_CONTEXT_ID_Pos) /*!< Bit mask of CONTEXT_ID field. */ 1164 1165 1166 /* Peripheral: CC_DIN */ 1167 /* Description: CRYPTOCELL Data IN interface */ 1168 1169 /* Register: CC_DIN_DIN_BUFFER */ 1170 /* Description: Used by CPU to write data directly to the DIN buffer, which is then sent to the cryptographic engines for processing. */ 1171 1172 /* Bits 31..0 : This register is mapped into 8 addresses in order to enable a CPU burst. */ 1173 #define CC_DIN_DIN_BUFFER_DATA_Pos (0UL) /*!< Position of DATA field. */ 1174 #define CC_DIN_DIN_BUFFER_DATA_Msk (0xFFFFFFFFUL << CC_DIN_DIN_BUFFER_DATA_Pos) /*!< Bit mask of DATA field. */ 1175 1176 /* Register: CC_DIN_DIN_DMA_MEM_BUSY */ 1177 /* Description: Status register for DIN DMA engine activity when accessing memory. */ 1178 1179 /* Bit 0 : DIN memory DMA engine status. */ 1180 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1181 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Msk (0x1UL << CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1182 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Idle (0x0UL) /*!< DIN memory DMA engine is idle */ 1183 #define CC_DIN_DIN_DMA_MEM_BUSY_STATUS_Busy (0x1UL) /*!< DIN memory DMA engine is busy */ 1184 1185 /* Register: CC_DIN_SRC_MEM_ADDR */ 1186 /* Description: Data source address in memory. */ 1187 1188 /* Bits 31..0 : Source address in memory. */ 1189 #define CC_DIN_SRC_MEM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ 1190 #define CC_DIN_SRC_MEM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DIN_SRC_MEM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ 1191 1192 /* Register: CC_DIN_SRC_MEM_SIZE */ 1193 /* Description: The number of bytes to be read from memory. Writing to this register triggers the DMA operation. */ 1194 1195 /* Bit 31 : This field is reserved */ 1196 #define CC_DIN_SRC_MEM_SIZE_LAST_Pos (31UL) /*!< Position of LAST field. */ 1197 #define CC_DIN_SRC_MEM_SIZE_LAST_Msk (0x1UL << CC_DIN_SRC_MEM_SIZE_LAST_Pos) /*!< Bit mask of LAST field. */ 1198 1199 /* Bit 30 : This field is reserved */ 1200 #define CC_DIN_SRC_MEM_SIZE_FIRST_Pos (30UL) /*!< Position of FIRST field. */ 1201 #define CC_DIN_SRC_MEM_SIZE_FIRST_Msk (0x1UL << CC_DIN_SRC_MEM_SIZE_FIRST_Pos) /*!< Bit mask of FIRST field. */ 1202 1203 /* Bits 29..0 : Total number of bytes to read from memory. */ 1204 #define CC_DIN_SRC_MEM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ 1205 #define CC_DIN_SRC_MEM_SIZE_SIZE_Msk (0x3FFFFFFFUL << CC_DIN_SRC_MEM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ 1206 1207 /* Register: CC_DIN_SRC_SRAM_ADDR */ 1208 /* Description: Data source address in RNG SRAM. */ 1209 1210 /* Bits 31..0 : Source address in RNG SRAM. */ 1211 #define CC_DIN_SRC_SRAM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ 1212 #define CC_DIN_SRC_SRAM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DIN_SRC_SRAM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ 1213 1214 /* Register: CC_DIN_SRC_SRAM_SIZE */ 1215 /* Description: The number of bytes to be read from RNG SRAM. Writing to this register triggers the DMA operation. */ 1216 1217 /* Bits 31..0 : Total number of bytes to read from RNG SRAM. */ 1218 #define CC_DIN_SRC_SRAM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ 1219 #define CC_DIN_SRC_SRAM_SIZE_SIZE_Msk (0xFFFFFFFFUL << CC_DIN_SRC_SRAM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ 1220 1221 /* Register: CC_DIN_DIN_DMA_SRAM_BUSY */ 1222 /* Description: Status register for DIN DMA engine activity when accessing RNG SRAM. */ 1223 1224 /* Bit 0 : DIN RNG SRAM DMA engine status. */ 1225 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1226 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Msk (0x1UL << CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1227 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Idle (0x0UL) /*!< DIN RNG SRAM DMA engine is idle */ 1228 #define CC_DIN_DIN_DMA_SRAM_BUSY_STATUS_Busy (0x1UL) /*!< DIN RNG SRAM DMA engine is busy */ 1229 1230 /* Register: CC_DIN_DIN_DMA_SRAM_ENDIANNESS */ 1231 /* Description: Configure the endianness of DIN DMA transactions towards RNG SRAM. */ 1232 1233 /* Bit 0 : Endianness of DIN DMA transactions towards RNG SRAM. The default value is little-endian. */ 1234 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */ 1235 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 1236 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for RNG SRAM DMA transactions */ 1237 #define CC_DIN_DIN_DMA_SRAM_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for RNG SRAM DMA transactions */ 1238 1239 /* Register: CC_DIN_DIN_SW_RESET */ 1240 /* Description: Reset the DIN DMA engine. */ 1241 1242 /* Bit 0 : Writing any value to this address resets the DIN DMA engine. The reset takes 4 CPU clock cycles to complete. */ 1243 #define CC_DIN_DIN_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 1244 #define CC_DIN_DIN_SW_RESET_RESET_Msk (0x1UL << CC_DIN_DIN_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 1245 #define CC_DIN_DIN_SW_RESET_RESET_Enable (0x1UL) /*!< Reset DIN DMA engine. */ 1246 1247 /* Register: CC_DIN_DIN_CPU_DATA */ 1248 /* Description: Specifies the number of bytes the CPU will write to the DIN_BUFFER, ensuring the cryptographic engine processes the correct amount of data. */ 1249 1250 /* Bits 15..0 : When using CPU direct write to the DIN_BUFFER, the size of input data in bytes should be written to this register. */ 1251 #define CC_DIN_DIN_CPU_DATA_SIZE_Pos (0UL) /*!< Position of SIZE field. */ 1252 #define CC_DIN_DIN_CPU_DATA_SIZE_Msk (0xFFFFUL << CC_DIN_DIN_CPU_DATA_SIZE_Pos) /*!< Bit mask of SIZE field. */ 1253 1254 /* Register: CC_DIN_DIN_WRITE_ALIGN */ 1255 /* Description: Indicates that the next CPU write to the DIN_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). */ 1256 1257 /* Bit 0 : Next CPU write to the DIN_BUFFER is the last word. */ 1258 #define CC_DIN_DIN_WRITE_ALIGN_LAST_Pos (0UL) /*!< Position of LAST field. */ 1259 #define CC_DIN_DIN_WRITE_ALIGN_LAST_Msk (0x1UL << CC_DIN_DIN_WRITE_ALIGN_LAST_Pos) /*!< Bit mask of LAST field. */ 1260 #define CC_DIN_DIN_WRITE_ALIGN_LAST_Confirm (0x1UL) /*!< The next CPU write is the last in the sequence. */ 1261 1262 /* Register: CC_DIN_DIN_FIFO_EMPTY */ 1263 /* Description: Register indicating if DIN FIFO is empty and if more data can be accepted. */ 1264 1265 /* Bit 0 : DIN FIFO status */ 1266 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1267 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_Msk (0x1UL << CC_DIN_DIN_FIFO_EMPTY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1268 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_NotEmpty (0x0UL) /*!< DIN FIFO is not empty */ 1269 #define CC_DIN_DIN_FIFO_EMPTY_STATUS_Empty (0x1UL) /*!< DIN FIFO is empty, and more data can be accepted */ 1270 1271 /* Register: CC_DIN_DIN_FIFO_RESET */ 1272 /* Description: Reset the DIN FIFO, effectively clearing the FIFO for new data. */ 1273 1274 /* Bit 0 : Writing any value to this address resets the DIN FIFO. */ 1275 #define CC_DIN_DIN_FIFO_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 1276 #define CC_DIN_DIN_FIFO_RESET_RESET_Msk (0x1UL << CC_DIN_DIN_FIFO_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 1277 #define CC_DIN_DIN_FIFO_RESET_RESET_Enable (0x1UL) /*!< Reset DIN FIFO. */ 1278 1279 1280 /* Peripheral: CC_DOUT */ 1281 /* Description: CRYPTOCELL Data OUT interface */ 1282 1283 /* Register: CC_DOUT_DOUT_BUFFER */ 1284 /* Description: Cryptographic results directly accessible by the CPU. */ 1285 1286 /* Bits 31..0 : This address can be used by the CPU to read data directly from the DOUT buffer. */ 1287 #define CC_DOUT_DOUT_BUFFER_DATA_Pos (0UL) /*!< Position of DATA field. */ 1288 #define CC_DOUT_DOUT_BUFFER_DATA_Msk (0xFFFFFFFFUL << CC_DOUT_DOUT_BUFFER_DATA_Pos) /*!< Bit mask of DATA field. */ 1289 1290 /* Register: CC_DOUT_DOUT_DMA_MEM_BUSY */ 1291 /* Description: Status register for DOUT DMA engine activity when accessing memory. */ 1292 1293 /* Bit 0 : DOUT memory DMA engine status. */ 1294 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1295 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1296 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Idle (0x0UL) /*!< DOUT memory DMA engine is idle */ 1297 #define CC_DOUT_DOUT_DMA_MEM_BUSY_STATUS_Busy (0x1UL) /*!< DOUT memory DMA engine is busy */ 1298 1299 /* Register: CC_DOUT_DST_MEM_ADDR */ 1300 /* Description: Data destination address in memory. */ 1301 1302 /* Bits 31..0 : Destination address in memory. */ 1303 #define CC_DOUT_DST_MEM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ 1304 #define CC_DOUT_DST_MEM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DOUT_DST_MEM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ 1305 1306 /* Register: CC_DOUT_DST_MEM_SIZE */ 1307 /* Description: The number of bytes to be written to memory. */ 1308 1309 /* Bit 31 : This field is reserved */ 1310 #define CC_DOUT_DST_MEM_SIZE_LAST_Pos (31UL) /*!< Position of LAST field. */ 1311 #define CC_DOUT_DST_MEM_SIZE_LAST_Msk (0x1UL << CC_DOUT_DST_MEM_SIZE_LAST_Pos) /*!< Bit mask of LAST field. */ 1312 1313 /* Bit 30 : This field is reserved */ 1314 #define CC_DOUT_DST_MEM_SIZE_FIRST_Pos (30UL) /*!< Position of FIRST field. */ 1315 #define CC_DOUT_DST_MEM_SIZE_FIRST_Msk (0x1UL << CC_DOUT_DST_MEM_SIZE_FIRST_Pos) /*!< Bit mask of FIRST field. */ 1316 1317 /* Bits 29..0 : Total number of bytes to write to memory. */ 1318 #define CC_DOUT_DST_MEM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ 1319 #define CC_DOUT_DST_MEM_SIZE_SIZE_Msk (0x3FFFFFFFUL << CC_DOUT_DST_MEM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ 1320 1321 /* Register: CC_DOUT_DST_SRAM_ADDR */ 1322 /* Description: Data destination address in RNG SRAM. */ 1323 1324 /* Bits 31..0 : Destination address in RNG SRAM. */ 1325 #define CC_DOUT_DST_SRAM_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ 1326 #define CC_DOUT_DST_SRAM_ADDR_ADDR_Msk (0xFFFFFFFFUL << CC_DOUT_DST_SRAM_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ 1327 1328 /* Register: CC_DOUT_DST_SRAM_SIZE */ 1329 /* Description: The number of bytes to be written to RNG SRAM. */ 1330 1331 /* Bits 31..0 : Total number of bytes to write to RNG SRAM. */ 1332 #define CC_DOUT_DST_SRAM_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ 1333 #define CC_DOUT_DST_SRAM_SIZE_SIZE_Msk (0xFFFFFFFFUL << CC_DOUT_DST_SRAM_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ 1334 1335 /* Register: CC_DOUT_DOUT_DMA_SRAM_BUSY */ 1336 /* Description: Status register for DOUT DMA engine activity when accessing RNG SRAM. */ 1337 1338 /* Bit 0 : DOUT RNG SRAM DMA engine status. */ 1339 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1340 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1341 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Idle (0x0UL) /*!< DOUT RNG SRAM DMA engine is idle */ 1342 #define CC_DOUT_DOUT_DMA_SRAM_BUSY_STATUS_Busy (0x1UL) /*!< DOUT RNG SRAM DMA engine is busy */ 1343 1344 /* Register: CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS */ 1345 /* Description: Configure the endianness of DOUT DMA transactions towards RNG SRAM. */ 1346 1347 /* Bit 0 : Endianness of DOUT DMA transactions towards RNG SRAM. The default value is little-endian. */ 1348 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */ 1349 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 1350 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for RNG SRAM DMA transactions */ 1351 #define CC_DOUT_DOUT_DMA_SRAM_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for RNG SRAM DMA transactions */ 1352 1353 /* Register: CC_DOUT_DOUT_READ_ALIGN */ 1354 /* Description: Indication that the next CPU read from the DOUT_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding). */ 1355 1356 /* Bit 0 : Next CPU read from the DOUT_BUFFER is the last word, and the remaining read aligned content can be flushed. */ 1357 #define CC_DOUT_DOUT_READ_ALIGN_LAST_Pos (0UL) /*!< Position of LAST field. */ 1358 #define CC_DOUT_DOUT_READ_ALIGN_LAST_Msk (0x1UL << CC_DOUT_DOUT_READ_ALIGN_LAST_Pos) /*!< Bit mask of LAST field. */ 1359 #define CC_DOUT_DOUT_READ_ALIGN_LAST_Flush (0x1UL) /*!< Flush the remaining read aligned content. */ 1360 1361 /* Register: CC_DOUT_DOUT_FIFO_EMPTY */ 1362 /* Description: Register indicating if DOUT FIFO is empty or if more data will come. */ 1363 1364 /* Bit 0 : DOUT FIFO status */ 1365 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1366 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Msk (0x1UL << CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1367 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_NotEmpty (0x0UL) /*!< DOUT FIFO is not empty, and more data will come */ 1368 #define CC_DOUT_DOUT_FIFO_EMPTY_STATUS_Empty (0x1UL) /*!< DOUT FIFO is empty */ 1369 1370 /* Register: CC_DOUT_DOUT_SW_RESET */ 1371 /* Description: Reset the DOUT DMA engine. */ 1372 1373 /* Bit 0 : Writing any value to this address resets the DOUT DMA engine. The reset takes 4 CPU clock cycles to complete. */ 1374 #define CC_DOUT_DOUT_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 1375 #define CC_DOUT_DOUT_SW_RESET_RESET_Msk (0x1UL << CC_DOUT_DOUT_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 1376 #define CC_DOUT_DOUT_SW_RESET_RESET_Enable (0x1UL) /*!< Reset DOUT DMA engine. */ 1377 1378 1379 /* Peripheral: CC_HASH */ 1380 /* Description: CRYPTOCELL HASH engine */ 1381 1382 /* Register: CC_HASH_HASH_H */ 1383 /* Description: Description collection: HASH_H value registers. The initial HASH_H[0] register holds the least significant bits [31:0] of the value. */ 1384 1385 /* Bits 31..0 : Write the initial hash value before start of digest operation, and read the final hash value result after 1386 the digest operation has been completed. */ 1387 #define CC_HASH_HASH_H_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 1388 #define CC_HASH_HASH_H_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_H_VALUE_Pos) /*!< Bit mask of VALUE field. */ 1389 1390 /* Register: CC_HASH_HASH_PAD_AUTO */ 1391 /* Description: Configure the HASH engine to automatically pad data at the end of the DMA transfer to complete the digest operation. */ 1392 1393 /* Bit 0 : Enable automatic padding in hardware. */ 1394 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Pos (0UL) /*!< Position of HWPAD field. */ 1395 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Msk (0x1UL << CC_HASH_HASH_PAD_AUTO_HWPAD_Pos) /*!< Bit mask of HWPAD field. */ 1396 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Disable (0x0UL) /*!< Do not enable automatic hardware padding. */ 1397 #define CC_HASH_HASH_PAD_AUTO_HWPAD_Enable (0x1UL) /*!< Enable automatic hardware padding. */ 1398 1399 /* Register: CC_HASH_HASH_INIT_STATE */ 1400 /* Description: Configure HASH engine initial state registers. */ 1401 1402 /* Bit 0 : Enable loading of data to initial state registers. Digest/IV for HASH/AES_MAC. */ 1403 #define CC_HASH_HASH_INIT_STATE_LOAD_Pos (0UL) /*!< Position of LOAD field. */ 1404 #define CC_HASH_HASH_INIT_STATE_LOAD_Msk (0x1UL << CC_HASH_HASH_INIT_STATE_LOAD_Pos) /*!< Bit mask of LOAD field. */ 1405 #define CC_HASH_HASH_INIT_STATE_LOAD_Disable (0x0UL) /*!< Disable loading of data to initial state registers. */ 1406 #define CC_HASH_HASH_INIT_STATE_LOAD_Enable (0x1UL) /*!< Enable loading of data to initial state registers. */ 1407 1408 /* Register: CC_HASH_HASH_VERSION */ 1409 /* Description: HASH engine HW version */ 1410 1411 /* Bits 15..12 : Major version number */ 1412 #define CC_HASH_HASH_VERSION_MAJOR_VERSION_NUMBER_Pos (12UL) /*!< Position of MAJOR_VERSION_NUMBER field. */ 1413 #define CC_HASH_HASH_VERSION_MAJOR_VERSION_NUMBER_Msk (0xFUL << CC_HASH_HASH_VERSION_MAJOR_VERSION_NUMBER_Pos) /*!< Bit mask of MAJOR_VERSION_NUMBER field. */ 1414 1415 /* Bits 11..8 : Minor version number */ 1416 #define CC_HASH_HASH_VERSION_MINOR_VERSION_NUMBER_Pos (8UL) /*!< Position of MINOR_VERSION_NUMBER field. */ 1417 #define CC_HASH_HASH_VERSION_MINOR_VERSION_NUMBER_Msk (0xFUL << CC_HASH_HASH_VERSION_MINOR_VERSION_NUMBER_Pos) /*!< Bit mask of MINOR_VERSION_NUMBER field. */ 1418 1419 /* Bits 7..0 : */ 1420 #define CC_HASH_HASH_VERSION_PATCH_Pos (0UL) /*!< Position of PATCH field. */ 1421 #define CC_HASH_HASH_VERSION_PATCH_Msk (0xFFUL << CC_HASH_HASH_VERSION_PATCH_Pos) /*!< Bit mask of PATCH field. */ 1422 1423 /* Register: CC_HASH_HASH_CONTROL */ 1424 /* Description: Control the HASH engine behavior. */ 1425 1426 /* Bits 3..0 : Select HASH mode to execute */ 1427 #define CC_HASH_HASH_CONTROL_MODE_Pos (0UL) /*!< Position of MODE field. */ 1428 #define CC_HASH_HASH_CONTROL_MODE_Msk (0xFUL << CC_HASH_HASH_CONTROL_MODE_Pos) /*!< Bit mask of MODE field. */ 1429 #define CC_HASH_HASH_CONTROL_MODE_SHA1 (0x1UL) /*!< Select SHA1 mode */ 1430 #define CC_HASH_HASH_CONTROL_MODE_SHA256 (0x2UL) /*!< Select SHA256 mode */ 1431 #define CC_HASH_HASH_CONTROL_MODE_SHA224 (0xAUL) /*!< Select SHA224 mode */ 1432 1433 /* Register: CC_HASH_HASH_PAD */ 1434 /* Description: Enable the hardware padding feature of the HASH engine. */ 1435 1436 /* Bit 0 : Configure hardware padding feature. */ 1437 #define CC_HASH_HASH_PAD_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 1438 #define CC_HASH_HASH_PAD_ENABLE_Msk (0x1UL << CC_HASH_HASH_PAD_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 1439 #define CC_HASH_HASH_PAD_ENABLE_Disable (0x0UL) /*!< Disable hardware padding feature. */ 1440 #define CC_HASH_HASH_PAD_ENABLE_Enable (0x1UL) /*!< Enable hardware padding feature. */ 1441 1442 /* Register: CC_HASH_HASH_PAD_FORCE */ 1443 /* Description: Force the hardware padding operation to trigger if the input data length is zero bytes. */ 1444 1445 /* Bit 2 : Trigger hardware padding operation. */ 1446 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Pos (2UL) /*!< Position of ENABLE field. */ 1447 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Msk (0x1UL << CC_HASH_HASH_PAD_FORCE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 1448 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Disable (0x0UL) /*!< Do not force hardware padding to trigger. */ 1449 #define CC_HASH_HASH_PAD_FORCE_ENABLE_Enable (0x1UL) /*!< Force hardware padding to trigger. */ 1450 1451 /* Register: CC_HASH_HASH_CUR_LEN_0 */ 1452 /* Description: Bits [31:0] of the number of bytes that have been digested so far. */ 1453 1454 /* Bits 31..0 : Bits [31:0] of current length of digested data in bytes. */ 1455 #define CC_HASH_HASH_CUR_LEN_0_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 1456 #define CC_HASH_HASH_CUR_LEN_0_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_CUR_LEN_0_VALUE_Pos) /*!< Bit mask of VALUE field. */ 1457 1458 /* Register: CC_HASH_HASH_CUR_LEN_1 */ 1459 /* Description: Bits [63:32] of the number of bytes that have been digested so far. */ 1460 1461 /* Bits 31..0 : Bits [63:32] of current length of digested data in bytes. */ 1462 #define CC_HASH_HASH_CUR_LEN_1_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 1463 #define CC_HASH_HASH_CUR_LEN_1_VALUE_Msk (0xFFFFFFFFUL << CC_HASH_HASH_CUR_LEN_1_VALUE_Pos) /*!< Bit mask of VALUE field. */ 1464 1465 /* Register: CC_HASH_HASH_HW_FLAGS */ 1466 /* Description: Hardware configuration of the HASH engine. Reset value holds the supported features. */ 1467 1468 /* Bit 18 : If this flag is set, the engine include HASH to DOUT support. */ 1469 #define CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Pos (18UL) /*!< Position of DUMP_HASH_TO_DOUT_EXISTS field. */ 1470 #define CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_DUMP_HASH_TO_DOUT_EXISTS_Pos) /*!< Bit mask of DUMP_HASH_TO_DOUT_EXISTS field. */ 1471 1472 /* Bit 17 : If this flag is set, the engine include compare digest logic. */ 1473 #define CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Pos (17UL) /*!< Position of HASH_COMPARE_EXISTS field. */ 1474 #define CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_HASH_COMPARE_EXISTS_Pos) /*!< Bit mask of HASH_COMPARE_EXISTS field. */ 1475 1476 /* Bit 16 : If this flag is set, the engine include SHA-256 support. */ 1477 #define CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Pos (16UL) /*!< Position of SHA_256_EXISTS field. */ 1478 #define CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_SHA_256_EXISTS_Pos) /*!< Bit mask of SHA_256_EXISTS field. */ 1479 1480 /* Bit 15 : If this flag is set, the engine include HMAC support. */ 1481 #define CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Pos (15UL) /*!< Position of HMAC_EXISTS field. */ 1482 #define CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_HMAC_EXISTS_Pos) /*!< Bit mask of HMAC_EXISTS field. */ 1483 1484 /* Bit 14 : If this flag is set, the engine include MD5 support. */ 1485 #define CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Pos (14UL) /*!< Position of MD5_EXISTS field. */ 1486 #define CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_MD5_EXISTS_Pos) /*!< Bit mask of MD5_EXISTS field. */ 1487 1488 /* Bit 13 : If this flag is set, the engine include pad block support. */ 1489 #define CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Pos (13UL) /*!< Position of PAD_EXISTS field. */ 1490 #define CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_PAD_EXISTS_Pos) /*!< Bit mask of PAD_EXISTS field. */ 1491 1492 /* Bit 12 : If this flag is set, the engine include SHA-512 support. */ 1493 #define CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Pos (12UL) /*!< Position of SHA_512_EXISTS field. */ 1494 #define CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Msk (0x1UL << CC_HASH_HASH_HW_FLAGS_SHA_512_EXISTS_Pos) /*!< Bit mask of SHA_512_EXISTS field. */ 1495 1496 /* Bits 11..8 : Determine the granularity of word size. */ 1497 #define CC_HASH_HASH_HW_FLAGS_DW_Pos (8UL) /*!< Position of DW field. */ 1498 #define CC_HASH_HASH_HW_FLAGS_DW_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_DW_Pos) /*!< Bit mask of DW field. */ 1499 #define CC_HASH_HASH_HW_FLAGS_DW_32Bits (0x0UL) /*!< 32 bits word data. */ 1500 #define CC_HASH_HASH_HW_FLAGS_DW_64Bits (0x1UL) /*!< 64 bits word data. */ 1501 1502 /* Bits 7..4 : Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi. */ 1503 #define CC_HASH_HASH_HW_FLAGS_CH_Pos (4UL) /*!< Position of CH field. */ 1504 #define CC_HASH_HASH_HW_FLAGS_CH_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_CH_Pos) /*!< Bit mask of CH field. */ 1505 #define CC_HASH_HASH_HW_FLAGS_CH_One (0x0UL) /*!< One Hi value is updated at a time. */ 1506 #define CC_HASH_HASH_HW_FLAGS_CH_All (0x1UL) /*!< All Hi values are updated at the same time. */ 1507 1508 /* Bits 3..0 : Indicates the number of concurrent words the hash is using to compute signature. */ 1509 #define CC_HASH_HASH_HW_FLAGS_CW_Pos (0UL) /*!< Position of CW field. */ 1510 #define CC_HASH_HASH_HW_FLAGS_CW_Msk (0xFUL << CC_HASH_HASH_HW_FLAGS_CW_Pos) /*!< Bit mask of CW field. */ 1511 #define CC_HASH_HASH_HW_FLAGS_CW_One (0x1UL) /*!< One concurrent word used by hash during signature generation */ 1512 #define CC_HASH_HASH_HW_FLAGS_CW_Two (0x2UL) /*!< Two concurrent words used by hash during signature generation */ 1513 1514 /* Register: CC_HASH_HASH_SW_RESET */ 1515 /* Description: Reset the HASH engine. */ 1516 1517 /* Bit 0 : Writing any value to this address resets the HASH engine. The reset takes 4 CPU clock cycles to complete. */ 1518 #define CC_HASH_HASH_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 1519 #define CC_HASH_HASH_SW_RESET_RESET_Msk (0x1UL << CC_HASH_HASH_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 1520 #define CC_HASH_HASH_SW_RESET_RESET_Enable (0x1UL) /*!< Reset HASH engine. */ 1521 1522 /* Register: CC_HASH_HASH_ENDIANNESS */ 1523 /* Description: Configure the endianness of HASH data and padding generation. */ 1524 1525 /* Bit 0 : Endianness of HASH data and padding generation. The default value is little-endian. */ 1526 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_Pos (0UL) /*!< Position of ENDIAN field. */ 1527 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_Msk (0x1UL << CC_HASH_HASH_ENDIANNESS_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 1528 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_LittleEndian (0x0UL) /*!< Use little-endian format for data and padding */ 1529 #define CC_HASH_HASH_ENDIANNESS_ENDIAN_BigEndian (0x1UL) /*!< Use big-endian format for data and padding */ 1530 1531 1532 /* Peripheral: CC_HOST_RGF */ 1533 /* Description: CRYPTOCELL HOST register interface */ 1534 1535 /* Register: CC_HOST_RGF_IRR */ 1536 /* Description: Interrupt request register. Each bit of this register holds the interrupt 1537 status of a single interrupt source. If corresponding IMR bit is 1538 unmasked, an interrupt is generated. */ 1539 1540 /* Bit 10 : The RNG interrupt status. */ 1541 #define CC_HOST_RGF_IRR_RNG_INT_Pos (10UL) /*!< Position of RNG_INT field. */ 1542 #define CC_HOST_RGF_IRR_RNG_INT_Msk (0x1UL << CC_HOST_RGF_IRR_RNG_INT_Pos) /*!< Bit mask of RNG_INT field. */ 1543 1544 /* Bit 9 : The PKA end of operation interrupt status. */ 1545 #define CC_HOST_RGF_IRR_PKA_INT_Pos (9UL) /*!< Position of PKA_INT field. */ 1546 #define CC_HOST_RGF_IRR_PKA_INT_Msk (0x1UL << CC_HOST_RGF_IRR_PKA_INT_Pos) /*!< Bit mask of PKA_INT field. */ 1547 1548 /* Bit 8 : The AHB error interrupt status. */ 1549 #define CC_HOST_RGF_IRR_AHB_ERR_INT_Pos (8UL) /*!< Position of AHB_ERR_INT field. */ 1550 #define CC_HOST_RGF_IRR_AHB_ERR_INT_Msk (0x1UL << CC_HOST_RGF_IRR_AHB_ERR_INT_Pos) /*!< Bit mask of AHB_ERR_INT field. */ 1551 1552 /* Bit 7 : The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to memory. */ 1553 #define CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Pos (7UL) /*!< Position of DOUT_TO_MEM_INT field. */ 1554 #define CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Msk (0x1UL << CC_HOST_RGF_IRR_DOUT_TO_MEM_INT_Pos) /*!< Bit mask of DOUT_TO_MEM_INT field. */ 1555 1556 /* Bit 6 : The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from memory to DIN buffer. */ 1557 #define CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Pos (6UL) /*!< Position of MEM_TO_DIN_INT field. */ 1558 #define CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Msk (0x1UL << CC_HOST_RGF_IRR_MEM_TO_DIN_INT_Pos) /*!< Bit mask of MEM_TO_DIN_INT field. */ 1559 1560 /* Bit 5 : The DOUT to RNG SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered from DOUT buffer to RNG SRAM. */ 1561 #define CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Pos (5UL) /*!< Position of DOUT_TO_SRAM_INT field. */ 1562 #define CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Msk (0x1UL << CC_HOST_RGF_IRR_DOUT_TO_SRAM_INT_Pos) /*!< Bit mask of DOUT_TO_SRAM_INT field. */ 1563 1564 /* Bit 4 : The RNG SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered from RNG SRAM to DIN buffer. */ 1565 #define CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Pos (4UL) /*!< Position of SRAM_TO_DIN_INT field. */ 1566 #define CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Msk (0x1UL << CC_HOST_RGF_IRR_SRAM_TO_DIN_INT_Pos) /*!< Bit mask of SRAM_TO_DIN_INT field. */ 1567 1568 /* Register: CC_HOST_RGF_IMR */ 1569 /* Description: Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. */ 1570 1571 /* Bit 10 : The RNG interrupt mask. */ 1572 #define CC_HOST_RGF_IMR_RNG_MASK_Pos (10UL) /*!< Position of RNG_MASK field. */ 1573 #define CC_HOST_RGF_IMR_RNG_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_RNG_MASK_Pos) /*!< Bit mask of RNG_MASK field. */ 1574 #define CC_HOST_RGF_IMR_RNG_MASK_IRQEnable (0x0UL) /*!< Do not mask RNG interrupt i.e. interrupt is generated */ 1575 #define CC_HOST_RGF_IMR_RNG_MASK_IRQDisable (0x1UL) /*!< Mask RNG interrupt i.e. no interrupt is generated */ 1576 1577 /* Bit 9 : The PKA end of operation interrupt mask. */ 1578 #define CC_HOST_RGF_IMR_PKA_MASK_Pos (9UL) /*!< Position of PKA_MASK field. */ 1579 #define CC_HOST_RGF_IMR_PKA_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_PKA_MASK_Pos) /*!< Bit mask of PKA_MASK field. */ 1580 #define CC_HOST_RGF_IMR_PKA_MASK_IRQEnable (0x0UL) /*!< Do not mask PKA end of operation interrupt i.e. interrupt is generated */ 1581 #define CC_HOST_RGF_IMR_PKA_MASK_IRQDisable (0x1UL) /*!< Mask PKA end of operation interrupt i.e. no interrupt is generated */ 1582 1583 /* Bit 8 : The AHB error interrupt mask. */ 1584 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_Pos (8UL) /*!< Position of AHB_ERR_MASK field. */ 1585 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_AHB_ERR_MASK_Pos) /*!< Bit mask of AHB_ERR_MASK field. */ 1586 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask AHB error interrupt i.e. interrupt is generated */ 1587 #define CC_HOST_RGF_IMR_AHB_ERR_MASK_IRQDisable (0x1UL) /*!< Mask AHB error interrupt i.e. no interrupt is generated */ 1588 1589 /* Bit 7 : The DOUT to memory DMA done interrupt mask. */ 1590 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Pos (7UL) /*!< Position of DOUT_TO_MEM_MASK field. */ 1591 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_Pos) /*!< Bit mask of DOUT_TO_MEM_MASK field. */ 1592 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_IRQEnable (0x0UL) /*!< Do not mask DOUT to memory DMA done interrupt i.e. interrupt is generated */ 1593 #define CC_HOST_RGF_IMR_DOUT_TO_MEM_MASK_IRQDisable (0x1UL) /*!< Mask DOUT to memory DMA done interrupt i.e. no interrupt is generated */ 1594 1595 /* Bit 6 : The memory to DIN DMA done interrupt mask. */ 1596 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Pos (6UL) /*!< Position of MEM_TO_DIN_MASK field. */ 1597 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_Pos) /*!< Bit mask of MEM_TO_DIN_MASK field. */ 1598 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_IRQEnable (0x0UL) /*!< Do not mask memory to DIN DMA done interrupt i.e. interrupt is generated */ 1599 #define CC_HOST_RGF_IMR_MEM_TO_DIN_MASK_IRQDisable (0x1UL) /*!< Mask memory to DIN DMA done interrupt i.e. no interrupt is generated */ 1600 1601 /* Bit 5 : The DOUT to RNG SRAM DMA done interrupt mask. */ 1602 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Pos (5UL) /*!< Position of DOUT_TO_SRAM_MASK field. */ 1603 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_Pos) /*!< Bit mask of DOUT_TO_SRAM_MASK field. */ 1604 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_IRQEnable (0x0UL) /*!< Do not mask DOUT to RNG SRAM DMA done interrupt i.e. interrupt is generated */ 1605 #define CC_HOST_RGF_IMR_DOUT_TO_SRAM_MASK_IRQDisable (0x1UL) /*!< Mask DOUT to RNG SRAM DMA done interrupt i.e. no interrupt is generated */ 1606 1607 /* Bit 4 : The RNG SRAM to DIN DMA done interrupt mask. */ 1608 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Pos (4UL) /*!< Position of SRAM_TO_DIN_MASK field. */ 1609 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Msk (0x1UL << CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_Pos) /*!< Bit mask of SRAM_TO_DIN_MASK field. */ 1610 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_IRQEnable (0x0UL) /*!< Do not mask RNG SRAM to DIN DMA done interrupt i.e. interrupt is generated */ 1611 #define CC_HOST_RGF_IMR_SRAM_TO_DIN_MASK_IRQDisable (0x1UL) /*!< Mask RNG SRAM to DIN DMA done interrupt i.e. no interrupt is generated */ 1612 1613 /* Register: CC_HOST_RGF_ICR */ 1614 /* Description: Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR. */ 1615 1616 /* Bit 10 : The RNG interrupt clear. Register RNG_ISR in the RNG engine must be cleared before this interrupt can be cleared. */ 1617 #define CC_HOST_RGF_ICR_RNG_CLEAR_Pos (10UL) /*!< Position of RNG_CLEAR field. */ 1618 #define CC_HOST_RGF_ICR_RNG_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_RNG_CLEAR_Pos) /*!< Bit mask of RNG_CLEAR field. */ 1619 1620 /* Bit 9 : The PKA end of operation interrupt clear. */ 1621 #define CC_HOST_RGF_ICR_PKA_CLEAR_Pos (9UL) /*!< Position of PKA_CLEAR field. */ 1622 #define CC_HOST_RGF_ICR_PKA_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_PKA_CLEAR_Pos) /*!< Bit mask of PKA_CLEAR field. */ 1623 1624 /* Bit 8 : The AHB error interrupt clear. */ 1625 #define CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Pos (8UL) /*!< Position of AHB_ERR_CLEAR field. */ 1626 #define CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_AHB_ERR_CLEAR_Pos) /*!< Bit mask of AHB_ERR_CLEAR field. */ 1627 1628 /* Bit 7 : The DOUT to memory DMA done interrupt clear. */ 1629 #define CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Pos (7UL) /*!< Position of DOUT_TO_MEM_CLEAR field. */ 1630 #define CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_DOUT_TO_MEM_CLEAR_Pos) /*!< Bit mask of DOUT_TO_MEM_CLEAR field. */ 1631 1632 /* Bit 6 : The memory to DIN DMA done interrupt clear. */ 1633 #define CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Pos (6UL) /*!< Position of MEM_TO_DIN_CLEAR field. */ 1634 #define CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_MEM_TO_DIN_CLEAR_Pos) /*!< Bit mask of MEM_TO_DIN_CLEAR field. */ 1635 1636 /* Bit 5 : The DOUT to RNG SRAM DMA done interrupt clear. */ 1637 #define CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Pos (5UL) /*!< Position of DOUT_TO_SRAM_CLEAR field. */ 1638 #define CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_DOUT_TO_SRAM_CLEAR_Pos) /*!< Bit mask of DOUT_TO_SRAM_CLEAR field. */ 1639 1640 /* Bit 4 : The RNG SRAM to DIN DMA done interrupt clear. */ 1641 #define CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Pos (4UL) /*!< Position of SRAM_TO_DIN_CLEAR field. */ 1642 #define CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Msk (0x1UL << CC_HOST_RGF_ICR_SRAM_TO_DIN_CLEAR_Pos) /*!< Bit mask of SRAM_TO_DIN_CLEAR field. */ 1643 1644 /* Register: CC_HOST_RGF_ENDIANNESS */ 1645 /* Description: This register defines the endianness of the Host-accessible registers, and can only be written once. */ 1646 1647 /* Bit 15 : DIN read word endianness. */ 1648 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Pos (15UL) /*!< Position of DIN_RD_WBG field. */ 1649 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_Pos) /*!< Bit mask of DIN_RD_WBG field. */ 1650 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_LittleEndian (0x0UL) /*!< Configure DIN read word as little-endian */ 1651 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_WBG_BigEndian (0x1UL) /*!< Configure DIN read word as big-endian */ 1652 1653 /* Bit 11 : DOUT write word endianness. */ 1654 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Pos (11UL) /*!< Position of DOUT_WR_WBG field. */ 1655 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_Pos) /*!< Bit mask of DOUT_WR_WBG field. */ 1656 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_LittleEndian (0x0UL) /*!< Configure DOUT write word as little-endian */ 1657 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_WBG_BigEndian (0x1UL) /*!< Configure DOUT write word as big-endian */ 1658 1659 /* Bit 7 : DIN read endianness. */ 1660 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Pos (7UL) /*!< Position of DIN_RD_BG field. */ 1661 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_Pos) /*!< Bit mask of DIN_RD_BG field. */ 1662 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_LittleEndian (0x0UL) /*!< Configure DIN read as little-endian */ 1663 #define CC_HOST_RGF_ENDIANNESS_DIN_RD_BG_BigEndian (0x1UL) /*!< Configure DIN read as big-endian */ 1664 1665 /* Bit 3 : DOUT write endianness. */ 1666 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Pos (3UL) /*!< Position of DOUT_WR_BG field. */ 1667 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Msk (0x1UL << CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_Pos) /*!< Bit mask of DOUT_WR_BG field. */ 1668 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_LittleEndian (0x0UL) /*!< Configure DOUT write as little-endian */ 1669 #define CC_HOST_RGF_ENDIANNESS_DOUT_WR_BG_BigEndian (0x1UL) /*!< Configure DOUT write as big-endian */ 1670 1671 /* Register: CC_HOST_RGF_HOST_SIGNATURE */ 1672 /* Description: This register holds the CRYPTOCELL subsystem signature. See reset value. */ 1673 1674 /* Bits 31..0 : Fixed-value identification signature used by host driver to verify CRYPTOCELL presence at this address. */ 1675 #define CC_HOST_RGF_HOST_SIGNATURE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 1676 #define CC_HOST_RGF_HOST_SIGNATURE_VALUE_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_SIGNATURE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 1677 1678 /* Register: CC_HOST_RGF_HOST_BOOT */ 1679 /* Description: Hardware configuration of the CRYPTOCELL subsystem. Reset value holds the supported features. */ 1680 1681 /* Bit 30 : If this flag is set, the AES engine is present */ 1682 #define CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Pos (30UL) /*!< Position of AES_EXISTS_LOCAL field. */ 1683 #define CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_EXISTS_LOCAL field. */ 1684 1685 /* Bit 29 : If this flag is set, the AES engine only support encryption */ 1686 #define CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Pos (29UL) /*!< Position of ONLY_ENCRYPT_LOCAL field. */ 1687 #define CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_ONLY_ENCRYPT_LOCAL_Pos) /*!< Bit mask of ONLY_ENCRYPT_LOCAL field. */ 1688 1689 /* Bit 28 : If this flag is set, the AES engine supports 192/256 bits key sizes */ 1690 #define CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Pos (28UL) /*!< Position of SUPPORT_256_192_KEY_LOCAL field. */ 1691 #define CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_Pos) /*!< Bit mask of SUPPORT_256_192_KEY_LOCAL field. */ 1692 1693 /* Bit 27 : If this flag is set, the AES engine supports tunneling operations */ 1694 #define CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Pos (27UL) /*!< Position of TUNNELING_ENB_LOCAL field. */ 1695 #define CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_TUNNELING_ENB_LOCAL_Pos) /*!< Bit mask of TUNNELING_ENB_LOCAL field. */ 1696 1697 /* Bit 26 : If this flag is set, the AES engine data input support byte size resolution */ 1698 #define CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Pos (26UL) /*!< Position of AES_DIN_BYTE_RESOLUTION_LOCAL field. */ 1699 #define CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_Pos) /*!< Bit mask of AES_DIN_BYTE_RESOLUTION_LOCAL field. */ 1700 1701 /* Bit 25 : If this flag is set, AES CTR mode is supported */ 1702 #define CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Pos (25UL) /*!< Position of CTR_EXISTS_LOCAL field. */ 1703 #define CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_CTR_EXISTS_LOCAL_Pos) /*!< Bit mask of CTR_EXISTS_LOCAL field. */ 1704 1705 /* Bit 24 : If this flag is set, AES XEX mode is supported */ 1706 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Pos (24UL) /*!< Position of AES_XEX_EXISTS_LOCAL field. */ 1707 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XEX_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_XEX_EXISTS_LOCAL field. */ 1708 1709 /* Bit 23 : If this flag is set, AES XEX mode T-value calculation in HW is supported */ 1710 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Pos (23UL) /*!< Position of AES_XEX_HW_T_CALC_LOCAL field. */ 1711 #define CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_Pos) /*!< Bit mask of AES_XEX_HW_T_CALC_LOCAL field. */ 1712 1713 /* Bit 22 : If this flag is set, AES CCM mode is supported */ 1714 #define CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Pos (22UL) /*!< Position of AES_CCM_EXISTS_LOCAL field. */ 1715 #define CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_CCM_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_CCM_EXISTS_LOCAL field. */ 1716 1717 /* Bit 21 : If this flag is set, AES CMAC mode is supported */ 1718 #define CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Pos (21UL) /*!< Position of AES_CMAC_EXISTS_LOCAL field. */ 1719 #define CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_CMAC_EXISTS_LOCAL field. */ 1720 1721 /* Bit 20 : If this flag is set, AES XCBC-MAC mode is supported */ 1722 #define CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Pos (20UL) /*!< Position of AES_XCBC_MAC_EXISTS_LOCAL field. */ 1723 #define CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_Pos) /*!< Bit mask of AES_XCBC_MAC_EXISTS_LOCAL field. */ 1724 1725 /* Bit 19 : If this flag is set, the DES engine is present */ 1726 #define CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Pos (19UL) /*!< Position of DES_EXISTS_LOCAL field. */ 1727 #define CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_DES_EXISTS_LOCAL_Pos) /*!< Bit mask of DES_EXISTS_LOCAL field. */ 1728 1729 /* Bit 18 : If this flag is set, the C2 engine is present */ 1730 #define CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Pos (18UL) /*!< Position of C2_EXISTS_LOCAL field. */ 1731 #define CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_C2_EXISTS_LOCAL_Pos) /*!< Bit mask of C2_EXISTS_LOCAL field. */ 1732 1733 /* Bit 17 : If this flag is set, the HASH engine is present */ 1734 #define CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Pos (17UL) /*!< Position of HASH_EXISTS_LOCAL field. */ 1735 #define CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_HASH_EXISTS_LOCAL_Pos) /*!< Bit mask of HASH_EXISTS_LOCAL field. */ 1736 1737 /* Bit 16 : If this flag is set, the HASH engine supports MD5 */ 1738 #define CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Pos (16UL) /*!< Position of MD5_PRSNT_LOCAL field. */ 1739 #define CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_MD5_PRSNT_LOCAL_Pos) /*!< Bit mask of MD5_PRSNT_LOCAL field. */ 1740 1741 /* Bit 15 : If this flag is set, the HASH engine supports SHA256 */ 1742 #define CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Pos (15UL) /*!< Position of SHA_256_PRSNT_LOCAL field. */ 1743 #define CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SHA_256_PRSNT_LOCAL_Pos) /*!< Bit mask of SHA_256_PRSNT_LOCAL field. */ 1744 1745 /* Bit 14 : If this flag is set, the HASH engine supports SHA512 */ 1746 #define CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Pos (14UL) /*!< Position of SHA_512_PRSNT_LOCAL field. */ 1747 #define CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_SHA_512_PRSNT_LOCAL_Pos) /*!< Bit mask of SHA_512_PRSNT_LOCAL field. */ 1748 1749 /* Bit 13 : If this flag is set, the RC4 engine is present */ 1750 #define CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Pos (13UL) /*!< Position of RC4_EXISTS_LOCAL field. */ 1751 #define CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RC4_EXISTS_LOCAL_Pos) /*!< Bit mask of RC4_EXISTS_LOCAL field. */ 1752 1753 /* Bit 12 : If this flag is set, the PKA engine is present */ 1754 #define CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Pos (12UL) /*!< Position of PKA_EXISTS_LOCAL field. */ 1755 #define CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_PKA_EXISTS_LOCAL_Pos) /*!< Bit mask of PKA_EXISTS_LOCAL field. */ 1756 1757 /* Bit 11 : If this flag is set, the RNG engine is present */ 1758 #define CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Pos (11UL) /*!< Position of RNG_EXISTS_LOCAL field. */ 1759 #define CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RNG_EXISTS_LOCAL_Pos) /*!< Bit mask of RNG_EXISTS_LOCAL field. */ 1760 1761 /* Bit 10 : If this flag is set, PAU is supported */ 1762 #define CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Pos (10UL) /*!< Position of PAU_EXISTS_LOCAL field. */ 1763 #define CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_PAU_EXISTS_LOCAL_Pos) /*!< Bit mask of PAU_EXISTS_LOCAL field. */ 1764 1765 /* Bit 9 : If this flag is set, Descriptors are supported */ 1766 #define CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Pos (9UL) /*!< Position of DSCRPTR_EXISTS_LOCAL field. */ 1767 #define CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_Pos) /*!< Bit mask of DSCRPTR_EXISTS_LOCAL field. */ 1768 1769 /* Bits 8..6 : SRAM size */ 1770 #define CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Pos (6UL) /*!< Position of SRAM_SIZE_LOCAL field. */ 1771 #define CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Msk (0x7UL << CC_HOST_RGF_HOST_BOOT_SRAM_SIZE_LOCAL_Pos) /*!< Bit mask of SRAM_SIZE_LOCAL field. */ 1772 1773 /* Bit 5 : If this flag is set, RKEK ECC is supported */ 1774 #define CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Pos (5UL) /*!< Position of RKEK_ECC_EXISTS_LOCAL_N field. */ 1775 #define CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_Pos) /*!< Bit mask of RKEK_ECC_EXISTS_LOCAL_N field. */ 1776 1777 /* Bit 3 : If this flag is set, external secure memory is supported */ 1778 #define CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Pos (3UL) /*!< Position of EXT_MEM_SECURED_LOCAL field. */ 1779 #define CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_EXT_MEM_SECURED_LOCAL_Pos) /*!< Bit mask of EXT_MEM_SECURED_LOCAL field. */ 1780 1781 /* Bit 2 : If this flag is set, HASH in fuses is supported */ 1782 #define CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Pos (2UL) /*!< Position of HASH_IN_FUSES_LOCAL field. */ 1783 #define CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_HASH_IN_FUSES_LOCAL_Pos) /*!< Bit mask of HASH_IN_FUSES_LOCAL field. */ 1784 1785 /* Bit 1 : If this flag is set, large RKEK is supported */ 1786 #define CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Pos (1UL) /*!< Position of LARGE_RKEK_LOCAL field. */ 1787 #define CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_LARGE_RKEK_LOCAL_Pos) /*!< Bit mask of LARGE_RKEK_LOCAL field. */ 1788 1789 /* Bit 0 : If this flag is set, full power gating is implemented */ 1790 #define CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Pos (0UL) /*!< Position of POWER_GATING_EXISTS_LOCAL field. */ 1791 #define CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Msk (0x1UL << CC_HOST_RGF_HOST_BOOT_POWER_GATING_EXISTS_LOCAL_Pos) /*!< Bit mask of POWER_GATING_EXISTS_LOCAL field. */ 1792 1793 /* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */ 1794 /* Description: AES hardware key select. */ 1795 1796 /* Bits 1..0 : Select the source of the HW key that is used by the AES engine */ 1797 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */ 1798 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */ 1799 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0x0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */ 1800 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (0x1UL) /*!< Use hard-coded RTL key K_PRTL */ 1801 #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (0x2UL) /*!< Use provided session key */ 1802 1803 /* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */ 1804 /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ 1805 1806 /* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ 1807 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */ 1808 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */ 1809 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0x0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ 1810 #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (0x1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */ 1811 1812 /* Register: CC_HOST_RGF_HOST_IOT_KDR0 */ 1813 /* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */ 1814 1815 /* Bits 31..0 : This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. Write: K_DR bits 31:0. */ 1816 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */ 1817 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */ 1818 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_NotRetained (0x00000000UL) /*!< Read: 128 bits K_DR key value is not yet retained in the CRYPTOCELL AO power domain. */ 1819 #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Retained (0x00000001UL) /*!< Read: 128 bits K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */ 1820 1821 /* Register: CC_HOST_RGF_HOST_IOT_KDR1 */ 1822 /* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ 1823 1824 /* Bits 31..0 : K_DR bits 63:32 */ 1825 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */ 1826 #define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */ 1827 1828 /* Register: CC_HOST_RGF_HOST_IOT_KDR2 */ 1829 /* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ 1830 1831 /* Bits 31..0 : K_DR bits 95:64 */ 1832 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */ 1833 #define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */ 1834 1835 /* Register: CC_HOST_RGF_HOST_IOT_KDR3 */ 1836 /* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ 1837 1838 /* Bits 31..0 : K_DR bits 127:96 */ 1839 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */ 1840 #define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */ 1841 1842 /* Register: CC_HOST_RGF_HOST_IOT_LCS */ 1843 /* Description: Controls life-cycle state (LCS) for CRYPTOCELL subsystem */ 1844 1845 /* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */ 1846 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */ 1847 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */ 1848 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0x0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */ 1849 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (0x1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */ 1850 1851 /* Bits 2..0 : Life-cycle state value. This field is write-once per reset. */ 1852 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */ 1853 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */ 1854 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_DebugEnable (0x0UL) /*!< CC310 operates in debug mode */ 1855 #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (0x2UL) /*!< CC310 operates in secure mode */ 1856 1857 1858 /* Peripheral: CC_MISC */ 1859 /* Description: CRYPTOCELL MISC interface */ 1860 1861 /* Register: CC_MISC_AES_CLK */ 1862 /* Description: Clock control for the AES engine. */ 1863 1864 /* Bit 0 : Enables clock for the AES engine. */ 1865 #define CC_MISC_AES_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 1866 #define CC_MISC_AES_CLK_ENABLE_Msk (0x1UL << CC_MISC_AES_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 1867 #define CC_MISC_AES_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the AES engine. */ 1868 #define CC_MISC_AES_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the AES engine. */ 1869 1870 /* Register: CC_MISC_HASH_CLK */ 1871 /* Description: Clock control for the HASH engine. */ 1872 1873 /* Bit 0 : Enables clock for the HASH engine. */ 1874 #define CC_MISC_HASH_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 1875 #define CC_MISC_HASH_CLK_ENABLE_Msk (0x1UL << CC_MISC_HASH_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 1876 #define CC_MISC_HASH_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the HASH engine. */ 1877 #define CC_MISC_HASH_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the HASH engine. */ 1878 1879 /* Register: CC_MISC_PKA_CLK */ 1880 /* Description: Clock control for the PKA engine. */ 1881 1882 /* Bit 0 : Enables clock for the PKA engine. */ 1883 #define CC_MISC_PKA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 1884 #define CC_MISC_PKA_CLK_ENABLE_Msk (0x1UL << CC_MISC_PKA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 1885 #define CC_MISC_PKA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the PKA engine. */ 1886 #define CC_MISC_PKA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the PKA engine. */ 1887 1888 /* Register: CC_MISC_DMA_CLK */ 1889 /* Description: Clock control for the DMA engines. */ 1890 1891 /* Bit 0 : Enables clock for the DMA engines. */ 1892 #define CC_MISC_DMA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 1893 #define CC_MISC_DMA_CLK_ENABLE_Msk (0x1UL << CC_MISC_DMA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 1894 #define CC_MISC_DMA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the DMA engines. */ 1895 #define CC_MISC_DMA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the DMA engines. */ 1896 1897 /* Register: CC_MISC_CLK_STATUS */ 1898 /* Description: CRYPTOCELL clocks status register. */ 1899 1900 /* Bit 8 : Status of DMA engines clock. */ 1901 #define CC_MISC_CLK_STATUS_DMA_CLK_Pos (8UL) /*!< Position of DMA_CLK field. */ 1902 #define CC_MISC_CLK_STATUS_DMA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_DMA_CLK_Pos) /*!< Bit mask of DMA_CLK field. */ 1903 #define CC_MISC_CLK_STATUS_DMA_CLK_Disabled (0x0UL) /*!< Clocks for DMA engines are disabled */ 1904 #define CC_MISC_CLK_STATUS_DMA_CLK_Enabled (0x1UL) /*!< Clocks for DMA engines are enabled */ 1905 1906 /* Bit 7 : Status of CHACHA engine clock. */ 1907 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Pos (7UL) /*!< Position of CHACHA_CLK field. */ 1908 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_CHACHA_CLK_Pos) /*!< Bit mask of CHACHA_CLK field. */ 1909 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Disabled (0x0UL) /*!< Clock for CHACHA engine is disabled */ 1910 #define CC_MISC_CLK_STATUS_CHACHA_CLK_Enabled (0x1UL) /*!< Clock for CHACHA engine is enabled */ 1911 1912 /* Bit 3 : Status of PKA engine clock. */ 1913 #define CC_MISC_CLK_STATUS_PKA_CLK_Pos (3UL) /*!< Position of PKA_CLK field. */ 1914 #define CC_MISC_CLK_STATUS_PKA_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_PKA_CLK_Pos) /*!< Bit mask of PKA_CLK field. */ 1915 #define CC_MISC_CLK_STATUS_PKA_CLK_Disabled (0x0UL) /*!< Clock for PKA engine is disabled */ 1916 #define CC_MISC_CLK_STATUS_PKA_CLK_Enabled (0x1UL) /*!< Clock for PKA engine is enabled */ 1917 1918 /* Bit 2 : Status of HASH engine clock. */ 1919 #define CC_MISC_CLK_STATUS_HASH_CLK_Pos (2UL) /*!< Position of HASH_CLK field. */ 1920 #define CC_MISC_CLK_STATUS_HASH_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_HASH_CLK_Pos) /*!< Bit mask of HASH_CLK field. */ 1921 #define CC_MISC_CLK_STATUS_HASH_CLK_Disabled (0x0UL) /*!< Clock for HASH engine is disabled */ 1922 #define CC_MISC_CLK_STATUS_HASH_CLK_Enabled (0x1UL) /*!< Clock for HASH engine is enabled */ 1923 1924 /* Bit 0 : Status of AES engine clock. */ 1925 #define CC_MISC_CLK_STATUS_AES_CLK_Pos (0UL) /*!< Position of AES_CLK field. */ 1926 #define CC_MISC_CLK_STATUS_AES_CLK_Msk (0x1UL << CC_MISC_CLK_STATUS_AES_CLK_Pos) /*!< Bit mask of AES_CLK field. */ 1927 #define CC_MISC_CLK_STATUS_AES_CLK_Disabled (0x0UL) /*!< Clock for AES engine is disabled */ 1928 #define CC_MISC_CLK_STATUS_AES_CLK_Enabled (0x1UL) /*!< Clock for AES engine is enabled */ 1929 1930 /* Register: CC_MISC_CHACHA_CLK */ 1931 /* Description: Clock control for the CHACHA engine. */ 1932 1933 /* Bit 0 : Enables clock for the CHACHA engine. */ 1934 #define CC_MISC_CHACHA_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 1935 #define CC_MISC_CHACHA_CLK_ENABLE_Msk (0x1UL << CC_MISC_CHACHA_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 1936 #define CC_MISC_CHACHA_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for the CHACHA engine. */ 1937 #define CC_MISC_CHACHA_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for the CHACHA engine. */ 1938 1939 1940 /* Peripheral: CC_PKA */ 1941 /* Description: CRYPTOCELL PKA engine */ 1942 1943 /* Register: CC_PKA_MEMORY_MAP */ 1944 /* Description: Description collection: Register for mapping the virtual register R[n] to a physical address in the PKA SRAM. */ 1945 1946 /* Bits 9..1 : The physical word address used for the virtual register. */ 1947 #define CC_PKA_MEMORY_MAP_ADDR_Pos (1UL) /*!< Position of ADDR field. */ 1948 #define CC_PKA_MEMORY_MAP_ADDR_Msk (0x1FFUL << CC_PKA_MEMORY_MAP_ADDR_Pos) /*!< Bit mask of ADDR field. */ 1949 1950 /* Register: CC_PKA_OPCODE */ 1951 /* Description: Operation code to be executed by the PKA engine. Writing to this register triggers the PKA operation. */ 1952 1953 /* Bits 31..27 : Operation code to be executed by the PKA engine */ 1954 #define CC_PKA_OPCODE_OPCODE_Pos (27UL) /*!< Position of OPCODE field. */ 1955 #define CC_PKA_OPCODE_OPCODE_Msk (0x1FUL << CC_PKA_OPCODE_OPCODE_Pos) /*!< Bit mask of OPCODE field. */ 1956 #define CC_PKA_OPCODE_OPCODE_Terminate (0x00UL) /*!< Terminate operation */ 1957 #define CC_PKA_OPCODE_OPCODE_AddInc (0x04UL) /*!< Add or Increment */ 1958 #define CC_PKA_OPCODE_OPCODE_SubDecNeg (0x05UL) /*!< Subtract, Decrement, or Negate */ 1959 #define CC_PKA_OPCODE_OPCODE_ModAddInc (0x06UL) /*!< Modular Add or Modular Increment */ 1960 #define CC_PKA_OPCODE_OPCODE_ModSubDecNeg (0x07UL) /*!< Modular Subtract, Modular Decrement, or Modular Negate */ 1961 #define CC_PKA_OPCODE_OPCODE_ANDTST0CLR0 (0x08UL) /*!< Perform AND, test, or clear */ 1962 #define CC_PKA_OPCODE_OPCODE_ORCOPYSET0 (0x09UL) /*!< Perform OR, copy, or set bits */ 1963 #define CC_PKA_OPCODE_OPCODE_XORFLP0INVCMP (0x0AUL) /*!< Perform XOR, flip bits, invert, or compare */ 1964 #define CC_PKA_OPCODE_OPCODE_SHR0 (0x0CUL) /*!< Shift right 0 operation */ 1965 #define CC_PKA_OPCODE_OPCODE_SHR1 (0x0DUL) /*!< Shift right 1 operation */ 1966 #define CC_PKA_OPCODE_OPCODE_SHL0 (0x0EUL) /*!< Shift left 0 operation */ 1967 #define CC_PKA_OPCODE_OPCODE_SHL1 (0x0FUL) /*!< Shift left 1 operation */ 1968 #define CC_PKA_OPCODE_OPCODE_MulLow (0x10UL) /*!< Multiply low operation */ 1969 #define CC_PKA_OPCODE_OPCODE_ModMul (0x11UL) /*!< Modular multiply operation */ 1970 #define CC_PKA_OPCODE_OPCODE_ModMulN (0x12UL) /*!< Modular multiply N operation */ 1971 #define CC_PKA_OPCODE_OPCODE_ModExp (0x13UL) /*!< Modular exponentiation operation */ 1972 #define CC_PKA_OPCODE_OPCODE_Division (0x14UL) /*!< Division operation */ 1973 #define CC_PKA_OPCODE_OPCODE_ModInv (0x15UL) /*!< Modular inversion operation */ 1974 #define CC_PKA_OPCODE_OPCODE_ModDiv (0x16UL) /*!< Modular division operation */ 1975 #define CC_PKA_OPCODE_OPCODE_MulHigh (0x17UL) /*!< Multiply high operation */ 1976 #define CC_PKA_OPCODE_OPCODE_ModMLAC (0x18UL) /*!< Modular multiplication acceleration */ 1977 #define CC_PKA_OPCODE_OPCODE_ModMLACNR (0x19UL) /*!< Modular multiplication acceleration where final reduction is omitted */ 1978 #define CC_PKA_OPCODE_OPCODE_Reduction (0x1BUL) /*!< Reduction operation */ 1979 1980 /* Bits 26..24 : The length of the operands. This value serves as an PKA length register index. E.g.: if LEN field value is set to 0, PKA_L[0] holds the size of the operands. */ 1981 #define CC_PKA_OPCODE_LEN_Pos (24UL) /*!< Position of LEN field. */ 1982 #define CC_PKA_OPCODE_LEN_Msk (0x7UL << CC_PKA_OPCODE_LEN_Pos) /*!< Bit mask of LEN field. */ 1983 1984 /* Bit 23 : This field controls the interpretation of REG_A. */ 1985 #define CC_PKA_OPCODE_CONST_A_Pos (23UL) /*!< Position of CONST_A field. */ 1986 #define CC_PKA_OPCODE_CONST_A_Msk (0x1UL << CC_PKA_OPCODE_CONST_A_Pos) /*!< Bit mask of CONST_A field. */ 1987 #define CC_PKA_OPCODE_CONST_A_Register (0x0UL) /*!< REG_A is intepreted as a register index. */ 1988 #define CC_PKA_OPCODE_CONST_A_Constant (0x1UL) /*!< REG_A is intepreted as a constant. */ 1989 1990 /* Bits 22..18 : Operand A virtual register index. */ 1991 #define CC_PKA_OPCODE_REG_A_Pos (18UL) /*!< Position of REG_A field. */ 1992 #define CC_PKA_OPCODE_REG_A_Msk (0x1FUL << CC_PKA_OPCODE_REG_A_Pos) /*!< Bit mask of REG_A field. */ 1993 1994 /* Bit 17 : This field controls the interpretation of REG_B. */ 1995 #define CC_PKA_OPCODE_CONST_B_Pos (17UL) /*!< Position of CONST_B field. */ 1996 #define CC_PKA_OPCODE_CONST_B_Msk (0x1UL << CC_PKA_OPCODE_CONST_B_Pos) /*!< Bit mask of CONST_B field. */ 1997 #define CC_PKA_OPCODE_CONST_B_Register (0x0UL) /*!< REG_B is intepreted as a register index. */ 1998 #define CC_PKA_OPCODE_CONST_B_Constant (0x1UL) /*!< REG_B is intepreted as a constant. */ 1999 2000 /* Bits 16..12 : Operand B virtual register index. */ 2001 #define CC_PKA_OPCODE_REG_B_Pos (12UL) /*!< Position of REG_B field. */ 2002 #define CC_PKA_OPCODE_REG_B_Msk (0x1FUL << CC_PKA_OPCODE_REG_B_Pos) /*!< Bit mask of REG_B field. */ 2003 2004 /* Bit 11 : This field controls the interpretation of REG_R. */ 2005 #define CC_PKA_OPCODE_DISCARD_R_Pos (11UL) /*!< Position of DISCARD_R field. */ 2006 #define CC_PKA_OPCODE_DISCARD_R_Msk (0x1UL << CC_PKA_OPCODE_DISCARD_R_Pos) /*!< Bit mask of DISCARD_R field. */ 2007 #define CC_PKA_OPCODE_DISCARD_R_Register (0x0UL) /*!< REG_R is intepreted as a register index. */ 2008 #define CC_PKA_OPCODE_DISCARD_R_Discard (0x1UL) /*!< Result is discarded. */ 2009 2010 /* Bits 10..6 : Result register virtual register index. */ 2011 #define CC_PKA_OPCODE_REG_R_Pos (6UL) /*!< Position of REG_R field. */ 2012 #define CC_PKA_OPCODE_REG_R_Msk (0x1FUL << CC_PKA_OPCODE_REG_R_Pos) /*!< Bit mask of REG_R field. */ 2013 2014 /* Bits 5..0 : Holds the operation tag or the operand C virtual register index. */ 2015 #define CC_PKA_OPCODE_TAG_Pos (0UL) /*!< Position of TAG field. */ 2016 #define CC_PKA_OPCODE_TAG_Msk (0x3FUL << CC_PKA_OPCODE_TAG_Pos) /*!< Bit mask of TAG field. */ 2017 2018 /* Register: CC_PKA_N_NP_T0_T1_ADDR */ 2019 /* Description: This register defines the N, Np, T0, and T1 virtual register index. */ 2020 2021 /* Bits 19..15 : Temporary register 1 virtual register index. Default is R31. */ 2022 #define CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Pos (15UL) /*!< Position of T1_VIRTUAL_ADDR field. */ 2023 #define CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_Pos) /*!< Bit mask of T1_VIRTUAL_ADDR field. */ 2024 2025 /* Bits 14..10 : Temporary register 0 virtual register index. Default is R30. */ 2026 #define CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Pos (10UL) /*!< Position of T0_VIRTUAL_ADDR field. */ 2027 #define CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_Pos) /*!< Bit mask of T0_VIRTUAL_ADDR field. */ 2028 2029 /* Bits 9..5 : Register Np virtual register index. Default is R1. */ 2030 #define CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Pos (5UL) /*!< Position of NP_VIRTUAL_ADDR field. */ 2031 #define CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_Pos) /*!< Bit mask of NP_VIRTUAL_ADDR field. */ 2032 2033 /* Bits 4..0 : Register N virtual register index. Default is R0. */ 2034 #define CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Pos (0UL) /*!< Position of N_VIRTUAL_ADDR field. */ 2035 #define CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Msk (0x1FUL << CC_PKA_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_Pos) /*!< Bit mask of N_VIRTUAL_ADDR field. */ 2036 2037 /* Register: CC_PKA_PKA_STATUS */ 2038 /* Description: This register holds the status for the PKA pipeline. */ 2039 2040 /* Bits 20..16 : Opcode of the last operation */ 2041 #define CC_PKA_PKA_STATUS_OPCODE_Pos (16UL) /*!< Position of OPCODE field. */ 2042 #define CC_PKA_PKA_STATUS_OPCODE_Msk (0x1FUL << CC_PKA_PKA_STATUS_OPCODE_Pos) /*!< Bit mask of OPCODE field. */ 2043 2044 /* Bit 15 : Indicates the modular inverse of zero. */ 2045 #define CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Pos (15UL) /*!< Position of MODINV_OF_ZERO field. */ 2046 #define CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_MODINV_OF_ZERO_Pos) /*!< Bit mask of MODINV_OF_ZERO field. */ 2047 2048 /* Bit 14 : Indication if the division is done by zero. */ 2049 #define CC_PKA_PKA_STATUS_DIV_BY_ZERO_Pos (14UL) /*!< Position of DIV_BY_ZERO field. */ 2050 #define CC_PKA_PKA_STATUS_DIV_BY_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_DIV_BY_ZERO_Pos) /*!< Bit mask of DIV_BY_ZERO field. */ 2051 2052 /* Bit 13 : Modular overflow flag. */ 2053 #define CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Pos (13UL) /*!< Position of ALU_MODOVRFLW field. */ 2054 #define CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_MODOVRFLW_Pos) /*!< Bit mask of ALU_MODOVRFLW field. */ 2055 2056 /* Bit 12 : Indicates if the result of ALU OUT is zero. */ 2057 #define CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Pos (12UL) /*!< Position of ALU_OUT_ZERO field. */ 2058 #define CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_OUT_ZERO_Pos) /*!< Bit mask of ALU_OUT_ZERO field. */ 2059 2060 /* Bit 11 : Indicates the last subtraction operation sign. */ 2061 #define CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Pos (11UL) /*!< Position of ALU_SUB_IS_ZERO field. */ 2062 #define CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_SUB_IS_ZERO_Pos) /*!< Bit mask of ALU_SUB_IS_ZERO field. */ 2063 2064 /* Bit 10 : Holds the carry of the last modular operation. */ 2065 #define CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Pos (10UL) /*!< Position of ALU_CARRY_MOD field. */ 2066 #define CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_CARRY_MOD_Pos) /*!< Bit mask of ALU_CARRY_MOD field. */ 2067 2068 /* Bit 9 : Holds the carry of the last ALU operation. */ 2069 #define CC_PKA_PKA_STATUS_ALU_CARRY_Pos (9UL) /*!< Position of ALU_CARRY field. */ 2070 #define CC_PKA_PKA_STATUS_ALU_CARRY_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_CARRY_Pos) /*!< Bit mask of ALU_CARRY field. */ 2071 2072 /* Bit 8 : Indicates the MSB sign of the last operation. */ 2073 #define CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Pos (8UL) /*!< Position of ALU_SIGN_OUT field. */ 2074 #define CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Msk (0x1UL << CC_PKA_PKA_STATUS_ALU_SIGN_OUT_Pos) /*!< Bit mask of ALU_SIGN_OUT field. */ 2075 2076 /* Bits 7..4 : The least significant 4-bits of the operand updated in shift operation. */ 2077 #define CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Pos (4UL) /*!< Position of ALU_LSB_4BITS field. */ 2078 #define CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Msk (0xFUL << CC_PKA_PKA_STATUS_ALU_LSB_4BITS_Pos) /*!< Bit mask of ALU_LSB_4BITS field. */ 2079 2080 /* Bits 3..0 : The most significant 4-bits of the operand updated in shift operation. */ 2081 #define CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Pos (0UL) /*!< Position of ALU_MSB_4BITS field. */ 2082 #define CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Msk (0xFUL << CC_PKA_PKA_STATUS_ALU_MSB_4BITS_Pos) /*!< Bit mask of ALU_MSB_4BITS field. */ 2083 2084 /* Register: CC_PKA_PKA_SW_RESET */ 2085 /* Description: Reset the PKA engine. */ 2086 2087 /* Bit 0 : Writing any value to this address resets the PKA engine. The reset takes 4 CPU clock cycles to complete. */ 2088 #define CC_PKA_PKA_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 2089 #define CC_PKA_PKA_SW_RESET_RESET_Msk (0x1UL << CC_PKA_PKA_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 2090 #define CC_PKA_PKA_SW_RESET_RESET_Enable (0x1UL) /*!< Reset PKA engine. */ 2091 2092 /* Register: CC_PKA_PKA_L */ 2093 /* Description: Description collection: This register holds the operands bit size. */ 2094 2095 /* Bits 12..0 : Operand bit size. */ 2096 #define CC_PKA_PKA_L_OpSize_Pos (0UL) /*!< Position of OpSize field. */ 2097 #define CC_PKA_PKA_L_OpSize_Msk (0x1FFFUL << CC_PKA_PKA_L_OpSize_Pos) /*!< Bit mask of OpSize field. */ 2098 2099 /* Register: CC_PKA_PKA_PIPE */ 2100 /* Description: Status register indicating if the PKA pipeline is ready to receive a new OPCODE. */ 2101 2102 /* Bit 0 : PKA pipeline status. */ 2103 #define CC_PKA_PKA_PIPE_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 2104 #define CC_PKA_PKA_PIPE_STATUS_Msk (0x1UL << CC_PKA_PKA_PIPE_STATUS_Pos) /*!< Bit mask of STATUS field. */ 2105 #define CC_PKA_PKA_PIPE_STATUS_NotReady (0x0UL) /*!< PKA pipeline is not ready for a new OPCODE */ 2106 #define CC_PKA_PKA_PIPE_STATUS_Ready (0x1UL) /*!< PKA pipeline is ready for a new OPCODE */ 2107 2108 /* Register: CC_PKA_PKA_DONE */ 2109 /* Description: Status register indicating if the PKA operation has been completed. */ 2110 2111 /* Bit 0 : PKA operation status. */ 2112 #define CC_PKA_PKA_DONE_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 2113 #define CC_PKA_PKA_DONE_STATUS_Msk (0x1UL << CC_PKA_PKA_DONE_STATUS_Pos) /*!< Bit mask of STATUS field. */ 2114 #define CC_PKA_PKA_DONE_STATUS_Processing (0x0UL) /*!< PKA operation is processing */ 2115 #define CC_PKA_PKA_DONE_STATUS_Completed (0x1UL) /*!< PKA operation is completed and pipeline is empty */ 2116 2117 /* Register: CC_PKA_PKA_VERSION */ 2118 /* Description: PKA engine HW version. Reset value holds the version. */ 2119 2120 /* Bits 31..0 : */ 2121 #define CC_PKA_PKA_VERSION_PKA_VERSION_Pos (0UL) /*!< Position of PKA_VERSION field. */ 2122 #define CC_PKA_PKA_VERSION_PKA_VERSION_Msk (0xFFFFFFFFUL << CC_PKA_PKA_VERSION_PKA_VERSION_Pos) /*!< Bit mask of PKA_VERSION field. */ 2123 2124 /* Register: CC_PKA_PKA_SRAM_WADDR */ 2125 /* Description: Start address in PKA SRAM for subsequent write transactions. */ 2126 2127 /* Bits 31..0 : PKA SRAM start address for write transaction */ 2128 #define CC_PKA_PKA_SRAM_WADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ 2129 #define CC_PKA_PKA_SRAM_WADDR_ADDR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ 2130 2131 /* Register: CC_PKA_PKA_SRAM_WDATA */ 2132 /* Description: Write data to PKA SRAM. Writing to this register triggers a DMA transaction writing data into PKA SRAM. The DMA address offset is automatically incremented during write. */ 2133 2134 /* Bits 31..0 : Data to write to PKA SRAM. */ 2135 #define CC_PKA_PKA_SRAM_WDATA_DATA_Pos (0UL) /*!< Position of DATA field. */ 2136 #define CC_PKA_PKA_SRAM_WDATA_DATA_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WDATA_DATA_Pos) /*!< Bit mask of DATA field. */ 2137 2138 /* Register: CC_PKA_PKA_SRAM_RDATA */ 2139 /* Description: Read data from PKA SRAM. Reading from this register triggers a DMA transaction read data from PKA SRAM. The DMA address offset is automatically incremented during read. */ 2140 2141 /* Bits 31..0 : Data to read from PKA SRAM */ 2142 #define CC_PKA_PKA_SRAM_RDATA_DATA_Pos (0UL) /*!< Position of DATA field. */ 2143 #define CC_PKA_PKA_SRAM_RDATA_DATA_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_RDATA_DATA_Pos) /*!< Bit mask of DATA field. */ 2144 2145 /* Register: CC_PKA_PKA_SRAM_WCLEAR */ 2146 /* Description: Register for clearing PKA SRAM write buffer. */ 2147 2148 /* Bits 31..0 : Clear the PKA SRAM write buffer. */ 2149 #define CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */ 2150 #define CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_WCLEAR_CLEAR_Pos) /*!< Bit mask of CLEAR field. */ 2151 2152 /* Register: CC_PKA_PKA_SRAM_RADDR */ 2153 /* Description: Start address in PKA SRAM for subsequent read transactions. */ 2154 2155 /* Bits 31..0 : PKA SRAM start address for read transaction */ 2156 #define CC_PKA_PKA_SRAM_RADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ 2157 #define CC_PKA_PKA_SRAM_RADDR_ADDR_Msk (0xFFFFFFFFUL << CC_PKA_PKA_SRAM_RADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ 2158 2159 2160 /* Peripheral: CC_RNG */ 2161 /* Description: CRYPTOCELL RNG engine */ 2162 2163 /* Register: CC_RNG_RNG_IMR */ 2164 /* Description: Interrupt mask register. Each bit of this register holds the mask of a single interrupt source. */ 2165 2166 /* Bit 5 : See RNG_ISR for explanation on this interrupt. */ 2167 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_Pos (5UL) /*!< Position of DMA_DONE_MASK field. */ 2168 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_DMA_DONE_MASK_Pos) /*!< Bit mask of DMA_DONE_MASK field. */ 2169 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_IRQEnable (0x0UL) /*!< Do not mask the RNG DMA completion interrupt i.e. interrupt is generated */ 2170 #define CC_RNG_RNG_IMR_DMA_DONE_MASK_IRQDisable (0x1UL) /*!< Mask the RNG DMA completion interrupt i.e. no interrupt is generated */ 2171 2172 /* Bit 4 : See RNG_ISR for explanation on this interrupt. */ 2173 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_Pos (4UL) /*!< Position of WATCHDOG_MASK field. */ 2174 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_WATCHDOG_MASK_Pos) /*!< Bit mask of WATCHDOG_MASK field. */ 2175 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_IRQEnable (0x0UL) /*!< Do not mask the watchdog interrupt i.e. interrupt is generated */ 2176 #define CC_RNG_RNG_IMR_WATCHDOG_MASK_IRQDisable (0x1UL) /*!< Mask the watchdog interrupt i.e. no interrupt is generated */ 2177 2178 /* Bit 3 : See RNG_ISR for explanation on this interrupt. */ 2179 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_Pos (3UL) /*!< Position of VNC_ERR_MASK field. */ 2180 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_VNC_ERR_MASK_Pos) /*!< Bit mask of VNC_ERR_MASK field. */ 2181 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask the von Neumann corrector error interrupt i.e. interrupt is generated */ 2182 #define CC_RNG_RNG_IMR_VNC_ERR_MASK_IRQDisable (0x1UL) /*!< Mask the von Neumann corrector error interrupt i.e. no interrupt is generated */ 2183 2184 /* Bit 2 : See RNG_ISR for explanation on this interrupt. */ 2185 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Pos (2UL) /*!< Position of CRNGT_ERR_MASK field. */ 2186 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_CRNGT_ERR_MASK_Pos) /*!< Bit mask of CRNGT_ERR_MASK field. */ 2187 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask the CRNGT error interrupt i.e. interrupt is generated */ 2188 #define CC_RNG_RNG_IMR_CRNGT_ERR_MASK_IRQDisable (0x1UL) /*!< Mask the CRNGT error interrupt i.e. no interrupt is generated */ 2189 2190 /* Bit 1 : See RNG_ISR for explanation on this interrupt. */ 2191 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Pos (1UL) /*!< Position of AUTOCORR_ERR_MASK field. */ 2192 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_Pos) /*!< Bit mask of AUTOCORR_ERR_MASK field. */ 2193 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_IRQEnable (0x0UL) /*!< Do not mask autocorrelation interrupt i.e. interrupt is generated */ 2194 #define CC_RNG_RNG_IMR_AUTOCORR_ERR_MASK_IRQDisable (0x1UL) /*!< Mask autocorrelation interrupt i.e. no interrupt is generated */ 2195 2196 /* Bit 0 : See RNG_ISR for explanation on this interrupt. */ 2197 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_Pos (0UL) /*!< Position of EHR_VALID_MASK field. */ 2198 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_Msk (0x1UL << CC_RNG_RNG_IMR_EHR_VALID_MASK_Pos) /*!< Bit mask of EHR_VALID_MASK field. */ 2199 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_IRQEnable (0x0UL) /*!< Do not mask EHR interrupt i.e. interrupt is generated */ 2200 #define CC_RNG_RNG_IMR_EHR_VALID_MASK_IRQDisable (0x1UL) /*!< Mask EHR interrupt i.e. no interrupt is generated */ 2201 2202 /* Register: CC_RNG_RNG_ISR */ 2203 /* Description: Interrupt status register. Each bit of this register holds the interrupt 2204 status of a single interrupt source. If corresponding RNG_IMR bit is 2205 unmasked, an interrupt is generated. */ 2206 2207 /* Bit 5 : RNG DMA to SRAM is completed. */ 2208 #define CC_RNG_RNG_ISR_DMA_DONE_INT_Pos (5UL) /*!< Position of DMA_DONE_INT field. */ 2209 #define CC_RNG_RNG_ISR_DMA_DONE_INT_Msk (0x1UL << CC_RNG_RNG_ISR_DMA_DONE_INT_Pos) /*!< Bit mask of DMA_DONE_INT field. */ 2210 2211 /* Bit 4 : Maximum number of CPU clock cycles per sample have been exceeded. See RNG_WATCHDOG_VAL for more information. */ 2212 #define CC_RNG_RNG_ISR_WATCHDOG_INT_Pos (4UL) /*!< Position of WATCHDOG_INT field. */ 2213 #define CC_RNG_RNG_ISR_WATCHDOG_INT_Msk (0x1UL << CC_RNG_RNG_ISR_WATCHDOG_INT_Pos) /*!< Bit mask of WATCHDOG_INT field. */ 2214 2215 /* Bit 3 : von Neumann corrector error. Failure occurs if 32 consecutive collected bits are identical, ZERO, or ONE. */ 2216 #define CC_RNG_RNG_ISR_VNC_ERR_INT_Pos (3UL) /*!< Position of VNC_ERR_INT field. */ 2217 #define CC_RNG_RNG_ISR_VNC_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_VNC_ERR_INT_Pos) /*!< Bit mask of VNC_ERR_INT field. */ 2218 2219 /* Bit 2 : Continuous random number generator test error. Failure occurs when two consecutive blocks of 16 collected bits are equal. */ 2220 #define CC_RNG_RNG_ISR_CRNGT_ERR_INT_Pos (2UL) /*!< Position of CRNGT_ERR_INT field. */ 2221 #define CC_RNG_RNG_ISR_CRNGT_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_CRNGT_ERR_INT_Pos) /*!< Bit mask of CRNGT_ERR_INT field. */ 2222 2223 /* Bit 1 : Autocorrelation error. Failure occurs when autocorrelation test has failed four times in a row. Once set, the TRNG ceases to function until next reset. */ 2224 #define CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Pos (1UL) /*!< Position of AUTOCORR_ERR_INT field. */ 2225 #define CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Msk (0x1UL << CC_RNG_RNG_ISR_AUTOCORR_ERR_INT_Pos) /*!< Bit mask of AUTOCORR_ERR_INT field. */ 2226 2227 /* Bit 0 : 192-bits have been collected and are ready to be read. */ 2228 #define CC_RNG_RNG_ISR_EHR_VALID_INT_Pos (0UL) /*!< Position of EHR_VALID_INT field. */ 2229 #define CC_RNG_RNG_ISR_EHR_VALID_INT_Msk (0x1UL << CC_RNG_RNG_ISR_EHR_VALID_INT_Pos) /*!< Bit mask of EHR_VALID_INT field. */ 2230 2231 /* Register: CC_RNG_RNG_ICR */ 2232 /* Description: Interrupt clear register. Writing a 1 bit into a field in this register 2233 will clear the corresponding bit in RNG_ISR. */ 2234 2235 /* Bit 5 : Writing value '1' clears corresponding bit in RNG_ISR */ 2236 #define CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Pos (5UL) /*!< Position of DMA_DONE_CLEAR field. */ 2237 #define CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_DMA_DONE_CLEAR_Pos) /*!< Bit mask of DMA_DONE_CLEAR field. */ 2238 2239 /* Bit 4 : Writing value '1' clears corresponding bit in RNG_ISR */ 2240 #define CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Pos (4UL) /*!< Position of WATCHDOG_CLEAR field. */ 2241 #define CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_WATCHDOG_CLEAR_Pos) /*!< Bit mask of WATCHDOG_CLEAR field. */ 2242 2243 /* Bit 3 : Writing value '1' clears corresponding bit in RNG_ISR */ 2244 #define CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Pos (3UL) /*!< Position of VNC_ERR_CLEAR field. */ 2245 #define CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_VNC_ERR_CLEAR_Pos) /*!< Bit mask of VNC_ERR_CLEAR field. */ 2246 2247 /* Bit 2 : Writing value '1' clears corresponding bit in RNG_ISR */ 2248 #define CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Pos (2UL) /*!< Position of CRNGT_ERR_CLEAR field. */ 2249 #define CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_CRNGT_ERR_CLEAR_Pos) /*!< Bit mask of CRNGT_ERR_CLEAR field. */ 2250 2251 /* Bit 1 : Cannot be cleared by software! Only RNG reset clears this bit. */ 2252 #define CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Pos (1UL) /*!< Position of AUTOCORR_ERR_CLEAR field. */ 2253 #define CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_AUTOCORR_ERR_CLEAR_Pos) /*!< Bit mask of AUTOCORR_ERR_CLEAR field. */ 2254 2255 /* Bit 0 : Writing value '1' clears corresponding bit in RNG_ISR */ 2256 #define CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Pos (0UL) /*!< Position of EHR_VALID_CLEAR field. */ 2257 #define CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Msk (0x1UL << CC_RNG_RNG_ICR_EHR_VALID_CLEAR_Pos) /*!< Bit mask of EHR_VALID_CLEAR field. */ 2258 2259 /* Register: CC_RNG_TRNG_CONFIG */ 2260 /* Description: TRNG ring oscillator length configuration */ 2261 2262 /* Bits 1..0 : Set the length of the oscillator ring (= the number of inverters) out of four possible configurations. */ 2263 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_Pos (0UL) /*!< Position of ROSC_LEN field. */ 2264 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_Msk (0x3UL << CC_RNG_TRNG_CONFIG_ROSC_LEN_Pos) /*!< Bit mask of ROSC_LEN field. */ 2265 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC1 (0x0UL) /*!< Use shortest ROSC1 ring oscillator configuration. */ 2266 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC2 (0x1UL) /*!< Use ROSC2 ring oscillator configuration. */ 2267 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC3 (0x2UL) /*!< Use ROSC3 ring oscillator configuration. */ 2268 #define CC_RNG_TRNG_CONFIG_ROSC_LEN_ROSC4 (0x3UL) /*!< Use longest ROSC4 ring oscillator configuration. */ 2269 2270 /* Register: CC_RNG_TRNG_VALID */ 2271 /* Description: This register indicates if TRNG entropy collection is valid. */ 2272 2273 /* Bit 0 : A value of 1 indicates that collection of bits in the TRNG is completed, and data can be read from EHR_DATA registers. */ 2274 #define CC_RNG_TRNG_VALID_EHR_DATA_Pos (0UL) /*!< Position of EHR_DATA field. */ 2275 #define CC_RNG_TRNG_VALID_EHR_DATA_Msk (0x1UL << CC_RNG_TRNG_VALID_EHR_DATA_Pos) /*!< Bit mask of EHR_DATA field. */ 2276 #define CC_RNG_TRNG_VALID_EHR_DATA_NotValid (0x0UL) /*!< Collection of bits not valid. */ 2277 #define CC_RNG_TRNG_VALID_EHR_DATA_Valid (0x1UL) /*!< Collection of bits valid. */ 2278 2279 /* Register: CC_RNG_EHR_DATA */ 2280 /* Description: Description collection: The entropy holding registers (EHR) hold 192-bits random data collected by the TRNG. The initial EHR_DATA[0] register holds the least significant bits [31:0] of the random data value. */ 2281 2282 /* Bits 31..0 : Random data value. */ 2283 #define CC_RNG_EHR_DATA_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 2284 #define CC_RNG_EHR_DATA_VALUE_Msk (0xFFFFFFFFUL << CC_RNG_EHR_DATA_VALUE_Pos) /*!< Bit mask of VALUE field. */ 2285 2286 /* Register: CC_RNG_NOISE_SOURCE */ 2287 /* Description: This register controls the ring oscillator circuit used as a noise source. */ 2288 2289 /* Bit 0 : Enable or disable the noise source. */ 2290 #define CC_RNG_NOISE_SOURCE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 2291 #define CC_RNG_NOISE_SOURCE_ENABLE_Msk (0x1UL << CC_RNG_NOISE_SOURCE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 2292 #define CC_RNG_NOISE_SOURCE_ENABLE_Disabled (0x0UL) /*!< Noise source is disabled */ 2293 #define CC_RNG_NOISE_SOURCE_ENABLE_Enabled (0x1UL) /*!< Noise source is enabled */ 2294 2295 /* Register: CC_RNG_SAMPLE_CNT */ 2296 /* Description: Sample count defining the number of CPU clock cycles between two consecutive noise source samples. */ 2297 2298 /* Bits 31..0 : Number of CPU clock cycles between two consecutive noise source samples. */ 2299 #define CC_RNG_SAMPLE_CNT_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 2300 #define CC_RNG_SAMPLE_CNT_VALUE_Msk (0xFFFFFFFFUL << CC_RNG_SAMPLE_CNT_VALUE_Pos) /*!< Bit mask of VALUE field. */ 2301 2302 /* Register: CC_RNG_AUTOCORR_STATISTIC */ 2303 /* Description: Statistics counter for autocorrelation test activations. Statistics collection is stopped if one of the counters reach its limit of all ones. */ 2304 2305 /* Bits 21..14 : Count each time an autocorrelation test fails. Any write to the field resets the counter. */ 2306 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Pos (14UL) /*!< Position of AUTOCORR_FAILS field. */ 2307 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Msk (0xFFUL << CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_Pos) /*!< Bit mask of AUTOCORR_FAILS field. */ 2308 2309 /* Bits 13..0 : Count each time an autocorrelation test starts. Any write to the field resets the counter. */ 2310 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Pos (0UL) /*!< Position of AUTOCORR_TRYS field. */ 2311 #define CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Msk (0x3FFFUL << CC_RNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_Pos) /*!< Bit mask of AUTOCORR_TRYS field. */ 2312 2313 /* Register: CC_RNG_TRNG_DEBUG */ 2314 /* Description: Debug register for the TRNG. This register is used to bypass TRNG tests in hardware. */ 2315 2316 /* Bit 3 : Bypass the autocorrelation test. */ 2317 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Pos (3UL) /*!< Position of AUTOCORR_BYPASS field. */ 2318 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Pos) /*!< Bit mask of AUTOCORR_BYPASS field. */ 2319 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Disabled (0x0UL) /*!< Autocorrelation test is active */ 2320 #define CC_RNG_TRNG_DEBUG_AUTOCORR_BYPASS_Enabled (0x1UL) /*!< Bypass the autocorrelation test */ 2321 2322 /* Bit 2 : Bypass the Continuous Random Number Generator Test (CRNGT). */ 2323 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Pos (2UL) /*!< Position of CRNGT_BYPASS field. */ 2324 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Pos) /*!< Bit mask of CRNGT_BYPASS field. */ 2325 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Disabled (0x0UL) /*!< CRNGT is active */ 2326 #define CC_RNG_TRNG_DEBUG_CRNGT_BYPASS_Enabled (0x1UL) /*!< Bypass CRNGT */ 2327 2328 /* Bit 1 : Bypass the von Neumann corrector post-processing test, including the 32 consecutive bits test. */ 2329 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Pos (1UL) /*!< Position of VNC_BYPASS field. */ 2330 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Msk (0x1UL << CC_RNG_TRNG_DEBUG_VNC_BYPASS_Pos) /*!< Bit mask of VNC_BYPASS field. */ 2331 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Disabled (0x0UL) /*!< von Neumann corrector post-processing is active */ 2332 #define CC_RNG_TRNG_DEBUG_VNC_BYPASS_Enabled (0x1UL) /*!< Bypass the von Neumann corrector */ 2333 2334 /* Register: CC_RNG_RNG_SW_RESET */ 2335 /* Description: Reset the RNG engine. */ 2336 2337 /* Bit 0 : Writing any value to this address resets the RNG engine. The reset takes 4 CPU clock cycles to complete. */ 2338 #define CC_RNG_RNG_SW_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 2339 #define CC_RNG_RNG_SW_RESET_RESET_Msk (0x1UL << CC_RNG_RNG_SW_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 2340 #define CC_RNG_RNG_SW_RESET_RESET_Enable (0x1UL) /*!< Reset RNG engine. */ 2341 2342 /* Register: CC_RNG_RNG_BUSY */ 2343 /* Description: Status register for RNG engine activity. */ 2344 2345 /* Bit 1 : TRNG status. */ 2346 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Pos (1UL) /*!< Position of TRNG_STATUS field. */ 2347 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Msk (0x1UL << CC_RNG_RNG_BUSY_TRNG_STATUS_Pos) /*!< Bit mask of TRNG_STATUS field. */ 2348 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Idle (0x0UL) /*!< TRNG is idle */ 2349 #define CC_RNG_RNG_BUSY_TRNG_STATUS_Busy (0x1UL) /*!< TRNG is busy */ 2350 2351 /* Bit 0 : RNG engine status. */ 2352 #define CC_RNG_RNG_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 2353 #define CC_RNG_RNG_BUSY_STATUS_Msk (0x1UL << CC_RNG_RNG_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 2354 #define CC_RNG_RNG_BUSY_STATUS_Idle (0x0UL) /*!< RNG engine is idle */ 2355 #define CC_RNG_RNG_BUSY_STATUS_Busy (0x1UL) /*!< RNG engine is busy */ 2356 2357 /* Register: CC_RNG_TRNG_RESET */ 2358 /* Description: Reset the TRNG, including internal counter of collected bits and registers EHR_DATA and TRNG_VALID. */ 2359 2360 /* Bit 0 : Writing any value to this address resets the internal bits counter and registers EHR_DATA and TRNG_VALID. Register NOISE_SOURCE must be disabled in order for the reset to take place. */ 2361 #define CC_RNG_TRNG_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 2362 #define CC_RNG_TRNG_RESET_RESET_Msk (0x1UL << CC_RNG_TRNG_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 2363 #define CC_RNG_TRNG_RESET_RESET_Enable (0x1UL) /*!< Reset TRNG. */ 2364 2365 /* Register: CC_RNG_RNG_HW_FLAGS */ 2366 /* Description: Hardware configuration of RNG engine. Reset value holds the supported features. */ 2367 2368 /* Bit 7 : */ 2369 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Pos (7UL) /*!< Position of RNG_USE_5_SBOXES field. */ 2370 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Pos) /*!< Bit mask of RNG_USE_5_SBOXES field. */ 2371 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Disable (0x0UL) /*!< 20 SBOX AES */ 2372 #define CC_RNG_RNG_HW_FLAGS_RNG_USE_5_SBOXES_Enable (0x1UL) /*!< 5 SBOX AES */ 2373 2374 /* Bit 6 : If this flag is set, the engine include support for automatic reseeding. */ 2375 #define CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Pos (6UL) /*!< Position of RESEEDING_EXISTS field. */ 2376 #define CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_RESEEDING_EXISTS_Pos) /*!< Bit mask of RESEEDING_EXISTS field. */ 2377 2378 /* Bit 5 : If this flag is set, the engine include support for known answer tests. */ 2379 #define CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Pos (5UL) /*!< Position of KAT_EXISTS field. */ 2380 #define CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_KAT_EXISTS_Pos) /*!< Bit mask of KAT_EXISTS field. */ 2381 2382 /* Bit 4 : If this flag is set, the engine include a pseudo-random number generator. */ 2383 #define CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Pos (4UL) /*!< Position of PRNG_EXISTS field. */ 2384 #define CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_PRNG_EXISTS_Pos) /*!< Bit mask of PRNG_EXISTS field. */ 2385 2386 /* Bit 3 : If this flag is set, the engine include support for bypassing TRNG tests. */ 2387 #define CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Pos (3UL) /*!< Position of BYPASS_EXISTS field. */ 2388 #define CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_BYPASS_EXISTS_Pos) /*!< Bit mask of BYPASS_EXISTS field. */ 2389 2390 /* Bit 2 : If this flag is set, the engine include support for autocorrelation test. */ 2391 #define CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Pos (2UL) /*!< Position of AUTOCORR_EXISTS field. */ 2392 #define CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_AUTOCORR_EXISTS_Pos) /*!< Bit mask of AUTOCORR_EXISTS field. */ 2393 2394 /* Bit 1 : If this flag is set, the engine include support for continuous random number generator test. */ 2395 #define CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Pos (1UL) /*!< Position of CRNGT_EXISTS field. */ 2396 #define CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_CRNGT_EXISTS_Pos) /*!< Bit mask of CRNGT_EXISTS field. */ 2397 2398 /* Bit 0 : Data width supported by the entropy collector */ 2399 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Pos (0UL) /*!< Position of EHR_WIDTH field. */ 2400 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Msk (0x1UL << CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_Pos) /*!< Bit mask of EHR_WIDTH field. */ 2401 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_128Bits (0x0UL) /*!< 128 bits EHR width */ 2402 #define CC_RNG_RNG_HW_FLAGS_EHR_WIDTH_192Bits (0x1UL) /*!< 192 bits EHR width */ 2403 2404 /* Register: CC_RNG_RNG_CLK */ 2405 /* Description: Control clock for the RNG engine. */ 2406 2407 /* Bit 0 : Enables clock for the RNG engine. */ 2408 #define CC_RNG_RNG_CLK_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 2409 #define CC_RNG_RNG_CLK_ENABLE_Msk (0x1UL << CC_RNG_RNG_CLK_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 2410 #define CC_RNG_RNG_CLK_ENABLE_Disable (0x0UL) /*!< Disable clock for RNG engine. */ 2411 #define CC_RNG_RNG_CLK_ENABLE_Enable (0x1UL) /*!< Enable clock for RNG engine. */ 2412 2413 /* Register: CC_RNG_RNG_DMA */ 2414 /* Description: Writing to this register enables the RNG DMA engine. */ 2415 2416 /* Bit 0 : */ 2417 #define CC_RNG_RNG_DMA_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 2418 #define CC_RNG_RNG_DMA_ENABLE_Msk (0x1UL << CC_RNG_RNG_DMA_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 2419 #define CC_RNG_RNG_DMA_ENABLE_Disable (0x0UL) /*!< Disable RNG DMA engine */ 2420 #define CC_RNG_RNG_DMA_ENABLE_Enable (0x1UL) /*!< Enable RNG DMA engine This value is cleared when the RNG DMA engine completes its operation. */ 2421 2422 /* Register: CC_RNG_RNG_DMA_ROSC_LEN */ 2423 /* Description: This register defines which ring oscillator length configuration should be used when using the RNG DMA engine. */ 2424 2425 /* Bit 3 : Use longest ROSC4 ring oscillator configuration. */ 2426 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Pos (3UL) /*!< Position of ROSC4 field. */ 2427 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */ 2428 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Disable (0x0UL) /*!< Disable ROSC4 */ 2429 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC4_Enable (0x1UL) /*!< Enable ROSC4 */ 2430 2431 /* Bit 2 : Use ROSC3 ring oscillator configuration. */ 2432 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Pos (2UL) /*!< Position of ROSC3 field. */ 2433 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */ 2434 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Disable (0x0UL) /*!< Disable ROSC3 */ 2435 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC3_Enable (0x1UL) /*!< Enable ROSC3 */ 2436 2437 /* Bit 1 : Use ROSC2 ring oscillator configuration. */ 2438 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Pos (1UL) /*!< Position of ROSC2 field. */ 2439 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */ 2440 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Disable (0x0UL) /*!< Disable ROSC2 */ 2441 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC2_Enable (0x1UL) /*!< Enable ROSC2 */ 2442 2443 /* Bit 0 : Use shortest ROSC1 ring oscillator configuration. */ 2444 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */ 2445 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Msk (0x1UL << CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */ 2446 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Disable (0x0UL) /*!< Disable ROSC1 */ 2447 #define CC_RNG_RNG_DMA_ROSC_LEN_ROSC1_Enable (0x1UL) /*!< Enable ROSC1 */ 2448 2449 /* Register: CC_RNG_RNG_DMA_SRAM_ADDR */ 2450 /* Description: This register defines the start address in TRNG SRAM for the TRNG data to be collected by the RNG DMA engine. */ 2451 2452 /* Bits 10..0 : Start address of the TRNG data in TRNG SRAM. */ 2453 #define CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Pos (0UL) /*!< Position of RNG_SRAM_DMA_ADDR field. */ 2454 #define CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Msk (0x7FFUL << CC_RNG_RNG_DMA_SRAM_ADDR_RNG_SRAM_DMA_ADDR_Pos) /*!< Bit mask of RNG_SRAM_DMA_ADDR field. */ 2455 2456 /* Register: CC_RNG_RNG_DMA_SAMPLES_NUM */ 2457 /* Description: This register defines the number of 192-bits samples that the RNG DMA engine collects per run. */ 2458 2459 /* Bits 7..0 : Defines the number of 192-bits samples that the DMA engine collects per run. */ 2460 #define CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Pos (0UL) /*!< Position of RNG_SAMPLES_NUM field. */ 2461 #define CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Msk (0xFFUL << CC_RNG_RNG_DMA_SAMPLES_NUM_RNG_SAMPLES_NUM_Pos) /*!< Bit mask of RNG_SAMPLES_NUM field. */ 2462 2463 /* Register: CC_RNG_RNG_WATCHDOG_VAL */ 2464 /* Description: This register defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. */ 2465 2466 /* Bits 31..0 : Defines the maximum number of CPU clock cycles per TRNG collection of 192-bits samples. If the number of cycles for a collection exceeds this threshold the WATCHDOG interrupt is triggered. */ 2467 #define CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Pos (0UL) /*!< Position of RNG_WATCHDOG_VAL field. */ 2468 #define CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Msk (0xFFFFFFFFUL << CC_RNG_RNG_WATCHDOG_VAL_RNG_WATCHDOG_VAL_Pos) /*!< Bit mask of RNG_WATCHDOG_VAL field. */ 2469 2470 /* Register: CC_RNG_RNG_DMA_BUSY */ 2471 /* Description: Status register for RNG DMA engine activity. */ 2472 2473 /* Bits 10..3 : Number of samples already collected using the current ring oscillator configuration. */ 2474 #define CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Pos (3UL) /*!< Position of NUM_OF_SAMPLES field. */ 2475 #define CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Msk (0xFFUL << CC_RNG_RNG_DMA_BUSY_NUM_OF_SAMPLES_Pos) /*!< Bit mask of NUM_OF_SAMPLES field. */ 2476 2477 /* Bits 2..1 : The active ring oscillator length configuration used by the RNG DMA engine. */ 2478 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Pos (1UL) /*!< Position of ROSC_LEN field. */ 2479 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Msk (0x3UL << CC_RNG_RNG_DMA_BUSY_ROSC_LEN_Pos) /*!< Bit mask of ROSC_LEN field. */ 2480 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC1 (0x0UL) /*!< Shortest ROSC1 ring oscillator configuration used. */ 2481 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC2 (0x1UL) /*!< ROSC2 ring oscillator configuration used. */ 2482 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC3 (0x2UL) /*!< ROSC3 ring oscillator configuration used. */ 2483 #define CC_RNG_RNG_DMA_BUSY_ROSC_LEN_ROSC4 (0x3UL) /*!< Longest ROSC4 ring oscillator configuration used. */ 2484 2485 /* Bit 0 : RNG DMA engine status. */ 2486 #define CC_RNG_RNG_DMA_BUSY_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 2487 #define CC_RNG_RNG_DMA_BUSY_STATUS_Msk (0x1UL << CC_RNG_RNG_DMA_BUSY_STATUS_Pos) /*!< Bit mask of STATUS field. */ 2488 #define CC_RNG_RNG_DMA_BUSY_STATUS_Idle (0x0UL) /*!< RNG DMA engine is idle */ 2489 #define CC_RNG_RNG_DMA_BUSY_STATUS_Busy (0x1UL) /*!< RNG DMA engine is busy */ 2490 2491 2492 /* Peripheral: CC_RNG_SRAM */ 2493 /* Description: CRYPTOCELL RNG SRAM interface */ 2494 2495 /* Register: CC_RNG_SRAM_SRAM_DATA */ 2496 /* Description: Read/Write data from RNG SRAM */ 2497 2498 /* Bits 31..0 : 32 bits DMA read/write from/to RNG SRAM. A 'read' or 'write' operation to this register will trigger the DMA address to be automatically incremented. */ 2499 #define CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Pos (0UL) /*!< Position of SRAM_DATA field. */ 2500 #define CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Msk (0xFFFFFFFFUL << CC_RNG_SRAM_SRAM_DATA_SRAM_DATA_Pos) /*!< Bit mask of SRAM_DATA field. */ 2501 2502 /* Register: CC_RNG_SRAM_SRAM_ADDR */ 2503 /* Description: First address given to RNG SRAM DMA for read/write transactions from/to RNG SRAM. */ 2504 2505 /* Bits 14..0 : RNG SRAM starting address */ 2506 #define CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Pos (0UL) /*!< Position of SRAM_ADDR field. */ 2507 #define CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Msk (0x7FFFUL << CC_RNG_SRAM_SRAM_ADDR_SRAM_ADDR_Pos) /*!< Bit mask of SRAM_ADDR field. */ 2508 2509 /* Register: CC_RNG_SRAM_SRAM_DATA_READY */ 2510 /* Description: RNG SRAM DMA engine is ready to read/write from/to RNG SRAM. */ 2511 2512 /* Bit 0 : RNG SRAM DMA status. */ 2513 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Pos (0UL) /*!< Position of SRAM_READY field. */ 2514 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Msk (0x1UL << CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Pos) /*!< Bit mask of SRAM_READY field. */ 2515 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Busy (0x0UL) /*!< DMA is busy */ 2516 #define CC_RNG_SRAM_SRAM_DATA_READY_SRAM_READY_Idle (0x1UL) /*!< DMA is idle */ 2517 2518 2519 /* Peripheral: CLOCK */ 2520 /* Description: Clock management 0 */ 2521 2522 /* Register: CLOCK_TASKS_HFCLKSTART */ 2523 /* Description: Start HFCLK source */ 2524 2525 /* Bit 0 : Start HFCLK source */ 2526 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ 2527 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ 2528 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (0x1UL) /*!< Trigger task */ 2529 2530 /* Register: CLOCK_TASKS_HFCLKSTOP */ 2531 /* Description: Stop HFCLK source */ 2532 2533 /* Bit 0 : Stop HFCLK source */ 2534 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ 2535 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ 2536 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */ 2537 2538 /* Register: CLOCK_TASKS_LFCLKSTART */ 2539 /* Description: Start LFCLK source */ 2540 2541 /* Bit 0 : Start LFCLK source */ 2542 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ 2543 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ 2544 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (0x1UL) /*!< Trigger task */ 2545 2546 /* Register: CLOCK_TASKS_LFCLKSTOP */ 2547 /* Description: Stop LFCLK source */ 2548 2549 /* Bit 0 : Stop LFCLK source */ 2550 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ 2551 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ 2552 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */ 2553 2554 /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */ 2555 /* Description: Subscribe configuration for task HFCLKSTART */ 2556 2557 /* Bit 31 : */ 2558 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ 2559 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ 2560 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ 2561 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ 2562 2563 /* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */ 2564 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2565 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2566 2567 /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */ 2568 /* Description: Subscribe configuration for task HFCLKSTOP */ 2569 2570 /* Bit 31 : */ 2571 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 2572 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ 2573 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 2574 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 2575 2576 /* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */ 2577 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2578 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2579 2580 /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */ 2581 /* Description: Subscribe configuration for task LFCLKSTART */ 2582 2583 /* Bit 31 : */ 2584 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ 2585 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ 2586 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ 2587 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ 2588 2589 /* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */ 2590 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2591 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2592 2593 /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */ 2594 /* Description: Subscribe configuration for task LFCLKSTOP */ 2595 2596 /* Bit 31 : */ 2597 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 2598 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ 2599 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 2600 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 2601 2602 /* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */ 2603 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2604 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2605 2606 /* Register: CLOCK_EVENTS_HFCLKSTARTED */ 2607 /* Description: HFCLK oscillator started */ 2608 2609 /* Bit 0 : HFCLK oscillator started */ 2610 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ 2611 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ 2612 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ 2613 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (0x1UL) /*!< Event generated */ 2614 2615 /* Register: CLOCK_EVENTS_LFCLKSTARTED */ 2616 /* Description: LFCLK started */ 2617 2618 /* Bit 0 : LFCLK started */ 2619 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ 2620 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ 2621 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ 2622 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (0x1UL) /*!< Event generated */ 2623 2624 /* Register: CLOCK_PUBLISH_HFCLKSTARTED */ 2625 /* Description: Publish configuration for event HFCLKSTARTED */ 2626 2627 /* Bit 31 : */ 2628 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 2629 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 2630 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 2631 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 2632 2633 /* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to */ 2634 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2635 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2636 2637 /* Register: CLOCK_PUBLISH_LFCLKSTARTED */ 2638 /* Description: Publish configuration for event LFCLKSTARTED */ 2639 2640 /* Bit 31 : */ 2641 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 2642 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 2643 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 2644 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 2645 2646 /* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to */ 2647 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2648 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2649 2650 /* Register: CLOCK_INTEN */ 2651 /* Description: Enable or disable interrupt */ 2652 2653 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */ 2654 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 2655 #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 2656 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0x0UL) /*!< Disable */ 2657 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (0x1UL) /*!< Enable */ 2658 2659 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */ 2660 #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 2661 #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 2662 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0x0UL) /*!< Disable */ 2663 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (0x1UL) /*!< Enable */ 2664 2665 /* Register: CLOCK_INTENSET */ 2666 /* Description: Enable interrupt */ 2667 2668 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ 2669 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 2670 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 2671 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 2672 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 2673 #define CLOCK_INTENSET_LFCLKSTARTED_Set (0x1UL) /*!< Enable */ 2674 2675 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ 2676 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 2677 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 2678 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 2679 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 2680 #define CLOCK_INTENSET_HFCLKSTARTED_Set (0x1UL) /*!< Enable */ 2681 2682 /* Register: CLOCK_INTENCLR */ 2683 /* Description: Disable interrupt */ 2684 2685 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ 2686 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 2687 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 2688 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 2689 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 2690 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (0x1UL) /*!< Disable */ 2691 2692 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ 2693 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 2694 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 2695 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 2696 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 2697 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (0x1UL) /*!< Disable */ 2698 2699 /* Register: CLOCK_INTPEND */ 2700 /* Description: Pending interrupts */ 2701 2702 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */ 2703 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 2704 #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 2705 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0x0UL) /*!< Read: Not pending */ 2706 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (0x1UL) /*!< Read: Pending */ 2707 2708 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */ 2709 #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 2710 #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 2711 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0x0UL) /*!< Read: Not pending */ 2712 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (0x1UL) /*!< Read: Pending */ 2713 2714 /* Register: CLOCK_HFCLKRUN */ 2715 /* Description: Status indicating that HFCLKSTART task has been triggered */ 2716 2717 /* Bit 0 : HFCLKSTART task triggered or not */ 2718 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 2719 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 2720 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */ 2721 #define CLOCK_HFCLKRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */ 2722 2723 /* Register: CLOCK_HFCLKSTAT */ 2724 /* Description: The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE). */ 2725 2726 /* Bit 16 : HFCLK state */ 2727 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 2728 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 2729 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0x0UL) /*!< HFXO has not been started or HFCLKSTOP task has been triggered */ 2730 #define CLOCK_HFCLKSTAT_STATE_Running (0x1UL) /*!< HFXO has been started (HFCLKSTARTED event has been generated) */ 2731 2732 /* Bit 0 : Active clock source */ 2733 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 2734 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 2735 #define CLOCK_HFCLKSTAT_SRC_HFINT (0x0UL) /*!< HFINT - 64 MHz on-chip oscillator */ 2736 #define CLOCK_HFCLKSTAT_SRC_HFXO (0x1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */ 2737 2738 /* Register: CLOCK_LFCLKRUN */ 2739 /* Description: Status indicating that LFCLKSTART task has been triggered */ 2740 2741 /* Bit 0 : LFCLKSTART task triggered or not */ 2742 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 2743 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 2744 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */ 2745 #define CLOCK_LFCLKRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */ 2746 2747 /* Register: CLOCK_LFCLKSTAT */ 2748 /* Description: The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE). */ 2749 2750 /* Bit 16 : LFCLK state */ 2751 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 2752 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 2753 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0x0UL) /*!< Requested LFCLK source has not been started or LFCLKSTOP task has been triggered */ 2754 #define CLOCK_LFCLKSTAT_STATE_Running (0x1UL) /*!< Requested LFCLK source has been started (LFCLKSTARTED event has been generated) */ 2755 2756 /* Bits 1..0 : Active clock source */ 2757 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 2758 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 2759 #define CLOCK_LFCLKSTAT_SRC_RFU (0x0UL) /*!< Reserved for future use */ 2760 #define CLOCK_LFCLKSTAT_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */ 2761 #define CLOCK_LFCLKSTAT_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */ 2762 2763 /* Register: CLOCK_LFCLKSRCCOPY */ 2764 /* Description: Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered */ 2765 2766 /* Bits 1..0 : Clock source */ 2767 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ 2768 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ 2769 #define CLOCK_LFCLKSRCCOPY_SRC_RFU (0x0UL) /*!< Reserved for future use */ 2770 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */ 2771 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */ 2772 2773 /* Register: CLOCK_LFCLKSRC */ 2774 /* Description: Clock source for the LFCLK. LFCLKSTART task starts a clock source selected with this register. */ 2775 2776 /* Bits 1..0 : Clock source */ 2777 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 2778 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 2779 #define CLOCK_LFCLKSRC_SRC_RFU (0x0UL) /*!< Reserved for future use (equals selecting LFRC) */ 2780 #define CLOCK_LFCLKSRC_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */ 2781 #define CLOCK_LFCLKSRC_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */ 2782 2783 2784 /* Peripheral: CRYPTOCELL */ 2785 /* Description: CRYPTOCELL register interface */ 2786 2787 /* Register: CRYPTOCELL_ENABLE */ 2788 /* Description: Enable CRYPTOCELL subsystem. */ 2789 2790 /* Bit 0 : Enable or disable the CRYPTOCELL subsystem. */ 2791 #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 2792 #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 2793 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0x0UL) /*!< CRYPTOCELL subsystem disabled. */ 2794 #define CRYPTOCELL_ENABLE_ENABLE_Enabled (0x1UL) /*!< CRYPTOCELL subsystem enabled. */ 2795 2796 2797 /* Peripheral: CTRLAPPERI */ 2798 /* Description: Control access port */ 2799 2800 /* Register: CTRLAPPERI_MAILBOX_RXDATA */ 2801 /* Description: Data sent from the debugger to the CPU. */ 2802 2803 /* Bits 31..0 : Data received from debugger */ 2804 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */ 2805 #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */ 2806 2807 /* Register: CTRLAPPERI_MAILBOX_RXSTATUS */ 2808 /* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */ 2809 2810 /* Bit 0 : Status of data in register RXDATA */ 2811 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */ 2812 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */ 2813 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register RXDATA */ 2814 #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (0x1UL) /*!< Data pending in register RXDATA */ 2815 2816 /* Register: CTRLAPPERI_MAILBOX_TXDATA */ 2817 /* Description: Data sent from the CPU to the debugger. */ 2818 2819 /* Bits 31..0 : Data sent to debugger */ 2820 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */ 2821 #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */ 2822 2823 /* Register: CTRLAPPERI_MAILBOX_TXSTATUS */ 2824 /* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */ 2825 2826 /* Bit 0 : Status of data in register TXDATA */ 2827 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */ 2828 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */ 2829 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register TXDATA */ 2830 #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (0x1UL) /*!< Data pending in register TXDATA */ 2831 2832 /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */ 2833 /* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */ 2834 2835 /* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */ 2836 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ 2837 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ 2838 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0x0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */ 2839 #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (0x1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */ 2840 2841 /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */ 2842 /* Description: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */ 2843 2844 /* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ 2845 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ 2846 #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ 2847 2848 2849 /* Peripheral: DPPIC */ 2850 /* Description: Distributed programmable peripheral interconnect controller 0 */ 2851 2852 /* Register: DPPIC_TASKS_CHG_EN */ 2853 /* Description: Description cluster: Enable channel group n */ 2854 2855 /* Bit 0 : Enable channel group n */ 2856 #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ 2857 #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ 2858 #define DPPIC_TASKS_CHG_EN_EN_Trigger (0x1UL) /*!< Trigger task */ 2859 2860 /* Register: DPPIC_TASKS_CHG_DIS */ 2861 /* Description: Description cluster: Disable channel group n */ 2862 2863 /* Bit 0 : Disable channel group n */ 2864 #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ 2865 #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ 2866 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (0x1UL) /*!< Trigger task */ 2867 2868 /* Register: DPPIC_SUBSCRIBE_CHG_EN */ 2869 /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */ 2870 2871 /* Bit 31 : */ 2872 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */ 2873 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ 2874 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0x0UL) /*!< Disable subscription */ 2875 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (0x1UL) /*!< Enable subscription */ 2876 2877 /* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */ 2878 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2879 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2880 2881 /* Register: DPPIC_SUBSCRIBE_CHG_DIS */ 2882 /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */ 2883 2884 /* Bit 31 : */ 2885 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */ 2886 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */ 2887 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0x0UL) /*!< Disable subscription */ 2888 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (0x1UL) /*!< Enable subscription */ 2889 2890 /* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */ 2891 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2892 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2893 2894 /* Register: DPPIC_CHEN */ 2895 /* Description: Channel enable register */ 2896 2897 /* Bit 15 : Enable or disable channel 15 */ 2898 #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ 2899 #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ 2900 #define DPPIC_CHEN_CH15_Disabled (0x0UL) /*!< Disable channel */ 2901 #define DPPIC_CHEN_CH15_Enabled (0x1UL) /*!< Enable channel */ 2902 2903 /* Bit 14 : Enable or disable channel 14 */ 2904 #define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ 2905 #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ 2906 #define DPPIC_CHEN_CH14_Disabled (0x0UL) /*!< Disable channel */ 2907 #define DPPIC_CHEN_CH14_Enabled (0x1UL) /*!< Enable channel */ 2908 2909 /* Bit 13 : Enable or disable channel 13 */ 2910 #define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ 2911 #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ 2912 #define DPPIC_CHEN_CH13_Disabled (0x0UL) /*!< Disable channel */ 2913 #define DPPIC_CHEN_CH13_Enabled (0x1UL) /*!< Enable channel */ 2914 2915 /* Bit 12 : Enable or disable channel 12 */ 2916 #define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ 2917 #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ 2918 #define DPPIC_CHEN_CH12_Disabled (0x0UL) /*!< Disable channel */ 2919 #define DPPIC_CHEN_CH12_Enabled (0x1UL) /*!< Enable channel */ 2920 2921 /* Bit 11 : Enable or disable channel 11 */ 2922 #define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ 2923 #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ 2924 #define DPPIC_CHEN_CH11_Disabled (0x0UL) /*!< Disable channel */ 2925 #define DPPIC_CHEN_CH11_Enabled (0x1UL) /*!< Enable channel */ 2926 2927 /* Bit 10 : Enable or disable channel 10 */ 2928 #define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ 2929 #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ 2930 #define DPPIC_CHEN_CH10_Disabled (0x0UL) /*!< Disable channel */ 2931 #define DPPIC_CHEN_CH10_Enabled (0x1UL) /*!< Enable channel */ 2932 2933 /* Bit 9 : Enable or disable channel 9 */ 2934 #define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ 2935 #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ 2936 #define DPPIC_CHEN_CH9_Disabled (0x0UL) /*!< Disable channel */ 2937 #define DPPIC_CHEN_CH9_Enabled (0x1UL) /*!< Enable channel */ 2938 2939 /* Bit 8 : Enable or disable channel 8 */ 2940 #define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ 2941 #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ 2942 #define DPPIC_CHEN_CH8_Disabled (0x0UL) /*!< Disable channel */ 2943 #define DPPIC_CHEN_CH8_Enabled (0x1UL) /*!< Enable channel */ 2944 2945 /* Bit 7 : Enable or disable channel 7 */ 2946 #define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ 2947 #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ 2948 #define DPPIC_CHEN_CH7_Disabled (0x0UL) /*!< Disable channel */ 2949 #define DPPIC_CHEN_CH7_Enabled (0x1UL) /*!< Enable channel */ 2950 2951 /* Bit 6 : Enable or disable channel 6 */ 2952 #define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ 2953 #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ 2954 #define DPPIC_CHEN_CH6_Disabled (0x0UL) /*!< Disable channel */ 2955 #define DPPIC_CHEN_CH6_Enabled (0x1UL) /*!< Enable channel */ 2956 2957 /* Bit 5 : Enable or disable channel 5 */ 2958 #define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ 2959 #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ 2960 #define DPPIC_CHEN_CH5_Disabled (0x0UL) /*!< Disable channel */ 2961 #define DPPIC_CHEN_CH5_Enabled (0x1UL) /*!< Enable channel */ 2962 2963 /* Bit 4 : Enable or disable channel 4 */ 2964 #define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ 2965 #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ 2966 #define DPPIC_CHEN_CH4_Disabled (0x0UL) /*!< Disable channel */ 2967 #define DPPIC_CHEN_CH4_Enabled (0x1UL) /*!< Enable channel */ 2968 2969 /* Bit 3 : Enable or disable channel 3 */ 2970 #define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ 2971 #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ 2972 #define DPPIC_CHEN_CH3_Disabled (0x0UL) /*!< Disable channel */ 2973 #define DPPIC_CHEN_CH3_Enabled (0x1UL) /*!< Enable channel */ 2974 2975 /* Bit 2 : Enable or disable channel 2 */ 2976 #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ 2977 #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ 2978 #define DPPIC_CHEN_CH2_Disabled (0x0UL) /*!< Disable channel */ 2979 #define DPPIC_CHEN_CH2_Enabled (0x1UL) /*!< Enable channel */ 2980 2981 /* Bit 1 : Enable or disable channel 1 */ 2982 #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ 2983 #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ 2984 #define DPPIC_CHEN_CH1_Disabled (0x0UL) /*!< Disable channel */ 2985 #define DPPIC_CHEN_CH1_Enabled (0x1UL) /*!< Enable channel */ 2986 2987 /* Bit 0 : Enable or disable channel 0 */ 2988 #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ 2989 #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ 2990 #define DPPIC_CHEN_CH0_Disabled (0x0UL) /*!< Disable channel */ 2991 #define DPPIC_CHEN_CH0_Enabled (0x1UL) /*!< Enable channel */ 2992 2993 /* Register: DPPIC_CHENSET */ 2994 /* Description: Channel enable set register */ 2995 2996 /* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */ 2997 #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ 2998 #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ 2999 #define DPPIC_CHENSET_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */ 3000 #define DPPIC_CHENSET_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */ 3001 #define DPPIC_CHENSET_CH15_Set (0x1UL) /*!< Write: Enable channel */ 3002 3003 /* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */ 3004 #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ 3005 #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ 3006 #define DPPIC_CHENSET_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */ 3007 #define DPPIC_CHENSET_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */ 3008 #define DPPIC_CHENSET_CH14_Set (0x1UL) /*!< Write: Enable channel */ 3009 3010 /* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */ 3011 #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ 3012 #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ 3013 #define DPPIC_CHENSET_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */ 3014 #define DPPIC_CHENSET_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */ 3015 #define DPPIC_CHENSET_CH13_Set (0x1UL) /*!< Write: Enable channel */ 3016 3017 /* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */ 3018 #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ 3019 #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ 3020 #define DPPIC_CHENSET_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */ 3021 #define DPPIC_CHENSET_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */ 3022 #define DPPIC_CHENSET_CH12_Set (0x1UL) /*!< Write: Enable channel */ 3023 3024 /* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */ 3025 #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ 3026 #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ 3027 #define DPPIC_CHENSET_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */ 3028 #define DPPIC_CHENSET_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */ 3029 #define DPPIC_CHENSET_CH11_Set (0x1UL) /*!< Write: Enable channel */ 3030 3031 /* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */ 3032 #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ 3033 #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ 3034 #define DPPIC_CHENSET_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */ 3035 #define DPPIC_CHENSET_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */ 3036 #define DPPIC_CHENSET_CH10_Set (0x1UL) /*!< Write: Enable channel */ 3037 3038 /* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */ 3039 #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ 3040 #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ 3041 #define DPPIC_CHENSET_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */ 3042 #define DPPIC_CHENSET_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */ 3043 #define DPPIC_CHENSET_CH9_Set (0x1UL) /*!< Write: Enable channel */ 3044 3045 /* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */ 3046 #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ 3047 #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ 3048 #define DPPIC_CHENSET_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */ 3049 #define DPPIC_CHENSET_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */ 3050 #define DPPIC_CHENSET_CH8_Set (0x1UL) /*!< Write: Enable channel */ 3051 3052 /* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */ 3053 #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ 3054 #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ 3055 #define DPPIC_CHENSET_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */ 3056 #define DPPIC_CHENSET_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */ 3057 #define DPPIC_CHENSET_CH7_Set (0x1UL) /*!< Write: Enable channel */ 3058 3059 /* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */ 3060 #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ 3061 #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ 3062 #define DPPIC_CHENSET_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */ 3063 #define DPPIC_CHENSET_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */ 3064 #define DPPIC_CHENSET_CH6_Set (0x1UL) /*!< Write: Enable channel */ 3065 3066 /* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */ 3067 #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ 3068 #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ 3069 #define DPPIC_CHENSET_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */ 3070 #define DPPIC_CHENSET_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */ 3071 #define DPPIC_CHENSET_CH5_Set (0x1UL) /*!< Write: Enable channel */ 3072 3073 /* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */ 3074 #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ 3075 #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ 3076 #define DPPIC_CHENSET_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */ 3077 #define DPPIC_CHENSET_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */ 3078 #define DPPIC_CHENSET_CH4_Set (0x1UL) /*!< Write: Enable channel */ 3079 3080 /* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */ 3081 #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ 3082 #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ 3083 #define DPPIC_CHENSET_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */ 3084 #define DPPIC_CHENSET_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */ 3085 #define DPPIC_CHENSET_CH3_Set (0x1UL) /*!< Write: Enable channel */ 3086 3087 /* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */ 3088 #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ 3089 #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ 3090 #define DPPIC_CHENSET_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */ 3091 #define DPPIC_CHENSET_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */ 3092 #define DPPIC_CHENSET_CH2_Set (0x1UL) /*!< Write: Enable channel */ 3093 3094 /* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */ 3095 #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ 3096 #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ 3097 #define DPPIC_CHENSET_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */ 3098 #define DPPIC_CHENSET_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */ 3099 #define DPPIC_CHENSET_CH1_Set (0x1UL) /*!< Write: Enable channel */ 3100 3101 /* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */ 3102 #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ 3103 #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ 3104 #define DPPIC_CHENSET_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */ 3105 #define DPPIC_CHENSET_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */ 3106 #define DPPIC_CHENSET_CH0_Set (0x1UL) /*!< Write: Enable channel */ 3107 3108 /* Register: DPPIC_CHENCLR */ 3109 /* Description: Channel enable clear register */ 3110 3111 /* Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */ 3112 #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ 3113 #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ 3114 #define DPPIC_CHENCLR_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */ 3115 #define DPPIC_CHENCLR_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */ 3116 #define DPPIC_CHENCLR_CH15_Clear (0x1UL) /*!< Write: Disable channel */ 3117 3118 /* Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */ 3119 #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ 3120 #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ 3121 #define DPPIC_CHENCLR_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */ 3122 #define DPPIC_CHENCLR_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */ 3123 #define DPPIC_CHENCLR_CH14_Clear (0x1UL) /*!< Write: Disable channel */ 3124 3125 /* Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */ 3126 #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ 3127 #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ 3128 #define DPPIC_CHENCLR_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */ 3129 #define DPPIC_CHENCLR_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */ 3130 #define DPPIC_CHENCLR_CH13_Clear (0x1UL) /*!< Write: Disable channel */ 3131 3132 /* Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */ 3133 #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ 3134 #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ 3135 #define DPPIC_CHENCLR_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */ 3136 #define DPPIC_CHENCLR_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */ 3137 #define DPPIC_CHENCLR_CH12_Clear (0x1UL) /*!< Write: Disable channel */ 3138 3139 /* Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */ 3140 #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ 3141 #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ 3142 #define DPPIC_CHENCLR_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */ 3143 #define DPPIC_CHENCLR_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */ 3144 #define DPPIC_CHENCLR_CH11_Clear (0x1UL) /*!< Write: Disable channel */ 3145 3146 /* Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */ 3147 #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ 3148 #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ 3149 #define DPPIC_CHENCLR_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */ 3150 #define DPPIC_CHENCLR_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */ 3151 #define DPPIC_CHENCLR_CH10_Clear (0x1UL) /*!< Write: Disable channel */ 3152 3153 /* Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */ 3154 #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ 3155 #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ 3156 #define DPPIC_CHENCLR_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */ 3157 #define DPPIC_CHENCLR_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */ 3158 #define DPPIC_CHENCLR_CH9_Clear (0x1UL) /*!< Write: Disable channel */ 3159 3160 /* Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */ 3161 #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ 3162 #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ 3163 #define DPPIC_CHENCLR_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */ 3164 #define DPPIC_CHENCLR_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */ 3165 #define DPPIC_CHENCLR_CH8_Clear (0x1UL) /*!< Write: Disable channel */ 3166 3167 /* Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */ 3168 #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ 3169 #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ 3170 #define DPPIC_CHENCLR_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */ 3171 #define DPPIC_CHENCLR_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */ 3172 #define DPPIC_CHENCLR_CH7_Clear (0x1UL) /*!< Write: Disable channel */ 3173 3174 /* Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */ 3175 #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ 3176 #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ 3177 #define DPPIC_CHENCLR_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */ 3178 #define DPPIC_CHENCLR_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */ 3179 #define DPPIC_CHENCLR_CH6_Clear (0x1UL) /*!< Write: Disable channel */ 3180 3181 /* Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */ 3182 #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ 3183 #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ 3184 #define DPPIC_CHENCLR_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */ 3185 #define DPPIC_CHENCLR_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */ 3186 #define DPPIC_CHENCLR_CH5_Clear (0x1UL) /*!< Write: Disable channel */ 3187 3188 /* Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */ 3189 #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ 3190 #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ 3191 #define DPPIC_CHENCLR_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */ 3192 #define DPPIC_CHENCLR_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */ 3193 #define DPPIC_CHENCLR_CH4_Clear (0x1UL) /*!< Write: Disable channel */ 3194 3195 /* Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */ 3196 #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ 3197 #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ 3198 #define DPPIC_CHENCLR_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */ 3199 #define DPPIC_CHENCLR_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */ 3200 #define DPPIC_CHENCLR_CH3_Clear (0x1UL) /*!< Write: Disable channel */ 3201 3202 /* Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */ 3203 #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ 3204 #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ 3205 #define DPPIC_CHENCLR_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */ 3206 #define DPPIC_CHENCLR_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */ 3207 #define DPPIC_CHENCLR_CH2_Clear (0x1UL) /*!< Write: Disable channel */ 3208 3209 /* Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */ 3210 #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ 3211 #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ 3212 #define DPPIC_CHENCLR_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */ 3213 #define DPPIC_CHENCLR_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */ 3214 #define DPPIC_CHENCLR_CH1_Clear (0x1UL) /*!< Write: Disable channel */ 3215 3216 /* Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */ 3217 #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ 3218 #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ 3219 #define DPPIC_CHENCLR_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */ 3220 #define DPPIC_CHENCLR_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */ 3221 #define DPPIC_CHENCLR_CH0_Clear (0x1UL) /*!< Write: Disable channel */ 3222 3223 /* Register: DPPIC_CHG */ 3224 /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */ 3225 3226 /* Bit 15 : Include or exclude channel 15 */ 3227 #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ 3228 #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ 3229 #define DPPIC_CHG_CH15_Excluded (0x0UL) /*!< Exclude */ 3230 #define DPPIC_CHG_CH15_Included (0x1UL) /*!< Include */ 3231 3232 /* Bit 14 : Include or exclude channel 14 */ 3233 #define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ 3234 #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ 3235 #define DPPIC_CHG_CH14_Excluded (0x0UL) /*!< Exclude */ 3236 #define DPPIC_CHG_CH14_Included (0x1UL) /*!< Include */ 3237 3238 /* Bit 13 : Include or exclude channel 13 */ 3239 #define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ 3240 #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ 3241 #define DPPIC_CHG_CH13_Excluded (0x0UL) /*!< Exclude */ 3242 #define DPPIC_CHG_CH13_Included (0x1UL) /*!< Include */ 3243 3244 /* Bit 12 : Include or exclude channel 12 */ 3245 #define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ 3246 #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ 3247 #define DPPIC_CHG_CH12_Excluded (0x0UL) /*!< Exclude */ 3248 #define DPPIC_CHG_CH12_Included (0x1UL) /*!< Include */ 3249 3250 /* Bit 11 : Include or exclude channel 11 */ 3251 #define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ 3252 #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ 3253 #define DPPIC_CHG_CH11_Excluded (0x0UL) /*!< Exclude */ 3254 #define DPPIC_CHG_CH11_Included (0x1UL) /*!< Include */ 3255 3256 /* Bit 10 : Include or exclude channel 10 */ 3257 #define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ 3258 #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ 3259 #define DPPIC_CHG_CH10_Excluded (0x0UL) /*!< Exclude */ 3260 #define DPPIC_CHG_CH10_Included (0x1UL) /*!< Include */ 3261 3262 /* Bit 9 : Include or exclude channel 9 */ 3263 #define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ 3264 #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ 3265 #define DPPIC_CHG_CH9_Excluded (0x0UL) /*!< Exclude */ 3266 #define DPPIC_CHG_CH9_Included (0x1UL) /*!< Include */ 3267 3268 /* Bit 8 : Include or exclude channel 8 */ 3269 #define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ 3270 #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ 3271 #define DPPIC_CHG_CH8_Excluded (0x0UL) /*!< Exclude */ 3272 #define DPPIC_CHG_CH8_Included (0x1UL) /*!< Include */ 3273 3274 /* Bit 7 : Include or exclude channel 7 */ 3275 #define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ 3276 #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ 3277 #define DPPIC_CHG_CH7_Excluded (0x0UL) /*!< Exclude */ 3278 #define DPPIC_CHG_CH7_Included (0x1UL) /*!< Include */ 3279 3280 /* Bit 6 : Include or exclude channel 6 */ 3281 #define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ 3282 #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ 3283 #define DPPIC_CHG_CH6_Excluded (0x0UL) /*!< Exclude */ 3284 #define DPPIC_CHG_CH6_Included (0x1UL) /*!< Include */ 3285 3286 /* Bit 5 : Include or exclude channel 5 */ 3287 #define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ 3288 #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ 3289 #define DPPIC_CHG_CH5_Excluded (0x0UL) /*!< Exclude */ 3290 #define DPPIC_CHG_CH5_Included (0x1UL) /*!< Include */ 3291 3292 /* Bit 4 : Include or exclude channel 4 */ 3293 #define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ 3294 #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ 3295 #define DPPIC_CHG_CH4_Excluded (0x0UL) /*!< Exclude */ 3296 #define DPPIC_CHG_CH4_Included (0x1UL) /*!< Include */ 3297 3298 /* Bit 3 : Include or exclude channel 3 */ 3299 #define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ 3300 #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ 3301 #define DPPIC_CHG_CH3_Excluded (0x0UL) /*!< Exclude */ 3302 #define DPPIC_CHG_CH3_Included (0x1UL) /*!< Include */ 3303 3304 /* Bit 2 : Include or exclude channel 2 */ 3305 #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ 3306 #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ 3307 #define DPPIC_CHG_CH2_Excluded (0x0UL) /*!< Exclude */ 3308 #define DPPIC_CHG_CH2_Included (0x1UL) /*!< Include */ 3309 3310 /* Bit 1 : Include or exclude channel 1 */ 3311 #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ 3312 #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ 3313 #define DPPIC_CHG_CH1_Excluded (0x0UL) /*!< Exclude */ 3314 #define DPPIC_CHG_CH1_Included (0x1UL) /*!< Include */ 3315 3316 /* Bit 0 : Include or exclude channel 0 */ 3317 #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ 3318 #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ 3319 #define DPPIC_CHG_CH0_Excluded (0x0UL) /*!< Exclude */ 3320 #define DPPIC_CHG_CH0_Included (0x1UL) /*!< Include */ 3321 3322 3323 /* Peripheral: EGU */ 3324 /* Description: Event generator unit 0 */ 3325 3326 /* Register: EGU_TASKS_TRIGGER */ 3327 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ 3328 3329 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ 3330 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ 3331 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ 3332 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */ 3333 3334 /* Register: EGU_SUBSCRIBE_TRIGGER */ 3335 /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */ 3336 3337 /* Bit 31 : */ 3338 #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ 3339 #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */ 3340 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL) /*!< Disable subscription */ 3341 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL) /*!< Enable subscription */ 3342 3343 /* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */ 3344 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3345 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3346 3347 /* Register: EGU_EVENTS_TRIGGERED */ 3348 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ 3349 3350 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ 3351 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ 3352 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ 3353 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated */ 3354 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated */ 3355 3356 /* Register: EGU_PUBLISH_TRIGGERED */ 3357 /* Description: Description collection: Publish configuration for event TRIGGERED[n] */ 3358 3359 /* Bit 31 : */ 3360 #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ 3361 #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */ 3362 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0x0UL) /*!< Disable publishing */ 3363 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (0x1UL) /*!< Enable publishing */ 3364 3365 /* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to */ 3366 #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3367 #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3368 3369 /* Register: EGU_INTEN */ 3370 /* Description: Enable or disable interrupt */ 3371 3372 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ 3373 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 3374 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 3375 #define EGU_INTEN_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ 3376 #define EGU_INTEN_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ 3377 3378 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ 3379 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 3380 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 3381 #define EGU_INTEN_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ 3382 #define EGU_INTEN_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ 3383 3384 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ 3385 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 3386 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 3387 #define EGU_INTEN_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ 3388 #define EGU_INTEN_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ 3389 3390 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ 3391 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 3392 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 3393 #define EGU_INTEN_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ 3394 #define EGU_INTEN_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ 3395 3396 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ 3397 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 3398 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 3399 #define EGU_INTEN_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ 3400 #define EGU_INTEN_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ 3401 3402 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ 3403 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 3404 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 3405 #define EGU_INTEN_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ 3406 #define EGU_INTEN_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ 3407 3408 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ 3409 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 3410 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 3411 #define EGU_INTEN_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ 3412 #define EGU_INTEN_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ 3413 3414 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ 3415 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 3416 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 3417 #define EGU_INTEN_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ 3418 #define EGU_INTEN_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ 3419 3420 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ 3421 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 3422 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 3423 #define EGU_INTEN_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ 3424 #define EGU_INTEN_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ 3425 3426 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ 3427 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 3428 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 3429 #define EGU_INTEN_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ 3430 #define EGU_INTEN_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ 3431 3432 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ 3433 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 3434 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 3435 #define EGU_INTEN_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ 3436 #define EGU_INTEN_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ 3437 3438 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ 3439 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 3440 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 3441 #define EGU_INTEN_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ 3442 #define EGU_INTEN_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ 3443 3444 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ 3445 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 3446 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 3447 #define EGU_INTEN_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ 3448 #define EGU_INTEN_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ 3449 3450 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ 3451 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 3452 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 3453 #define EGU_INTEN_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ 3454 #define EGU_INTEN_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ 3455 3456 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ 3457 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 3458 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 3459 #define EGU_INTEN_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ 3460 #define EGU_INTEN_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ 3461 3462 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ 3463 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 3464 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 3465 #define EGU_INTEN_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ 3466 #define EGU_INTEN_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ 3467 3468 /* Register: EGU_INTENSET */ 3469 /* Description: Enable interrupt */ 3470 3471 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ 3472 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 3473 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 3474 #define EGU_INTENSET_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ 3475 #define EGU_INTENSET_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ 3476 #define EGU_INTENSET_TRIGGERED15_Set (0x1UL) /*!< Enable */ 3477 3478 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ 3479 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 3480 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 3481 #define EGU_INTENSET_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ 3482 #define EGU_INTENSET_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ 3483 #define EGU_INTENSET_TRIGGERED14_Set (0x1UL) /*!< Enable */ 3484 3485 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ 3486 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 3487 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 3488 #define EGU_INTENSET_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ 3489 #define EGU_INTENSET_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ 3490 #define EGU_INTENSET_TRIGGERED13_Set (0x1UL) /*!< Enable */ 3491 3492 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ 3493 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 3494 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 3495 #define EGU_INTENSET_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ 3496 #define EGU_INTENSET_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ 3497 #define EGU_INTENSET_TRIGGERED12_Set (0x1UL) /*!< Enable */ 3498 3499 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ 3500 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 3501 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 3502 #define EGU_INTENSET_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ 3503 #define EGU_INTENSET_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ 3504 #define EGU_INTENSET_TRIGGERED11_Set (0x1UL) /*!< Enable */ 3505 3506 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ 3507 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 3508 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 3509 #define EGU_INTENSET_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ 3510 #define EGU_INTENSET_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ 3511 #define EGU_INTENSET_TRIGGERED10_Set (0x1UL) /*!< Enable */ 3512 3513 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ 3514 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 3515 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 3516 #define EGU_INTENSET_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ 3517 #define EGU_INTENSET_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ 3518 #define EGU_INTENSET_TRIGGERED9_Set (0x1UL) /*!< Enable */ 3519 3520 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ 3521 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 3522 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 3523 #define EGU_INTENSET_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ 3524 #define EGU_INTENSET_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ 3525 #define EGU_INTENSET_TRIGGERED8_Set (0x1UL) /*!< Enable */ 3526 3527 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ 3528 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 3529 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 3530 #define EGU_INTENSET_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ 3531 #define EGU_INTENSET_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ 3532 #define EGU_INTENSET_TRIGGERED7_Set (0x1UL) /*!< Enable */ 3533 3534 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ 3535 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 3536 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 3537 #define EGU_INTENSET_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ 3538 #define EGU_INTENSET_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ 3539 #define EGU_INTENSET_TRIGGERED6_Set (0x1UL) /*!< Enable */ 3540 3541 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ 3542 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 3543 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 3544 #define EGU_INTENSET_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ 3545 #define EGU_INTENSET_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ 3546 #define EGU_INTENSET_TRIGGERED5_Set (0x1UL) /*!< Enable */ 3547 3548 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ 3549 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 3550 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 3551 #define EGU_INTENSET_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ 3552 #define EGU_INTENSET_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ 3553 #define EGU_INTENSET_TRIGGERED4_Set (0x1UL) /*!< Enable */ 3554 3555 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ 3556 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 3557 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 3558 #define EGU_INTENSET_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ 3559 #define EGU_INTENSET_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ 3560 #define EGU_INTENSET_TRIGGERED3_Set (0x1UL) /*!< Enable */ 3561 3562 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ 3563 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 3564 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 3565 #define EGU_INTENSET_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ 3566 #define EGU_INTENSET_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ 3567 #define EGU_INTENSET_TRIGGERED2_Set (0x1UL) /*!< Enable */ 3568 3569 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ 3570 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 3571 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 3572 #define EGU_INTENSET_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ 3573 #define EGU_INTENSET_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ 3574 #define EGU_INTENSET_TRIGGERED1_Set (0x1UL) /*!< Enable */ 3575 3576 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ 3577 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 3578 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 3579 #define EGU_INTENSET_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ 3580 #define EGU_INTENSET_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ 3581 #define EGU_INTENSET_TRIGGERED0_Set (0x1UL) /*!< Enable */ 3582 3583 /* Register: EGU_INTENCLR */ 3584 /* Description: Disable interrupt */ 3585 3586 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ 3587 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 3588 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 3589 #define EGU_INTENCLR_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ 3590 #define EGU_INTENCLR_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ 3591 #define EGU_INTENCLR_TRIGGERED15_Clear (0x1UL) /*!< Disable */ 3592 3593 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ 3594 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 3595 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 3596 #define EGU_INTENCLR_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ 3597 #define EGU_INTENCLR_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ 3598 #define EGU_INTENCLR_TRIGGERED14_Clear (0x1UL) /*!< Disable */ 3599 3600 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ 3601 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 3602 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 3603 #define EGU_INTENCLR_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ 3604 #define EGU_INTENCLR_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ 3605 #define EGU_INTENCLR_TRIGGERED13_Clear (0x1UL) /*!< Disable */ 3606 3607 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ 3608 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 3609 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 3610 #define EGU_INTENCLR_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ 3611 #define EGU_INTENCLR_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ 3612 #define EGU_INTENCLR_TRIGGERED12_Clear (0x1UL) /*!< Disable */ 3613 3614 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ 3615 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 3616 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 3617 #define EGU_INTENCLR_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ 3618 #define EGU_INTENCLR_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ 3619 #define EGU_INTENCLR_TRIGGERED11_Clear (0x1UL) /*!< Disable */ 3620 3621 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ 3622 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 3623 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 3624 #define EGU_INTENCLR_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ 3625 #define EGU_INTENCLR_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ 3626 #define EGU_INTENCLR_TRIGGERED10_Clear (0x1UL) /*!< Disable */ 3627 3628 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ 3629 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 3630 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 3631 #define EGU_INTENCLR_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ 3632 #define EGU_INTENCLR_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ 3633 #define EGU_INTENCLR_TRIGGERED9_Clear (0x1UL) /*!< Disable */ 3634 3635 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ 3636 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 3637 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 3638 #define EGU_INTENCLR_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ 3639 #define EGU_INTENCLR_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ 3640 #define EGU_INTENCLR_TRIGGERED8_Clear (0x1UL) /*!< Disable */ 3641 3642 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ 3643 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 3644 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 3645 #define EGU_INTENCLR_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ 3646 #define EGU_INTENCLR_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ 3647 #define EGU_INTENCLR_TRIGGERED7_Clear (0x1UL) /*!< Disable */ 3648 3649 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ 3650 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 3651 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 3652 #define EGU_INTENCLR_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ 3653 #define EGU_INTENCLR_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ 3654 #define EGU_INTENCLR_TRIGGERED6_Clear (0x1UL) /*!< Disable */ 3655 3656 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ 3657 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 3658 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 3659 #define EGU_INTENCLR_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ 3660 #define EGU_INTENCLR_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ 3661 #define EGU_INTENCLR_TRIGGERED5_Clear (0x1UL) /*!< Disable */ 3662 3663 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ 3664 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 3665 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 3666 #define EGU_INTENCLR_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ 3667 #define EGU_INTENCLR_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ 3668 #define EGU_INTENCLR_TRIGGERED4_Clear (0x1UL) /*!< Disable */ 3669 3670 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ 3671 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 3672 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 3673 #define EGU_INTENCLR_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ 3674 #define EGU_INTENCLR_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ 3675 #define EGU_INTENCLR_TRIGGERED3_Clear (0x1UL) /*!< Disable */ 3676 3677 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ 3678 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 3679 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 3680 #define EGU_INTENCLR_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ 3681 #define EGU_INTENCLR_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ 3682 #define EGU_INTENCLR_TRIGGERED2_Clear (0x1UL) /*!< Disable */ 3683 3684 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ 3685 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 3686 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 3687 #define EGU_INTENCLR_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ 3688 #define EGU_INTENCLR_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ 3689 #define EGU_INTENCLR_TRIGGERED1_Clear (0x1UL) /*!< Disable */ 3690 3691 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ 3692 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 3693 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 3694 #define EGU_INTENCLR_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ 3695 #define EGU_INTENCLR_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ 3696 #define EGU_INTENCLR_TRIGGERED0_Clear (0x1UL) /*!< Disable */ 3697 3698 3699 /* Peripheral: ETB */ 3700 /* Description: Embedded Trace Buffer */ 3701 3702 /* Register: ETB_RDP */ 3703 /* Description: ETB RAM Depth Register */ 3704 3705 /* Bits 31..0 : Defines the depth, in words, of the trace RAM. */ 3706 #define ETB_RDP_ETB_RAM_DEPTH_Pos (0UL) /*!< Position of ETB_RAM_DEPTH field. */ 3707 #define ETB_RDP_ETB_RAM_DEPTH_Msk (0xFFFFFFFFUL << ETB_RDP_ETB_RAM_DEPTH_Pos) /*!< Bit mask of ETB_RAM_DEPTH field. */ 3708 3709 /* Register: ETB_STS */ 3710 /* Description: ETB Status Register */ 3711 3712 /* Bit 3 : Formatter pipeline empty. All data stored to RAM. */ 3713 #define ETB_STS_FTEMPTY_Pos (3UL) /*!< Position of FTEMPTY field. */ 3714 #define ETB_STS_FTEMPTY_Msk (0x1UL << ETB_STS_FTEMPTY_Pos) /*!< Bit mask of FTEMPTY field. */ 3715 3716 /* Bit 2 : The acquisition complete flag indicates that capture has been completed when the formatter stops because of any of the methods defined in the Formatter and Flush Control Register, or TraceCaptEn = 0. This also results in FtStopped in the Formatter and Flush Status Register going HIGH. */ 3717 #define ETB_STS_ACQCOMP_Pos (2UL) /*!< Position of ACQCOMP field. */ 3718 #define ETB_STS_ACQCOMP_Msk (0x1UL << ETB_STS_ACQCOMP_Pos) /*!< Bit mask of ACQCOMP field. */ 3719 3720 /* Bit 1 : The Triggered bit is set when a trigger has been observed. This does not indicate that a trigger has been embedded in the trace data by the formatter, but is determined by the programming of the Formatter and Flush Control Register. */ 3721 #define ETB_STS_TRIGGERED_Pos (1UL) /*!< Position of TRIGGERED field. */ 3722 #define ETB_STS_TRIGGERED_Msk (0x1UL << ETB_STS_TRIGGERED_Pos) /*!< Bit mask of TRIGGERED field. */ 3723 3724 /* Bit 0 : RAM Full. The flag indicates when the RAM write pointer has wrapped around. */ 3725 #define ETB_STS_FULL_Pos (0UL) /*!< Position of FULL field. */ 3726 #define ETB_STS_FULL_Msk (0x1UL << ETB_STS_FULL_Pos) /*!< Bit mask of FULL field. */ 3727 3728 /* Register: ETB_RRD */ 3729 /* Description: ETB RAM Read Data Register */ 3730 3731 /* Bits 31..0 : Data read from the ETB Trace RAM. */ 3732 #define ETB_RRD_RAM_READ_DATA_Pos (0UL) /*!< Position of RAM_READ_DATA field. */ 3733 #define ETB_RRD_RAM_READ_DATA_Msk (0xFFFFFFFFUL << ETB_RRD_RAM_READ_DATA_Pos) /*!< Bit mask of RAM_READ_DATA field. */ 3734 3735 /* Register: ETB_RRP */ 3736 /* Description: ETB RAM Read Pointer Register */ 3737 3738 /* Bits 9..0 : Sets the read pointer used to read entries from the Trace RAM over the APB interface. */ 3739 #define ETB_RRP_RAM_READ_POINTER_Pos (0UL) /*!< Position of RAM_READ_POINTER field. */ 3740 #define ETB_RRP_RAM_READ_POINTER_Msk (0x3FFUL << ETB_RRP_RAM_READ_POINTER_Pos) /*!< Bit mask of RAM_READ_POINTER field. */ 3741 3742 /* Register: ETB_RWP */ 3743 /* Description: ETB RAM Write Pointer Register */ 3744 3745 /* Bits 9..0 : Sets the write pointer used to write entries from the CoreSight bus into the Trace RAM. */ 3746 #define ETB_RWP_RAM_WRITE_POINTER_Pos (0UL) /*!< Position of RAM_WRITE_POINTER field. */ 3747 #define ETB_RWP_RAM_WRITE_POINTER_Msk (0x3FFUL << ETB_RWP_RAM_WRITE_POINTER_Pos) /*!< Bit mask of RAM_WRITE_POINTER field. */ 3748 3749 /* Register: ETB_TRG */ 3750 /* Description: ETB Trigger Counter Register */ 3751 3752 /* Bits 9..0 : The counter is used as follows:Trace after - The counter is set to a large value, slightly less than the number of entries in the RAM. Trace before - The counter is set to a small value. Trace about - The counter is set to half the depth of the Trace RAM. This register must not be written to when trace capture is enabled (FtStopped=0, TraceCaptEn=1). If a write is attempted, the register is not updated. A read access is permitted with trace capture enabled. */ 3753 #define ETB_TRG_TRIGGER_COUNTER_Pos (0UL) /*!< Position of TRIGGER_COUNTER field. */ 3754 #define ETB_TRG_TRIGGER_COUNTER_Msk (0x3FFUL << ETB_TRG_TRIGGER_COUNTER_Pos) /*!< Bit mask of TRIGGER_COUNTER field. */ 3755 3756 /* Register: ETB_CTL */ 3757 /* Description: ETB Control Register */ 3758 3759 /* Bit 0 : ETB Trace Capture Enable. This is the master enable bit forcing FtStopped HIGH when TraceCaptEn is LOW. When capture is disabled, any remaining data in the ATB formatter is stored to RAM. When all data is stored the formatter outputs FtStopped. Capture is fully disabled, or complete, when FtStopped goes HIGH. See ETB Formatter and Flush Status Register, FFSR, 0x300. */ 3760 #define ETB_CTL_TRACECAPTEN_Pos (0UL) /*!< Position of TRACECAPTEN field. */ 3761 #define ETB_CTL_TRACECAPTEN_Msk (0x1UL << ETB_CTL_TRACECAPTEN_Pos) /*!< Bit mask of TRACECAPTEN field. */ 3762 3763 /* Register: ETB_RWD */ 3764 /* Description: ETB RAM Write Data Register */ 3765 3766 /* Bits 31..0 : Data written to the ETB Trace RAM. When trace capture is disabled, the contents of this register are placed into the ETB Trace RAM when this register is written to. Writing to this register increments the RAM Write Pointer Register. If trace capture is enabled, and this register is accessed, then a read from this register outputs 0xFFFFFFFF. Reads of this register never increment the RAM Write Pointer Register. A constant stream of 1s being output corresponds to a synchronization output from the ETB. If a write access is attempted, the data is not written into Trace RAM. */ 3767 #define ETB_RWD_RAM_WRITE_DATA_Pos (0UL) /*!< Position of RAM_WRITE_DATA field. */ 3768 #define ETB_RWD_RAM_WRITE_DATA_Msk (0xFFFFFFFFUL << ETB_RWD_RAM_WRITE_DATA_Pos) /*!< Bit mask of RAM_WRITE_DATA field. */ 3769 3770 /* Register: ETB_FFSR */ 3771 /* Description: ETB Formatter and Flush Status Register */ 3772 3773 /* Bit 1 : Formatter stopped. The formatter has received a stop request signal and all trace data and post-amble has been output. Any more trace data on the ATB interface is ignored and atreadys goes HIGH. */ 3774 #define ETB_FFSR_FTSTOPPED_Pos (1UL) /*!< Position of FTSTOPPED field. */ 3775 #define ETB_FFSR_FTSTOPPED_Msk (0x1UL << ETB_FFSR_FTSTOPPED_Pos) /*!< Bit mask of FTSTOPPED field. */ 3776 3777 /* Bit 0 : Flush In Progress. This is an indication of the current state of afvalids. */ 3778 #define ETB_FFSR_FLINPROG_Pos (0UL) /*!< Position of FLINPROG field. */ 3779 #define ETB_FFSR_FLINPROG_Msk (0x1UL << ETB_FFSR_FLINPROG_Pos) /*!< Bit mask of FLINPROG field. */ 3780 3781 /* Register: ETB_FFCR */ 3782 /* Description: ETB Formatter and Flush Control Register */ 3783 3784 /* Bit 13 : Stop the formatter after a Trigger Event is observed. Reset to disabled (zero). */ 3785 #define ETB_FFCR_STOPTRIG_Pos (13UL) /*!< Position of STOPTRIG field. */ 3786 #define ETB_FFCR_STOPTRIG_Msk (0x1UL << ETB_FFCR_STOPTRIG_Pos) /*!< Bit mask of STOPTRIG field. */ 3787 3788 /* Bit 12 : This forces the FIFO to drain off any part-completed packets. Setting this bit enables this function but this is clear on reset (disabled). */ 3789 #define ETB_FFCR_STOPFL_Pos (12UL) /*!< Position of STOPFL field. */ 3790 #define ETB_FFCR_STOPFL_Msk (0x1UL << ETB_FFCR_STOPFL_Pos) /*!< Bit mask of STOPFL field. */ 3791 3792 /* Bit 10 : Indicates a trigger on Flush completion (afreadys being returned). */ 3793 #define ETB_FFCR_TRIGFL_Pos (10UL) /*!< Position of TRIGFL field. */ 3794 #define ETB_FFCR_TRIGFL_Msk (0x1UL << ETB_FFCR_TRIGFL_Pos) /*!< Bit mask of TRIGFL field. */ 3795 3796 /* Bit 9 : Indicate a trigger on a Trigger Event. */ 3797 #define ETB_FFCR_TRIGEVT_Pos (9UL) /*!< Position of TRIGEVT field. */ 3798 #define ETB_FFCR_TRIGEVT_Msk (0x1UL << ETB_FFCR_TRIGEVT_Pos) /*!< Bit mask of TRIGEVT field. */ 3799 3800 /* Bit 8 : Indicate a trigger on trigin being asserted. */ 3801 #define ETB_FFCR_TRIGIN_Pos (8UL) /*!< Position of TRIGIN field. */ 3802 #define ETB_FFCR_TRIGIN_Msk (0x1UL << ETB_FFCR_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */ 3803 3804 /* Bit 6 : Setting this bit causes a flush to be generated. This is cleared when this flush has been serviced. This bit is clear on reset. */ 3805 #define ETB_FFCR_FONMAN_Pos (6UL) /*!< Position of FONMAN field. */ 3806 #define ETB_FFCR_FONMAN_Msk (0x1UL << ETB_FFCR_FONMAN_Pos) /*!< Bit mask of FONMAN field. */ 3807 3808 /* Bit 5 : Generate flush using Trigger event. Set this bit to cause a flush of data in the system when a Trigger Event occurs. This bit is clear on reset. A Trigger Event is defined as when the Trigger counter reaches zero (where fitted) or, in the case of the trigger counter being zero (or not fitted), when trigin is HIGH. */ 3809 #define ETB_FFCR_FONTRIG_Pos (5UL) /*!< Position of FONTRIG field. */ 3810 #define ETB_FFCR_FONTRIG_Msk (0x1UL << ETB_FFCR_FONTRIG_Pos) /*!< Bit mask of FONTRIG field. */ 3811 3812 /* Bit 4 : Set this bit to enable use of the flushin connection. This is clear on reset. */ 3813 #define ETB_FFCR_FONFLIN_Pos (4UL) /*!< Position of FONFLIN field. */ 3814 #define ETB_FFCR_FONFLIN_Msk (0x1UL << ETB_FFCR_FONFLIN_Pos) /*!< Bit mask of FONFLIN field. */ 3815 3816 /* Bit 1 : Continuous mode in the ETB corresponds to normal mode with the embedding of triggers. Can only be changed when FtStopped is HIGH. This bit is clear on reset. */ 3817 #define ETB_FFCR_ENFCONT_Pos (1UL) /*!< Position of ENFCONT field. */ 3818 #define ETB_FFCR_ENFCONT_Msk (0x1UL << ETB_FFCR_ENFCONT_Pos) /*!< Bit mask of ENFCONT field. */ 3819 3820 /* Bit 0 : Do not embed Triggers into the formatted stream. Trace disable cycles and triggers are indicated by TRACECTL, where fitted. Can only be changed when FtStopped is HIGH. This bit is clear on reset. */ 3821 #define ETB_FFCR_ENFTC_Pos (0UL) /*!< Position of ENFTC field. */ 3822 #define ETB_FFCR_ENFTC_Msk (0x1UL << ETB_FFCR_ENFTC_Pos) /*!< Bit mask of ENFTC field. */ 3823 3824 /* Register: ETB_ITMISCOP0 */ 3825 /* Description: Integration Test Miscellaneous Output Register 0 */ 3826 3827 /* Bit 1 : Set the value of full output port. */ 3828 #define ETB_ITMISCOP0_FULL_Pos (1UL) /*!< Position of FULL field. */ 3829 #define ETB_ITMISCOP0_FULL_Msk (0x1UL << ETB_ITMISCOP0_FULL_Pos) /*!< Bit mask of FULL field. */ 3830 3831 /* Bit 0 : Set the value of acqcomp. */ 3832 #define ETB_ITMISCOP0_ACQCOMP_Pos (0UL) /*!< Position of ACQCOMP field. */ 3833 #define ETB_ITMISCOP0_ACQCOMP_Msk (0x1UL << ETB_ITMISCOP0_ACQCOMP_Pos) /*!< Bit mask of ACQCOMP field. */ 3834 3835 /* Register: ETB_ITTRFLINACK */ 3836 /* Description: Integration Test Trigger In and Flush In Acknowledge Register */ 3837 3838 /* Bit 1 : Set the value of flushinack. */ 3839 #define ETB_ITTRFLINACK_FLUSHINACK_Pos (1UL) /*!< Position of FLUSHINACK field. */ 3840 #define ETB_ITTRFLINACK_FLUSHINACK_Msk (0x1UL << ETB_ITTRFLINACK_FLUSHINACK_Pos) /*!< Bit mask of FLUSHINACK field. */ 3841 3842 /* Bit 0 : Set the value of triginack. */ 3843 #define ETB_ITTRFLINACK_TRIGINACK_Pos (0UL) /*!< Position of TRIGINACK field. */ 3844 #define ETB_ITTRFLINACK_TRIGINACK_Msk (0x1UL << ETB_ITTRFLINACK_TRIGINACK_Pos) /*!< Bit mask of TRIGINACK field. */ 3845 3846 /* Register: ETB_ITTRFLIN */ 3847 /* Description: Integration Test Trigger In and Flush In Register */ 3848 3849 /* Bit 1 : Read the value of flushin. */ 3850 #define ETB_ITTRFLIN_FLUSHIN_Pos (1UL) /*!< Position of FLUSHIN field. */ 3851 #define ETB_ITTRFLIN_FLUSHIN_Msk (0x1UL << ETB_ITTRFLIN_FLUSHIN_Pos) /*!< Bit mask of FLUSHIN field. */ 3852 3853 /* Bit 0 : Read the value of trigin. */ 3854 #define ETB_ITTRFLIN_TRIGIN_Pos (0UL) /*!< Position of TRIGIN field. */ 3855 #define ETB_ITTRFLIN_TRIGIN_Msk (0x1UL << ETB_ITTRFLIN_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */ 3856 3857 /* Register: ETB_ITATBDATA0 */ 3858 /* Description: Integration Test ATB Data Register 0 */ 3859 3860 /* Bit 4 : Read the value of atdatas[31]. */ 3861 #define ETB_ITATBDATA0_ATDATA_31_Pos (4UL) /*!< Position of ATDATA_31 field. */ 3862 #define ETB_ITATBDATA0_ATDATA_31_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_31_Pos) /*!< Bit mask of ATDATA_31 field. */ 3863 3864 /* Bit 3 : Read the value of atdatas[23]. */ 3865 #define ETB_ITATBDATA0_ATDATA_23_Pos (3UL) /*!< Position of ATDATA_23 field. */ 3866 #define ETB_ITATBDATA0_ATDATA_23_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_23_Pos) /*!< Bit mask of ATDATA_23 field. */ 3867 3868 /* Bit 2 : Read the value of atdatas[15]. */ 3869 #define ETB_ITATBDATA0_ATDATA_15_Pos (2UL) /*!< Position of ATDATA_15 field. */ 3870 #define ETB_ITATBDATA0_ATDATA_15_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_15_Pos) /*!< Bit mask of ATDATA_15 field. */ 3871 3872 /* Bit 1 : Read the value of atdatas[7]. */ 3873 #define ETB_ITATBDATA0_ATDATA_7_Pos (1UL) /*!< Position of ATDATA_7 field. */ 3874 #define ETB_ITATBDATA0_ATDATA_7_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_7_Pos) /*!< Bit mask of ATDATA_7 field. */ 3875 3876 /* Bit 0 : Read the value of atdatas[0]. */ 3877 #define ETB_ITATBDATA0_ATDATA_0_Pos (0UL) /*!< Position of ATDATA_0 field. */ 3878 #define ETB_ITATBDATA0_ATDATA_0_Msk (0x1UL << ETB_ITATBDATA0_ATDATA_0_Pos) /*!< Bit mask of ATDATA_0 field. */ 3879 3880 /* Register: ETB_ITATBCTR2 */ 3881 /* Description: Integration Test ATB Control Register 2 */ 3882 3883 /* Bit 1 : Set the value of afvalids. */ 3884 #define ETB_ITATBCTR2_AFVALIDS_Pos (1UL) /*!< Position of AFVALIDS field. */ 3885 #define ETB_ITATBCTR2_AFVALIDS_Msk (0x1UL << ETB_ITATBCTR2_AFVALIDS_Pos) /*!< Bit mask of AFVALIDS field. */ 3886 3887 /* Bit 0 : Set the value of atreadys. */ 3888 #define ETB_ITATBCTR2_ATREADYS_Pos (0UL) /*!< Position of ATREADYS field. */ 3889 #define ETB_ITATBCTR2_ATREADYS_Msk (0x1UL << ETB_ITATBCTR2_ATREADYS_Pos) /*!< Bit mask of ATREADYS field. */ 3890 3891 /* Register: ETB_ITATBCTR1 */ 3892 /* Description: Integration Test ATB Control Register 1 */ 3893 3894 /* Bits 6..0 : Read the value of atids. */ 3895 #define ETB_ITATBCTR1_ATID_Pos (0UL) /*!< Position of ATID field. */ 3896 #define ETB_ITATBCTR1_ATID_Msk (0x7FUL << ETB_ITATBCTR1_ATID_Pos) /*!< Bit mask of ATID field. */ 3897 3898 /* Register: ETB_ITATBCTR0 */ 3899 /* Description: Integration Test ATB Control Register 0 */ 3900 3901 /* Bits 9..8 : Read the value of atbytess. */ 3902 #define ETB_ITATBCTR0_ATBYTES_Pos (8UL) /*!< Position of ATBYTES field. */ 3903 #define ETB_ITATBCTR0_ATBYTES_Msk (0x3UL << ETB_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field. */ 3904 3905 /* Bit 1 : Read the value of afreadys. */ 3906 #define ETB_ITATBCTR0_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */ 3907 #define ETB_ITATBCTR0_AFREADY_Msk (0x1UL << ETB_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ 3908 3909 /* Bit 0 : Read the value of atvalids. */ 3910 #define ETB_ITATBCTR0_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ 3911 #define ETB_ITATBCTR0_ATVALID_Msk (0x1UL << ETB_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ 3912 3913 /* Register: ETB_ITCTRL */ 3914 /* Description: Integration Mode Control Register */ 3915 3916 /* Bit 0 : Allows the component to switch from functional mode to integration mode or back. */ 3917 #define ETB_ITCTRL_INTEGRATION_MODE_Pos (0UL) /*!< Position of INTEGRATION_MODE field. */ 3918 #define ETB_ITCTRL_INTEGRATION_MODE_Msk (0x1UL << ETB_ITCTRL_INTEGRATION_MODE_Pos) /*!< Bit mask of INTEGRATION_MODE field. */ 3919 3920 /* Register: ETB_CLAIMSET */ 3921 /* Description: Claim Tag Set Register */ 3922 3923 /* Bits 3..0 : This claim tag bit is implemented */ 3924 #define ETB_CLAIMSET_CLAIMSET_Pos (0UL) /*!< Position of CLAIMSET field. */ 3925 #define ETB_CLAIMSET_CLAIMSET_Msk (0xFUL << ETB_CLAIMSET_CLAIMSET_Pos) /*!< Bit mask of CLAIMSET field. */ 3926 3927 /* Register: ETB_CLAIMCLR */ 3928 /* Description: Claim Tag Clear Register */ 3929 3930 /* Bits 3..0 : The value present reflects the current setting of the Claim Tag. */ 3931 #define ETB_CLAIMCLR_CLAIMCLR_Pos (0UL) /*!< Position of CLAIMCLR field. */ 3932 #define ETB_CLAIMCLR_CLAIMCLR_Msk (0xFUL << ETB_CLAIMCLR_CLAIMCLR_Pos) /*!< Bit mask of CLAIMCLR field. */ 3933 3934 /* Register: ETB_LAR */ 3935 /* Description: Lock Access Register */ 3936 3937 /* Bits 31..0 : A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the affect of removing write access. */ 3938 #define ETB_LAR_ACCESS_W_Pos (0UL) /*!< Position of ACCESS_W field. */ 3939 #define ETB_LAR_ACCESS_W_Msk (0xFFFFFFFFUL << ETB_LAR_ACCESS_W_Pos) /*!< Bit mask of ACCESS_W field. */ 3940 3941 /* Register: ETB_LSR */ 3942 /* Description: Lock Status Register */ 3943 3944 /* Bit 2 : Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit */ 3945 #define ETB_LSR_LOCKTYPE_Pos (2UL) /*!< Position of LOCKTYPE field. */ 3946 #define ETB_LSR_LOCKTYPE_Msk (0x1UL << ETB_LSR_LOCKTYPE_Pos) /*!< Bit mask of LOCKTYPE field. */ 3947 3948 /* Bit 1 : Returns the current status of the Lock. This bit reads as 0 when read from an external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers. */ 3949 #define ETB_LSR_LOCKGRANT_Pos (1UL) /*!< Position of LOCKGRANT field. */ 3950 #define ETB_LSR_LOCKGRANT_Msk (0x1UL << ETB_LSR_LOCKGRANT_Pos) /*!< Bit mask of LOCKGRANT field. */ 3951 3952 /* Bit 0 : Indicates that a lock control mechanism exists for this device. This bit reads as 0 when read from an external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers. */ 3953 #define ETB_LSR_LOCKEXIST_Pos (0UL) /*!< Position of LOCKEXIST field. */ 3954 #define ETB_LSR_LOCKEXIST_Msk (0x1UL << ETB_LSR_LOCKEXIST_Pos) /*!< Bit mask of LOCKEXIST field. */ 3955 3956 /* Register: ETB_AUTHSTATUS */ 3957 /* Description: Authentication Status Register */ 3958 3959 /* Bits 7..6 : Indicates the security level for secure non-invasive debug */ 3960 #define ETB_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ 3961 #define ETB_AUTHSTATUS_SNID_Msk (0x3UL << ETB_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ 3962 3963 /* Bits 5..4 : Indicates the security level for secure invasive debug */ 3964 #define ETB_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ 3965 #define ETB_AUTHSTATUS_SID_Msk (0x3UL << ETB_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ 3966 3967 /* Bits 3..2 : Indicates the security level for non-secure non-invasive debug */ 3968 #define ETB_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ 3969 #define ETB_AUTHSTATUS_NSNID_Msk (0x3UL << ETB_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ 3970 3971 /* Bits 1..0 : Indicates the security level for non-secure invasive debug */ 3972 #define ETB_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ 3973 #define ETB_AUTHSTATUS_NSID_Msk (0x3UL << ETB_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ 3974 3975 /* Register: ETB_DEVID */ 3976 /* Description: Device Configuration Register */ 3977 3978 /* Bit 5 : This bit returns 0 on reads indicating that the ETB RAM operates synchronously to atclk. */ 3979 #define ETB_DEVID_RAMCLK_Pos (5UL) /*!< Position of RAMCLK field. */ 3980 #define ETB_DEVID_RAMCLK_Msk (0x1UL << ETB_DEVID_RAMCLK_Pos) /*!< Bit mask of RAMCLK field. */ 3981 3982 /* Bits 4..0 : When non-zero this value indicates the type/number of ATB multiplexing present on the input to the ATB. */ 3983 #define ETB_DEVID_EXTMUXNUM_Pos (0UL) /*!< Position of EXTMUXNUM field. */ 3984 #define ETB_DEVID_EXTMUXNUM_Msk (0x1FUL << ETB_DEVID_EXTMUXNUM_Pos) /*!< Bit mask of EXTMUXNUM field. */ 3985 3986 /* Register: ETB_DEVTYPE */ 3987 /* Description: Device Type Identifier Register */ 3988 3989 /* Bits 7..4 : Sub-classification within the major category */ 3990 #define ETB_DEVTYPE_SUB_TYPE_Pos (4UL) /*!< Position of SUB_TYPE field. */ 3991 #define ETB_DEVTYPE_SUB_TYPE_Msk (0xFUL << ETB_DEVTYPE_SUB_TYPE_Pos) /*!< Bit mask of SUB_TYPE field. */ 3992 3993 /* Bits 3..0 : Major classification grouping for this debug/trace component */ 3994 #define ETB_DEVTYPE_MAJOR_TYPE_Pos (0UL) /*!< Position of MAJOR_TYPE field. */ 3995 #define ETB_DEVTYPE_MAJOR_TYPE_Msk (0xFUL << ETB_DEVTYPE_MAJOR_TYPE_Pos) /*!< Bit mask of MAJOR_TYPE field. */ 3996 3997 /* Register: ETB_PERIPHID4 */ 3998 /* Description: Peripheral ID4 Register */ 3999 4000 /* Bits 7..4 : This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. */ 4001 #define ETB_PERIPHID4_SIZE_Pos (4UL) /*!< Position of SIZE field. */ 4002 #define ETB_PERIPHID4_SIZE_Msk (0xFUL << ETB_PERIPHID4_SIZE_Pos) /*!< Bit mask of SIZE field. */ 4003 4004 /* Bits 3..0 : JEDEC continuation code indicating the designer of the component (along with the identity code) */ 4005 #define ETB_PERIPHID4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */ 4006 #define ETB_PERIPHID4_DES_2_Msk (0xFUL << ETB_PERIPHID4_DES_2_Pos) /*!< Bit mask of DES_2 field. */ 4007 4008 /* Register: ETB_PERIPHID0 */ 4009 /* Description: Peripheral ID0 Register */ 4010 4011 /* Bits 7..0 : Bits [7:0] of the component's part number. This is selected by the designer of the component. */ 4012 #define ETB_PERIPHID0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */ 4013 #define ETB_PERIPHID0_PART_0_Msk (0xFFUL << ETB_PERIPHID0_PART_0_Pos) /*!< Bit mask of PART_0 field. */ 4014 4015 /* Register: ETB_PERIPHID1 */ 4016 /* Description: Peripheral ID1 Register */ 4017 4018 /* Bits 7..4 : Bits 3:0 of the JEDEC identity code indicating the designer of the component (along with the continuation code) */ 4019 #define ETB_PERIPHID1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */ 4020 #define ETB_PERIPHID1_DES_0_Msk (0xFUL << ETB_PERIPHID1_DES_0_Pos) /*!< Bit mask of DES_0 field. */ 4021 4022 /* Bits 3..0 : Bits [11:8] of the component's part number. This is selected by the designer of the component. */ 4023 #define ETB_PERIPHID1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */ 4024 #define ETB_PERIPHID1_PART_1_Msk (0xFUL << ETB_PERIPHID1_PART_1_Pos) /*!< Bit mask of PART_1 field. */ 4025 4026 /* Register: ETB_PERIPHID2 */ 4027 /* Description: Peripheral ID2 Register */ 4028 4029 /* Bits 7..4 : The Revision field is an incremental value starting at 0x0 for the first design of this component. This only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the exact major/minor revision. */ 4030 #define ETB_PERIPHID2_REVISION_Pos (4UL) /*!< Position of REVISION field. */ 4031 #define ETB_PERIPHID2_REVISION_Msk (0xFUL << ETB_PERIPHID2_REVISION_Pos) /*!< Bit mask of REVISION field. */ 4032 4033 /* Bit 3 : Always set. Indicates that a JEDEC assigned value is used */ 4034 #define ETB_PERIPHID2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */ 4035 #define ETB_PERIPHID2_JEDEC_Msk (0x1UL << ETB_PERIPHID2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */ 4036 4037 /* Bits 2..0 : Bits 6:4 of the JEDEC identity code indicating the designer of the component (along with the continuation code) */ 4038 #define ETB_PERIPHID2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */ 4039 #define ETB_PERIPHID2_DES_1_Msk (0x7UL << ETB_PERIPHID2_DES_1_Pos) /*!< Bit mask of DES_1 field. */ 4040 4041 /* Register: ETB_PERIPHID3 */ 4042 /* Description: Peripheral ID3 Register */ 4043 4044 /* Bits 7..4 : This field indicates minor errata fixes specific to this design, for example metal fixes after implementation. In most cases this field is zero. It is recommended that component designers ensure this field can be changed by a metal fix if required, for example by driving it from registers that reset to zero. */ 4045 #define ETB_PERIPHID3_REVAND_Pos (4UL) /*!< Position of REVAND field. */ 4046 #define ETB_PERIPHID3_REVAND_Msk (0xFUL << ETB_PERIPHID3_REVAND_Pos) /*!< Bit mask of REVAND field. */ 4047 4048 /* Bits 3..0 : Where the component is reusable IP, this value indicates if the customer has modified the behavior of the component. In most cases this field is zero. */ 4049 #define ETB_PERIPHID3_CMOD_Pos (0UL) /*!< Position of CMOD field. */ 4050 #define ETB_PERIPHID3_CMOD_Msk (0xFUL << ETB_PERIPHID3_CMOD_Pos) /*!< Bit mask of CMOD field. */ 4051 4052 /* Register: ETB_COMPID0 */ 4053 /* Description: Component ID0 Register */ 4054 4055 /* Bits 7..0 : Contains bits [7:0] of the component identification */ 4056 #define ETB_COMPID0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */ 4057 #define ETB_COMPID0_PRMBL_0_Msk (0xFFUL << ETB_COMPID0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */ 4058 4059 /* Register: ETB_COMPID1 */ 4060 /* Description: Component ID1 Register */ 4061 4062 /* Bits 7..4 : Class of the component. E. g. ROM table, CoreSight component etc. Constitutes bits [15:12] of the component identification. */ 4063 #define ETB_COMPID1_CLASS_Pos (4UL) /*!< Position of CLASS field. */ 4064 #define ETB_COMPID1_CLASS_Msk (0xFUL << ETB_COMPID1_CLASS_Pos) /*!< Bit mask of CLASS field. */ 4065 4066 /* Bits 3..0 : Contains bits [11:8] of the component identification */ 4067 #define ETB_COMPID1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */ 4068 #define ETB_COMPID1_PRMBL_1_Msk (0xFUL << ETB_COMPID1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */ 4069 4070 /* Register: ETB_COMPID2 */ 4071 /* Description: Component ID2 Register */ 4072 4073 /* Bits 7..0 : Contains bits [23:16] of the component identification */ 4074 #define ETB_COMPID2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */ 4075 #define ETB_COMPID2_PRMBL_2_Msk (0xFFUL << ETB_COMPID2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */ 4076 4077 /* Register: ETB_COMPID3 */ 4078 /* Description: Component ID3 Register */ 4079 4080 /* Bits 7..0 : Contains bits [31:24] of the component identification */ 4081 #define ETB_COMPID3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */ 4082 #define ETB_COMPID3_PRMBL_3_Msk (0xFFUL << ETB_COMPID3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */ 4083 4084 4085 /* Peripheral: ETM */ 4086 /* Description: Embedded Trace Macrocell */ 4087 4088 /* Register: ETM_TRCPRGCTLR */ 4089 /* Description: Enables the trace unit. */ 4090 4091 /* Bit 0 : Trace unit enable bit */ 4092 #define ETM_TRCPRGCTLR_EN_Pos (0UL) /*!< Position of EN field. */ 4093 #define ETM_TRCPRGCTLR_EN_Msk (0x1UL << ETM_TRCPRGCTLR_EN_Pos) /*!< Bit mask of EN field. */ 4094 #define ETM_TRCPRGCTLR_EN_Disabled (0x0UL) /*!< The trace unit is disabled. All trace resources are inactive and no trace is generated. */ 4095 #define ETM_TRCPRGCTLR_EN_Enabled (0x1UL) /*!< The trace unit is enabled. */ 4096 4097 /* Register: ETM_TRCPROCSELR */ 4098 /* Description: Controls which PE to trace. Might ignore writes when the trace unit is enabled or not idle. Before writing to this register, ensure that TRCSTATR.IDLE == 1 so that the trace unit can synchronize with the chosen PE. Implemented if TRCIDR3.NUMPROC is greater than zero. */ 4099 4100 /* Bits 4..0 : PE select bits that select the PE to trace. */ 4101 #define ETM_TRCPROCSELR_PROCSEL_Pos (0UL) /*!< Position of PROCSEL field. */ 4102 #define ETM_TRCPROCSELR_PROCSEL_Msk (0x1FUL << ETM_TRCPROCSELR_PROCSEL_Pos) /*!< Bit mask of PROCSEL field. */ 4103 4104 /* Register: ETM_TRCSTATR */ 4105 /* Description: Idle status bit */ 4106 4107 /* Bit 1 : Programmers' model stable bit */ 4108 #define ETM_TRCSTATR_PMSTABLE_Pos (1UL) /*!< Position of PMSTABLE field. */ 4109 #define ETM_TRCSTATR_PMSTABLE_Msk (0x1UL << ETM_TRCSTATR_PMSTABLE_Pos) /*!< Bit mask of PMSTABLE field. */ 4110 #define ETM_TRCSTATR_PMSTABLE_NotStable (0x0UL) /*!< The programmers' model is not stable. */ 4111 #define ETM_TRCSTATR_PMSTABLE_Stable (0x1UL) /*!< The programmers' model is stable. */ 4112 4113 /* Bit 0 : Trace unit enable bit */ 4114 #define ETM_TRCSTATR_IDLE_Pos (0UL) /*!< Position of IDLE field. */ 4115 #define ETM_TRCSTATR_IDLE_Msk (0x1UL << ETM_TRCSTATR_IDLE_Pos) /*!< Bit mask of IDLE field. */ 4116 #define ETM_TRCSTATR_IDLE_NotIdle (0x0UL) /*!< The trace unit is not idle. */ 4117 #define ETM_TRCSTATR_IDLE_Idle (0x1UL) /*!< The trace unit is idle. */ 4118 4119 /* Register: ETM_TRCCONFIGR */ 4120 /* Description: Controls the tracing options This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. */ 4121 4122 /* Bit 17 : Data value tracing bit. */ 4123 #define ETM_TRCCONFIGR_DV_Pos (17UL) /*!< Position of DV field. */ 4124 #define ETM_TRCCONFIGR_DV_Msk (0x1UL << ETM_TRCCONFIGR_DV_Pos) /*!< Bit mask of DV field. */ 4125 #define ETM_TRCCONFIGR_DV_Disabled (0x0UL) /*!< Data value tracing is disabled. */ 4126 #define ETM_TRCCONFIGR_DV_Enabled (0x1UL) /*!< Data value tracing is enabled. */ 4127 4128 /* Bit 16 : Data address tracing bit. */ 4129 #define ETM_TRCCONFIGR_DA_Pos (16UL) /*!< Position of DA field. */ 4130 #define ETM_TRCCONFIGR_DA_Msk (0x1UL << ETM_TRCCONFIGR_DA_Pos) /*!< Bit mask of DA field. */ 4131 #define ETM_TRCCONFIGR_DA_Disabled (0x0UL) /*!< Data address tracing is disabled. */ 4132 #define ETM_TRCCONFIGR_DA_Enabled (0x1UL) /*!< Data address tracing is enabled. */ 4133 4134 /* Bit 15 : Control bit to select the Virtual context identifier value used by the trace unit, both for trace generation and in the Virtual context identifier comparators. */ 4135 #define ETM_TRCCONFIGR_VMIDOPT_Pos (15UL) /*!< Position of VMIDOPT field. */ 4136 #define ETM_TRCCONFIGR_VMIDOPT_Msk (0x1UL << ETM_TRCCONFIGR_VMIDOPT_Pos) /*!< Bit mask of VMIDOPT field. */ 4137 #define ETM_TRCCONFIGR_VMIDOPT_VTTBR_EL2 (0x0UL) /*!< VTTBR_EL2.VMID is used. If the trace unit supports a Virtual context 4138 identifier larger than the VTTBR_EL2.VMID, the upper unused bits are always 4139 zero. If the trace unit supports a Virtual context identifier larger than 8 bits and 4140 if the VTCR_EL2.VS bit forces use of an 8-bit Virtual context identifier, bits 4141 [15:8] of the trace unit Virtual context identifier are always zero. */ 4142 #define ETM_TRCCONFIGR_VMIDOPT_CONTEXTIDR_EL2 (0x1UL) /*!< CONTEXTIDR_EL2 is used. */ 4143 4144 /* Bits 14..13 : Q element enable field. */ 4145 #define ETM_TRCCONFIGR_QE_Pos (13UL) /*!< Position of QE field. */ 4146 #define ETM_TRCCONFIGR_QE_Msk (0x3UL << ETM_TRCCONFIGR_QE_Pos) /*!< Bit mask of QE field. */ 4147 #define ETM_TRCCONFIGR_QE_Disabled (0x0UL) /*!< Q elements are disabled. */ 4148 #define ETM_TRCCONFIGR_QE_OnlyWithoutInstCounts (0x1UL) /*!< Q elements with instruction counts are enabled. Q elements without instruction counts are disabled. */ 4149 #define ETM_TRCCONFIGR_QE_Enabled (0x3UL) /*!< Q elements with and without instruction counts are enabled. */ 4150 4151 /* Bit 12 : Return stack enable bit. */ 4152 #define ETM_TRCCONFIGR_RS_Pos (12UL) /*!< Position of RS field. */ 4153 #define ETM_TRCCONFIGR_RS_Msk (0x1UL << ETM_TRCCONFIGR_RS_Pos) /*!< Bit mask of RS field. */ 4154 #define ETM_TRCCONFIGR_RS_Disabled (0x0UL) /*!< Return stack is disabled. */ 4155 #define ETM_TRCCONFIGR_RS_Enabled (0x1UL) /*!< Return stack is enabled. */ 4156 4157 /* Bit 11 : Global timestamp tracing bit. */ 4158 #define ETM_TRCCONFIGR_TS_Pos (11UL) /*!< Position of TS field. */ 4159 #define ETM_TRCCONFIGR_TS_Msk (0x1UL << ETM_TRCCONFIGR_TS_Pos) /*!< Bit mask of TS field. */ 4160 #define ETM_TRCCONFIGR_TS_Disabled (0x0UL) /*!< Global timestamp tracing is disabled. */ 4161 #define ETM_TRCCONFIGR_TS_Enabled (0x1UL) /*!< Global timestamp tracing is enabled. */ 4162 4163 /* Bits 10..8 : Conditional instruction tracing bit. */ 4164 #define ETM_TRCCONFIGR_COND_Pos (8UL) /*!< Position of COND field. */ 4165 #define ETM_TRCCONFIGR_COND_Msk (0x7UL << ETM_TRCCONFIGR_COND_Pos) /*!< Bit mask of COND field. */ 4166 #define ETM_TRCCONFIGR_COND_Disabled (0x0UL) /*!< Conditional instruction tracing is disabled. */ 4167 #define ETM_TRCCONFIGR_COND_LoadOnly (0x1UL) /*!< Conditional load instructions are traced. */ 4168 #define ETM_TRCCONFIGR_COND_StoreOnly (0x2UL) /*!< Conditional store instructions are traced. */ 4169 #define ETM_TRCCONFIGR_COND_LoadAndStore (0x3UL) /*!< Conditional load and store instructions are traced. */ 4170 #define ETM_TRCCONFIGR_COND_All (0x7UL) /*!< All conditional instructions are traced. */ 4171 4172 /* Bit 7 : Virtual context identifier tracing bit. */ 4173 #define ETM_TRCCONFIGR_VMID_Pos (7UL) /*!< Position of VMID field. */ 4174 #define ETM_TRCCONFIGR_VMID_Msk (0x1UL << ETM_TRCCONFIGR_VMID_Pos) /*!< Bit mask of VMID field. */ 4175 #define ETM_TRCCONFIGR_VMID_Disabled (0x0UL) /*!< Virtual context identifier tracing is disabled. */ 4176 #define ETM_TRCCONFIGR_VMID_Enabled (0x1UL) /*!< Virtual context identifier tracing is enabled. */ 4177 4178 /* Bit 6 : Context ID tracing bit. */ 4179 #define ETM_TRCCONFIGR_CID_Pos (6UL) /*!< Position of CID field. */ 4180 #define ETM_TRCCONFIGR_CID_Msk (0x1UL << ETM_TRCCONFIGR_CID_Pos) /*!< Bit mask of CID field. */ 4181 #define ETM_TRCCONFIGR_CID_Disabled (0x0UL) /*!< Context ID tracing is disabled. */ 4182 #define ETM_TRCCONFIGR_CID_Enabled (0x1UL) /*!< Context ID tracing is enabled. */ 4183 4184 /* Bit 4 : Cycle counting instruction trace bit. */ 4185 #define ETM_TRCCONFIGR_CCI_Pos (4UL) /*!< Position of CCI field. */ 4186 #define ETM_TRCCONFIGR_CCI_Msk (0x1UL << ETM_TRCCONFIGR_CCI_Pos) /*!< Bit mask of CCI field. */ 4187 #define ETM_TRCCONFIGR_CCI_Disabled (0x0UL) /*!< Cycle counting in the instruction trace is disabled. */ 4188 #define ETM_TRCCONFIGR_CCI_Enabled (0x1UL) /*!< Cycle counting in the instruction trace is enabled. */ 4189 4190 /* Bit 3 : Branch broadcast mode bit. */ 4191 #define ETM_TRCCONFIGR_BB_Pos (3UL) /*!< Position of BB field. */ 4192 #define ETM_TRCCONFIGR_BB_Msk (0x1UL << ETM_TRCCONFIGR_BB_Pos) /*!< Bit mask of BB field. */ 4193 #define ETM_TRCCONFIGR_BB_Disabled (0x0UL) /*!< Branch broadcast mode is disabled. */ 4194 #define ETM_TRCCONFIGR_BB_Enabled (0x1UL) /*!< Branch broadcast mode is enabled. */ 4195 4196 /* Bit 2 : Instruction P0 field. This field controls whether store instructions are traced as P0 instructions. */ 4197 #define ETM_TRCCONFIGR_STOREASP0INST_Pos (2UL) /*!< Position of STOREASP0INST field. */ 4198 #define ETM_TRCCONFIGR_STOREASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_STOREASP0INST_Pos) /*!< Bit mask of STOREASP0INST field. */ 4199 #define ETM_TRCCONFIGR_STOREASP0INST_No (0x0UL) /*!< Do not trace store instructions as P0 instructions. */ 4200 #define ETM_TRCCONFIGR_STOREASP0INST_Yes (0x1UL) /*!< Trace store instructions as P0 instructions. */ 4201 4202 /* Bit 1 : Instruction P0 load field. This field controls whether load instructions are traced as P0 instructions. */ 4203 #define ETM_TRCCONFIGR_LOADASP0INST_Pos (1UL) /*!< Position of LOADASP0INST field. */ 4204 #define ETM_TRCCONFIGR_LOADASP0INST_Msk (0x1UL << ETM_TRCCONFIGR_LOADASP0INST_Pos) /*!< Bit mask of LOADASP0INST field. */ 4205 #define ETM_TRCCONFIGR_LOADASP0INST_No (0x0UL) /*!< Do not trace load instructions as P0 instructions. */ 4206 #define ETM_TRCCONFIGR_LOADASP0INST_Yes (0x1UL) /*!< Trace load instructions as P0 instructions. */ 4207 4208 /* Register: ETM_TRCEVENTCTL0R */ 4209 /* Description: Controls the tracing of arbitrary events. If the selected event occurs a trace element is generated in the trace stream according to the settings in TRCEVENTCTL1R.DATAEN and TRCEVENTCTL1R.INSTEN. */ 4210 4211 /* Bits 7..0 : Select which event should generate trace elements. */ 4212 #define ETM_TRCEVENTCTL0R_EVENT_Pos (0UL) /*!< Position of EVENT field. */ 4213 #define ETM_TRCEVENTCTL0R_EVENT_Msk (0xFFUL << ETM_TRCEVENTCTL0R_EVENT_Pos) /*!< Bit mask of EVENT field. */ 4214 4215 /* Register: ETM_TRCEVENTCTL1R */ 4216 /* Description: Controls the behavior of the events that TRCEVENTCTL0R selects. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. */ 4217 4218 /* Bit 12 : Low-power state behavior override bit. Controls how a trace unit behaves in low-power state. */ 4219 #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos (12UL) /*!< Position of LPOVERRIDE field. */ 4220 #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Msk (0x1UL << ETM_TRCEVENTCTL1R_LPOVERRIDE_Pos) /*!< Bit mask of LPOVERRIDE field. */ 4221 #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Disabled (0x0UL) /*!< Trace unit low-power state behavior is not affected. That is, the trace unit is enabled to enter low-power state. */ 4222 #define ETM_TRCEVENTCTL1R_LPOVERRIDE_Enabled (0x1UL) /*!< Trace unit low-power state behavior is overridden. That is, entry to a low-power state does not affect the trace unit resources or trace generation. */ 4223 4224 /* Bit 11 : AMBA Trace Bus (ATB) trigger enable bit. */ 4225 #define ETM_TRCEVENTCTL1R_ATB_Pos (11UL) /*!< Position of ATB field. */ 4226 #define ETM_TRCEVENTCTL1R_ATB_Msk (0x1UL << ETM_TRCEVENTCTL1R_ATB_Pos) /*!< Bit mask of ATB field. */ 4227 #define ETM_TRCEVENTCTL1R_ATB_Disabled (0x0UL) /*!< ATB trigger is disabled. */ 4228 #define ETM_TRCEVENTCTL1R_ATB_Enabled (0x1UL) /*!< ATB trigger is enabled. If a CoreSight ATB interface is implemented then when event 0 occurs the trace unit generates an ATB event. */ 4229 4230 /* Bit 4 : Data event enable bit. */ 4231 #define ETM_TRCEVENTCTL1R_DATAEN_Pos (4UL) /*!< Position of DATAEN field. */ 4232 #define ETM_TRCEVENTCTL1R_DATAEN_Msk (0x1UL << ETM_TRCEVENTCTL1R_DATAEN_Pos) /*!< Bit mask of DATAEN field. */ 4233 #define ETM_TRCEVENTCTL1R_DATAEN_Disabled (0x0UL) /*!< The trace unit does not generate an Event element if event 0 occurs. */ 4234 #define ETM_TRCEVENTCTL1R_DATAEN_Enabled (0x1UL) /*!< The trace unit generates an Event element in the data trace stream if event 0 occurs. */ 4235 4236 /* Bit 3 : Instruction event enable field. */ 4237 #define ETM_TRCEVENTCTL1R_INSTEN_3_Pos (3UL) /*!< Position of INSTEN_3 field. */ 4238 #define ETM_TRCEVENTCTL1R_INSTEN_3_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN_3_Pos) /*!< Bit mask of INSTEN_3 field. */ 4239 #define ETM_TRCEVENTCTL1R_INSTEN_3_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ 4240 #define ETM_TRCEVENTCTL1R_INSTEN_3_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 3, in the instruction trace stream. */ 4241 4242 /* Bit 2 : Instruction event enable field. */ 4243 #define ETM_TRCEVENTCTL1R_INSTEN_2_Pos (2UL) /*!< Position of INSTEN_2 field. */ 4244 #define ETM_TRCEVENTCTL1R_INSTEN_2_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN_2_Pos) /*!< Bit mask of INSTEN_2 field. */ 4245 #define ETM_TRCEVENTCTL1R_INSTEN_2_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ 4246 #define ETM_TRCEVENTCTL1R_INSTEN_2_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 2, in the instruction trace stream. */ 4247 4248 /* Bit 1 : Instruction event enable field. */ 4249 #define ETM_TRCEVENTCTL1R_INSTEN_1_Pos (1UL) /*!< Position of INSTEN_1 field. */ 4250 #define ETM_TRCEVENTCTL1R_INSTEN_1_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN_1_Pos) /*!< Bit mask of INSTEN_1 field. */ 4251 #define ETM_TRCEVENTCTL1R_INSTEN_1_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ 4252 #define ETM_TRCEVENTCTL1R_INSTEN_1_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 1, in the instruction trace stream. */ 4253 4254 /* Bit 0 : Instruction event enable field. */ 4255 #define ETM_TRCEVENTCTL1R_INSTEN_0_Pos (0UL) /*!< Position of INSTEN_0 field. */ 4256 #define ETM_TRCEVENTCTL1R_INSTEN_0_Msk (0x1UL << ETM_TRCEVENTCTL1R_INSTEN_0_Pos) /*!< Bit mask of INSTEN_0 field. */ 4257 #define ETM_TRCEVENTCTL1R_INSTEN_0_Disabled (0x0UL) /*!< The trace unit does not generate an Event element. */ 4258 #define ETM_TRCEVENTCTL1R_INSTEN_0_Enabled (0x1UL) /*!< The trace unit generates an Event element for event 0, in the instruction trace stream. */ 4259 4260 /* Register: ETM_TRCSTALLCTLR */ 4261 /* Description: Enables trace unit functionality that prevents trace unit buffer overflows. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCIDR3.STALLCTL == 1. */ 4262 4263 /* Bit 13 : Trace overflow prevention bit. */ 4264 #define ETM_TRCSTALLCTLR_NOOVERFLOW_Pos (13UL) /*!< Position of NOOVERFLOW field. */ 4265 #define ETM_TRCSTALLCTLR_NOOVERFLOW_Msk (0x1UL << ETM_TRCSTALLCTLR_NOOVERFLOW_Pos) /*!< Bit mask of NOOVERFLOW field. */ 4266 #define ETM_TRCSTALLCTLR_NOOVERFLOW_Disabled (0x0UL) /*!< Trace overflow prevention is disabled. */ 4267 #define ETM_TRCSTALLCTLR_NOOVERFLOW_Enabled (0x1UL) /*!< Trace overflow prevention is enabled. This might cause a significant performance impact. */ 4268 4269 /* Bit 12 : Data discard field. Controls if a trace unit can discard data trace elements on a store when the data trace buffer space is less than LEVEL. */ 4270 #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos (12UL) /*!< Position of DATADISCARDSTORE field. */ 4271 #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDSTORE_Pos) /*!< Bit mask of DATADISCARDSTORE field. */ 4272 #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements. */ 4273 #define ETM_TRCSTALLCTLR_DATADISCARDSTORE_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with data stores. */ 4274 4275 /* Bit 11 : Data discard field. Controls if a trace unit can discard data trace elements on a load when the data trace buffer space is less than LEVEL. */ 4276 #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos (11UL) /*!< Position of DATADISCARDLOAD field. */ 4277 #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Msk (0x1UL << ETM_TRCSTALLCTLR_DATADISCARDLOAD_Pos) /*!< Bit mask of DATADISCARDLOAD field. */ 4278 #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Disabled (0x0UL) /*!< The trace unit must not discard any data trace elements. */ 4279 #define ETM_TRCSTALLCTLR_DATADISCARDLOAD_Enabled (0x1UL) /*!< The trace unit can discard P1 and P2 elements associated with data loads. */ 4280 4281 /* Bit 10 : Prioritize instruction trace bit. Controls if a trace unit can prioritize instruction trace when the instruction trace buffer space is less than LEVEL. */ 4282 #define ETM_TRCSTALLCTLR_INSTPRIORITY_Pos (10UL) /*!< Position of INSTPRIORITY field. */ 4283 #define ETM_TRCSTALLCTLR_INSTPRIORITY_Msk (0x1UL << ETM_TRCSTALLCTLR_INSTPRIORITY_Pos) /*!< Bit mask of INSTPRIORITY field. */ 4284 #define ETM_TRCSTALLCTLR_INSTPRIORITY_Disabled (0x0UL) /*!< The trace unit must not prioritize instruction trace. */ 4285 #define ETM_TRCSTALLCTLR_INSTPRIORITY_Enabled (0x1UL) /*!< The trace unit can prioritize instruction trace. A trace unit might prioritize 4286 instruction trace by preventing output of data trace, or other means which ensure 4287 that the instruction trace has a higher priority than the data trace. */ 4288 4289 /* Bit 9 : Data stall bit. Controls if a trace unit can stall the PE when the data trace buffer space is less than LEVEL. */ 4290 #define ETM_TRCSTALLCTLR_DSTALL_Pos (9UL) /*!< Position of DSTALL field. */ 4291 #define ETM_TRCSTALLCTLR_DSTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_DSTALL_Pos) /*!< Bit mask of DSTALL field. */ 4292 #define ETM_TRCSTALLCTLR_DSTALL_Disabled (0x0UL) /*!< The trace unit must not stall the PE. */ 4293 #define ETM_TRCSTALLCTLR_DSTALL_Enabled (0x1UL) /*!< The trace unit can stall the PE. */ 4294 4295 /* Bit 8 : Instruction stall bit. Controls if a trace unit can stall the PE when the instruction trace buffer space is less than LEVEL. */ 4296 #define ETM_TRCSTALLCTLR_ISTALL_Pos (8UL) /*!< Position of ISTALL field. */ 4297 #define ETM_TRCSTALLCTLR_ISTALL_Msk (0x1UL << ETM_TRCSTALLCTLR_ISTALL_Pos) /*!< Bit mask of ISTALL field. */ 4298 #define ETM_TRCSTALLCTLR_ISTALL_Disabled (0x0UL) /*!< The trace unit must not stall the PE. */ 4299 #define ETM_TRCSTALLCTLR_ISTALL_Enabled (0x1UL) /*!< The trace unit can stall the PE. */ 4300 4301 /* Bits 3..0 : Threshold level field. If LEVEL is nonzero then a trace unit might suppress the generation of: Global timestamps in the instruction trace stream and the data trace stream. Cycle counting in the instruction trace stream, although the cumulative cycle count remains correct. */ 4302 #define ETM_TRCSTALLCTLR_LEVEL_Pos (0UL) /*!< Position of LEVEL field. */ 4303 #define ETM_TRCSTALLCTLR_LEVEL_Msk (0xFUL << ETM_TRCSTALLCTLR_LEVEL_Pos) /*!< Bit mask of LEVEL field. */ 4304 #define ETM_TRCSTALLCTLR_LEVEL_Min (0x0UL) /*!< Zero invasion. This setting has a greater risk of a FIFO overflow */ 4305 #define ETM_TRCSTALLCTLR_LEVEL_Max (0xFUL) /*!< Maximum invasion occurs but there is less risk of a FIFO overflow. */ 4306 4307 /* Register: ETM_TRCTSCTLR */ 4308 /* Description: Controls the insertion of global timestamps in the trace streams. When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.TS == 1. */ 4309 4310 /* Bits 7..0 : Select which event should generate time stamps. */ 4311 #define ETM_TRCTSCTLR_EVENT_Pos (0UL) /*!< Position of EVENT field. */ 4312 #define ETM_TRCTSCTLR_EVENT_Msk (0xFFUL << ETM_TRCTSCTLR_EVENT_Pos) /*!< Bit mask of EVENT field. */ 4313 4314 /* Register: ETM_TRCSYNCPR */ 4315 /* Description: Controls how often trace synchronization requests occur. Might ignore writes when the trace unit is enabled or not idle. If writes are permitted then the register must be programmed. */ 4316 4317 /* Bits 4..0 : Controls how many bytes of trace, the sum of instruction and data, that a trace unit can 4318 generate before a trace synchronization request occurs. The number of bytes is always a power of two, calculated by 2^PERIOD */ 4319 #define ETM_TRCSYNCPR_PERIOD_Pos (0UL) /*!< Position of PERIOD field. */ 4320 #define ETM_TRCSYNCPR_PERIOD_Msk (0x1FUL << ETM_TRCSYNCPR_PERIOD_Pos) /*!< Bit mask of PERIOD field. */ 4321 #define ETM_TRCSYNCPR_PERIOD_Disabled (0x00UL) /*!< Trace synchronization requests are disabled. This setting does not disable other types of trace synchronization request. */ 4322 4323 /* Register: ETM_TRCCCCTLR */ 4324 /* Description: Sets the threshold value for cycle counting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.CCI==1. */ 4325 4326 /* Bits 11..0 : Sets the threshold value for instruction trace cycle counting. */ 4327 #define ETM_TRCCCCTLR_THRESHOLD_Pos (0UL) /*!< Position of THRESHOLD field. */ 4328 #define ETM_TRCCCCTLR_THRESHOLD_Msk (0xFFFUL << ETM_TRCCCCTLR_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ 4329 4330 /* Register: ETM_TRCBBCTLR */ 4331 /* Description: Controls which regions in the memory map are enabled to use branch broadcasting. Might ignore writes when the trace unit is enabled or not idle. Must be programmed if TRCCONFIGR.BB == 1. */ 4332 4333 /* Bit 7 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. 4334 Each field represents an address range comparator pair, so field[7] controls the selection of address range comparator pair 7. */ 4335 #define ETM_TRCBBCTLR_RANGE_7_Pos (7UL) /*!< Position of RANGE_7 field. */ 4336 #define ETM_TRCBBCTLR_RANGE_7_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_7_Pos) /*!< Bit mask of RANGE_7 field. */ 4337 #define ETM_TRCBBCTLR_RANGE_7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not selected. */ 4338 #define ETM_TRCBBCTLR_RANGE_7_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */ 4339 4340 /* Bit 6 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. 4341 Each field represents an address range comparator pair, so field[6] controls the selection of address range comparator pair 6. */ 4342 #define ETM_TRCBBCTLR_RANGE_6_Pos (6UL) /*!< Position of RANGE_6 field. */ 4343 #define ETM_TRCBBCTLR_RANGE_6_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_6_Pos) /*!< Bit mask of RANGE_6 field. */ 4344 #define ETM_TRCBBCTLR_RANGE_6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not selected. */ 4345 #define ETM_TRCBBCTLR_RANGE_6_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */ 4346 4347 /* Bit 5 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. 4348 Each field represents an address range comparator pair, so field[5] controls the selection of address range comparator pair 5. */ 4349 #define ETM_TRCBBCTLR_RANGE_5_Pos (5UL) /*!< Position of RANGE_5 field. */ 4350 #define ETM_TRCBBCTLR_RANGE_5_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_5_Pos) /*!< Bit mask of RANGE_5 field. */ 4351 #define ETM_TRCBBCTLR_RANGE_5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not selected. */ 4352 #define ETM_TRCBBCTLR_RANGE_5_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */ 4353 4354 /* Bit 4 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. 4355 Each field represents an address range comparator pair, so field[4] controls the selection of address range comparator pair 4. */ 4356 #define ETM_TRCBBCTLR_RANGE_4_Pos (4UL) /*!< Position of RANGE_4 field. */ 4357 #define ETM_TRCBBCTLR_RANGE_4_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_4_Pos) /*!< Bit mask of RANGE_4 field. */ 4358 #define ETM_TRCBBCTLR_RANGE_4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not selected. */ 4359 #define ETM_TRCBBCTLR_RANGE_4_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */ 4360 4361 /* Bit 3 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. 4362 Each field represents an address range comparator pair, so field[3] controls the selection of address range comparator pair 3. */ 4363 #define ETM_TRCBBCTLR_RANGE_3_Pos (3UL) /*!< Position of RANGE_3 field. */ 4364 #define ETM_TRCBBCTLR_RANGE_3_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_3_Pos) /*!< Bit mask of RANGE_3 field. */ 4365 #define ETM_TRCBBCTLR_RANGE_3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not selected. */ 4366 #define ETM_TRCBBCTLR_RANGE_3_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */ 4367 4368 /* Bit 2 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. 4369 Each field represents an address range comparator pair, so field[2] controls the selection of address range comparator pair 2. */ 4370 #define ETM_TRCBBCTLR_RANGE_2_Pos (2UL) /*!< Position of RANGE_2 field. */ 4371 #define ETM_TRCBBCTLR_RANGE_2_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_2_Pos) /*!< Bit mask of RANGE_2 field. */ 4372 #define ETM_TRCBBCTLR_RANGE_2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not selected. */ 4373 #define ETM_TRCBBCTLR_RANGE_2_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */ 4374 4375 /* Bit 1 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. 4376 Each field represents an address range comparator pair, so field[1] controls the selection of address range comparator pair 1. */ 4377 #define ETM_TRCBBCTLR_RANGE_1_Pos (1UL) /*!< Position of RANGE_1 field. */ 4378 #define ETM_TRCBBCTLR_RANGE_1_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_1_Pos) /*!< Bit mask of RANGE_1 field. */ 4379 #define ETM_TRCBBCTLR_RANGE_1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not selected. */ 4380 #define ETM_TRCBBCTLR_RANGE_1_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */ 4381 4382 /* Bit 0 : Address range field. Selects which address range comparator pairs are in use with branch broadcasting. 4383 Each field represents an address range comparator pair, so field[0] controls the selection of address range comparator pair 0. */ 4384 #define ETM_TRCBBCTLR_RANGE_0_Pos (0UL) /*!< Position of RANGE_0 field. */ 4385 #define ETM_TRCBBCTLR_RANGE_0_Msk (0x1UL << ETM_TRCBBCTLR_RANGE_0_Pos) /*!< Bit mask of RANGE_0 field. */ 4386 #define ETM_TRCBBCTLR_RANGE_0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not selected. */ 4387 #define ETM_TRCBBCTLR_RANGE_0_Enabled (0x1UL) /*!< The address range that address range comparator pair n defines, is selected. */ 4388 4389 /* Register: ETM_TRCTRACEIDR */ 4390 /* Description: Sets the trace ID for instruction trace. If data trace is enabled then it also sets the trace ID for data trace, to (trace ID for instruction trace) + 1. This register must always be programmed as part of trace unit initialization. Might ignore writes when the trace unit is enabled or not idle. */ 4391 4392 /* Bits 6..0 : Trace ID field. Sets the trace ID value for instruction trace. Bit[0] must be zero if data trace is enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1. */ 4393 #define ETM_TRCTRACEIDR_TRACEID_Pos (0UL) /*!< Position of TRACEID field. */ 4394 #define ETM_TRCTRACEIDR_TRACEID_Msk (0x7FUL << ETM_TRCTRACEIDR_TRACEID_Pos) /*!< Bit mask of TRACEID field. */ 4395 4396 /* Register: ETM_TRCQCTLR */ 4397 /* Description: Controls when Q elements are enabled. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed if it is implemented and TRCCONFIGR.QE is set to any value other than 0b00. */ 4398 4399 /* Bit 8 : Selects whether the address range comparators selected by the RANGE field indicate 4400 address ranges where the trace unit is permitted to generate Q elements or address ranges 4401 where the trace unit is not permitted to generate Q elements: */ 4402 #define ETM_TRCQCTLR_MODE_Pos (8UL) /*!< Position of MODE field. */ 4403 #define ETM_TRCQCTLR_MODE_Msk (0x1UL << ETM_TRCQCTLR_MODE_Pos) /*!< Bit mask of MODE field. */ 4404 #define ETM_TRCQCTLR_MODE_Exclude (0x0UL) /*!< Exclude mode. The address range comparators selected by the RANGE field 4405 indicate address ranges where the trace unit cannot generate Q elements. If no 4406 ranges are selected, Q elements are permitted across the entire memory map. */ 4407 #define ETM_TRCQCTLR_MODE_Include (0x1UL) /*!< Include mode. The address range comparators selected by the RANGE field 4408 indicate address ranges where the trace unit can generate Q elements. If all the 4409 implemented bits in RANGE are set to 0 then Q elements are disabled. */ 4410 4411 /* Bit 7 : Specifies the address range comparators to be used for controlling Q elements. */ 4412 #define ETM_TRCQCTLR_RANGE_7_Pos (7UL) /*!< Position of RANGE_7 field. */ 4413 #define ETM_TRCQCTLR_RANGE_7_Msk (0x1UL << ETM_TRCQCTLR_RANGE_7_Pos) /*!< Bit mask of RANGE_7 field. */ 4414 #define ETM_TRCQCTLR_RANGE_7_Disabled (0x0UL) /*!< Address range comparator 7 is disabled. */ 4415 #define ETM_TRCQCTLR_RANGE_7_Enabled (0x1UL) /*!< Address range comparator 7 is selected for use. */ 4416 4417 /* Bit 6 : Specifies the address range comparators to be used for controlling Q elements. */ 4418 #define ETM_TRCQCTLR_RANGE_6_Pos (6UL) /*!< Position of RANGE_6 field. */ 4419 #define ETM_TRCQCTLR_RANGE_6_Msk (0x1UL << ETM_TRCQCTLR_RANGE_6_Pos) /*!< Bit mask of RANGE_6 field. */ 4420 #define ETM_TRCQCTLR_RANGE_6_Disabled (0x0UL) /*!< Address range comparator 6 is disabled. */ 4421 #define ETM_TRCQCTLR_RANGE_6_Enabled (0x1UL) /*!< Address range comparator 6 is selected for use. */ 4422 4423 /* Bit 5 : Specifies the address range comparators to be used for controlling Q elements. */ 4424 #define ETM_TRCQCTLR_RANGE_5_Pos (5UL) /*!< Position of RANGE_5 field. */ 4425 #define ETM_TRCQCTLR_RANGE_5_Msk (0x1UL << ETM_TRCQCTLR_RANGE_5_Pos) /*!< Bit mask of RANGE_5 field. */ 4426 #define ETM_TRCQCTLR_RANGE_5_Disabled (0x0UL) /*!< Address range comparator 5 is disabled. */ 4427 #define ETM_TRCQCTLR_RANGE_5_Enabled (0x1UL) /*!< Address range comparator 5 is selected for use. */ 4428 4429 /* Bit 4 : Specifies the address range comparators to be used for controlling Q elements. */ 4430 #define ETM_TRCQCTLR_RANGE_4_Pos (4UL) /*!< Position of RANGE_4 field. */ 4431 #define ETM_TRCQCTLR_RANGE_4_Msk (0x1UL << ETM_TRCQCTLR_RANGE_4_Pos) /*!< Bit mask of RANGE_4 field. */ 4432 #define ETM_TRCQCTLR_RANGE_4_Disabled (0x0UL) /*!< Address range comparator 4 is disabled. */ 4433 #define ETM_TRCQCTLR_RANGE_4_Enabled (0x1UL) /*!< Address range comparator 4 is selected for use. */ 4434 4435 /* Bit 3 : Specifies the address range comparators to be used for controlling Q elements. */ 4436 #define ETM_TRCQCTLR_RANGE_3_Pos (3UL) /*!< Position of RANGE_3 field. */ 4437 #define ETM_TRCQCTLR_RANGE_3_Msk (0x1UL << ETM_TRCQCTLR_RANGE_3_Pos) /*!< Bit mask of RANGE_3 field. */ 4438 #define ETM_TRCQCTLR_RANGE_3_Disabled (0x0UL) /*!< Address range comparator 3 is disabled. */ 4439 #define ETM_TRCQCTLR_RANGE_3_Enabled (0x1UL) /*!< Address range comparator 3 is selected for use. */ 4440 4441 /* Bit 2 : Specifies the address range comparators to be used for controlling Q elements. */ 4442 #define ETM_TRCQCTLR_RANGE_2_Pos (2UL) /*!< Position of RANGE_2 field. */ 4443 #define ETM_TRCQCTLR_RANGE_2_Msk (0x1UL << ETM_TRCQCTLR_RANGE_2_Pos) /*!< Bit mask of RANGE_2 field. */ 4444 #define ETM_TRCQCTLR_RANGE_2_Disabled (0x0UL) /*!< Address range comparator 2 is disabled. */ 4445 #define ETM_TRCQCTLR_RANGE_2_Enabled (0x1UL) /*!< Address range comparator 2 is selected for use. */ 4446 4447 /* Bit 1 : Specifies the address range comparators to be used for controlling Q elements. */ 4448 #define ETM_TRCQCTLR_RANGE_1_Pos (1UL) /*!< Position of RANGE_1 field. */ 4449 #define ETM_TRCQCTLR_RANGE_1_Msk (0x1UL << ETM_TRCQCTLR_RANGE_1_Pos) /*!< Bit mask of RANGE_1 field. */ 4450 #define ETM_TRCQCTLR_RANGE_1_Disabled (0x0UL) /*!< Address range comparator 1 is disabled. */ 4451 #define ETM_TRCQCTLR_RANGE_1_Enabled (0x1UL) /*!< Address range comparator 1 is selected for use. */ 4452 4453 /* Bit 0 : Specifies the address range comparators to be used for controlling Q elements. */ 4454 #define ETM_TRCQCTLR_RANGE_0_Pos (0UL) /*!< Position of RANGE_0 field. */ 4455 #define ETM_TRCQCTLR_RANGE_0_Msk (0x1UL << ETM_TRCQCTLR_RANGE_0_Pos) /*!< Bit mask of RANGE_0 field. */ 4456 #define ETM_TRCQCTLR_RANGE_0_Disabled (0x0UL) /*!< Address range comparator 0 is disabled. */ 4457 #define ETM_TRCQCTLR_RANGE_0_Enabled (0x1UL) /*!< Address range comparator 0 is selected for use. */ 4458 4459 /* Register: ETM_TRCVICTLR */ 4460 /* Description: Controls instruction trace filtering. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. Must be programmed, particularly to set the value of the SSSTATUS bit, which sets the state of the start/stop logic. */ 4461 4462 /* Bit 23 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 3. */ 4463 #define ETM_TRCVICTLR_EXLEVEL3_NS_Pos (23UL) /*!< Position of EXLEVEL3_NS field. */ 4464 #define ETM_TRCVICTLR_EXLEVEL3_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_NS_Pos) /*!< Bit mask of EXLEVEL3_NS field. */ 4465 #define ETM_TRCVICTLR_EXLEVEL3_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for Exception level 3. */ 4466 #define ETM_TRCVICTLR_EXLEVEL3_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure state, for Exception level 3. */ 4467 4468 /* Bit 22 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 2. */ 4469 #define ETM_TRCVICTLR_EXLEVEL2_NS_Pos (22UL) /*!< Position of EXLEVEL2_NS field. */ 4470 #define ETM_TRCVICTLR_EXLEVEL2_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_NS_Pos) /*!< Bit mask of EXLEVEL2_NS field. */ 4471 #define ETM_TRCVICTLR_EXLEVEL2_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for Exception level 2. */ 4472 #define ETM_TRCVICTLR_EXLEVEL2_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure state, for Exception level 2. */ 4473 4474 /* Bit 21 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 1. */ 4475 #define ETM_TRCVICTLR_EXLEVEL1_NS_Pos (21UL) /*!< Position of EXLEVEL1_NS field. */ 4476 #define ETM_TRCVICTLR_EXLEVEL1_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_NS_Pos) /*!< Bit mask of EXLEVEL1_NS field. */ 4477 #define ETM_TRCVICTLR_EXLEVEL1_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for Exception level 1. */ 4478 #define ETM_TRCVICTLR_EXLEVEL1_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure state, for Exception level 1. */ 4479 4480 /* Bit 20 : In Non-secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 0. */ 4481 #define ETM_TRCVICTLR_EXLEVEL0_NS_Pos (20UL) /*!< Position of EXLEVEL0_NS field. */ 4482 #define ETM_TRCVICTLR_EXLEVEL0_NS_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_NS_Pos) /*!< Bit mask of EXLEVEL0_NS field. */ 4483 #define ETM_TRCVICTLR_EXLEVEL0_NS_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Non-secure state, for Exception level 0. */ 4484 #define ETM_TRCVICTLR_EXLEVEL0_NS_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Non-secure state, for Exception level 0. */ 4485 4486 /* Bit 19 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 3. */ 4487 #define ETM_TRCVICTLR_EXLEVEL3_S_Pos (19UL) /*!< Position of EXLEVEL3_S field. */ 4488 #define ETM_TRCVICTLR_EXLEVEL3_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL3_S_Pos) /*!< Bit mask of EXLEVEL3_S field. */ 4489 #define ETM_TRCVICTLR_EXLEVEL3_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for Exception level 3. */ 4490 #define ETM_TRCVICTLR_EXLEVEL3_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, for Exception level 3. */ 4491 4492 /* Bit 18 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 2. */ 4493 #define ETM_TRCVICTLR_EXLEVEL2_S_Pos (18UL) /*!< Position of EXLEVEL2_S field. */ 4494 #define ETM_TRCVICTLR_EXLEVEL2_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL2_S_Pos) /*!< Bit mask of EXLEVEL2_S field. */ 4495 #define ETM_TRCVICTLR_EXLEVEL2_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for Exception level 2. */ 4496 #define ETM_TRCVICTLR_EXLEVEL2_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, for Exception level 2. */ 4497 4498 /* Bit 17 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 1. */ 4499 #define ETM_TRCVICTLR_EXLEVEL1_S_Pos (17UL) /*!< Position of EXLEVEL1_S field. */ 4500 #define ETM_TRCVICTLR_EXLEVEL1_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL1_S_Pos) /*!< Bit mask of EXLEVEL1_S field. */ 4501 #define ETM_TRCVICTLR_EXLEVEL1_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for Exception level 1. */ 4502 #define ETM_TRCVICTLR_EXLEVEL1_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, for Exception level 1. */ 4503 4504 /* Bit 16 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding Exception level 0. */ 4505 #define ETM_TRCVICTLR_EXLEVEL0_S_Pos (16UL) /*!< Position of EXLEVEL0_S field. */ 4506 #define ETM_TRCVICTLR_EXLEVEL0_S_Msk (0x1UL << ETM_TRCVICTLR_EXLEVEL0_S_Pos) /*!< Bit mask of EXLEVEL0_S field. */ 4507 #define ETM_TRCVICTLR_EXLEVEL0_S_Enabled (0x0UL) /*!< The trace unit generates instruction trace, in Secure state, for Exception level 0. */ 4508 #define ETM_TRCVICTLR_EXLEVEL0_S_Disabled (0x1UL) /*!< The trace unit does not generate instruction trace, in Secure state, for Exception level 0. */ 4509 4510 /* Bit 11 : When TRCIDR3.TRCERR==1, this bit controls whether a trace unit must trace a System error exception. */ 4511 #define ETM_TRCVICTLR_TRCERR_Pos (11UL) /*!< Position of TRCERR field. */ 4512 #define ETM_TRCVICTLR_TRCERR_Msk (0x1UL << ETM_TRCVICTLR_TRCERR_Pos) /*!< Bit mask of TRCERR field. */ 4513 #define ETM_TRCVICTLR_TRCERR_Disabled (0x0UL) /*!< The trace unit does not trace a System error exception unless it traces the exception or instruction immediately prior to the System error exception. */ 4514 #define ETM_TRCVICTLR_TRCERR_Enabled (0x1UL) /*!< The trace unit always traces a System error exception, regardless of the value of ViewInst. */ 4515 4516 /* Bit 10 : Controls whether a trace unit must trace a Reset exception. */ 4517 #define ETM_TRCVICTLR_TRCRESET_Pos (10UL) /*!< Position of TRCRESET field. */ 4518 #define ETM_TRCVICTLR_TRCRESET_Msk (0x1UL << ETM_TRCVICTLR_TRCRESET_Pos) /*!< Bit mask of TRCRESET field. */ 4519 #define ETM_TRCVICTLR_TRCRESET_Disabled (0x0UL) /*!< The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception. */ 4520 #define ETM_TRCVICTLR_TRCRESET_Enabled (0x1UL) /*!< The trace unit always traces a Reset exception. */ 4521 4522 /* Bit 9 : When TRCIDR4.NUMACPAIRS > 0 or TRCIDR4.NUMPC > 0, this bit returns the status of the start/stop logic. */ 4523 #define ETM_TRCVICTLR_SSSTATUS_Pos (9UL) /*!< Position of SSSTATUS field. */ 4524 #define ETM_TRCVICTLR_SSSTATUS_Msk (0x1UL << ETM_TRCVICTLR_SSSTATUS_Pos) /*!< Bit mask of SSSTATUS field. */ 4525 #define ETM_TRCVICTLR_SSSTATUS_Stopped (0x0UL) /*!< The start/stop logic is in the stopped state. */ 4526 #define ETM_TRCVICTLR_SSSTATUS_Started (0x1UL) /*!< The start/stop logic is in the started state. */ 4527 4528 /* Bits 4..0 : Select which resource number should be filtered. */ 4529 #define ETM_TRCVICTLR_EVENT_SEL_Pos (0UL) /*!< Position of EVENT_SEL field. */ 4530 #define ETM_TRCVICTLR_EVENT_SEL_Msk (0x1FUL << ETM_TRCVICTLR_EVENT_SEL_Pos) /*!< Bit mask of EVENT_SEL field. */ 4531 #define ETM_TRCVICTLR_EVENT_SEL_Disabled (0x00UL) /*!< This event is not filtered. */ 4532 #define ETM_TRCVICTLR_EVENT_SEL_Enabled (0x01UL) /*!< This event is filtered. */ 4533 4534 /* Register: ETM_TRCVIIECTLR */ 4535 /* Description: ViewInst exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. */ 4536 4537 /* Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */ 4538 #define ETM_TRCVIIECTLR_EXCLUDE_7_Pos (23UL) /*!< Position of EXCLUDE_7 field. */ 4539 #define ETM_TRCVIIECTLR_EXCLUDE_7_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_7_Pos) /*!< Bit mask of EXCLUDE_7 field. */ 4540 #define ETM_TRCVIIECTLR_EXCLUDE_7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not selected for ViewInst exclude control. */ 4541 #define ETM_TRCVIIECTLR_EXCLUDE_7_Enabled (0x1UL) /*!< The address range that address range comparator pair 7 defines, is selected for ViewInst exclude control. */ 4542 4543 /* Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */ 4544 #define ETM_TRCVIIECTLR_EXCLUDE_6_Pos (22UL) /*!< Position of EXCLUDE_6 field. */ 4545 #define ETM_TRCVIIECTLR_EXCLUDE_6_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_6_Pos) /*!< Bit mask of EXCLUDE_6 field. */ 4546 #define ETM_TRCVIIECTLR_EXCLUDE_6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not selected for ViewInst exclude control. */ 4547 #define ETM_TRCVIIECTLR_EXCLUDE_6_Enabled (0x1UL) /*!< The address range that address range comparator pair 6 defines, is selected for ViewInst exclude control. */ 4548 4549 /* Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */ 4550 #define ETM_TRCVIIECTLR_EXCLUDE_5_Pos (21UL) /*!< Position of EXCLUDE_5 field. */ 4551 #define ETM_TRCVIIECTLR_EXCLUDE_5_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_5_Pos) /*!< Bit mask of EXCLUDE_5 field. */ 4552 #define ETM_TRCVIIECTLR_EXCLUDE_5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not selected for ViewInst exclude control. */ 4553 #define ETM_TRCVIIECTLR_EXCLUDE_5_Enabled (0x1UL) /*!< The address range that address range comparator pair 5 defines, is selected for ViewInst exclude control. */ 4554 4555 /* Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */ 4556 #define ETM_TRCVIIECTLR_EXCLUDE_4_Pos (20UL) /*!< Position of EXCLUDE_4 field. */ 4557 #define ETM_TRCVIIECTLR_EXCLUDE_4_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_4_Pos) /*!< Bit mask of EXCLUDE_4 field. */ 4558 #define ETM_TRCVIIECTLR_EXCLUDE_4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not selected for ViewInst exclude control. */ 4559 #define ETM_TRCVIIECTLR_EXCLUDE_4_Enabled (0x1UL) /*!< The address range that address range comparator pair 4 defines, is selected for ViewInst exclude control. */ 4560 4561 /* Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */ 4562 #define ETM_TRCVIIECTLR_EXCLUDE_3_Pos (19UL) /*!< Position of EXCLUDE_3 field. */ 4563 #define ETM_TRCVIIECTLR_EXCLUDE_3_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_3_Pos) /*!< Bit mask of EXCLUDE_3 field. */ 4564 #define ETM_TRCVIIECTLR_EXCLUDE_3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not selected for ViewInst exclude control. */ 4565 #define ETM_TRCVIIECTLR_EXCLUDE_3_Enabled (0x1UL) /*!< The address range that address range comparator pair 3 defines, is selected for ViewInst exclude control. */ 4566 4567 /* Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */ 4568 #define ETM_TRCVIIECTLR_EXCLUDE_2_Pos (18UL) /*!< Position of EXCLUDE_2 field. */ 4569 #define ETM_TRCVIIECTLR_EXCLUDE_2_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_2_Pos) /*!< Bit mask of EXCLUDE_2 field. */ 4570 #define ETM_TRCVIIECTLR_EXCLUDE_2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not selected for ViewInst exclude control. */ 4571 #define ETM_TRCVIIECTLR_EXCLUDE_2_Enabled (0x1UL) /*!< The address range that address range comparator pair 2 defines, is selected for ViewInst exclude control. */ 4572 4573 /* Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */ 4574 #define ETM_TRCVIIECTLR_EXCLUDE_1_Pos (17UL) /*!< Position of EXCLUDE_1 field. */ 4575 #define ETM_TRCVIIECTLR_EXCLUDE_1_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_1_Pos) /*!< Bit mask of EXCLUDE_1 field. */ 4576 #define ETM_TRCVIIECTLR_EXCLUDE_1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not selected for ViewInst exclude control. */ 4577 #define ETM_TRCVIIECTLR_EXCLUDE_1_Enabled (0x1UL) /*!< The address range that address range comparator pair 1 defines, is selected for ViewInst exclude control. */ 4578 4579 /* Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewInst exclude control. */ 4580 #define ETM_TRCVIIECTLR_EXCLUDE_0_Pos (16UL) /*!< Position of EXCLUDE_0 field. */ 4581 #define ETM_TRCVIIECTLR_EXCLUDE_0_Msk (0x1UL << ETM_TRCVIIECTLR_EXCLUDE_0_Pos) /*!< Bit mask of EXCLUDE_0 field. */ 4582 #define ETM_TRCVIIECTLR_EXCLUDE_0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not selected for ViewInst exclude control. */ 4583 #define ETM_TRCVIIECTLR_EXCLUDE_0_Enabled (0x1UL) /*!< The address range that address range comparator pair 0 defines, is selected for ViewInst exclude control. */ 4584 4585 /* Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */ 4586 #define ETM_TRCVIIECTLR_INCLUDE_7_Pos (7UL) /*!< Position of INCLUDE_7 field. */ 4587 #define ETM_TRCVIIECTLR_INCLUDE_7_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_7_Pos) /*!< Bit mask of INCLUDE_7 field. */ 4588 #define ETM_TRCVIIECTLR_INCLUDE_7_Disabled (0x0UL) /*!< The address range that address range comparator pair 7 defines, is not selected for ViewInst include control. */ 4589 #define ETM_TRCVIIECTLR_INCLUDE_7_Enabled (0x1UL) /*!< The address range that address range comparator pair 7 defines, is selected for ViewInst include control. */ 4590 4591 /* Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */ 4592 #define ETM_TRCVIIECTLR_INCLUDE_6_Pos (6UL) /*!< Position of INCLUDE_6 field. */ 4593 #define ETM_TRCVIIECTLR_INCLUDE_6_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_6_Pos) /*!< Bit mask of INCLUDE_6 field. */ 4594 #define ETM_TRCVIIECTLR_INCLUDE_6_Disabled (0x0UL) /*!< The address range that address range comparator pair 6 defines, is not selected for ViewInst include control. */ 4595 #define ETM_TRCVIIECTLR_INCLUDE_6_Enabled (0x1UL) /*!< The address range that address range comparator pair 6 defines, is selected for ViewInst include control. */ 4596 4597 /* Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */ 4598 #define ETM_TRCVIIECTLR_INCLUDE_5_Pos (5UL) /*!< Position of INCLUDE_5 field. */ 4599 #define ETM_TRCVIIECTLR_INCLUDE_5_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_5_Pos) /*!< Bit mask of INCLUDE_5 field. */ 4600 #define ETM_TRCVIIECTLR_INCLUDE_5_Disabled (0x0UL) /*!< The address range that address range comparator pair 5 defines, is not selected for ViewInst include control. */ 4601 #define ETM_TRCVIIECTLR_INCLUDE_5_Enabled (0x1UL) /*!< The address range that address range comparator pair 5 defines, is selected for ViewInst include control. */ 4602 4603 /* Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */ 4604 #define ETM_TRCVIIECTLR_INCLUDE_4_Pos (4UL) /*!< Position of INCLUDE_4 field. */ 4605 #define ETM_TRCVIIECTLR_INCLUDE_4_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_4_Pos) /*!< Bit mask of INCLUDE_4 field. */ 4606 #define ETM_TRCVIIECTLR_INCLUDE_4_Disabled (0x0UL) /*!< The address range that address range comparator pair 4 defines, is not selected for ViewInst include control. */ 4607 #define ETM_TRCVIIECTLR_INCLUDE_4_Enabled (0x1UL) /*!< The address range that address range comparator pair 4 defines, is selected for ViewInst include control. */ 4608 4609 /* Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */ 4610 #define ETM_TRCVIIECTLR_INCLUDE_3_Pos (3UL) /*!< Position of INCLUDE_3 field. */ 4611 #define ETM_TRCVIIECTLR_INCLUDE_3_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_3_Pos) /*!< Bit mask of INCLUDE_3 field. */ 4612 #define ETM_TRCVIIECTLR_INCLUDE_3_Disabled (0x0UL) /*!< The address range that address range comparator pair 3 defines, is not selected for ViewInst include control. */ 4613 #define ETM_TRCVIIECTLR_INCLUDE_3_Enabled (0x1UL) /*!< The address range that address range comparator pair 3 defines, is selected for ViewInst include control. */ 4614 4615 /* Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */ 4616 #define ETM_TRCVIIECTLR_INCLUDE_2_Pos (2UL) /*!< Position of INCLUDE_2 field. */ 4617 #define ETM_TRCVIIECTLR_INCLUDE_2_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_2_Pos) /*!< Bit mask of INCLUDE_2 field. */ 4618 #define ETM_TRCVIIECTLR_INCLUDE_2_Disabled (0x0UL) /*!< The address range that address range comparator pair 2 defines, is not selected for ViewInst include control. */ 4619 #define ETM_TRCVIIECTLR_INCLUDE_2_Enabled (0x1UL) /*!< The address range that address range comparator pair 2 defines, is selected for ViewInst include control. */ 4620 4621 /* Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */ 4622 #define ETM_TRCVIIECTLR_INCLUDE_1_Pos (1UL) /*!< Position of INCLUDE_1 field. */ 4623 #define ETM_TRCVIIECTLR_INCLUDE_1_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_1_Pos) /*!< Bit mask of INCLUDE_1 field. */ 4624 #define ETM_TRCVIIECTLR_INCLUDE_1_Disabled (0x0UL) /*!< The address range that address range comparator pair 1 defines, is not selected for ViewInst include control. */ 4625 #define ETM_TRCVIIECTLR_INCLUDE_1_Enabled (0x1UL) /*!< The address range that address range comparator pair 1 defines, is selected for ViewInst include control. */ 4626 4627 /* Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewInst include control. */ 4628 #define ETM_TRCVIIECTLR_INCLUDE_0_Pos (0UL) /*!< Position of INCLUDE_0 field. */ 4629 #define ETM_TRCVIIECTLR_INCLUDE_0_Msk (0x1UL << ETM_TRCVIIECTLR_INCLUDE_0_Pos) /*!< Bit mask of INCLUDE_0 field. */ 4630 #define ETM_TRCVIIECTLR_INCLUDE_0_Disabled (0x0UL) /*!< The address range that address range comparator pair 0 defines, is not selected for ViewInst include control. */ 4631 #define ETM_TRCVIIECTLR_INCLUDE_0_Enabled (0x1UL) /*!< The address range that address range comparator pair 0 defines, is selected for ViewInst include control. */ 4632 4633 /* Register: ETM_TRCVISSCTLR */ 4634 /* Description: Use this to set, or read, the single address comparators that control the ViewInst start/stop 4635 logic. The start/stop logic is active for an instruction which causes a start and remains active 4636 up to and including an instruction which causes a stop, and then the start/stop logic becomes 4637 inactive. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed. */ 4638 4639 /* Bit 23 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */ 4640 #define ETM_TRCVISSCTLR_STOP_7_Pos (23UL) /*!< Position of STOP_7 field. */ 4641 #define ETM_TRCVISSCTLR_STOP_7_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_7_Pos) /*!< Bit mask of STOP_7 field. */ 4642 #define ETM_TRCVISSCTLR_STOP_7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected as a stop resource. */ 4643 #define ETM_TRCVISSCTLR_STOP_7_Enabled (0x1UL) /*!< The single address comparator 7, is selected as a stop resource. */ 4644 4645 /* Bit 22 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */ 4646 #define ETM_TRCVISSCTLR_STOP_6_Pos (22UL) /*!< Position of STOP_6 field. */ 4647 #define ETM_TRCVISSCTLR_STOP_6_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_6_Pos) /*!< Bit mask of STOP_6 field. */ 4648 #define ETM_TRCVISSCTLR_STOP_6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected as a stop resource. */ 4649 #define ETM_TRCVISSCTLR_STOP_6_Enabled (0x1UL) /*!< The single address comparator 6, is selected as a stop resource. */ 4650 4651 /* Bit 21 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */ 4652 #define ETM_TRCVISSCTLR_STOP_5_Pos (21UL) /*!< Position of STOP_5 field. */ 4653 #define ETM_TRCVISSCTLR_STOP_5_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_5_Pos) /*!< Bit mask of STOP_5 field. */ 4654 #define ETM_TRCVISSCTLR_STOP_5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected as a stop resource. */ 4655 #define ETM_TRCVISSCTLR_STOP_5_Enabled (0x1UL) /*!< The single address comparator 5, is selected as a stop resource. */ 4656 4657 /* Bit 20 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */ 4658 #define ETM_TRCVISSCTLR_STOP_4_Pos (20UL) /*!< Position of STOP_4 field. */ 4659 #define ETM_TRCVISSCTLR_STOP_4_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_4_Pos) /*!< Bit mask of STOP_4 field. */ 4660 #define ETM_TRCVISSCTLR_STOP_4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected as a stop resource. */ 4661 #define ETM_TRCVISSCTLR_STOP_4_Enabled (0x1UL) /*!< The single address comparator 4, is selected as a stop resource. */ 4662 4663 /* Bit 19 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */ 4664 #define ETM_TRCVISSCTLR_STOP_3_Pos (19UL) /*!< Position of STOP_3 field. */ 4665 #define ETM_TRCVISSCTLR_STOP_3_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_3_Pos) /*!< Bit mask of STOP_3 field. */ 4666 #define ETM_TRCVISSCTLR_STOP_3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected as a stop resource. */ 4667 #define ETM_TRCVISSCTLR_STOP_3_Enabled (0x1UL) /*!< The single address comparator 3, is selected as a stop resource. */ 4668 4669 /* Bit 18 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */ 4670 #define ETM_TRCVISSCTLR_STOP_2_Pos (18UL) /*!< Position of STOP_2 field. */ 4671 #define ETM_TRCVISSCTLR_STOP_2_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_2_Pos) /*!< Bit mask of STOP_2 field. */ 4672 #define ETM_TRCVISSCTLR_STOP_2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected as a stop resource. */ 4673 #define ETM_TRCVISSCTLR_STOP_2_Enabled (0x1UL) /*!< The single address comparator 2, is selected as a stop resource. */ 4674 4675 /* Bit 17 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */ 4676 #define ETM_TRCVISSCTLR_STOP_1_Pos (17UL) /*!< Position of STOP_1 field. */ 4677 #define ETM_TRCVISSCTLR_STOP_1_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_1_Pos) /*!< Bit mask of STOP_1 field. */ 4678 #define ETM_TRCVISSCTLR_STOP_1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected as a stop resource. */ 4679 #define ETM_TRCVISSCTLR_STOP_1_Enabled (0x1UL) /*!< The single address comparator 1, is selected as a stop resource. */ 4680 4681 /* Bit 16 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of stopping trace */ 4682 #define ETM_TRCVISSCTLR_STOP_0_Pos (16UL) /*!< Position of STOP_0 field. */ 4683 #define ETM_TRCVISSCTLR_STOP_0_Msk (0x1UL << ETM_TRCVISSCTLR_STOP_0_Pos) /*!< Bit mask of STOP_0 field. */ 4684 #define ETM_TRCVISSCTLR_STOP_0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected as a stop resource. */ 4685 #define ETM_TRCVISSCTLR_STOP_0_Enabled (0x1UL) /*!< The single address comparator 0, is selected as a stop resource. */ 4686 4687 /* Bit 7 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */ 4688 #define ETM_TRCVISSCTLR_START_7_Pos (7UL) /*!< Position of START_7 field. */ 4689 #define ETM_TRCVISSCTLR_START_7_Msk (0x1UL << ETM_TRCVISSCTLR_START_7_Pos) /*!< Bit mask of START_7 field. */ 4690 #define ETM_TRCVISSCTLR_START_7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected as a start resource. */ 4691 #define ETM_TRCVISSCTLR_START_7_Enabled (0x1UL) /*!< The single address comparator 7, is selected as a start resource. */ 4692 4693 /* Bit 6 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */ 4694 #define ETM_TRCVISSCTLR_START_6_Pos (6UL) /*!< Position of START_6 field. */ 4695 #define ETM_TRCVISSCTLR_START_6_Msk (0x1UL << ETM_TRCVISSCTLR_START_6_Pos) /*!< Bit mask of START_6 field. */ 4696 #define ETM_TRCVISSCTLR_START_6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected as a start resource. */ 4697 #define ETM_TRCVISSCTLR_START_6_Enabled (0x1UL) /*!< The single address comparator 6, is selected as a start resource. */ 4698 4699 /* Bit 5 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */ 4700 #define ETM_TRCVISSCTLR_START_5_Pos (5UL) /*!< Position of START_5 field. */ 4701 #define ETM_TRCVISSCTLR_START_5_Msk (0x1UL << ETM_TRCVISSCTLR_START_5_Pos) /*!< Bit mask of START_5 field. */ 4702 #define ETM_TRCVISSCTLR_START_5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected as a start resource. */ 4703 #define ETM_TRCVISSCTLR_START_5_Enabled (0x1UL) /*!< The single address comparator 5, is selected as a start resource. */ 4704 4705 /* Bit 4 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */ 4706 #define ETM_TRCVISSCTLR_START_4_Pos (4UL) /*!< Position of START_4 field. */ 4707 #define ETM_TRCVISSCTLR_START_4_Msk (0x1UL << ETM_TRCVISSCTLR_START_4_Pos) /*!< Bit mask of START_4 field. */ 4708 #define ETM_TRCVISSCTLR_START_4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected as a start resource. */ 4709 #define ETM_TRCVISSCTLR_START_4_Enabled (0x1UL) /*!< The single address comparator 4, is selected as a start resource. */ 4710 4711 /* Bit 3 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */ 4712 #define ETM_TRCVISSCTLR_START_3_Pos (3UL) /*!< Position of START_3 field. */ 4713 #define ETM_TRCVISSCTLR_START_3_Msk (0x1UL << ETM_TRCVISSCTLR_START_3_Pos) /*!< Bit mask of START_3 field. */ 4714 #define ETM_TRCVISSCTLR_START_3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected as a start resource. */ 4715 #define ETM_TRCVISSCTLR_START_3_Enabled (0x1UL) /*!< The single address comparator 3, is selected as a start resource. */ 4716 4717 /* Bit 2 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */ 4718 #define ETM_TRCVISSCTLR_START_2_Pos (2UL) /*!< Position of START_2 field. */ 4719 #define ETM_TRCVISSCTLR_START_2_Msk (0x1UL << ETM_TRCVISSCTLR_START_2_Pos) /*!< Bit mask of START_2 field. */ 4720 #define ETM_TRCVISSCTLR_START_2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected as a start resource. */ 4721 #define ETM_TRCVISSCTLR_START_2_Enabled (0x1UL) /*!< The single address comparator 2, is selected as a start resource. */ 4722 4723 /* Bit 1 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */ 4724 #define ETM_TRCVISSCTLR_START_1_Pos (1UL) /*!< Position of START_1 field. */ 4725 #define ETM_TRCVISSCTLR_START_1_Msk (0x1UL << ETM_TRCVISSCTLR_START_1_Pos) /*!< Bit mask of START_1 field. */ 4726 #define ETM_TRCVISSCTLR_START_1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected as a start resource. */ 4727 #define ETM_TRCVISSCTLR_START_1_Enabled (0x1UL) /*!< The single address comparator 1, is selected as a start resource. */ 4728 4729 /* Bit 0 : Selects which single address comparators are in use with ViewInst start/stop control, for the purpose of starting trace. */ 4730 #define ETM_TRCVISSCTLR_START_0_Pos (0UL) /*!< Position of START_0 field. */ 4731 #define ETM_TRCVISSCTLR_START_0_Msk (0x1UL << ETM_TRCVISSCTLR_START_0_Pos) /*!< Bit mask of START_0 field. */ 4732 #define ETM_TRCVISSCTLR_START_0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected as a start resource. */ 4733 #define ETM_TRCVISSCTLR_START_0_Enabled (0x1UL) /*!< The single address comparator 0, is selected as a start resource. */ 4734 4735 /* Register: ETM_TRCVIPCSSCTLR */ 4736 /* Description: Use this to set, or read, which PE comparator inputs can control the ViewInst start/stop logic. Might ignore writes when the trace unit is enabled or not idle. If implemented then this register must be programmed. */ 4737 4738 /* Bit 23 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */ 4739 #define ETM_TRCVIPCSSCTLR_STOP_7_Pos (23UL) /*!< Position of STOP_7 field. */ 4740 #define ETM_TRCVIPCSSCTLR_STOP_7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_7_Pos) /*!< Bit mask of STOP_7 field. */ 4741 #define ETM_TRCVIPCSSCTLR_STOP_7_Disabled (0x0UL) /*!< The single PE comparator input 7, is not selected as a stop resource. */ 4742 #define ETM_TRCVIPCSSCTLR_STOP_7_Enabled (0x1UL) /*!< The single PE comparator input 7, is selected as a stop resource. */ 4743 4744 /* Bit 22 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */ 4745 #define ETM_TRCVIPCSSCTLR_STOP_6_Pos (22UL) /*!< Position of STOP_6 field. */ 4746 #define ETM_TRCVIPCSSCTLR_STOP_6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_6_Pos) /*!< Bit mask of STOP_6 field. */ 4747 #define ETM_TRCVIPCSSCTLR_STOP_6_Disabled (0x0UL) /*!< The single PE comparator input 6, is not selected as a stop resource. */ 4748 #define ETM_TRCVIPCSSCTLR_STOP_6_Enabled (0x1UL) /*!< The single PE comparator input 6, is selected as a stop resource. */ 4749 4750 /* Bit 21 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */ 4751 #define ETM_TRCVIPCSSCTLR_STOP_5_Pos (21UL) /*!< Position of STOP_5 field. */ 4752 #define ETM_TRCVIPCSSCTLR_STOP_5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_5_Pos) /*!< Bit mask of STOP_5 field. */ 4753 #define ETM_TRCVIPCSSCTLR_STOP_5_Disabled (0x0UL) /*!< The single PE comparator input 5, is not selected as a stop resource. */ 4754 #define ETM_TRCVIPCSSCTLR_STOP_5_Enabled (0x1UL) /*!< The single PE comparator input 5, is selected as a stop resource. */ 4755 4756 /* Bit 20 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */ 4757 #define ETM_TRCVIPCSSCTLR_STOP_4_Pos (20UL) /*!< Position of STOP_4 field. */ 4758 #define ETM_TRCVIPCSSCTLR_STOP_4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_4_Pos) /*!< Bit mask of STOP_4 field. */ 4759 #define ETM_TRCVIPCSSCTLR_STOP_4_Disabled (0x0UL) /*!< The single PE comparator input 4, is not selected as a stop resource. */ 4760 #define ETM_TRCVIPCSSCTLR_STOP_4_Enabled (0x1UL) /*!< The single PE comparator input 4, is selected as a stop resource. */ 4761 4762 /* Bit 19 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */ 4763 #define ETM_TRCVIPCSSCTLR_STOP_3_Pos (19UL) /*!< Position of STOP_3 field. */ 4764 #define ETM_TRCVIPCSSCTLR_STOP_3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_3_Pos) /*!< Bit mask of STOP_3 field. */ 4765 #define ETM_TRCVIPCSSCTLR_STOP_3_Disabled (0x0UL) /*!< The single PE comparator input 3, is not selected as a stop resource. */ 4766 #define ETM_TRCVIPCSSCTLR_STOP_3_Enabled (0x1UL) /*!< The single PE comparator input 3, is selected as a stop resource. */ 4767 4768 /* Bit 18 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */ 4769 #define ETM_TRCVIPCSSCTLR_STOP_2_Pos (18UL) /*!< Position of STOP_2 field. */ 4770 #define ETM_TRCVIPCSSCTLR_STOP_2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_2_Pos) /*!< Bit mask of STOP_2 field. */ 4771 #define ETM_TRCVIPCSSCTLR_STOP_2_Disabled (0x0UL) /*!< The single PE comparator input 2, is not selected as a stop resource. */ 4772 #define ETM_TRCVIPCSSCTLR_STOP_2_Enabled (0x1UL) /*!< The single PE comparator input 2, is selected as a stop resource. */ 4773 4774 /* Bit 17 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */ 4775 #define ETM_TRCVIPCSSCTLR_STOP_1_Pos (17UL) /*!< Position of STOP_1 field. */ 4776 #define ETM_TRCVIPCSSCTLR_STOP_1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_1_Pos) /*!< Bit mask of STOP_1 field. */ 4777 #define ETM_TRCVIPCSSCTLR_STOP_1_Disabled (0x0UL) /*!< The single PE comparator input 1, is not selected as a stop resource. */ 4778 #define ETM_TRCVIPCSSCTLR_STOP_1_Enabled (0x1UL) /*!< The single PE comparator input 1, is selected as a stop resource. */ 4779 4780 /* Bit 16 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of stopping trace. */ 4781 #define ETM_TRCVIPCSSCTLR_STOP_0_Pos (16UL) /*!< Position of STOP_0 field. */ 4782 #define ETM_TRCVIPCSSCTLR_STOP_0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_STOP_0_Pos) /*!< Bit mask of STOP_0 field. */ 4783 #define ETM_TRCVIPCSSCTLR_STOP_0_Disabled (0x0UL) /*!< The single PE comparator input 0, is not selected as a stop resource. */ 4784 #define ETM_TRCVIPCSSCTLR_STOP_0_Enabled (0x1UL) /*!< The single PE comparator input 0, is selected as a stop resource. */ 4785 4786 /* Bit 7 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */ 4787 #define ETM_TRCVIPCSSCTLR_START_7_Pos (7UL) /*!< Position of START_7 field. */ 4788 #define ETM_TRCVIPCSSCTLR_START_7_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_7_Pos) /*!< Bit mask of START_7 field. */ 4789 #define ETM_TRCVIPCSSCTLR_START_7_Disabled (0x0UL) /*!< The single PE comparator input 7, is not selected as a start resource. */ 4790 #define ETM_TRCVIPCSSCTLR_START_7_Enabled (0x1UL) /*!< The single PE comparator input 7, is selected as a start resource. */ 4791 4792 /* Bit 6 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */ 4793 #define ETM_TRCVIPCSSCTLR_START_6_Pos (6UL) /*!< Position of START_6 field. */ 4794 #define ETM_TRCVIPCSSCTLR_START_6_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_6_Pos) /*!< Bit mask of START_6 field. */ 4795 #define ETM_TRCVIPCSSCTLR_START_6_Disabled (0x0UL) /*!< The single PE comparator input 6, is not selected as a start resource. */ 4796 #define ETM_TRCVIPCSSCTLR_START_6_Enabled (0x1UL) /*!< The single PE comparator input 6, is selected as a start resource. */ 4797 4798 /* Bit 5 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */ 4799 #define ETM_TRCVIPCSSCTLR_START_5_Pos (5UL) /*!< Position of START_5 field. */ 4800 #define ETM_TRCVIPCSSCTLR_START_5_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_5_Pos) /*!< Bit mask of START_5 field. */ 4801 #define ETM_TRCVIPCSSCTLR_START_5_Disabled (0x0UL) /*!< The single PE comparator input 5, is not selected as a start resource. */ 4802 #define ETM_TRCVIPCSSCTLR_START_5_Enabled (0x1UL) /*!< The single PE comparator input 5, is selected as a start resource. */ 4803 4804 /* Bit 4 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */ 4805 #define ETM_TRCVIPCSSCTLR_START_4_Pos (4UL) /*!< Position of START_4 field. */ 4806 #define ETM_TRCVIPCSSCTLR_START_4_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_4_Pos) /*!< Bit mask of START_4 field. */ 4807 #define ETM_TRCVIPCSSCTLR_START_4_Disabled (0x0UL) /*!< The single PE comparator input 4, is not selected as a start resource. */ 4808 #define ETM_TRCVIPCSSCTLR_START_4_Enabled (0x1UL) /*!< The single PE comparator input 4, is selected as a start resource. */ 4809 4810 /* Bit 3 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */ 4811 #define ETM_TRCVIPCSSCTLR_START_3_Pos (3UL) /*!< Position of START_3 field. */ 4812 #define ETM_TRCVIPCSSCTLR_START_3_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_3_Pos) /*!< Bit mask of START_3 field. */ 4813 #define ETM_TRCVIPCSSCTLR_START_3_Disabled (0x0UL) /*!< The single PE comparator input 3, is not selected as a start resource. */ 4814 #define ETM_TRCVIPCSSCTLR_START_3_Enabled (0x1UL) /*!< The single PE comparator input 3, is selected as a start resource. */ 4815 4816 /* Bit 2 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */ 4817 #define ETM_TRCVIPCSSCTLR_START_2_Pos (2UL) /*!< Position of START_2 field. */ 4818 #define ETM_TRCVIPCSSCTLR_START_2_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_2_Pos) /*!< Bit mask of START_2 field. */ 4819 #define ETM_TRCVIPCSSCTLR_START_2_Disabled (0x0UL) /*!< The single PE comparator input 2, is not selected as a start resource. */ 4820 #define ETM_TRCVIPCSSCTLR_START_2_Enabled (0x1UL) /*!< The single PE comparator input 2, is selected as a start resource. */ 4821 4822 /* Bit 1 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */ 4823 #define ETM_TRCVIPCSSCTLR_START_1_Pos (1UL) /*!< Position of START_1 field. */ 4824 #define ETM_TRCVIPCSSCTLR_START_1_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_1_Pos) /*!< Bit mask of START_1 field. */ 4825 #define ETM_TRCVIPCSSCTLR_START_1_Disabled (0x0UL) /*!< The single PE comparator input 1, is not selected as a start resource. */ 4826 #define ETM_TRCVIPCSSCTLR_START_1_Enabled (0x1UL) /*!< The single PE comparator input 1, is selected as a start resource. */ 4827 4828 /* Bit 0 : Selects which PE comparator inputs are in use with ViewInst start/stop control, for the purpose of starting trace */ 4829 #define ETM_TRCVIPCSSCTLR_START_0_Pos (0UL) /*!< Position of START_0 field. */ 4830 #define ETM_TRCVIPCSSCTLR_START_0_Msk (0x1UL << ETM_TRCVIPCSSCTLR_START_0_Pos) /*!< Bit mask of START_0 field. */ 4831 #define ETM_TRCVIPCSSCTLR_START_0_Disabled (0x0UL) /*!< The single PE comparator input 0, is not selected as a start resource. */ 4832 #define ETM_TRCVIPCSSCTLR_START_0_Enabled (0x1UL) /*!< The single PE comparator input 0, is selected as a start resource. */ 4833 4834 /* Register: ETM_TRCVDCTLR */ 4835 /* Description: Controls data trace filtering. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when data tracing is enabled, that is, when either TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == 1. */ 4836 4837 /* Bit 12 : Controls the tracing of data transfers for exceptions and exception returns on Armv6-M, Armv7-M, and Armv8-M PEs. */ 4838 #define ETM_TRCVDCTLR_TRCEXDATA_Pos (12UL) /*!< Position of TRCEXDATA field. */ 4839 #define ETM_TRCVDCTLR_TRCEXDATA_Msk (0x1UL << ETM_TRCVDCTLR_TRCEXDATA_Pos) /*!< Bit mask of TRCEXDATA field. */ 4840 #define ETM_TRCVDCTLR_TRCEXDATA_Disabled (0x0UL) /*!< Exception and exception return data transfers are not traced. */ 4841 #define ETM_TRCVDCTLR_TRCEXDATA_Enabled (0x1UL) /*!< Exception and exception return data transfers are traced if the other aspects of ViewData indicate that the data transfers must be traced. */ 4842 4843 /* Bit 11 : Controls which information a trace unit populates in bits[63:56] of the data address. */ 4844 #define ETM_TRCVDCTLR_TBI_Pos (11UL) /*!< Position of TBI field. */ 4845 #define ETM_TRCVDCTLR_TBI_Msk (0x1UL << ETM_TRCVDCTLR_TBI_Pos) /*!< Bit mask of TBI field. */ 4846 #define ETM_TRCVDCTLR_TBI_SignExtend (0x0UL) /*!< The trace unit assigns bits[63:56] to have the same value as bit[55] of the data address, that is, it sign-extends the value. */ 4847 #define ETM_TRCVDCTLR_TBI_Copy (0x1UL) /*!< The trace unit assigns bits[63:56] to have the same value as bits[63:56] of the data address. */ 4848 4849 /* Bit 10 : Controls whether a trace unit traces data for transfers that are relative to the Program Counter (PC). */ 4850 #define ETM_TRCVDCTLR_PCREL_Pos (10UL) /*!< Position of PCREL field. */ 4851 #define ETM_TRCVDCTLR_PCREL_Msk (0x1UL << ETM_TRCVDCTLR_PCREL_Pos) /*!< Bit mask of PCREL field. */ 4852 #define ETM_TRCVDCTLR_PCREL_Enabled (0x0UL) /*!< The trace unit does not affect the tracing of PC-relative transfers. */ 4853 #define ETM_TRCVDCTLR_PCREL_Disabled (0x1UL) /*!< The trace unit does not trace the address or value portions of PC-relative transfers. */ 4854 4855 /* Bits 9..8 : Controls whether a trace unit traces data for transfers that are relative to the Stack Pointer (SP). */ 4856 #define ETM_TRCVDCTLR_SPREL_Pos (8UL) /*!< Position of SPREL field. */ 4857 #define ETM_TRCVDCTLR_SPREL_Msk (0x3UL << ETM_TRCVDCTLR_SPREL_Pos) /*!< Bit mask of SPREL field. */ 4858 #define ETM_TRCVDCTLR_SPREL_Enabled (0x0UL) /*!< The trace unit does not affect the tracing of SP-relative transfers. */ 4859 #define ETM_TRCVDCTLR_SPREL_DataOnly (0x2UL) /*!< The trace unit does not trace the address portion of SP-relative transfers. If data value tracing is enabled then the trace unit generates a P1 data address element. */ 4860 #define ETM_TRCVDCTLR_SPREL_Disabled (0x3UL) /*!< The trace unit does not trace the address or value portions of SP-relative transfers. */ 4861 4862 /* Bit 7 : Event unit enable bit. */ 4863 #define ETM_TRCVDCTLR_EVENT_7_Pos (7UL) /*!< Position of EVENT_7 field. */ 4864 #define ETM_TRCVDCTLR_EVENT_7_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_7_Pos) /*!< Bit mask of EVENT_7 field. */ 4865 #define ETM_TRCVDCTLR_EVENT_7_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ 4866 #define ETM_TRCVDCTLR_EVENT_7_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ 4867 4868 /* Bit 6 : Event unit enable bit. */ 4869 #define ETM_TRCVDCTLR_EVENT_6_Pos (6UL) /*!< Position of EVENT_6 field. */ 4870 #define ETM_TRCVDCTLR_EVENT_6_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_6_Pos) /*!< Bit mask of EVENT_6 field. */ 4871 #define ETM_TRCVDCTLR_EVENT_6_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ 4872 #define ETM_TRCVDCTLR_EVENT_6_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ 4873 4874 /* Bit 5 : Event unit enable bit. */ 4875 #define ETM_TRCVDCTLR_EVENT_5_Pos (5UL) /*!< Position of EVENT_5 field. */ 4876 #define ETM_TRCVDCTLR_EVENT_5_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_5_Pos) /*!< Bit mask of EVENT_5 field. */ 4877 #define ETM_TRCVDCTLR_EVENT_5_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ 4878 #define ETM_TRCVDCTLR_EVENT_5_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ 4879 4880 /* Bit 4 : Event unit enable bit. */ 4881 #define ETM_TRCVDCTLR_EVENT_4_Pos (4UL) /*!< Position of EVENT_4 field. */ 4882 #define ETM_TRCVDCTLR_EVENT_4_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_4_Pos) /*!< Bit mask of EVENT_4 field. */ 4883 #define ETM_TRCVDCTLR_EVENT_4_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ 4884 #define ETM_TRCVDCTLR_EVENT_4_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ 4885 4886 /* Bit 3 : Event unit enable bit. */ 4887 #define ETM_TRCVDCTLR_EVENT_3_Pos (3UL) /*!< Position of EVENT_3 field. */ 4888 #define ETM_TRCVDCTLR_EVENT_3_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_3_Pos) /*!< Bit mask of EVENT_3 field. */ 4889 #define ETM_TRCVDCTLR_EVENT_3_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ 4890 #define ETM_TRCVDCTLR_EVENT_3_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ 4891 4892 /* Bit 2 : Event unit enable bit. */ 4893 #define ETM_TRCVDCTLR_EVENT_2_Pos (2UL) /*!< Position of EVENT_2 field. */ 4894 #define ETM_TRCVDCTLR_EVENT_2_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_2_Pos) /*!< Bit mask of EVENT_2 field. */ 4895 #define ETM_TRCVDCTLR_EVENT_2_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ 4896 #define ETM_TRCVDCTLR_EVENT_2_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ 4897 4898 /* Bit 1 : Event unit enable bit. */ 4899 #define ETM_TRCVDCTLR_EVENT_1_Pos (1UL) /*!< Position of EVENT_1 field. */ 4900 #define ETM_TRCVDCTLR_EVENT_1_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_1_Pos) /*!< Bit mask of EVENT_1 field. */ 4901 #define ETM_TRCVDCTLR_EVENT_1_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ 4902 #define ETM_TRCVDCTLR_EVENT_1_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ 4903 4904 /* Bit 0 : Event unit enable bit. */ 4905 #define ETM_TRCVDCTLR_EVENT_0_Pos (0UL) /*!< Position of EVENT_0 field. */ 4906 #define ETM_TRCVDCTLR_EVENT_0_Msk (0x1UL << ETM_TRCVDCTLR_EVENT_0_Pos) /*!< Bit mask of EVENT_0 field. */ 4907 #define ETM_TRCVDCTLR_EVENT_0_Disabled (0x0UL) /*!< The trace event is not selected for trace filtering. */ 4908 #define ETM_TRCVDCTLR_EVENT_0_Enabled (0x1UL) /*!< The trace event is selected for trace filtering. */ 4909 4910 /* Register: ETM_TRCVDSACCTLR */ 4911 /* Description: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. */ 4912 4913 /* Bit 23 : Selects which single address comparators are in use with ViewData exclude control. */ 4914 #define ETM_TRCVDSACCTLR_EXCLUDE_7_Pos (23UL) /*!< Position of EXCLUDE_7 field. */ 4915 #define ETM_TRCVDSACCTLR_EXCLUDE_7_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_7_Pos) /*!< Bit mask of EXCLUDE_7 field. */ 4916 #define ETM_TRCVDSACCTLR_EXCLUDE_7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData exclude control. */ 4917 #define ETM_TRCVDSACCTLR_EXCLUDE_7_Enabled (0x1UL) /*!< The single address comparator 7, s selected for ViewData exclude control. */ 4918 4919 /* Bit 22 : Selects which single address comparators are in use with ViewData exclude control. */ 4920 #define ETM_TRCVDSACCTLR_EXCLUDE_6_Pos (22UL) /*!< Position of EXCLUDE_6 field. */ 4921 #define ETM_TRCVDSACCTLR_EXCLUDE_6_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_6_Pos) /*!< Bit mask of EXCLUDE_6 field. */ 4922 #define ETM_TRCVDSACCTLR_EXCLUDE_6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData exclude control. */ 4923 #define ETM_TRCVDSACCTLR_EXCLUDE_6_Enabled (0x1UL) /*!< The single address comparator 6, s selected for ViewData exclude control. */ 4924 4925 /* Bit 21 : Selects which single address comparators are in use with ViewData exclude control. */ 4926 #define ETM_TRCVDSACCTLR_EXCLUDE_5_Pos (21UL) /*!< Position of EXCLUDE_5 field. */ 4927 #define ETM_TRCVDSACCTLR_EXCLUDE_5_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_5_Pos) /*!< Bit mask of EXCLUDE_5 field. */ 4928 #define ETM_TRCVDSACCTLR_EXCLUDE_5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData exclude control. */ 4929 #define ETM_TRCVDSACCTLR_EXCLUDE_5_Enabled (0x1UL) /*!< The single address comparator 5, s selected for ViewData exclude control. */ 4930 4931 /* Bit 20 : Selects which single address comparators are in use with ViewData exclude control. */ 4932 #define ETM_TRCVDSACCTLR_EXCLUDE_4_Pos (20UL) /*!< Position of EXCLUDE_4 field. */ 4933 #define ETM_TRCVDSACCTLR_EXCLUDE_4_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_4_Pos) /*!< Bit mask of EXCLUDE_4 field. */ 4934 #define ETM_TRCVDSACCTLR_EXCLUDE_4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData exclude control. */ 4935 #define ETM_TRCVDSACCTLR_EXCLUDE_4_Enabled (0x1UL) /*!< The single address comparator 4, s selected for ViewData exclude control. */ 4936 4937 /* Bit 19 : Selects which single address comparators are in use with ViewData exclude control. */ 4938 #define ETM_TRCVDSACCTLR_EXCLUDE_3_Pos (19UL) /*!< Position of EXCLUDE_3 field. */ 4939 #define ETM_TRCVDSACCTLR_EXCLUDE_3_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_3_Pos) /*!< Bit mask of EXCLUDE_3 field. */ 4940 #define ETM_TRCVDSACCTLR_EXCLUDE_3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData exclude control. */ 4941 #define ETM_TRCVDSACCTLR_EXCLUDE_3_Enabled (0x1UL) /*!< The single address comparator 3, s selected for ViewData exclude control. */ 4942 4943 /* Bit 18 : Selects which single address comparators are in use with ViewData exclude control. */ 4944 #define ETM_TRCVDSACCTLR_EXCLUDE_2_Pos (18UL) /*!< Position of EXCLUDE_2 field. */ 4945 #define ETM_TRCVDSACCTLR_EXCLUDE_2_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_2_Pos) /*!< Bit mask of EXCLUDE_2 field. */ 4946 #define ETM_TRCVDSACCTLR_EXCLUDE_2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData exclude control. */ 4947 #define ETM_TRCVDSACCTLR_EXCLUDE_2_Enabled (0x1UL) /*!< The single address comparator 2, s selected for ViewData exclude control. */ 4948 4949 /* Bit 17 : Selects which single address comparators are in use with ViewData exclude control. */ 4950 #define ETM_TRCVDSACCTLR_EXCLUDE_1_Pos (17UL) /*!< Position of EXCLUDE_1 field. */ 4951 #define ETM_TRCVDSACCTLR_EXCLUDE_1_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_1_Pos) /*!< Bit mask of EXCLUDE_1 field. */ 4952 #define ETM_TRCVDSACCTLR_EXCLUDE_1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData exclude control. */ 4953 #define ETM_TRCVDSACCTLR_EXCLUDE_1_Enabled (0x1UL) /*!< The single address comparator 1, s selected for ViewData exclude control. */ 4954 4955 /* Bit 16 : Selects which single address comparators are in use with ViewData exclude control. */ 4956 #define ETM_TRCVDSACCTLR_EXCLUDE_0_Pos (16UL) /*!< Position of EXCLUDE_0 field. */ 4957 #define ETM_TRCVDSACCTLR_EXCLUDE_0_Msk (0x1UL << ETM_TRCVDSACCTLR_EXCLUDE_0_Pos) /*!< Bit mask of EXCLUDE_0 field. */ 4958 #define ETM_TRCVDSACCTLR_EXCLUDE_0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData exclude control. */ 4959 #define ETM_TRCVDSACCTLR_EXCLUDE_0_Enabled (0x1UL) /*!< The single address comparator 0, s selected for ViewData exclude control. */ 4960 4961 /* Bit 7 : Selects which single address comparators are in use with ViewData include control. */ 4962 #define ETM_TRCVDSACCTLR_INCLUDE_7_Pos (7UL) /*!< Position of INCLUDE_7 field. */ 4963 #define ETM_TRCVDSACCTLR_INCLUDE_7_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_7_Pos) /*!< Bit mask of INCLUDE_7 field. */ 4964 #define ETM_TRCVDSACCTLR_INCLUDE_7_Disabled (0x0UL) /*!< The single address comparator 7, is not selected for ViewData include control. */ 4965 #define ETM_TRCVDSACCTLR_INCLUDE_7_Enabled (0x1UL) /*!< The single address comparator 7, is selected for ViewData include control. */ 4966 4967 /* Bit 6 : Selects which single address comparators are in use with ViewData include control. */ 4968 #define ETM_TRCVDSACCTLR_INCLUDE_6_Pos (6UL) /*!< Position of INCLUDE_6 field. */ 4969 #define ETM_TRCVDSACCTLR_INCLUDE_6_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_6_Pos) /*!< Bit mask of INCLUDE_6 field. */ 4970 #define ETM_TRCVDSACCTLR_INCLUDE_6_Disabled (0x0UL) /*!< The single address comparator 6, is not selected for ViewData include control. */ 4971 #define ETM_TRCVDSACCTLR_INCLUDE_6_Enabled (0x1UL) /*!< The single address comparator 6, is selected for ViewData include control. */ 4972 4973 /* Bit 5 : Selects which single address comparators are in use with ViewData include control. */ 4974 #define ETM_TRCVDSACCTLR_INCLUDE_5_Pos (5UL) /*!< Position of INCLUDE_5 field. */ 4975 #define ETM_TRCVDSACCTLR_INCLUDE_5_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_5_Pos) /*!< Bit mask of INCLUDE_5 field. */ 4976 #define ETM_TRCVDSACCTLR_INCLUDE_5_Disabled (0x0UL) /*!< The single address comparator 5, is not selected for ViewData include control. */ 4977 #define ETM_TRCVDSACCTLR_INCLUDE_5_Enabled (0x1UL) /*!< The single address comparator 5, is selected for ViewData include control. */ 4978 4979 /* Bit 4 : Selects which single address comparators are in use with ViewData include control. */ 4980 #define ETM_TRCVDSACCTLR_INCLUDE_4_Pos (4UL) /*!< Position of INCLUDE_4 field. */ 4981 #define ETM_TRCVDSACCTLR_INCLUDE_4_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_4_Pos) /*!< Bit mask of INCLUDE_4 field. */ 4982 #define ETM_TRCVDSACCTLR_INCLUDE_4_Disabled (0x0UL) /*!< The single address comparator 4, is not selected for ViewData include control. */ 4983 #define ETM_TRCVDSACCTLR_INCLUDE_4_Enabled (0x1UL) /*!< The single address comparator 4, is selected for ViewData include control. */ 4984 4985 /* Bit 3 : Selects which single address comparators are in use with ViewData include control. */ 4986 #define ETM_TRCVDSACCTLR_INCLUDE_3_Pos (3UL) /*!< Position of INCLUDE_3 field. */ 4987 #define ETM_TRCVDSACCTLR_INCLUDE_3_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_3_Pos) /*!< Bit mask of INCLUDE_3 field. */ 4988 #define ETM_TRCVDSACCTLR_INCLUDE_3_Disabled (0x0UL) /*!< The single address comparator 3, is not selected for ViewData include control. */ 4989 #define ETM_TRCVDSACCTLR_INCLUDE_3_Enabled (0x1UL) /*!< The single address comparator 3, is selected for ViewData include control. */ 4990 4991 /* Bit 2 : Selects which single address comparators are in use with ViewData include control. */ 4992 #define ETM_TRCVDSACCTLR_INCLUDE_2_Pos (2UL) /*!< Position of INCLUDE_2 field. */ 4993 #define ETM_TRCVDSACCTLR_INCLUDE_2_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_2_Pos) /*!< Bit mask of INCLUDE_2 field. */ 4994 #define ETM_TRCVDSACCTLR_INCLUDE_2_Disabled (0x0UL) /*!< The single address comparator 2, is not selected for ViewData include control. */ 4995 #define ETM_TRCVDSACCTLR_INCLUDE_2_Enabled (0x1UL) /*!< The single address comparator 2, is selected for ViewData include control. */ 4996 4997 /* Bit 1 : Selects which single address comparators are in use with ViewData include control. */ 4998 #define ETM_TRCVDSACCTLR_INCLUDE_1_Pos (1UL) /*!< Position of INCLUDE_1 field. */ 4999 #define ETM_TRCVDSACCTLR_INCLUDE_1_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_1_Pos) /*!< Bit mask of INCLUDE_1 field. */ 5000 #define ETM_TRCVDSACCTLR_INCLUDE_1_Disabled (0x0UL) /*!< The single address comparator 1, is not selected for ViewData include control. */ 5001 #define ETM_TRCVDSACCTLR_INCLUDE_1_Enabled (0x1UL) /*!< The single address comparator 1, is selected for ViewData include control. */ 5002 5003 /* Bit 0 : Selects which single address comparators are in use with ViewData include control. */ 5004 #define ETM_TRCVDSACCTLR_INCLUDE_0_Pos (0UL) /*!< Position of INCLUDE_0 field. */ 5005 #define ETM_TRCVDSACCTLR_INCLUDE_0_Msk (0x1UL << ETM_TRCVDSACCTLR_INCLUDE_0_Pos) /*!< Bit mask of INCLUDE_0 field. */ 5006 #define ETM_TRCVDSACCTLR_INCLUDE_0_Disabled (0x0UL) /*!< The single address comparator 0, is not selected for ViewData include control. */ 5007 #define ETM_TRCVDSACCTLR_INCLUDE_0_Enabled (0x1UL) /*!< The single address comparator 0, is selected for ViewData include control. */ 5008 5009 /* Register: ETM_TRCVDARCCTLR */ 5010 /* Description: ViewData include / exclude control. Might ignore writes when the trace unit is enabled or not idle. This register must be programmed when one or more address comparators are implemented. */ 5011 5012 /* Bit 23 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */ 5013 #define ETM_TRCVDARCCTLR_EXCLUDE_7_Pos (23UL) /*!< Position of EXCLUDE_7 field. */ 5014 #define ETM_TRCVDARCCTLR_EXCLUDE_7_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_7_Pos) /*!< Bit mask of EXCLUDE_7 field. */ 5015 #define ETM_TRCVDARCCTLR_EXCLUDE_7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not selected for ViewData exclude control. */ 5016 #define ETM_TRCVDARCCTLR_EXCLUDE_7_Enabled (0x1UL) /*!< The address range that address range comparator 7 defines, s selected for ViewData exclude control. */ 5017 5018 /* Bit 22 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */ 5019 #define ETM_TRCVDARCCTLR_EXCLUDE_6_Pos (22UL) /*!< Position of EXCLUDE_6 field. */ 5020 #define ETM_TRCVDARCCTLR_EXCLUDE_6_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_6_Pos) /*!< Bit mask of EXCLUDE_6 field. */ 5021 #define ETM_TRCVDARCCTLR_EXCLUDE_6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not selected for ViewData exclude control. */ 5022 #define ETM_TRCVDARCCTLR_EXCLUDE_6_Enabled (0x1UL) /*!< The address range that address range comparator 6 defines, s selected for ViewData exclude control. */ 5023 5024 /* Bit 21 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */ 5025 #define ETM_TRCVDARCCTLR_EXCLUDE_5_Pos (21UL) /*!< Position of EXCLUDE_5 field. */ 5026 #define ETM_TRCVDARCCTLR_EXCLUDE_5_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_5_Pos) /*!< Bit mask of EXCLUDE_5 field. */ 5027 #define ETM_TRCVDARCCTLR_EXCLUDE_5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not selected for ViewData exclude control. */ 5028 #define ETM_TRCVDARCCTLR_EXCLUDE_5_Enabled (0x1UL) /*!< The address range that address range comparator 5 defines, s selected for ViewData exclude control. */ 5029 5030 /* Bit 20 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */ 5031 #define ETM_TRCVDARCCTLR_EXCLUDE_4_Pos (20UL) /*!< Position of EXCLUDE_4 field. */ 5032 #define ETM_TRCVDARCCTLR_EXCLUDE_4_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_4_Pos) /*!< Bit mask of EXCLUDE_4 field. */ 5033 #define ETM_TRCVDARCCTLR_EXCLUDE_4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not selected for ViewData exclude control. */ 5034 #define ETM_TRCVDARCCTLR_EXCLUDE_4_Enabled (0x1UL) /*!< The address range that address range comparator 4 defines, s selected for ViewData exclude control. */ 5035 5036 /* Bit 19 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */ 5037 #define ETM_TRCVDARCCTLR_EXCLUDE_3_Pos (19UL) /*!< Position of EXCLUDE_3 field. */ 5038 #define ETM_TRCVDARCCTLR_EXCLUDE_3_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_3_Pos) /*!< Bit mask of EXCLUDE_3 field. */ 5039 #define ETM_TRCVDARCCTLR_EXCLUDE_3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not selected for ViewData exclude control. */ 5040 #define ETM_TRCVDARCCTLR_EXCLUDE_3_Enabled (0x1UL) /*!< The address range that address range comparator 3 defines, s selected for ViewData exclude control. */ 5041 5042 /* Bit 18 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */ 5043 #define ETM_TRCVDARCCTLR_EXCLUDE_2_Pos (18UL) /*!< Position of EXCLUDE_2 field. */ 5044 #define ETM_TRCVDARCCTLR_EXCLUDE_2_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_2_Pos) /*!< Bit mask of EXCLUDE_2 field. */ 5045 #define ETM_TRCVDARCCTLR_EXCLUDE_2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not selected for ViewData exclude control. */ 5046 #define ETM_TRCVDARCCTLR_EXCLUDE_2_Enabled (0x1UL) /*!< The address range that address range comparator 2 defines, s selected for ViewData exclude control. */ 5047 5048 /* Bit 17 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */ 5049 #define ETM_TRCVDARCCTLR_EXCLUDE_1_Pos (17UL) /*!< Position of EXCLUDE_1 field. */ 5050 #define ETM_TRCVDARCCTLR_EXCLUDE_1_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_1_Pos) /*!< Bit mask of EXCLUDE_1 field. */ 5051 #define ETM_TRCVDARCCTLR_EXCLUDE_1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not selected for ViewData exclude control. */ 5052 #define ETM_TRCVDARCCTLR_EXCLUDE_1_Enabled (0x1UL) /*!< The address range that address range comparator 1 defines, s selected for ViewData exclude control. */ 5053 5054 /* Bit 16 : Exclude range field. Selects which address range comparator pairs are in use with ViewData exclude control. */ 5055 #define ETM_TRCVDARCCTLR_EXCLUDE_0_Pos (16UL) /*!< Position of EXCLUDE_0 field. */ 5056 #define ETM_TRCVDARCCTLR_EXCLUDE_0_Msk (0x1UL << ETM_TRCVDARCCTLR_EXCLUDE_0_Pos) /*!< Bit mask of EXCLUDE_0 field. */ 5057 #define ETM_TRCVDARCCTLR_EXCLUDE_0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not selected for ViewData exclude control. */ 5058 #define ETM_TRCVDARCCTLR_EXCLUDE_0_Enabled (0x1UL) /*!< The address range that address range comparator 0 defines, s selected for ViewData exclude control. */ 5059 5060 /* Bit 7 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */ 5061 #define ETM_TRCVDARCCTLR_INCLUDE_7_Pos (7UL) /*!< Position of INCLUDE_7 field. */ 5062 #define ETM_TRCVDARCCTLR_INCLUDE_7_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_7_Pos) /*!< Bit mask of INCLUDE_7 field. */ 5063 #define ETM_TRCVDARCCTLR_INCLUDE_7_Disabled (0x0UL) /*!< The address range that address range comparator 7 defines, is not selected for ViewData include control. */ 5064 #define ETM_TRCVDARCCTLR_INCLUDE_7_Enabled (0x1UL) /*!< The address range that address range comparator 7 defines, is selected for ViewData include control. */ 5065 5066 /* Bit 6 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */ 5067 #define ETM_TRCVDARCCTLR_INCLUDE_6_Pos (6UL) /*!< Position of INCLUDE_6 field. */ 5068 #define ETM_TRCVDARCCTLR_INCLUDE_6_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_6_Pos) /*!< Bit mask of INCLUDE_6 field. */ 5069 #define ETM_TRCVDARCCTLR_INCLUDE_6_Disabled (0x0UL) /*!< The address range that address range comparator 6 defines, is not selected for ViewData include control. */ 5070 #define ETM_TRCVDARCCTLR_INCLUDE_6_Enabled (0x1UL) /*!< The address range that address range comparator 6 defines, is selected for ViewData include control. */ 5071 5072 /* Bit 5 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */ 5073 #define ETM_TRCVDARCCTLR_INCLUDE_5_Pos (5UL) /*!< Position of INCLUDE_5 field. */ 5074 #define ETM_TRCVDARCCTLR_INCLUDE_5_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_5_Pos) /*!< Bit mask of INCLUDE_5 field. */ 5075 #define ETM_TRCVDARCCTLR_INCLUDE_5_Disabled (0x0UL) /*!< The address range that address range comparator 5 defines, is not selected for ViewData include control. */ 5076 #define ETM_TRCVDARCCTLR_INCLUDE_5_Enabled (0x1UL) /*!< The address range that address range comparator 5 defines, is selected for ViewData include control. */ 5077 5078 /* Bit 4 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */ 5079 #define ETM_TRCVDARCCTLR_INCLUDE_4_Pos (4UL) /*!< Position of INCLUDE_4 field. */ 5080 #define ETM_TRCVDARCCTLR_INCLUDE_4_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_4_Pos) /*!< Bit mask of INCLUDE_4 field. */ 5081 #define ETM_TRCVDARCCTLR_INCLUDE_4_Disabled (0x0UL) /*!< The address range that address range comparator 4 defines, is not selected for ViewData include control. */ 5082 #define ETM_TRCVDARCCTLR_INCLUDE_4_Enabled (0x1UL) /*!< The address range that address range comparator 4 defines, is selected for ViewData include control. */ 5083 5084 /* Bit 3 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */ 5085 #define ETM_TRCVDARCCTLR_INCLUDE_3_Pos (3UL) /*!< Position of INCLUDE_3 field. */ 5086 #define ETM_TRCVDARCCTLR_INCLUDE_3_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_3_Pos) /*!< Bit mask of INCLUDE_3 field. */ 5087 #define ETM_TRCVDARCCTLR_INCLUDE_3_Disabled (0x0UL) /*!< The address range that address range comparator 3 defines, is not selected for ViewData include control. */ 5088 #define ETM_TRCVDARCCTLR_INCLUDE_3_Enabled (0x1UL) /*!< The address range that address range comparator 3 defines, is selected for ViewData include control. */ 5089 5090 /* Bit 2 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */ 5091 #define ETM_TRCVDARCCTLR_INCLUDE_2_Pos (2UL) /*!< Position of INCLUDE_2 field. */ 5092 #define ETM_TRCVDARCCTLR_INCLUDE_2_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_2_Pos) /*!< Bit mask of INCLUDE_2 field. */ 5093 #define ETM_TRCVDARCCTLR_INCLUDE_2_Disabled (0x0UL) /*!< The address range that address range comparator 2 defines, is not selected for ViewData include control. */ 5094 #define ETM_TRCVDARCCTLR_INCLUDE_2_Enabled (0x1UL) /*!< The address range that address range comparator 2 defines, is selected for ViewData include control. */ 5095 5096 /* Bit 1 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */ 5097 #define ETM_TRCVDARCCTLR_INCLUDE_1_Pos (1UL) /*!< Position of INCLUDE_1 field. */ 5098 #define ETM_TRCVDARCCTLR_INCLUDE_1_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_1_Pos) /*!< Bit mask of INCLUDE_1 field. */ 5099 #define ETM_TRCVDARCCTLR_INCLUDE_1_Disabled (0x0UL) /*!< The address range that address range comparator 1 defines, is not selected for ViewData include control. */ 5100 #define ETM_TRCVDARCCTLR_INCLUDE_1_Enabled (0x1UL) /*!< The address range that address range comparator 1 defines, is selected for ViewData include control. */ 5101 5102 /* Bit 0 : Include range field. Selects which address range comparator pairs are in use with ViewData include control. */ 5103 #define ETM_TRCVDARCCTLR_INCLUDE_0_Pos (0UL) /*!< Position of INCLUDE_0 field. */ 5104 #define ETM_TRCVDARCCTLR_INCLUDE_0_Msk (0x1UL << ETM_TRCVDARCCTLR_INCLUDE_0_Pos) /*!< Bit mask of INCLUDE_0 field. */ 5105 #define ETM_TRCVDARCCTLR_INCLUDE_0_Disabled (0x0UL) /*!< The address range that address range comparator 0 defines, is not selected for ViewData include control. */ 5106 #define ETM_TRCVDARCCTLR_INCLUDE_0_Enabled (0x1UL) /*!< The address range that address range comparator 0 defines, is selected for ViewData include control. */ 5107 5108 /* Register: ETM_TRCSEQEVR */ 5109 /* Description: Description collection: Moves the sequencer state according to programmed events. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. */ 5110 5111 /* Bit 15 : Backward field. */ 5112 #define ETM_TRCSEQEVR_B_7_Pos (15UL) /*!< Position of B_7 field. */ 5113 #define ETM_TRCSEQEVR_B_7_Msk (0x1UL << ETM_TRCSEQEVR_B_7_Pos) /*!< Bit mask of B_7 field. */ 5114 #define ETM_TRCSEQEVR_B_7_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5115 #define ETM_TRCSEQEVR_B_7_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */ 5116 5117 /* Bit 14 : Backward field. */ 5118 #define ETM_TRCSEQEVR_B_6_Pos (14UL) /*!< Position of B_6 field. */ 5119 #define ETM_TRCSEQEVR_B_6_Msk (0x1UL << ETM_TRCSEQEVR_B_6_Pos) /*!< Bit mask of B_6 field. */ 5120 #define ETM_TRCSEQEVR_B_6_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5121 #define ETM_TRCSEQEVR_B_6_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */ 5122 5123 /* Bit 13 : Backward field. */ 5124 #define ETM_TRCSEQEVR_B_5_Pos (13UL) /*!< Position of B_5 field. */ 5125 #define ETM_TRCSEQEVR_B_5_Msk (0x1UL << ETM_TRCSEQEVR_B_5_Pos) /*!< Bit mask of B_5 field. */ 5126 #define ETM_TRCSEQEVR_B_5_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5127 #define ETM_TRCSEQEVR_B_5_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */ 5128 5129 /* Bit 12 : Backward field. */ 5130 #define ETM_TRCSEQEVR_B_4_Pos (12UL) /*!< Position of B_4 field. */ 5131 #define ETM_TRCSEQEVR_B_4_Msk (0x1UL << ETM_TRCSEQEVR_B_4_Pos) /*!< Bit mask of B_4 field. */ 5132 #define ETM_TRCSEQEVR_B_4_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5133 #define ETM_TRCSEQEVR_B_4_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */ 5134 5135 /* Bit 11 : Backward field. */ 5136 #define ETM_TRCSEQEVR_B_3_Pos (11UL) /*!< Position of B_3 field. */ 5137 #define ETM_TRCSEQEVR_B_3_Msk (0x1UL << ETM_TRCSEQEVR_B_3_Pos) /*!< Bit mask of B_3 field. */ 5138 #define ETM_TRCSEQEVR_B_3_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5139 #define ETM_TRCSEQEVR_B_3_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */ 5140 5141 /* Bit 10 : Backward field. */ 5142 #define ETM_TRCSEQEVR_B_2_Pos (10UL) /*!< Position of B_2 field. */ 5143 #define ETM_TRCSEQEVR_B_2_Msk (0x1UL << ETM_TRCSEQEVR_B_2_Pos) /*!< Bit mask of B_2 field. */ 5144 #define ETM_TRCSEQEVR_B_2_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5145 #define ETM_TRCSEQEVR_B_2_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */ 5146 5147 /* Bit 9 : Backward field. */ 5148 #define ETM_TRCSEQEVR_B_1_Pos (9UL) /*!< Position of B_1 field. */ 5149 #define ETM_TRCSEQEVR_B_1_Msk (0x1UL << ETM_TRCSEQEVR_B_1_Pos) /*!< Bit mask of B_1 field. */ 5150 #define ETM_TRCSEQEVR_B_1_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5151 #define ETM_TRCSEQEVR_B_1_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */ 5152 5153 /* Bit 8 : Backward field. */ 5154 #define ETM_TRCSEQEVR_B_0_Pos (8UL) /*!< Position of B_0 field. */ 5155 #define ETM_TRCSEQEVR_B_0_Msk (0x1UL << ETM_TRCSEQEVR_B_0_Pos) /*!< Bit mask of B_0 field. */ 5156 #define ETM_TRCSEQEVR_B_0_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5157 #define ETM_TRCSEQEVR_B_0_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n+1 to state n. */ 5158 5159 /* Bit 7 : Forward field. */ 5160 #define ETM_TRCSEQEVR_F_7_Pos (7UL) /*!< Position of F_7 field. */ 5161 #define ETM_TRCSEQEVR_F_7_Msk (0x1UL << ETM_TRCSEQEVR_F_7_Pos) /*!< Bit mask of F_7 field. */ 5162 #define ETM_TRCSEQEVR_F_7_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5163 #define ETM_TRCSEQEVR_F_7_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */ 5164 5165 /* Bit 6 : Forward field. */ 5166 #define ETM_TRCSEQEVR_F_6_Pos (6UL) /*!< Position of F_6 field. */ 5167 #define ETM_TRCSEQEVR_F_6_Msk (0x1UL << ETM_TRCSEQEVR_F_6_Pos) /*!< Bit mask of F_6 field. */ 5168 #define ETM_TRCSEQEVR_F_6_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5169 #define ETM_TRCSEQEVR_F_6_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */ 5170 5171 /* Bit 5 : Forward field. */ 5172 #define ETM_TRCSEQEVR_F_5_Pos (5UL) /*!< Position of F_5 field. */ 5173 #define ETM_TRCSEQEVR_F_5_Msk (0x1UL << ETM_TRCSEQEVR_F_5_Pos) /*!< Bit mask of F_5 field. */ 5174 #define ETM_TRCSEQEVR_F_5_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5175 #define ETM_TRCSEQEVR_F_5_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */ 5176 5177 /* Bit 4 : Forward field. */ 5178 #define ETM_TRCSEQEVR_F_4_Pos (4UL) /*!< Position of F_4 field. */ 5179 #define ETM_TRCSEQEVR_F_4_Msk (0x1UL << ETM_TRCSEQEVR_F_4_Pos) /*!< Bit mask of F_4 field. */ 5180 #define ETM_TRCSEQEVR_F_4_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5181 #define ETM_TRCSEQEVR_F_4_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */ 5182 5183 /* Bit 3 : Forward field. */ 5184 #define ETM_TRCSEQEVR_F_3_Pos (3UL) /*!< Position of F_3 field. */ 5185 #define ETM_TRCSEQEVR_F_3_Msk (0x1UL << ETM_TRCSEQEVR_F_3_Pos) /*!< Bit mask of F_3 field. */ 5186 #define ETM_TRCSEQEVR_F_3_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5187 #define ETM_TRCSEQEVR_F_3_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */ 5188 5189 /* Bit 2 : Forward field. */ 5190 #define ETM_TRCSEQEVR_F_2_Pos (2UL) /*!< Position of F_2 field. */ 5191 #define ETM_TRCSEQEVR_F_2_Msk (0x1UL << ETM_TRCSEQEVR_F_2_Pos) /*!< Bit mask of F_2 field. */ 5192 #define ETM_TRCSEQEVR_F_2_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5193 #define ETM_TRCSEQEVR_F_2_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */ 5194 5195 /* Bit 1 : Forward field. */ 5196 #define ETM_TRCSEQEVR_F_1_Pos (1UL) /*!< Position of F_1 field. */ 5197 #define ETM_TRCSEQEVR_F_1_Msk (0x1UL << ETM_TRCSEQEVR_F_1_Pos) /*!< Bit mask of F_1 field. */ 5198 #define ETM_TRCSEQEVR_F_1_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5199 #define ETM_TRCSEQEVR_F_1_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */ 5200 5201 /* Bit 0 : Forward field. */ 5202 #define ETM_TRCSEQEVR_F_0_Pos (0UL) /*!< Position of F_0 field. */ 5203 #define ETM_TRCSEQEVR_F_0_Msk (0x1UL << ETM_TRCSEQEVR_F_0_Pos) /*!< Bit mask of F_0 field. */ 5204 #define ETM_TRCSEQEVR_F_0_Disabled (0x0UL) /*!< The trace event does not affect the sequencer. */ 5205 #define ETM_TRCSEQEVR_F_0_Enabled (0x1UL) /*!< When the event occurs then the sequencer state moves from state n to state n+1. */ 5206 5207 /* Register: ETM_TRCSEQRSTEVR */ 5208 /* Description: Moves the sequencer to state 0 when a programmed event occurs. Might ignore writes when the trace unit is enabled or not idle. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. */ 5209 5210 /* Bits 7..0 : Select which event should reset the sequencer. */ 5211 #define ETM_TRCSEQRSTEVR_EVENT_Pos (0UL) /*!< Position of EVENT field. */ 5212 #define ETM_TRCSEQRSTEVR_EVENT_Msk (0xFFUL << ETM_TRCSEQRSTEVR_EVENT_Pos) /*!< Bit mask of EVENT field. */ 5213 5214 /* Register: ETM_TRCSEQSTR */ 5215 /* Description: Use this to set, or read, the sequencer state. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. */ 5216 5217 /* Bits 1..0 : Sets or returns the state of the sequencer. */ 5218 #define ETM_TRCSEQSTR_STATE_Pos (0UL) /*!< Position of STATE field. */ 5219 #define ETM_TRCSEQSTR_STATE_Msk (0x3UL << ETM_TRCSEQSTR_STATE_Pos) /*!< Bit mask of STATE field. */ 5220 #define ETM_TRCSEQSTR_STATE_State0 (0x0UL) /*!< The sequencer is in state 0. */ 5221 #define ETM_TRCSEQSTR_STATE_State1 (0x1UL) /*!< The sequencer is in state 1. */ 5222 #define ETM_TRCSEQSTR_STATE_State2 (0x2UL) /*!< The sequencer is in state 2. */ 5223 #define ETM_TRCSEQSTR_STATE_State3 (0x3UL) /*!< The sequencer is in state 3. */ 5224 5225 /* Register: ETM_TRCEXTINSELR */ 5226 /* Description: Use this to set, or read, which external inputs are resources to the trace unit. Might ignore writes when the trace unit is enabled or not idle. Only returns stable data when TRCSTATR.PMSTABLE == 1. When the sequencer is used, all sequencer state transitions must be programmed with a valid event. */ 5227 5228 /* Bits 31..24 : Each field in this collection selects an external input as a resource for the trace unit. */ 5229 #define ETM_TRCEXTINSELR_SEL_3_Pos (24UL) /*!< Position of SEL_3 field. */ 5230 #define ETM_TRCEXTINSELR_SEL_3_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL_3_Pos) /*!< Bit mask of SEL_3 field. */ 5231 5232 /* Bits 23..16 : Each field in this collection selects an external input as a resource for the trace unit. */ 5233 #define ETM_TRCEXTINSELR_SEL_2_Pos (16UL) /*!< Position of SEL_2 field. */ 5234 #define ETM_TRCEXTINSELR_SEL_2_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL_2_Pos) /*!< Bit mask of SEL_2 field. */ 5235 5236 /* Bits 15..8 : Each field in this collection selects an external input as a resource for the trace unit. */ 5237 #define ETM_TRCEXTINSELR_SEL_1_Pos (8UL) /*!< Position of SEL_1 field. */ 5238 #define ETM_TRCEXTINSELR_SEL_1_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL_1_Pos) /*!< Bit mask of SEL_1 field. */ 5239 5240 /* Bits 7..0 : Each field in this collection selects an external input as a resource for the trace unit. */ 5241 #define ETM_TRCEXTINSELR_SEL_0_Pos (0UL) /*!< Position of SEL_0 field. */ 5242 #define ETM_TRCEXTINSELR_SEL_0_Msk (0xFFUL << ETM_TRCEXTINSELR_SEL_0_Pos) /*!< Bit mask of SEL_0 field. */ 5243 5244 /* Register: ETM_TRCCNTRLDVR */ 5245 /* Description: Description collection: This sets or returns the reload count value for counter n. Might ignore writes when the trace unit is enabled or not idle. */ 5246 5247 /* Bits 15..0 : Contains the reload value for counter n. When a reload event occurs for counter n then the trace unit copies the VALUEn field into counter n. */ 5248 #define ETM_TRCCNTRLDVR_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 5249 #define ETM_TRCCNTRLDVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTRLDVR_VALUE_Pos) /*!< Bit mask of VALUE field. */ 5250 5251 /* Register: ETM_TRCCNTCTLR */ 5252 /* Description: Description collection: Controls the operation of counter n. Might ignore writes when the trace unit is enabled or not idle. */ 5253 5254 /* Bit 17 : For TRCCNTCTLR3 and TRCCNTCTLR1, this bit controls whether counter n decrements when a reload event occurs for counter n-1. */ 5255 #define ETM_TRCCNTCTLR_CNTCHAIN_Pos (17UL) /*!< Position of CNTCHAIN field. */ 5256 #define ETM_TRCCNTCTLR_CNTCHAIN_Msk (0x1UL << ETM_TRCCNTCTLR_CNTCHAIN_Pos) /*!< Bit mask of CNTCHAIN field. */ 5257 #define ETM_TRCCNTCTLR_CNTCHAIN_Disabled (0x0UL) /*!< Counter n does not decrement when a reload event for counter n-1 occurs. */ 5258 #define ETM_TRCCNTCTLR_CNTCHAIN_Enabled (0x1UL) /*!< Counter n decrements when a reload event for counter n-1 occurs. This concatenates counter n and counter n-1, to provide a larger count value. */ 5259 5260 /* Bit 16 : Controls whether a reload event occurs for counter n, when counter n reaches zero. */ 5261 #define ETM_TRCCNTCTLR_RLDSELF_Pos (16UL) /*!< Position of RLDSELF field. */ 5262 #define ETM_TRCCNTCTLR_RLDSELF_Msk (0x1UL << ETM_TRCCNTCTLR_RLDSELF_Pos) /*!< Bit mask of RLDSELF field. */ 5263 #define ETM_TRCCNTCTLR_RLDSELF_Disabled (0x0UL) /*!< The counter is in Normal mode. */ 5264 #define ETM_TRCCNTCTLR_RLDSELF_Enabled (0x1UL) /*!< The counter is in Self-reload mode. */ 5265 5266 /* Bits 15..8 : Selects an event, that when it occurs causes a reload event for counter n. */ 5267 #define ETM_TRCCNTCTLR_RLDEVENT_Pos (8UL) /*!< Position of RLDEVENT field. */ 5268 #define ETM_TRCCNTCTLR_RLDEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_RLDEVENT_Pos) /*!< Bit mask of RLDEVENT field. */ 5269 5270 /* Bits 7..0 : Selects an event, that when it occurs causes counter n to decrement. */ 5271 #define ETM_TRCCNTCTLR_CNTEVENT_Pos (0UL) /*!< Position of CNTEVENT field. */ 5272 #define ETM_TRCCNTCTLR_CNTEVENT_Msk (0xFFUL << ETM_TRCCNTCTLR_CNTEVENT_Pos) /*!< Bit mask of CNTEVENT field. */ 5273 5274 /* Register: ETM_TRCCNTVR */ 5275 /* Description: Description collection: This sets or returns the value of counter n. The count value is only stable when TRCSTATR.PMSTABLE == 1. If software uses counter n then it must write to this register to set the initial counter value. Might ignore writes when the trace unit is enabled or not idle. */ 5276 5277 /* Bits 15..0 : Contains the count value of counter n. */ 5278 #define ETM_TRCCNTVR_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 5279 #define ETM_TRCCNTVR_VALUE_Msk (0xFFFFUL << ETM_TRCCNTVR_VALUE_Pos) /*!< Bit mask of VALUE field. */ 5280 5281 /* Register: ETM_TRCRSCTLR */ 5282 /* Description: Description collection: Controls the selection of the resources in the trace unit. Might ignore writes when the trace unit is enabled or not idle. If software selects a non-implemented resource then CONSTRAINED UNPREDICTABLE 5283 behavior of the resource selector occurs, so the resource selector might fire 5284 unexpectedly or might not fire. Reads of the TRCRSCTLRn might return UNKNOWN. */ 5285 5286 /* Bit 0 : Trace unit enable bit */ 5287 #define ETM_TRCRSCTLR_EN_Pos (0UL) /*!< Position of EN field. */ 5288 #define ETM_TRCRSCTLR_EN_Msk (0x1UL << ETM_TRCRSCTLR_EN_Pos) /*!< Bit mask of EN field. */ 5289 #define ETM_TRCRSCTLR_EN_Disabled (0x0UL) /*!< The trace unit is disabled. All trace resources are inactive and no trace is generated. */ 5290 #define ETM_TRCRSCTLR_EN_Enabled (0x1UL) /*!< The trace unit is enabled. */ 5291 5292 /* Register: ETM_TRCSSCCR0 */ 5293 /* Description: Controls the single-shot comparator. */ 5294 5295 /* Bit 24 : Enables the single-shot comparator resource to be reset when it occurs, to enable another comparator match to be detected */ 5296 #define ETM_TRCSSCCR0_RST_Pos (24UL) /*!< Position of RST field. */ 5297 #define ETM_TRCSSCCR0_RST_Msk (0x1UL << ETM_TRCSSCCR0_RST_Pos) /*!< Bit mask of RST field. */ 5298 #define ETM_TRCSSCCR0_RST_Disabled (0x0UL) /*!< Multiple matches can not be detected. */ 5299 #define ETM_TRCSSCCR0_RST_Enabled (0x1UL) /*!< Multiple matches can occur. */ 5300 5301 /* Register: ETM_TRCSSCSR0 */ 5302 /* Description: Indicates the status of the single-shot comparators. TRCSSCSR0 is sensitive toinstruction addresses. */ 5303 5304 /* Bit 31 : Single-shot status. This indicates whether any of the selected comparators have matched. */ 5305 #define ETM_TRCSSCSR0_STATUS_Pos (31UL) /*!< Position of STATUS field. */ 5306 #define ETM_TRCSSCSR0_STATUS_Msk (0x1UL << ETM_TRCSSCSR0_STATUS_Pos) /*!< Bit mask of STATUS field. */ 5307 #define ETM_TRCSSCSR0_STATUS_NoMatch (0x0UL) /*!< Match has not occurred. */ 5308 #define ETM_TRCSSCSR0_STATUS_Match (0x1UL) /*!< Match has occurred at least once. */ 5309 5310 /* Bit 3 : Process counter value comparator support */ 5311 #define ETM_TRCSSCSR0_PC_Pos (3UL) /*!< Position of PC field. */ 5312 #define ETM_TRCSSCSR0_PC_Msk (0x1UL << ETM_TRCSSCSR0_PC_Pos) /*!< Bit mask of PC field. */ 5313 #define ETM_TRCSSCSR0_PC_False (0x0UL) /*!< Process counter value comparisons not supported. */ 5314 #define ETM_TRCSSCSR0_PC_True (0x1UL) /*!< Process counter value comparisons supported. */ 5315 5316 /* Bit 2 : Data value comparator support */ 5317 #define ETM_TRCSSCSR0_DV_Pos (2UL) /*!< Position of DV field. */ 5318 #define ETM_TRCSSCSR0_DV_Msk (0x1UL << ETM_TRCSSCSR0_DV_Pos) /*!< Bit mask of DV field. */ 5319 #define ETM_TRCSSCSR0_DV_False (0x0UL) /*!< Data value comparisons not supported. */ 5320 #define ETM_TRCSSCSR0_DV_True (0x1UL) /*!< Data value comparisons supported. */ 5321 5322 /* Bit 1 : Data address comparator support */ 5323 #define ETM_TRCSSCSR0_DA_Pos (1UL) /*!< Position of DA field. */ 5324 #define ETM_TRCSSCSR0_DA_Msk (0x1UL << ETM_TRCSSCSR0_DA_Pos) /*!< Bit mask of DA field. */ 5325 #define ETM_TRCSSCSR0_DA_False (0x0UL) /*!< Data address comparisons not supported. */ 5326 #define ETM_TRCSSCSR0_DA_True (0x1UL) /*!< Data address comparisons supported. */ 5327 5328 /* Bit 0 : Instruction address comparator support */ 5329 #define ETM_TRCSSCSR0_INST_Pos (0UL) /*!< Position of INST field. */ 5330 #define ETM_TRCSSCSR0_INST_Msk (0x1UL << ETM_TRCSSCSR0_INST_Pos) /*!< Bit mask of INST field. */ 5331 #define ETM_TRCSSCSR0_INST_False (0x0UL) /*!< Single-shot instruction address comparisons not supported. */ 5332 #define ETM_TRCSSCSR0_INST_True (0x1UL) /*!< Single-shot instruction address comparisons supported. */ 5333 5334 /* Register: ETM_TRCSSPCICR0 */ 5335 /* Description: Selects the processor comparator inputs for Single-shot control. */ 5336 5337 /* Bit 3 : Selects processor comparator 3 inputs for Single-shot control */ 5338 #define ETM_TRCSSPCICR0_PC_3_Pos (3UL) /*!< Position of PC_3 field. */ 5339 #define ETM_TRCSSPCICR0_PC_3_Msk (0x1UL << ETM_TRCSSPCICR0_PC_3_Pos) /*!< Bit mask of PC_3 field. */ 5340 #define ETM_TRCSSPCICR0_PC_3_Disabled (0x0UL) /*!< Processor comparator 3 is not selected for Single-shot control. */ 5341 #define ETM_TRCSSPCICR0_PC_3_Enabled (0x1UL) /*!< Processor comparator 3 is selected for Single-shot control. */ 5342 5343 /* Bit 2 : Selects processor comparator 2 inputs for Single-shot control */ 5344 #define ETM_TRCSSPCICR0_PC_2_Pos (2UL) /*!< Position of PC_2 field. */ 5345 #define ETM_TRCSSPCICR0_PC_2_Msk (0x1UL << ETM_TRCSSPCICR0_PC_2_Pos) /*!< Bit mask of PC_2 field. */ 5346 #define ETM_TRCSSPCICR0_PC_2_Disabled (0x0UL) /*!< Processor comparator 2 is not selected for Single-shot control. */ 5347 #define ETM_TRCSSPCICR0_PC_2_Enabled (0x1UL) /*!< Processor comparator 2 is selected for Single-shot control. */ 5348 5349 /* Bit 1 : Selects processor comparator 1 inputs for Single-shot control */ 5350 #define ETM_TRCSSPCICR0_PC_1_Pos (1UL) /*!< Position of PC_1 field. */ 5351 #define ETM_TRCSSPCICR0_PC_1_Msk (0x1UL << ETM_TRCSSPCICR0_PC_1_Pos) /*!< Bit mask of PC_1 field. */ 5352 #define ETM_TRCSSPCICR0_PC_1_Disabled (0x0UL) /*!< Processor comparator 1 is not selected for Single-shot control. */ 5353 #define ETM_TRCSSPCICR0_PC_1_Enabled (0x1UL) /*!< Processor comparator 1 is selected for Single-shot control. */ 5354 5355 /* Bit 0 : Selects processor comparator 0 inputs for Single-shot control */ 5356 #define ETM_TRCSSPCICR0_PC_0_Pos (0UL) /*!< Position of PC_0 field. */ 5357 #define ETM_TRCSSPCICR0_PC_0_Msk (0x1UL << ETM_TRCSSPCICR0_PC_0_Pos) /*!< Bit mask of PC_0 field. */ 5358 #define ETM_TRCSSPCICR0_PC_0_Disabled (0x0UL) /*!< Processor comparator 0 is not selected for Single-shot control. */ 5359 #define ETM_TRCSSPCICR0_PC_0_Enabled (0x1UL) /*!< Processor comparator 0 is selected for Single-shot control. */ 5360 5361 /* Register: ETM_TRCPDCR */ 5362 /* Description: Controls the single-shot comparator. */ 5363 5364 /* Bit 24 : Power up request, to request that power to ETM and access to the trace registers is maintained. */ 5365 #define ETM_TRCPDCR_PU_Pos (24UL) /*!< Position of PU field. */ 5366 #define ETM_TRCPDCR_PU_Msk (0x1UL << ETM_TRCPDCR_PU_Pos) /*!< Bit mask of PU field. */ 5367 #define ETM_TRCPDCR_PU_Disabled (0x0UL) /*!< Power not requested. */ 5368 #define ETM_TRCPDCR_PU_Enabled (0x1UL) /*!< Power requested. */ 5369 5370 /* Register: ETM_TRCPDSR */ 5371 /* Description: Indicates the power down status of the ETM. */ 5372 5373 /* Bit 1 : Sticky power down state. This bit is set to 1 when power to the ETM registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR */ 5374 #define ETM_TRCPDSR_STICKYPD_Pos (1UL) /*!< Position of STICKYPD field. */ 5375 #define ETM_TRCPDSR_STICKYPD_Msk (0x1UL << ETM_TRCPDSR_STICKYPD_Pos) /*!< Bit mask of STICKYPD field. */ 5376 #define ETM_TRCPDSR_STICKYPD_NotPoweredDown (0x0UL) /*!< Trace register power has not been removed since the TRCPDSR was last read. */ 5377 #define ETM_TRCPDSR_STICKYPD_PoweredDown (0x1UL) /*!< Trace register power has been removed since the TRCPDSR was last read. */ 5378 5379 /* Bit 0 : Indicates ETM is powered up */ 5380 #define ETM_TRCPDSR_POWER_Pos (0UL) /*!< Position of POWER field. */ 5381 #define ETM_TRCPDSR_POWER_Msk (0x1UL << ETM_TRCPDSR_POWER_Pos) /*!< Bit mask of POWER field. */ 5382 #define ETM_TRCPDSR_POWER_NotPoweredUp (0x0UL) /*!< ETM is not powered up. All registers are not accessible. */ 5383 #define ETM_TRCPDSR_POWER_PoweredUp (0x1UL) /*!< ETM is powered up. All registers are accessible. */ 5384 5385 /* Register: ETM_TRCITATBIDR */ 5386 /* Description: Sets the state of output pins. */ 5387 5388 /* Bit 6 : Drives the ATIDMI[6] output pin. */ 5389 #define ETM_TRCITATBIDR_ID_6_Pos (6UL) /*!< Position of ID_6 field. */ 5390 #define ETM_TRCITATBIDR_ID_6_Msk (0x1UL << ETM_TRCITATBIDR_ID_6_Pos) /*!< Bit mask of ID_6 field. */ 5391 5392 /* Bit 5 : Drives the ATIDMI[5] output pin. */ 5393 #define ETM_TRCITATBIDR_ID_5_Pos (5UL) /*!< Position of ID_5 field. */ 5394 #define ETM_TRCITATBIDR_ID_5_Msk (0x1UL << ETM_TRCITATBIDR_ID_5_Pos) /*!< Bit mask of ID_5 field. */ 5395 5396 /* Bit 4 : Drives the ATIDMI[4] output pin. */ 5397 #define ETM_TRCITATBIDR_ID_4_Pos (4UL) /*!< Position of ID_4 field. */ 5398 #define ETM_TRCITATBIDR_ID_4_Msk (0x1UL << ETM_TRCITATBIDR_ID_4_Pos) /*!< Bit mask of ID_4 field. */ 5399 5400 /* Bit 3 : Drives the ATIDMI[3] output pin. */ 5401 #define ETM_TRCITATBIDR_ID_3_Pos (3UL) /*!< Position of ID_3 field. */ 5402 #define ETM_TRCITATBIDR_ID_3_Msk (0x1UL << ETM_TRCITATBIDR_ID_3_Pos) /*!< Bit mask of ID_3 field. */ 5403 5404 /* Bit 2 : Drives the ATIDMI[2] output pin. */ 5405 #define ETM_TRCITATBIDR_ID_2_Pos (2UL) /*!< Position of ID_2 field. */ 5406 #define ETM_TRCITATBIDR_ID_2_Msk (0x1UL << ETM_TRCITATBIDR_ID_2_Pos) /*!< Bit mask of ID_2 field. */ 5407 5408 /* Bit 1 : Drives the ATIDMI[1] output pin. */ 5409 #define ETM_TRCITATBIDR_ID_1_Pos (1UL) /*!< Position of ID_1 field. */ 5410 #define ETM_TRCITATBIDR_ID_1_Msk (0x1UL << ETM_TRCITATBIDR_ID_1_Pos) /*!< Bit mask of ID_1 field. */ 5411 5412 /* Bit 0 : Drives the ATIDMI[0] output pin. */ 5413 #define ETM_TRCITATBIDR_ID_0_Pos (0UL) /*!< Position of ID_0 field. */ 5414 #define ETM_TRCITATBIDR_ID_0_Msk (0x1UL << ETM_TRCITATBIDR_ID_0_Pos) /*!< Bit mask of ID_0 field. */ 5415 5416 /* Register: ETM_TRCITIATBINR */ 5417 /* Description: Reads the state of the input pins. */ 5418 5419 /* Bit 1 : Returns the value of the AFREADYMI input pin. */ 5420 #define ETM_TRCITIATBINR_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */ 5421 #define ETM_TRCITIATBINR_AFREADY_Msk (0x1UL << ETM_TRCITIATBINR_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ 5422 5423 /* Bit 0 : Returns the value of the ATVALIDMI input pin. */ 5424 #define ETM_TRCITIATBINR_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ 5425 #define ETM_TRCITIATBINR_ATVALID_Msk (0x1UL << ETM_TRCITIATBINR_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ 5426 5427 /* Register: ETM_TRCITIATBOUTR */ 5428 /* Description: Sets the state of the output pins. */ 5429 5430 /* Bit 1 : Drives the AFREADYMI output pin. */ 5431 #define ETM_TRCITIATBOUTR_AFREADY_Pos (1UL) /*!< Position of AFREADY field. */ 5432 #define ETM_TRCITIATBOUTR_AFREADY_Msk (0x1UL << ETM_TRCITIATBOUTR_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ 5433 5434 /* Bit 0 : Drives the ATVALIDMI output pin. */ 5435 #define ETM_TRCITIATBOUTR_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ 5436 #define ETM_TRCITIATBOUTR_ATVALID_Msk (0x1UL << ETM_TRCITIATBOUTR_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ 5437 5438 /* Register: ETM_TRCITCTRL */ 5439 /* Description: Enables topology detection or integration testing, by putting ETM-M33 into integration mode. */ 5440 5441 /* Bit 0 : Integration mode enable */ 5442 #define ETM_TRCITCTRL_IME_Pos (0UL) /*!< Position of IME field. */ 5443 #define ETM_TRCITCTRL_IME_Msk (0x1UL << ETM_TRCITCTRL_IME_Pos) /*!< Bit mask of IME field. */ 5444 #define ETM_TRCITCTRL_IME_Disabled (0x0UL) /*!< ETM is not in integration mode. */ 5445 #define ETM_TRCITCTRL_IME_Enabled (0x1UL) /*!< ETM is in integration mode. */ 5446 5447 /* Register: ETM_TRCCLAIMSET */ 5448 /* Description: Sets bits in the claim tag and determines the number of claim tag bits implemented. */ 5449 5450 /* Bit 3 : Claim tag set register */ 5451 #define ETM_TRCCLAIMSET_SET_3_Pos (3UL) /*!< Position of SET_3 field. */ 5452 #define ETM_TRCCLAIMSET_SET_3_Msk (0x1UL << ETM_TRCCLAIMSET_SET_3_Pos) /*!< Bit mask of SET_3 field. */ 5453 #define ETM_TRCCLAIMSET_SET_3_NotSet (0x0UL) /*!< Claim tag 3 is not set. */ 5454 #define ETM_TRCCLAIMSET_SET_3_Set (0x1UL) /*!< Claim tag 3 is set. */ 5455 #define ETM_TRCCLAIMSET_SET_3_Claim (0x1UL) /*!< Set claim tag 3. */ 5456 5457 /* Bit 2 : Claim tag set register */ 5458 #define ETM_TRCCLAIMSET_SET_2_Pos (2UL) /*!< Position of SET_2 field. */ 5459 #define ETM_TRCCLAIMSET_SET_2_Msk (0x1UL << ETM_TRCCLAIMSET_SET_2_Pos) /*!< Bit mask of SET_2 field. */ 5460 #define ETM_TRCCLAIMSET_SET_2_NotSet (0x0UL) /*!< Claim tag 2 is not set. */ 5461 #define ETM_TRCCLAIMSET_SET_2_Set (0x1UL) /*!< Claim tag 2 is set. */ 5462 #define ETM_TRCCLAIMSET_SET_2_Claim (0x1UL) /*!< Set claim tag 2. */ 5463 5464 /* Bit 1 : Claim tag set register */ 5465 #define ETM_TRCCLAIMSET_SET_1_Pos (1UL) /*!< Position of SET_1 field. */ 5466 #define ETM_TRCCLAIMSET_SET_1_Msk (0x1UL << ETM_TRCCLAIMSET_SET_1_Pos) /*!< Bit mask of SET_1 field. */ 5467 #define ETM_TRCCLAIMSET_SET_1_NotSet (0x0UL) /*!< Claim tag 1 is not set. */ 5468 #define ETM_TRCCLAIMSET_SET_1_Set (0x1UL) /*!< Claim tag 1 is set. */ 5469 #define ETM_TRCCLAIMSET_SET_1_Claim (0x1UL) /*!< Set claim tag 1. */ 5470 5471 /* Bit 0 : Claim tag set register */ 5472 #define ETM_TRCCLAIMSET_SET_0_Pos (0UL) /*!< Position of SET_0 field. */ 5473 #define ETM_TRCCLAIMSET_SET_0_Msk (0x1UL << ETM_TRCCLAIMSET_SET_0_Pos) /*!< Bit mask of SET_0 field. */ 5474 #define ETM_TRCCLAIMSET_SET_0_NotSet (0x0UL) /*!< Claim tag 0 is not set. */ 5475 #define ETM_TRCCLAIMSET_SET_0_Set (0x1UL) /*!< Claim tag 0 is set. */ 5476 #define ETM_TRCCLAIMSET_SET_0_Claim (0x1UL) /*!< Set claim tag 0. */ 5477 5478 /* Register: ETM_TRCCLAIMCLR */ 5479 /* Description: Clears bits in the claim tag and determines the current value of the claim tag. */ 5480 5481 /* Bit 3 : Claim tag clear register */ 5482 #define ETM_TRCCLAIMCLR_CLR_3_Pos (3UL) /*!< Position of CLR_3 field. */ 5483 #define ETM_TRCCLAIMCLR_CLR_3_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR_3_Pos) /*!< Bit mask of CLR_3 field. */ 5484 #define ETM_TRCCLAIMCLR_CLR_3_NotSet (0x0UL) /*!< Claim tag 3 is not set. */ 5485 #define ETM_TRCCLAIMCLR_CLR_3_Set (0x1UL) /*!< Claim tag 3 is set. */ 5486 #define ETM_TRCCLAIMCLR_CLR_3_Clear (0x1UL) /*!< Clear claim tag 3. */ 5487 5488 /* Bit 2 : Claim tag clear register */ 5489 #define ETM_TRCCLAIMCLR_CLR_2_Pos (2UL) /*!< Position of CLR_2 field. */ 5490 #define ETM_TRCCLAIMCLR_CLR_2_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR_2_Pos) /*!< Bit mask of CLR_2 field. */ 5491 #define ETM_TRCCLAIMCLR_CLR_2_NotSet (0x0UL) /*!< Claim tag 2 is not set. */ 5492 #define ETM_TRCCLAIMCLR_CLR_2_Set (0x1UL) /*!< Claim tag 2 is set. */ 5493 #define ETM_TRCCLAIMCLR_CLR_2_Clear (0x1UL) /*!< Clear claim tag 2. */ 5494 5495 /* Bit 1 : Claim tag clear register */ 5496 #define ETM_TRCCLAIMCLR_CLR_1_Pos (1UL) /*!< Position of CLR_1 field. */ 5497 #define ETM_TRCCLAIMCLR_CLR_1_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR_1_Pos) /*!< Bit mask of CLR_1 field. */ 5498 #define ETM_TRCCLAIMCLR_CLR_1_NotSet (0x0UL) /*!< Claim tag 1 is not set. */ 5499 #define ETM_TRCCLAIMCLR_CLR_1_Set (0x1UL) /*!< Claim tag 1 is set. */ 5500 #define ETM_TRCCLAIMCLR_CLR_1_Clear (0x1UL) /*!< Clear claim tag 1. */ 5501 5502 /* Bit 0 : Claim tag clear register */ 5503 #define ETM_TRCCLAIMCLR_CLR_0_Pos (0UL) /*!< Position of CLR_0 field. */ 5504 #define ETM_TRCCLAIMCLR_CLR_0_Msk (0x1UL << ETM_TRCCLAIMCLR_CLR_0_Pos) /*!< Bit mask of CLR_0 field. */ 5505 #define ETM_TRCCLAIMCLR_CLR_0_NotSet (0x0UL) /*!< Claim tag 0 is not set. */ 5506 #define ETM_TRCCLAIMCLR_CLR_0_Set (0x1UL) /*!< Claim tag 0 is set. */ 5507 #define ETM_TRCCLAIMCLR_CLR_0_Clear (0x1UL) /*!< Clear claim tag 0. */ 5508 5509 /* Register: ETM_TRCAUTHSTATUS */ 5510 /* Description: Indicates the current level of tracing permitted by the system */ 5511 5512 /* Bits 7..6 : Secure Non-Invasive Debug */ 5513 #define ETM_TRCAUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ 5514 #define ETM_TRCAUTHSTATUS_SNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ 5515 #define ETM_TRCAUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 5516 #define ETM_TRCAUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */ 5517 5518 /* Bits 5..4 : Secure Invasive Debug */ 5519 #define ETM_TRCAUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ 5520 #define ETM_TRCAUTHSTATUS_SID_Msk (0x3UL << ETM_TRCAUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ 5521 #define ETM_TRCAUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 5522 #define ETM_TRCAUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */ 5523 5524 /* Bits 3..2 : Non-secure Non-Invasive Debug */ 5525 #define ETM_TRCAUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ 5526 #define ETM_TRCAUTHSTATUS_NSNID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ 5527 #define ETM_TRCAUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 5528 #define ETM_TRCAUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */ 5529 5530 /* Bits 1..0 : Non-secure Invasive Debug */ 5531 #define ETM_TRCAUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ 5532 #define ETM_TRCAUTHSTATUS_NSID_Msk (0x3UL << ETM_TRCAUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ 5533 #define ETM_TRCAUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 5534 #define ETM_TRCAUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */ 5535 5536 /* Register: ETM_TRCDEVARCH */ 5537 /* Description: The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 component */ 5538 5539 /* Bits 31..21 : Defines the architect of the component */ 5540 #define ETM_TRCDEVARCH_ARCHITECT_Pos (21UL) /*!< Position of ARCHITECT field. */ 5541 #define ETM_TRCDEVARCH_ARCHITECT_Msk (0x7FFUL << ETM_TRCDEVARCH_ARCHITECT_Pos) /*!< Bit mask of ARCHITECT field. */ 5542 #define ETM_TRCDEVARCH_ARCHITECT_Arm (0x23BUL) /*!< This peripheral was architected by Arm. */ 5543 5544 /* Bit 20 : This register is implemented */ 5545 #define ETM_TRCDEVARCH_PRESENT_Pos (20UL) /*!< Position of PRESENT field. */ 5546 #define ETM_TRCDEVARCH_PRESENT_Msk (0x1UL << ETM_TRCDEVARCH_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ 5547 #define ETM_TRCDEVARCH_PRESENT_Absent (0x0UL) /*!< The register is not implemented. */ 5548 #define ETM_TRCDEVARCH_PRESENT_Present (0x1UL) /*!< The register is implemented. */ 5549 5550 /* Bits 19..16 : Architecture revision */ 5551 #define ETM_TRCDEVARCH_REVISION_Pos (16UL) /*!< Position of REVISION field. */ 5552 #define ETM_TRCDEVARCH_REVISION_Msk (0xFUL << ETM_TRCDEVARCH_REVISION_Pos) /*!< Bit mask of REVISION field. */ 5553 #define ETM_TRCDEVARCH_REVISION_v2 (0x2UL) /*!< Component is part of architecture 4.2 */ 5554 5555 /* Bits 15..0 : Architecture ID */ 5556 #define ETM_TRCDEVARCH_ARCHID_Pos (0UL) /*!< Position of ARCHID field. */ 5557 #define ETM_TRCDEVARCH_ARCHID_Msk (0xFFFFUL << ETM_TRCDEVARCH_ARCHID_Pos) /*!< Bit mask of ARCHID field. */ 5558 #define ETM_TRCDEVARCH_ARCHID_ETMv42 (0x4A13UL) /*!< Component is an ETMv4 component */ 5559 5560 /* Register: ETM_TRCDEVTYPE */ 5561 /* Description: Controls the single-shot comparator. */ 5562 5563 /* Bits 7..4 : The sub-type of the component */ 5564 #define ETM_TRCDEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ 5565 #define ETM_TRCDEVTYPE_SUB_Msk (0xFUL << ETM_TRCDEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ 5566 #define ETM_TRCDEVTYPE_SUB_ProcessorTrace (0x1UL) /*!< Peripheral is a processor trace source. */ 5567 5568 /* Bits 3..0 : The main type of the component */ 5569 #define ETM_TRCDEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ 5570 #define ETM_TRCDEVTYPE_MAJOR_Msk (0xFUL << ETM_TRCDEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ 5571 #define ETM_TRCDEVTYPE_MAJOR_TraceSource (0x3UL) /*!< Peripheral is a trace source. */ 5572 5573 5574 /* Peripheral: FICR */ 5575 /* Description: Factory Information Configuration Registers */ 5576 5577 /* Register: FICR_SIPINFO_PARTNO */ 5578 /* Description: SIP part number */ 5579 5580 /* Bits 31..0 : */ 5581 #define FICR_SIPINFO_PARTNO_PARTNO_Pos (0UL) /*!< Position of PARTNO field. */ 5582 #define FICR_SIPINFO_PARTNO_PARTNO_Msk (0xFFFFFFFFUL << FICR_SIPINFO_PARTNO_PARTNO_Pos) /*!< Bit mask of PARTNO field. */ 5583 #define FICR_SIPINFO_PARTNO_PARTNO_9131 (0x00009131UL) /*!< Device is an nRF9131 sip */ 5584 #define FICR_SIPINFO_PARTNO_PARTNO_9151 (0x00009151UL) /*!< Device is an nRF9151 sip */ 5585 #define FICR_SIPINFO_PARTNO_PARTNO_9160 (0x00009160UL) /*!< Device is an nRF9160 sip */ 5586 #define FICR_SIPINFO_PARTNO_PARTNO_9161 (0x00009161UL) /*!< Device is an nRF9161 sip */ 5587 5588 /* Register: FICR_SIPINFO_HWREVISION */ 5589 /* Description: Description collection: SIP hardware revision, encoded in ASCII, for example B0A or B1A */ 5590 5591 /* Bits 7..0 : */ 5592 #define FICR_SIPINFO_HWREVISION_HWREVISION_Pos (0UL) /*!< Position of HWREVISION field. */ 5593 #define FICR_SIPINFO_HWREVISION_HWREVISION_Msk (0xFFUL << FICR_SIPINFO_HWREVISION_HWREVISION_Pos) /*!< Bit mask of HWREVISION field. */ 5594 5595 /* Register: FICR_SIPINFO_VARIANT */ 5596 /* Description: Description collection: SIP VARIANT, encoded in ASCII, for example SIAA, SIBA or SICA. 5597 See Ordering information for details. */ 5598 5599 /* Bits 7..0 : */ 5600 #define FICR_SIPINFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ 5601 #define FICR_SIPINFO_VARIANT_VARIANT_Msk (0xFFUL << FICR_SIPINFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ 5602 #define FICR_SIPINFO_VARIANT_VARIANT_A (0x41UL) /*!< Unspecified */ 5603 #define FICR_SIPINFO_VARIANT_VARIANT_B (0x42UL) /*!< Unspecified */ 5604 #define FICR_SIPINFO_VARIANT_VARIANT_C (0x43UL) /*!< Unspecified */ 5605 #define FICR_SIPINFO_VARIANT_VARIANT_I (0x49UL) /*!< Unspecified */ 5606 #define FICR_SIPINFO_VARIANT_VARIANT_L (0x4CUL) /*!< Unspecified */ 5607 #define FICR_SIPINFO_VARIANT_VARIANT_S (0x53UL) /*!< Unspecified */ 5608 5609 /* Register: FICR_INFO_DEVICEID */ 5610 /* Description: Description collection: Device identifier */ 5611 5612 /* Bits 31..0 : 64 bit unique device identifier */ 5613 #define FICR_INFO_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ 5614 #define FICR_INFO_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ 5615 5616 /* Register: FICR_INFO_RAM */ 5617 /* Description: RAM variant */ 5618 5619 /* Bits 31..0 : RAM variant */ 5620 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ 5621 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ 5622 #define FICR_INFO_RAM_RAM_K256 (0x00000100UL) /*!< 256 kByte RAM */ 5623 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 5624 5625 /* Register: FICR_INFO_FLASH */ 5626 /* Description: Flash variant */ 5627 5628 /* Bits 31..0 : Flash variant */ 5629 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ 5630 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ 5631 #define FICR_INFO_FLASH_FLASH_K1024 (0x00000400UL) /*!< 1 MByte FLASH */ 5632 5633 /* Register: FICR_INFO_CODEPAGESIZE */ 5634 /* Description: Code memory page size */ 5635 5636 /* Bits 31..0 : Code memory page size */ 5637 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ 5638 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ 5639 #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x00001000UL) /*!< 4 kByte */ 5640 5641 /* Register: FICR_INFO_CODESIZE */ 5642 /* Description: Code memory size */ 5643 5644 /* Bits 31..0 : Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE */ 5645 #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ 5646 #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ 5647 #define FICR_INFO_CODESIZE_CODESIZE_P256 (0x00000100UL) /*!< 256 pages */ 5648 5649 /* Register: FICR_INFO_DEVICETYPE */ 5650 /* Description: Device type */ 5651 5652 /* Bits 31..0 : Device type */ 5653 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */ 5654 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */ 5655 #define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x00000000UL) /*!< Device is an physical DIE */ 5656 #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */ 5657 5658 /* Register: FICR_TRIMCNF_ADDR */ 5659 /* Description: Description cluster: Address */ 5660 5661 /* Bits 31..0 : Address */ 5662 #define FICR_TRIMCNF_ADDR_Address_Pos (0UL) /*!< Position of Address field. */ 5663 #define FICR_TRIMCNF_ADDR_Address_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_ADDR_Address_Pos) /*!< Bit mask of Address field. */ 5664 5665 /* Register: FICR_TRIMCNF_DATA */ 5666 /* Description: Description cluster: Data */ 5667 5668 /* Bits 31..0 : Data */ 5669 #define FICR_TRIMCNF_DATA_Data_Pos (0UL) /*!< Position of Data field. */ 5670 #define FICR_TRIMCNF_DATA_Data_Msk (0xFFFFFFFFUL << FICR_TRIMCNF_DATA_Data_Pos) /*!< Bit mask of Data field. */ 5671 5672 /* Register: FICR_TRNG90B_BYTES */ 5673 /* Description: Amount of bytes for the required entropy bits */ 5674 5675 /* Bits 31..0 : Amount of bytes for the required entropy bits */ 5676 #define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */ 5677 #define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */ 5678 5679 /* Register: FICR_TRNG90B_RCCUTOFF */ 5680 /* Description: Repetition counter cutoff */ 5681 5682 /* Bits 31..0 : Repetition counter cutoff */ 5683 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */ 5684 #define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */ 5685 5686 /* Register: FICR_TRNG90B_APCUTOFF */ 5687 /* Description: Adaptive proportion cutoff */ 5688 5689 /* Bits 31..0 : Adaptive proportion cutoff */ 5690 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */ 5691 #define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */ 5692 5693 /* Register: FICR_TRNG90B_STARTUP */ 5694 /* Description: Amount of bytes for the startup tests */ 5695 5696 /* Bits 31..0 : Amount of bytes for the startup tests */ 5697 #define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */ 5698 #define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */ 5699 5700 /* Register: FICR_TRNG90B_ROSC1 */ 5701 /* Description: Sample count for ring oscillator configuration 1 */ 5702 5703 /* Bits 31..0 : Sample count for ring oscillator configuration 1 */ 5704 #define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */ 5705 #define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */ 5706 5707 /* Register: FICR_TRNG90B_ROSC2 */ 5708 /* Description: Sample count for ring oscillator configuration 2 */ 5709 5710 /* Bits 31..0 : Sample count for ring oscillator configuration 2 */ 5711 #define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */ 5712 #define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */ 5713 5714 /* Register: FICR_TRNG90B_ROSC3 */ 5715 /* Description: Sample count for ring oscillator configuration 3 */ 5716 5717 /* Bits 31..0 : Sample count for ring oscillator configuration 3 */ 5718 #define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */ 5719 #define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */ 5720 5721 /* Register: FICR_TRNG90B_ROSC4 */ 5722 /* Description: Sample count for ring oscillator configuration 4 */ 5723 5724 /* Bits 31..0 : Sample count for ring oscillator configuration 4 */ 5725 #define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */ 5726 #define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */ 5727 5728 5729 /* Peripheral: GPIOTE */ 5730 /* Description: GPIO Tasks and Events 0 */ 5731 5732 /* Register: GPIOTE_TASKS_OUT */ 5733 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ 5734 5735 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ 5736 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ 5737 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ 5738 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (0x1UL) /*!< Trigger task */ 5739 5740 /* Register: GPIOTE_TASKS_SET */ 5741 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ 5742 5743 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ 5744 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ 5745 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ 5746 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (0x1UL) /*!< Trigger task */ 5747 5748 /* Register: GPIOTE_TASKS_CLR */ 5749 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ 5750 5751 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ 5752 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ 5753 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ 5754 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (0x1UL) /*!< Trigger task */ 5755 5756 /* Register: GPIOTE_SUBSCRIBE_OUT */ 5757 /* Description: Description collection: Subscribe configuration for task OUT[n] */ 5758 5759 /* Bit 31 : */ 5760 #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */ 5761 #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */ 5762 #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0x0UL) /*!< Disable subscription */ 5763 #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (0x1UL) /*!< Enable subscription */ 5764 5765 /* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */ 5766 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5767 #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5768 5769 /* Register: GPIOTE_SUBSCRIBE_SET */ 5770 /* Description: Description collection: Subscribe configuration for task SET[n] */ 5771 5772 /* Bit 31 : */ 5773 #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */ 5774 #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */ 5775 #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0x0UL) /*!< Disable subscription */ 5776 #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (0x1UL) /*!< Enable subscription */ 5777 5778 /* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */ 5779 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5780 #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5781 5782 /* Register: GPIOTE_SUBSCRIBE_CLR */ 5783 /* Description: Description collection: Subscribe configuration for task CLR[n] */ 5784 5785 /* Bit 31 : */ 5786 #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */ 5787 #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */ 5788 #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0x0UL) /*!< Disable subscription */ 5789 #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (0x1UL) /*!< Enable subscription */ 5790 5791 /* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */ 5792 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5793 #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5794 5795 /* Register: GPIOTE_EVENTS_IN */ 5796 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ 5797 5798 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ 5799 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ 5800 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ 5801 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0x0UL) /*!< Event not generated */ 5802 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (0x1UL) /*!< Event generated */ 5803 5804 /* Register: GPIOTE_EVENTS_PORT */ 5805 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ 5806 5807 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ 5808 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ 5809 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ 5810 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0x0UL) /*!< Event not generated */ 5811 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (0x1UL) /*!< Event generated */ 5812 5813 /* Register: GPIOTE_PUBLISH_IN */ 5814 /* Description: Description collection: Publish configuration for event IN[n] */ 5815 5816 /* Bit 31 : */ 5817 #define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */ 5818 #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */ 5819 #define GPIOTE_PUBLISH_IN_EN_Disabled (0x0UL) /*!< Disable publishing */ 5820 #define GPIOTE_PUBLISH_IN_EN_Enabled (0x1UL) /*!< Enable publishing */ 5821 5822 /* Bits 7..0 : DPPI channel that event IN[n] will publish to */ 5823 #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5824 #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5825 5826 /* Register: GPIOTE_PUBLISH_PORT */ 5827 /* Description: Publish configuration for event PORT */ 5828 5829 /* Bit 31 : */ 5830 #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */ 5831 #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */ 5832 #define GPIOTE_PUBLISH_PORT_EN_Disabled (0x0UL) /*!< Disable publishing */ 5833 #define GPIOTE_PUBLISH_PORT_EN_Enabled (0x1UL) /*!< Enable publishing */ 5834 5835 /* Bits 7..0 : DPPI channel that event PORT will publish to */ 5836 #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5837 #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5838 5839 /* Register: GPIOTE_INTENSET */ 5840 /* Description: Enable interrupt */ 5841 5842 /* Bit 31 : Write '1' to enable interrupt for event PORT */ 5843 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ 5844 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ 5845 #define GPIOTE_INTENSET_PORT_Disabled (0x0UL) /*!< Read: Disabled */ 5846 #define GPIOTE_INTENSET_PORT_Enabled (0x1UL) /*!< Read: Enabled */ 5847 #define GPIOTE_INTENSET_PORT_Set (0x1UL) /*!< Enable */ 5848 5849 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */ 5850 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ 5851 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ 5852 #define GPIOTE_INTENSET_IN7_Disabled (0x0UL) /*!< Read: Disabled */ 5853 #define GPIOTE_INTENSET_IN7_Enabled (0x1UL) /*!< Read: Enabled */ 5854 #define GPIOTE_INTENSET_IN7_Set (0x1UL) /*!< Enable */ 5855 5856 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */ 5857 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ 5858 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ 5859 #define GPIOTE_INTENSET_IN6_Disabled (0x0UL) /*!< Read: Disabled */ 5860 #define GPIOTE_INTENSET_IN6_Enabled (0x1UL) /*!< Read: Enabled */ 5861 #define GPIOTE_INTENSET_IN6_Set (0x1UL) /*!< Enable */ 5862 5863 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */ 5864 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ 5865 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ 5866 #define GPIOTE_INTENSET_IN5_Disabled (0x0UL) /*!< Read: Disabled */ 5867 #define GPIOTE_INTENSET_IN5_Enabled (0x1UL) /*!< Read: Enabled */ 5868 #define GPIOTE_INTENSET_IN5_Set (0x1UL) /*!< Enable */ 5869 5870 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */ 5871 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ 5872 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ 5873 #define GPIOTE_INTENSET_IN4_Disabled (0x0UL) /*!< Read: Disabled */ 5874 #define GPIOTE_INTENSET_IN4_Enabled (0x1UL) /*!< Read: Enabled */ 5875 #define GPIOTE_INTENSET_IN4_Set (0x1UL) /*!< Enable */ 5876 5877 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */ 5878 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ 5879 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ 5880 #define GPIOTE_INTENSET_IN3_Disabled (0x0UL) /*!< Read: Disabled */ 5881 #define GPIOTE_INTENSET_IN3_Enabled (0x1UL) /*!< Read: Enabled */ 5882 #define GPIOTE_INTENSET_IN3_Set (0x1UL) /*!< Enable */ 5883 5884 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */ 5885 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ 5886 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ 5887 #define GPIOTE_INTENSET_IN2_Disabled (0x0UL) /*!< Read: Disabled */ 5888 #define GPIOTE_INTENSET_IN2_Enabled (0x1UL) /*!< Read: Enabled */ 5889 #define GPIOTE_INTENSET_IN2_Set (0x1UL) /*!< Enable */ 5890 5891 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */ 5892 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ 5893 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ 5894 #define GPIOTE_INTENSET_IN1_Disabled (0x0UL) /*!< Read: Disabled */ 5895 #define GPIOTE_INTENSET_IN1_Enabled (0x1UL) /*!< Read: Enabled */ 5896 #define GPIOTE_INTENSET_IN1_Set (0x1UL) /*!< Enable */ 5897 5898 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */ 5899 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ 5900 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ 5901 #define GPIOTE_INTENSET_IN0_Disabled (0x0UL) /*!< Read: Disabled */ 5902 #define GPIOTE_INTENSET_IN0_Enabled (0x1UL) /*!< Read: Enabled */ 5903 #define GPIOTE_INTENSET_IN0_Set (0x1UL) /*!< Enable */ 5904 5905 /* Register: GPIOTE_INTENCLR */ 5906 /* Description: Disable interrupt */ 5907 5908 /* Bit 31 : Write '1' to disable interrupt for event PORT */ 5909 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ 5910 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ 5911 #define GPIOTE_INTENCLR_PORT_Disabled (0x0UL) /*!< Read: Disabled */ 5912 #define GPIOTE_INTENCLR_PORT_Enabled (0x1UL) /*!< Read: Enabled */ 5913 #define GPIOTE_INTENCLR_PORT_Clear (0x1UL) /*!< Disable */ 5914 5915 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */ 5916 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ 5917 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ 5918 #define GPIOTE_INTENCLR_IN7_Disabled (0x0UL) /*!< Read: Disabled */ 5919 #define GPIOTE_INTENCLR_IN7_Enabled (0x1UL) /*!< Read: Enabled */ 5920 #define GPIOTE_INTENCLR_IN7_Clear (0x1UL) /*!< Disable */ 5921 5922 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */ 5923 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ 5924 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ 5925 #define GPIOTE_INTENCLR_IN6_Disabled (0x0UL) /*!< Read: Disabled */ 5926 #define GPIOTE_INTENCLR_IN6_Enabled (0x1UL) /*!< Read: Enabled */ 5927 #define GPIOTE_INTENCLR_IN6_Clear (0x1UL) /*!< Disable */ 5928 5929 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */ 5930 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ 5931 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ 5932 #define GPIOTE_INTENCLR_IN5_Disabled (0x0UL) /*!< Read: Disabled */ 5933 #define GPIOTE_INTENCLR_IN5_Enabled (0x1UL) /*!< Read: Enabled */ 5934 #define GPIOTE_INTENCLR_IN5_Clear (0x1UL) /*!< Disable */ 5935 5936 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */ 5937 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ 5938 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ 5939 #define GPIOTE_INTENCLR_IN4_Disabled (0x0UL) /*!< Read: Disabled */ 5940 #define GPIOTE_INTENCLR_IN4_Enabled (0x1UL) /*!< Read: Enabled */ 5941 #define GPIOTE_INTENCLR_IN4_Clear (0x1UL) /*!< Disable */ 5942 5943 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */ 5944 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ 5945 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ 5946 #define GPIOTE_INTENCLR_IN3_Disabled (0x0UL) /*!< Read: Disabled */ 5947 #define GPIOTE_INTENCLR_IN3_Enabled (0x1UL) /*!< Read: Enabled */ 5948 #define GPIOTE_INTENCLR_IN3_Clear (0x1UL) /*!< Disable */ 5949 5950 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */ 5951 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ 5952 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ 5953 #define GPIOTE_INTENCLR_IN2_Disabled (0x0UL) /*!< Read: Disabled */ 5954 #define GPIOTE_INTENCLR_IN2_Enabled (0x1UL) /*!< Read: Enabled */ 5955 #define GPIOTE_INTENCLR_IN2_Clear (0x1UL) /*!< Disable */ 5956 5957 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */ 5958 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ 5959 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ 5960 #define GPIOTE_INTENCLR_IN1_Disabled (0x0UL) /*!< Read: Disabled */ 5961 #define GPIOTE_INTENCLR_IN1_Enabled (0x1UL) /*!< Read: Enabled */ 5962 #define GPIOTE_INTENCLR_IN1_Clear (0x1UL) /*!< Disable */ 5963 5964 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */ 5965 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ 5966 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ 5967 #define GPIOTE_INTENCLR_IN0_Disabled (0x0UL) /*!< Read: Disabled */ 5968 #define GPIOTE_INTENCLR_IN0_Enabled (0x1UL) /*!< Read: Enabled */ 5969 #define GPIOTE_INTENCLR_IN0_Clear (0x1UL) /*!< Disable */ 5970 5971 /* Register: GPIOTE_CONFIG */ 5972 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ 5973 5974 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ 5975 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ 5976 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ 5977 #define GPIOTE_CONFIG_OUTINIT_Low (0x0UL) /*!< Task mode: Initial value of pin before task triggering is low */ 5978 #define GPIOTE_CONFIG_OUTINIT_High (0x1UL) /*!< Task mode: Initial value of pin before task triggering is high */ 5979 5980 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ 5981 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ 5982 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ 5983 #define GPIOTE_CONFIG_POLARITY_None (0x0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ 5984 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ 5985 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ 5986 #define GPIOTE_CONFIG_POLARITY_Toggle (0x3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ 5987 5988 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ 5989 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 5990 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 5991 5992 /* Bits 1..0 : Mode */ 5993 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ 5994 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 5995 #define GPIOTE_CONFIG_MODE_Disabled (0x0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ 5996 #define GPIOTE_CONFIG_MODE_Event (0x1UL) /*!< Event mode */ 5997 #define GPIOTE_CONFIG_MODE_Task (0x3UL) /*!< Task mode */ 5998 5999 6000 /* Peripheral: I2S */ 6001 /* Description: Inter-IC Sound 0 */ 6002 6003 /* Register: I2S_TASKS_START */ 6004 /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ 6005 6006 /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ 6007 #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 6008 #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 6009 #define I2S_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ 6010 6011 /* Register: I2S_TASKS_STOP */ 6012 /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ 6013 6014 /* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ 6015 #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 6016 #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 6017 #define I2S_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ 6018 6019 /* Register: I2S_SUBSCRIBE_START */ 6020 /* Description: Subscribe configuration for task START */ 6021 6022 /* Bit 31 : */ 6023 #define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 6024 #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 6025 #define I2S_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ 6026 #define I2S_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ 6027 6028 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 6029 #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6030 #define I2S_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6031 6032 /* Register: I2S_SUBSCRIBE_STOP */ 6033 /* Description: Subscribe configuration for task STOP */ 6034 6035 /* Bit 31 : */ 6036 #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 6037 #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 6038 #define I2S_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 6039 #define I2S_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 6040 6041 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 6042 #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6043 #define I2S_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << I2S_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6044 6045 /* Register: I2S_EVENTS_RXPTRUPD */ 6046 /* Description: The RXD.PTR register has been copied to internal double-buffers. 6047 When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ 6048 6049 /* Bit 0 : The RXD.PTR register has been copied to internal double-buffers. 6050 When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ 6051 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ 6052 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */ 6053 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */ 6054 #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (0x1UL) /*!< Event generated */ 6055 6056 /* Register: I2S_EVENTS_STOPPED */ 6057 /* Description: I2S transfer stopped. */ 6058 6059 /* Bit 0 : I2S transfer stopped. */ 6060 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 6061 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 6062 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ 6063 #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ 6064 6065 /* Register: I2S_EVENTS_TXPTRUPD */ 6066 /* Description: The TDX.PTR register has been copied to internal double-buffers. 6067 When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ 6068 6069 /* Bit 0 : The TDX.PTR register has been copied to internal double-buffers. 6070 When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ 6071 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ 6072 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */ 6073 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */ 6074 #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (0x1UL) /*!< Event generated */ 6075 6076 /* Register: I2S_PUBLISH_RXPTRUPD */ 6077 /* Description: Publish configuration for event RXPTRUPD */ 6078 6079 /* Bit 31 : */ 6080 #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ 6081 #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ 6082 #define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */ 6083 #define I2S_PUBLISH_RXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */ 6084 6085 /* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to */ 6086 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6087 #define I2S_PUBLISH_RXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_RXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6088 6089 /* Register: I2S_PUBLISH_STOPPED */ 6090 /* Description: Publish configuration for event STOPPED */ 6091 6092 /* Bit 31 : */ 6093 #define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 6094 #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 6095 #define I2S_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ 6096 #define I2S_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ 6097 6098 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 6099 #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6100 #define I2S_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << I2S_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6101 6102 /* Register: I2S_PUBLISH_TXPTRUPD */ 6103 /* Description: Publish configuration for event TXPTRUPD */ 6104 6105 /* Bit 31 : */ 6106 #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ 6107 #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ 6108 #define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */ 6109 #define I2S_PUBLISH_TXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */ 6110 6111 /* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to */ 6112 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6113 #define I2S_PUBLISH_TXPTRUPD_CHIDX_Msk (0xFFUL << I2S_PUBLISH_TXPTRUPD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6114 6115 /* Register: I2S_INTEN */ 6116 /* Description: Enable or disable interrupt */ 6117 6118 /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */ 6119 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ 6120 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ 6121 #define I2S_INTEN_TXPTRUPD_Disabled (0x0UL) /*!< Disable */ 6122 #define I2S_INTEN_TXPTRUPD_Enabled (0x1UL) /*!< Enable */ 6123 6124 /* Bit 2 : Enable or disable interrupt for event STOPPED */ 6125 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ 6126 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6127 #define I2S_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ 6128 #define I2S_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ 6129 6130 /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */ 6131 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ 6132 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ 6133 #define I2S_INTEN_RXPTRUPD_Disabled (0x0UL) /*!< Disable */ 6134 #define I2S_INTEN_RXPTRUPD_Enabled (0x1UL) /*!< Enable */ 6135 6136 /* Register: I2S_INTENSET */ 6137 /* Description: Enable interrupt */ 6138 6139 /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */ 6140 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ 6141 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ 6142 #define I2S_INTENSET_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ 6143 #define I2S_INTENSET_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ 6144 #define I2S_INTENSET_TXPTRUPD_Set (0x1UL) /*!< Enable */ 6145 6146 /* Bit 2 : Write '1' to enable interrupt for event STOPPED */ 6147 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ 6148 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6149 #define I2S_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 6150 #define I2S_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 6151 #define I2S_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ 6152 6153 /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ 6154 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ 6155 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ 6156 #define I2S_INTENSET_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ 6157 #define I2S_INTENSET_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ 6158 #define I2S_INTENSET_RXPTRUPD_Set (0x1UL) /*!< Enable */ 6159 6160 /* Register: I2S_INTENCLR */ 6161 /* Description: Disable interrupt */ 6162 6163 /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */ 6164 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ 6165 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ 6166 #define I2S_INTENCLR_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ 6167 #define I2S_INTENCLR_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ 6168 #define I2S_INTENCLR_TXPTRUPD_Clear (0x1UL) /*!< Disable */ 6169 6170 /* Bit 2 : Write '1' to disable interrupt for event STOPPED */ 6171 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ 6172 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6173 #define I2S_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 6174 #define I2S_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 6175 #define I2S_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ 6176 6177 /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ 6178 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ 6179 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ 6180 #define I2S_INTENCLR_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ 6181 #define I2S_INTENCLR_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ 6182 #define I2S_INTENCLR_RXPTRUPD_Clear (0x1UL) /*!< Disable */ 6183 6184 /* Register: I2S_ENABLE */ 6185 /* Description: Enable I2S module. */ 6186 6187 /* Bit 0 : Enable I2S module. */ 6188 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 6189 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 6190 #define I2S_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ 6191 #define I2S_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ 6192 6193 /* Register: I2S_CONFIG_MODE */ 6194 /* Description: I2S mode. */ 6195 6196 /* Bit 0 : I2S mode. */ 6197 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 6198 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 6199 #define I2S_CONFIG_MODE_MODE_Master (0x0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ 6200 #define I2S_CONFIG_MODE_MODE_Slave (0x1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ 6201 6202 /* Register: I2S_CONFIG_RXEN */ 6203 /* Description: Reception (RX) enable. */ 6204 6205 /* Bit 0 : Reception (RX) enable. */ 6206 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ 6207 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ 6208 #define I2S_CONFIG_RXEN_RXEN_Disabled (0x0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ 6209 #define I2S_CONFIG_RXEN_RXEN_Enabled (0x1UL) /*!< Reception enabled. */ 6210 6211 /* Register: I2S_CONFIG_TXEN */ 6212 /* Description: Transmission (TX) enable. */ 6213 6214 /* Bit 0 : Transmission (TX) enable. */ 6215 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ 6216 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ 6217 #define I2S_CONFIG_TXEN_TXEN_Disabled (0x0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ 6218 #define I2S_CONFIG_TXEN_TXEN_Enabled (0x1UL) /*!< Transmission enabled. */ 6219 6220 /* Register: I2S_CONFIG_MCKEN */ 6221 /* Description: Master clock generator enable. */ 6222 6223 /* Bit 0 : Master clock generator enable. */ 6224 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ 6225 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ 6226 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0x0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ 6227 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (0x1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ 6228 6229 /* Register: I2S_CONFIG_MCKFREQ */ 6230 /* Description: Master clock generator frequency. */ 6231 6232 /* Bits 31..0 : Master clock generator frequency. */ 6233 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ 6234 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ 6235 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ 6236 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ 6237 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ 6238 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ 6239 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ 6240 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ 6241 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ 6242 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ 6243 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ 6244 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ 6245 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ 6246 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ 6247 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ 6248 6249 /* Register: I2S_CONFIG_RATIO */ 6250 /* Description: MCK / LRCK ratio. */ 6251 6252 /* Bits 3..0 : MCK / LRCK ratio. */ 6253 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ 6254 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ 6255 #define I2S_CONFIG_RATIO_RATIO_32X (0x0UL) /*!< LRCK = MCK / 32 */ 6256 #define I2S_CONFIG_RATIO_RATIO_48X (0x1UL) /*!< LRCK = MCK / 48 */ 6257 #define I2S_CONFIG_RATIO_RATIO_64X (0x2UL) /*!< LRCK = MCK / 64 */ 6258 #define I2S_CONFIG_RATIO_RATIO_96X (0x3UL) /*!< LRCK = MCK / 96 */ 6259 #define I2S_CONFIG_RATIO_RATIO_128X (0x4UL) /*!< LRCK = MCK / 128 */ 6260 #define I2S_CONFIG_RATIO_RATIO_192X (0x5UL) /*!< LRCK = MCK / 192 */ 6261 #define I2S_CONFIG_RATIO_RATIO_256X (0x6UL) /*!< LRCK = MCK / 256 */ 6262 #define I2S_CONFIG_RATIO_RATIO_384X (0x7UL) /*!< LRCK = MCK / 384 */ 6263 #define I2S_CONFIG_RATIO_RATIO_512X (0x8UL) /*!< LRCK = MCK / 512 */ 6264 6265 /* Register: I2S_CONFIG_SWIDTH */ 6266 /* Description: Sample width. */ 6267 6268 /* Bits 1..0 : Sample width. */ 6269 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ 6270 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ 6271 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0x0UL) /*!< 8 bit. */ 6272 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (0x1UL) /*!< 16 bit. */ 6273 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (0x2UL) /*!< 24 bit. */ 6274 6275 /* Register: I2S_CONFIG_ALIGN */ 6276 /* Description: Alignment of sample within a frame. */ 6277 6278 /* Bit 0 : Alignment of sample within a frame. */ 6279 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ 6280 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ 6281 #define I2S_CONFIG_ALIGN_ALIGN_Left (0x0UL) /*!< Left-aligned. */ 6282 #define I2S_CONFIG_ALIGN_ALIGN_Right (0x1UL) /*!< Right-aligned. */ 6283 6284 /* Register: I2S_CONFIG_FORMAT */ 6285 /* Description: Frame format. */ 6286 6287 /* Bit 0 : Frame format. */ 6288 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ 6289 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ 6290 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0x0UL) /*!< Original I2S format. */ 6291 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (0x1UL) /*!< Alternate (left- or right-aligned) format. */ 6292 6293 /* Register: I2S_CONFIG_CHANNELS */ 6294 /* Description: Enable channels. */ 6295 6296 /* Bits 1..0 : Enable channels. */ 6297 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ 6298 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ 6299 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0x0UL) /*!< Stereo. */ 6300 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (0x1UL) /*!< Left only. */ 6301 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (0x2UL) /*!< Right only. */ 6302 6303 /* Register: I2S_RXD_PTR */ 6304 /* Description: Receive buffer RAM start address. */ 6305 6306 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ 6307 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 6308 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 6309 6310 /* Register: I2S_TXD_PTR */ 6311 /* Description: Transmit buffer RAM start address. */ 6312 6313 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ 6314 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 6315 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 6316 6317 /* Register: I2S_RXTXD_MAXCNT */ 6318 /* Description: Size of RXD and TXD buffers. */ 6319 6320 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ 6321 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 6322 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 6323 6324 /* Register: I2S_PSEL_MCK */ 6325 /* Description: Pin select for MCK signal. */ 6326 6327 /* Bit 31 : Connection */ 6328 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6329 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6330 #define I2S_PSEL_MCK_CONNECT_Connected (0x0UL) /*!< Connect */ 6331 #define I2S_PSEL_MCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 6332 6333 /* Bits 4..0 : Pin number */ 6334 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 6335 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ 6336 6337 /* Register: I2S_PSEL_SCK */ 6338 /* Description: Pin select for SCK signal. */ 6339 6340 /* Bit 31 : Connection */ 6341 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6342 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6343 #define I2S_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ 6344 #define I2S_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 6345 6346 /* Bits 4..0 : Pin number */ 6347 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 6348 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 6349 6350 /* Register: I2S_PSEL_LRCK */ 6351 /* Description: Pin select for LRCK signal. */ 6352 6353 /* Bit 31 : Connection */ 6354 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6355 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6356 #define I2S_PSEL_LRCK_CONNECT_Connected (0x0UL) /*!< Connect */ 6357 #define I2S_PSEL_LRCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 6358 6359 /* Bits 4..0 : Pin number */ 6360 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 6361 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ 6362 6363 /* Register: I2S_PSEL_SDIN */ 6364 /* Description: Pin select for SDIN signal. */ 6365 6366 /* Bit 31 : Connection */ 6367 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6368 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6369 #define I2S_PSEL_SDIN_CONNECT_Connected (0x0UL) /*!< Connect */ 6370 #define I2S_PSEL_SDIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 6371 6372 /* Bits 4..0 : Pin number */ 6373 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ 6374 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ 6375 6376 /* Register: I2S_PSEL_SDOUT */ 6377 /* Description: Pin select for SDOUT signal. */ 6378 6379 /* Bit 31 : Connection */ 6380 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6381 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6382 #define I2S_PSEL_SDOUT_CONNECT_Connected (0x0UL) /*!< Connect */ 6383 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 6384 6385 /* Bits 4..0 : Pin number */ 6386 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ 6387 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ 6388 6389 6390 /* Peripheral: IPC */ 6391 /* Description: Interprocessor communication 0 */ 6392 6393 /* Register: IPC_TASKS_SEND */ 6394 /* Description: Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] */ 6395 6396 /* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */ 6397 #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */ 6398 #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */ 6399 #define IPC_TASKS_SEND_TASKS_SEND_Trigger (0x1UL) /*!< Trigger task */ 6400 6401 /* Register: IPC_SUBSCRIBE_SEND */ 6402 /* Description: Description collection: Subscribe configuration for task SEND[n] */ 6403 6404 /* Bit 31 : */ 6405 #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */ 6406 #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */ 6407 #define IPC_SUBSCRIBE_SEND_EN_Disabled (0x0UL) /*!< Disable subscription */ 6408 #define IPC_SUBSCRIBE_SEND_EN_Enabled (0x1UL) /*!< Enable subscription */ 6409 6410 /* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */ 6411 #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6412 #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6413 6414 /* Register: IPC_EVENTS_RECEIVE */ 6415 /* Description: Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */ 6416 6417 /* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */ 6418 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */ 6419 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */ 6420 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0x0UL) /*!< Event not generated */ 6421 #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (0x1UL) /*!< Event generated */ 6422 6423 /* Register: IPC_PUBLISH_RECEIVE */ 6424 /* Description: Description collection: Publish configuration for event RECEIVE[n] */ 6425 6426 /* Bit 31 : */ 6427 #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */ 6428 #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */ 6429 #define IPC_PUBLISH_RECEIVE_EN_Disabled (0x0UL) /*!< Disable publishing */ 6430 #define IPC_PUBLISH_RECEIVE_EN_Enabled (0x1UL) /*!< Enable publishing */ 6431 6432 /* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to */ 6433 #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 6434 #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 6435 6436 /* Register: IPC_INTEN */ 6437 /* Description: Enable or disable interrupt */ 6438 6439 /* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ 6440 #define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ 6441 #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ 6442 #define IPC_INTEN_RECEIVE7_Disabled (0x0UL) /*!< Disable */ 6443 #define IPC_INTEN_RECEIVE7_Enabled (0x1UL) /*!< Enable */ 6444 6445 /* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ 6446 #define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ 6447 #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ 6448 #define IPC_INTEN_RECEIVE6_Disabled (0x0UL) /*!< Disable */ 6449 #define IPC_INTEN_RECEIVE6_Enabled (0x1UL) /*!< Enable */ 6450 6451 /* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ 6452 #define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ 6453 #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ 6454 #define IPC_INTEN_RECEIVE5_Disabled (0x0UL) /*!< Disable */ 6455 #define IPC_INTEN_RECEIVE5_Enabled (0x1UL) /*!< Enable */ 6456 6457 /* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ 6458 #define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ 6459 #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ 6460 #define IPC_INTEN_RECEIVE4_Disabled (0x0UL) /*!< Disable */ 6461 #define IPC_INTEN_RECEIVE4_Enabled (0x1UL) /*!< Enable */ 6462 6463 /* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ 6464 #define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ 6465 #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ 6466 #define IPC_INTEN_RECEIVE3_Disabled (0x0UL) /*!< Disable */ 6467 #define IPC_INTEN_RECEIVE3_Enabled (0x1UL) /*!< Enable */ 6468 6469 /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ 6470 #define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ 6471 #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ 6472 #define IPC_INTEN_RECEIVE2_Disabled (0x0UL) /*!< Disable */ 6473 #define IPC_INTEN_RECEIVE2_Enabled (0x1UL) /*!< Enable */ 6474 6475 /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ 6476 #define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ 6477 #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ 6478 #define IPC_INTEN_RECEIVE1_Disabled (0x0UL) /*!< Disable */ 6479 #define IPC_INTEN_RECEIVE1_Enabled (0x1UL) /*!< Enable */ 6480 6481 /* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ 6482 #define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ 6483 #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ 6484 #define IPC_INTEN_RECEIVE0_Disabled (0x0UL) /*!< Disable */ 6485 #define IPC_INTEN_RECEIVE0_Enabled (0x1UL) /*!< Enable */ 6486 6487 /* Register: IPC_INTENSET */ 6488 /* Description: Enable interrupt */ 6489 6490 /* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ 6491 #define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ 6492 #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ 6493 #define IPC_INTENSET_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ 6494 #define IPC_INTENSET_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ 6495 #define IPC_INTENSET_RECEIVE7_Set (0x1UL) /*!< Enable */ 6496 6497 /* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ 6498 #define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ 6499 #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ 6500 #define IPC_INTENSET_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ 6501 #define IPC_INTENSET_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ 6502 #define IPC_INTENSET_RECEIVE6_Set (0x1UL) /*!< Enable */ 6503 6504 /* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ 6505 #define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ 6506 #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ 6507 #define IPC_INTENSET_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ 6508 #define IPC_INTENSET_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ 6509 #define IPC_INTENSET_RECEIVE5_Set (0x1UL) /*!< Enable */ 6510 6511 /* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ 6512 #define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ 6513 #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ 6514 #define IPC_INTENSET_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ 6515 #define IPC_INTENSET_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ 6516 #define IPC_INTENSET_RECEIVE4_Set (0x1UL) /*!< Enable */ 6517 6518 /* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ 6519 #define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ 6520 #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ 6521 #define IPC_INTENSET_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ 6522 #define IPC_INTENSET_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ 6523 #define IPC_INTENSET_RECEIVE3_Set (0x1UL) /*!< Enable */ 6524 6525 /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ 6526 #define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ 6527 #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ 6528 #define IPC_INTENSET_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ 6529 #define IPC_INTENSET_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ 6530 #define IPC_INTENSET_RECEIVE2_Set (0x1UL) /*!< Enable */ 6531 6532 /* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ 6533 #define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ 6534 #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ 6535 #define IPC_INTENSET_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ 6536 #define IPC_INTENSET_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ 6537 #define IPC_INTENSET_RECEIVE1_Set (0x1UL) /*!< Enable */ 6538 6539 /* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ 6540 #define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ 6541 #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ 6542 #define IPC_INTENSET_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ 6543 #define IPC_INTENSET_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ 6544 #define IPC_INTENSET_RECEIVE0_Set (0x1UL) /*!< Enable */ 6545 6546 /* Register: IPC_INTENCLR */ 6547 /* Description: Disable interrupt */ 6548 6549 /* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ 6550 #define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ 6551 #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ 6552 #define IPC_INTENCLR_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ 6553 #define IPC_INTENCLR_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ 6554 #define IPC_INTENCLR_RECEIVE7_Clear (0x1UL) /*!< Disable */ 6555 6556 /* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ 6557 #define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ 6558 #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ 6559 #define IPC_INTENCLR_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ 6560 #define IPC_INTENCLR_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ 6561 #define IPC_INTENCLR_RECEIVE6_Clear (0x1UL) /*!< Disable */ 6562 6563 /* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ 6564 #define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ 6565 #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ 6566 #define IPC_INTENCLR_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ 6567 #define IPC_INTENCLR_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ 6568 #define IPC_INTENCLR_RECEIVE5_Clear (0x1UL) /*!< Disable */ 6569 6570 /* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ 6571 #define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ 6572 #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ 6573 #define IPC_INTENCLR_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ 6574 #define IPC_INTENCLR_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ 6575 #define IPC_INTENCLR_RECEIVE4_Clear (0x1UL) /*!< Disable */ 6576 6577 /* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ 6578 #define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ 6579 #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ 6580 #define IPC_INTENCLR_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ 6581 #define IPC_INTENCLR_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ 6582 #define IPC_INTENCLR_RECEIVE3_Clear (0x1UL) /*!< Disable */ 6583 6584 /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ 6585 #define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ 6586 #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ 6587 #define IPC_INTENCLR_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ 6588 #define IPC_INTENCLR_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ 6589 #define IPC_INTENCLR_RECEIVE2_Clear (0x1UL) /*!< Disable */ 6590 6591 /* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ 6592 #define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ 6593 #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ 6594 #define IPC_INTENCLR_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ 6595 #define IPC_INTENCLR_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ 6596 #define IPC_INTENCLR_RECEIVE1_Clear (0x1UL) /*!< Disable */ 6597 6598 /* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ 6599 #define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ 6600 #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ 6601 #define IPC_INTENCLR_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ 6602 #define IPC_INTENCLR_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ 6603 #define IPC_INTENCLR_RECEIVE0_Clear (0x1UL) /*!< Disable */ 6604 6605 /* Register: IPC_INTPEND */ 6606 /* Description: Pending interrupts */ 6607 6608 /* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ 6609 #define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ 6610 #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ 6611 #define IPC_INTPEND_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */ 6612 #define IPC_INTPEND_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */ 6613 6614 /* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ 6615 #define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ 6616 #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ 6617 #define IPC_INTPEND_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */ 6618 #define IPC_INTPEND_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */ 6619 6620 /* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ 6621 #define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ 6622 #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ 6623 #define IPC_INTPEND_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */ 6624 #define IPC_INTPEND_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */ 6625 6626 /* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ 6627 #define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ 6628 #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ 6629 #define IPC_INTPEND_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */ 6630 #define IPC_INTPEND_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */ 6631 6632 /* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ 6633 #define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ 6634 #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ 6635 #define IPC_INTPEND_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */ 6636 #define IPC_INTPEND_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */ 6637 6638 /* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ 6639 #define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ 6640 #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ 6641 #define IPC_INTPEND_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */ 6642 #define IPC_INTPEND_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */ 6643 6644 /* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ 6645 #define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ 6646 #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ 6647 #define IPC_INTPEND_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */ 6648 #define IPC_INTPEND_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */ 6649 6650 /* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ 6651 #define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ 6652 #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ 6653 #define IPC_INTPEND_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */ 6654 #define IPC_INTPEND_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */ 6655 6656 /* Register: IPC_SEND_CNF */ 6657 /* Description: Description collection: Send event configuration for TASKS_SEND[n] */ 6658 6659 /* Bit 7 : Enable broadcasting on IPC channel 7 */ 6660 #define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */ 6661 #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */ 6662 #define IPC_SEND_CNF_CHEN7_Disable (0x0UL) /*!< Disable broadcast */ 6663 #define IPC_SEND_CNF_CHEN7_Enable (0x1UL) /*!< Enable broadcast */ 6664 6665 /* Bit 6 : Enable broadcasting on IPC channel 6 */ 6666 #define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */ 6667 #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */ 6668 #define IPC_SEND_CNF_CHEN6_Disable (0x0UL) /*!< Disable broadcast */ 6669 #define IPC_SEND_CNF_CHEN6_Enable (0x1UL) /*!< Enable broadcast */ 6670 6671 /* Bit 5 : Enable broadcasting on IPC channel 5 */ 6672 #define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */ 6673 #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */ 6674 #define IPC_SEND_CNF_CHEN5_Disable (0x0UL) /*!< Disable broadcast */ 6675 #define IPC_SEND_CNF_CHEN5_Enable (0x1UL) /*!< Enable broadcast */ 6676 6677 /* Bit 4 : Enable broadcasting on IPC channel 4 */ 6678 #define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */ 6679 #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */ 6680 #define IPC_SEND_CNF_CHEN4_Disable (0x0UL) /*!< Disable broadcast */ 6681 #define IPC_SEND_CNF_CHEN4_Enable (0x1UL) /*!< Enable broadcast */ 6682 6683 /* Bit 3 : Enable broadcasting on IPC channel 3 */ 6684 #define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */ 6685 #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ 6686 #define IPC_SEND_CNF_CHEN3_Disable (0x0UL) /*!< Disable broadcast */ 6687 #define IPC_SEND_CNF_CHEN3_Enable (0x1UL) /*!< Enable broadcast */ 6688 6689 /* Bit 2 : Enable broadcasting on IPC channel 2 */ 6690 #define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */ 6691 #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ 6692 #define IPC_SEND_CNF_CHEN2_Disable (0x0UL) /*!< Disable broadcast */ 6693 #define IPC_SEND_CNF_CHEN2_Enable (0x1UL) /*!< Enable broadcast */ 6694 6695 /* Bit 1 : Enable broadcasting on IPC channel 1 */ 6696 #define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */ 6697 #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ 6698 #define IPC_SEND_CNF_CHEN1_Disable (0x0UL) /*!< Disable broadcast */ 6699 #define IPC_SEND_CNF_CHEN1_Enable (0x1UL) /*!< Enable broadcast */ 6700 6701 /* Bit 0 : Enable broadcasting on IPC channel 0 */ 6702 #define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ 6703 #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ 6704 #define IPC_SEND_CNF_CHEN0_Disable (0x0UL) /*!< Disable broadcast */ 6705 #define IPC_SEND_CNF_CHEN0_Enable (0x1UL) /*!< Enable broadcast */ 6706 6707 /* Register: IPC_RECEIVE_CNF */ 6708 /* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */ 6709 6710 /* Bit 7 : Enable subscription to IPC channel 7 */ 6711 #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */ 6712 #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */ 6713 #define IPC_RECEIVE_CNF_CHEN7_Disable (0x0UL) /*!< Disable events */ 6714 #define IPC_RECEIVE_CNF_CHEN7_Enable (0x1UL) /*!< Enable events */ 6715 6716 /* Bit 6 : Enable subscription to IPC channel 6 */ 6717 #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */ 6718 #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */ 6719 #define IPC_RECEIVE_CNF_CHEN6_Disable (0x0UL) /*!< Disable events */ 6720 #define IPC_RECEIVE_CNF_CHEN6_Enable (0x1UL) /*!< Enable events */ 6721 6722 /* Bit 5 : Enable subscription to IPC channel 5 */ 6723 #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */ 6724 #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */ 6725 #define IPC_RECEIVE_CNF_CHEN5_Disable (0x0UL) /*!< Disable events */ 6726 #define IPC_RECEIVE_CNF_CHEN5_Enable (0x1UL) /*!< Enable events */ 6727 6728 /* Bit 4 : Enable subscription to IPC channel 4 */ 6729 #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */ 6730 #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */ 6731 #define IPC_RECEIVE_CNF_CHEN4_Disable (0x0UL) /*!< Disable events */ 6732 #define IPC_RECEIVE_CNF_CHEN4_Enable (0x1UL) /*!< Enable events */ 6733 6734 /* Bit 3 : Enable subscription to IPC channel 3 */ 6735 #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */ 6736 #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ 6737 #define IPC_RECEIVE_CNF_CHEN3_Disable (0x0UL) /*!< Disable events */ 6738 #define IPC_RECEIVE_CNF_CHEN3_Enable (0x1UL) /*!< Enable events */ 6739 6740 /* Bit 2 : Enable subscription to IPC channel 2 */ 6741 #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */ 6742 #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ 6743 #define IPC_RECEIVE_CNF_CHEN2_Disable (0x0UL) /*!< Disable events */ 6744 #define IPC_RECEIVE_CNF_CHEN2_Enable (0x1UL) /*!< Enable events */ 6745 6746 /* Bit 1 : Enable subscription to IPC channel 1 */ 6747 #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */ 6748 #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ 6749 #define IPC_RECEIVE_CNF_CHEN1_Disable (0x0UL) /*!< Disable events */ 6750 #define IPC_RECEIVE_CNF_CHEN1_Enable (0x1UL) /*!< Enable events */ 6751 6752 /* Bit 0 : Enable subscription to IPC channel 0 */ 6753 #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ 6754 #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ 6755 #define IPC_RECEIVE_CNF_CHEN0_Disable (0x0UL) /*!< Disable events */ 6756 #define IPC_RECEIVE_CNF_CHEN0_Enable (0x1UL) /*!< Enable events */ 6757 6758 /* Register: IPC_GPMEM */ 6759 /* Description: Description collection: General purpose memory */ 6760 6761 /* Bits 31..0 : General purpose memory */ 6762 #define IPC_GPMEM_GPMEM_Pos (0UL) /*!< Position of GPMEM field. */ 6763 #define IPC_GPMEM_GPMEM_Msk (0xFFFFFFFFUL << IPC_GPMEM_GPMEM_Pos) /*!< Bit mask of GPMEM field. */ 6764 6765 6766 /* Peripheral: KMU */ 6767 /* Description: Key management unit 0 */ 6768 6769 /* Register: KMU_TASKS_PUSH_KEYSLOT */ 6770 /* Description: Push a key slot over secure APB */ 6771 6772 /* Bit 0 : Push a key slot over secure APB */ 6773 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL) /*!< Position of TASKS_PUSH_KEYSLOT field. */ 6774 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos) /*!< Bit mask of TASKS_PUSH_KEYSLOT field. */ 6775 #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (0x1UL) /*!< Trigger task */ 6776 6777 /* Register: KMU_EVENTS_KEYSLOT_PUSHED */ 6778 /* Description: Key slot successfully pushed over secure APB */ 6779 6780 /* Bit 0 : Key slot successfully pushed over secure APB */ 6781 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */ 6782 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */ 6783 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0x0UL) /*!< Event not generated */ 6784 #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (0x1UL) /*!< Event generated */ 6785 6786 /* Register: KMU_EVENTS_KEYSLOT_REVOKED */ 6787 /* Description: Key slot has been revoked and cannot be tasked for selection */ 6788 6789 /* Bit 0 : Key slot has been revoked and cannot be tasked for selection */ 6790 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */ 6791 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */ 6792 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0x0UL) /*!< Event not generated */ 6793 #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (0x1UL) /*!< Event generated */ 6794 6795 /* Register: KMU_EVENTS_KEYSLOT_ERROR */ 6796 /* Description: No key slot selected, no destination address defined, or error during push operation */ 6797 6798 /* Bit 0 : No key slot selected, no destination address defined, or error during push operation */ 6799 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_ERROR field. */ 6800 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos) /*!< Bit mask of EVENTS_KEYSLOT_ERROR field. */ 6801 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ 6802 #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (0x1UL) /*!< Event generated */ 6803 6804 /* Register: KMU_INTEN */ 6805 /* Description: Enable or disable interrupt */ 6806 6807 /* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */ 6808 #define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ 6809 #define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ 6810 #define KMU_INTEN_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Disable */ 6811 #define KMU_INTEN_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Enable */ 6812 6813 /* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */ 6814 #define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ 6815 #define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ 6816 #define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Disable */ 6817 #define KMU_INTEN_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Enable */ 6818 6819 /* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */ 6820 #define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ 6821 #define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ 6822 #define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Disable */ 6823 #define KMU_INTEN_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Enable */ 6824 6825 /* Register: KMU_INTENSET */ 6826 /* Description: Enable interrupt */ 6827 6828 /* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */ 6829 #define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ 6830 #define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ 6831 #define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ 6832 #define KMU_INTENSET_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ 6833 #define KMU_INTENSET_KEYSLOT_ERROR_Set (0x1UL) /*!< Enable */ 6834 6835 /* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */ 6836 #define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ 6837 #define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ 6838 #define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Read: Disabled */ 6839 #define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Read: Enabled */ 6840 #define KMU_INTENSET_KEYSLOT_REVOKED_Set (0x1UL) /*!< Enable */ 6841 6842 /* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */ 6843 #define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ 6844 #define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ 6845 #define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Read: Disabled */ 6846 #define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Read: Enabled */ 6847 #define KMU_INTENSET_KEYSLOT_PUSHED_Set (0x1UL) /*!< Enable */ 6848 6849 /* Register: KMU_INTENCLR */ 6850 /* Description: Disable interrupt */ 6851 6852 /* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */ 6853 #define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ 6854 #define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ 6855 #define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ 6856 #define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ 6857 #define KMU_INTENCLR_KEYSLOT_ERROR_Clear (0x1UL) /*!< Disable */ 6858 6859 /* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */ 6860 #define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ 6861 #define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ 6862 #define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Read: Disabled */ 6863 #define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Read: Enabled */ 6864 #define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (0x1UL) /*!< Disable */ 6865 6866 /* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */ 6867 #define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ 6868 #define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ 6869 #define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Read: Disabled */ 6870 #define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Read: Enabled */ 6871 #define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (0x1UL) /*!< Disable */ 6872 6873 /* Register: KMU_INTPEND */ 6874 /* Description: Pending interrupts */ 6875 6876 /* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */ 6877 #define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ 6878 #define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ 6879 #define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0x0UL) /*!< Read: Not pending */ 6880 #define KMU_INTPEND_KEYSLOT_ERROR_Pending (0x1UL) /*!< Read: Pending */ 6881 6882 /* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */ 6883 #define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ 6884 #define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ 6885 #define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0x0UL) /*!< Read: Not pending */ 6886 #define KMU_INTPEND_KEYSLOT_REVOKED_Pending (0x1UL) /*!< Read: Pending */ 6887 6888 /* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */ 6889 #define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ 6890 #define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ 6891 #define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0x0UL) /*!< Read: Not pending */ 6892 #define KMU_INTPEND_KEYSLOT_PUSHED_Pending (0x1UL) /*!< Read: Pending */ 6893 6894 /* Register: KMU_STATUS */ 6895 /* Description: Status bits for KMU operation */ 6896 6897 /* Bit 1 : Violation status */ 6898 #define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */ 6899 #define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos) /*!< Bit mask of BLOCKED field. */ 6900 #define KMU_STATUS_BLOCKED_Disabled (0x0UL) /*!< No access violation detected */ 6901 #define KMU_STATUS_BLOCKED_Enabled (0x1UL) /*!< Access violation detected and blocked */ 6902 6903 /* Bit 0 : Key slot ID successfully selected by the KMU */ 6904 #define KMU_STATUS_SELECTED_Pos (0UL) /*!< Position of SELECTED field. */ 6905 #define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ 6906 #define KMU_STATUS_SELECTED_Disabled (0x0UL) /*!< No key slot ID selected by KMU */ 6907 #define KMU_STATUS_SELECTED_Enabled (0x1UL) /*!< Key slot ID successfully selected by KMU */ 6908 6909 /* Register: KMU_SELECTKEYSLOT */ 6910 /* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */ 6911 6912 /* Bits 7..0 : Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR->KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. */ 6913 #define KMU_SELECTKEYSLOT_ID_Pos (0UL) /*!< Position of ID field. */ 6914 #define KMU_SELECTKEYSLOT_ID_Msk (0xFFUL << KMU_SELECTKEYSLOT_ID_Pos) /*!< Bit mask of ID field. */ 6915 6916 6917 /* Peripheral: NVMC */ 6918 /* Description: Non-volatile memory controller 0 */ 6919 6920 /* Register: NVMC_READY */ 6921 /* Description: Ready flag */ 6922 6923 /* Bit 0 : NVMC is ready or busy */ 6924 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ 6925 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ 6926 #define NVMC_READY_READY_Busy (0x0UL) /*!< NVMC is busy (on-going write or erase operation) */ 6927 #define NVMC_READY_READY_Ready (0x1UL) /*!< NVMC is ready */ 6928 6929 /* Register: NVMC_READYNEXT */ 6930 /* Description: Ready flag */ 6931 6932 /* Bit 0 : NVMC can accept a new write operation */ 6933 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ 6934 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ 6935 #define NVMC_READYNEXT_READYNEXT_Busy (0x0UL) /*!< NVMC cannot accept any write operation */ 6936 #define NVMC_READYNEXT_READYNEXT_Ready (0x1UL) /*!< NVMC is ready */ 6937 6938 /* Register: NVMC_CONFIG */ 6939 /* Description: Configuration register */ 6940 6941 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ 6942 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ 6943 #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ 6944 #define NVMC_CONFIG_WEN_Ren (0x0UL) /*!< Read only access */ 6945 #define NVMC_CONFIG_WEN_Wen (0x1UL) /*!< Write enabled */ 6946 #define NVMC_CONFIG_WEN_Een (0x2UL) /*!< Erase enabled */ 6947 #define NVMC_CONFIG_WEN_PEen (0x4UL) /*!< Partial erase enabled */ 6948 6949 /* Register: NVMC_ERASEALL */ 6950 /* Description: Register for erasing all non-volatile user memory */ 6951 6952 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. */ 6953 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ 6954 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ 6955 #define NVMC_ERASEALL_ERASEALL_NoOperation (0x0UL) /*!< No operation */ 6956 #define NVMC_ERASEALL_ERASEALL_Erase (0x1UL) /*!< Start chip erase */ 6957 6958 /* Register: NVMC_ERASEPAGEPARTIALCFG */ 6959 /* Description: Register for partial erase configuration */ 6960 6961 /* Bits 6..0 : Duration of the partial erase in milliseconds */ 6962 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ 6963 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ 6964 6965 /* Register: NVMC_ICACHECNF */ 6966 /* Description: I-code cache configuration register */ 6967 6968 /* Bit 8 : Cache profiling enable */ 6969 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ 6970 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ 6971 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0x0UL) /*!< Disable cache profiling */ 6972 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (0x1UL) /*!< Enable cache profiling */ 6973 6974 /* Bit 0 : Cache enable */ 6975 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ 6976 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ 6977 #define NVMC_ICACHECNF_CACHEEN_Disabled (0x0UL) /*!< Disable cache. Invalidates all cache entries. */ 6978 #define NVMC_ICACHECNF_CACHEEN_Enabled (0x1UL) /*!< Enable cache */ 6979 6980 /* Register: NVMC_IHIT */ 6981 /* Description: I-code cache hit counter */ 6982 6983 /* Bits 31..0 : Number of cache hits Write zero to clear */ 6984 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ 6985 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ 6986 6987 /* Register: NVMC_IMISS */ 6988 /* Description: I-code cache miss counter */ 6989 6990 /* Bits 31..0 : Number of cache misses Write zero to clear */ 6991 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ 6992 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ 6993 6994 /* Register: NVMC_CONFIGNS */ 6995 /* Description: Unspecified */ 6996 6997 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ 6998 #define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */ 6999 #define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */ 7000 #define NVMC_CONFIGNS_WEN_Ren (0x0UL) /*!< Read only access */ 7001 #define NVMC_CONFIGNS_WEN_Wen (0x1UL) /*!< Write enabled */ 7002 #define NVMC_CONFIGNS_WEN_Een (0x2UL) /*!< Erase enabled */ 7003 7004 /* Register: NVMC_WRITEUICRNS */ 7005 /* Description: Non-secure APPROTECT enable register */ 7006 7007 /* Bits 31..4 : Key to write in order to validate the write operation */ 7008 #define NVMC_WRITEUICRNS_KEY_Pos (4UL) /*!< Position of KEY field. */ 7009 #define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos) /*!< Bit mask of KEY field. */ 7010 #define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL) /*!< Key value */ 7011 7012 /* Bit 0 : Allow non-secure code to set APPROTECT */ 7013 #define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */ 7014 #define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */ 7015 #define NVMC_WRITEUICRNS_SET_Set (0x1UL) /*!< Set value */ 7016 7017 7018 /* Peripheral: GPIO */ 7019 /* Description: GPIO Port 0 */ 7020 7021 /* Register: GPIO_OUT */ 7022 /* Description: Write GPIO port */ 7023 7024 /* Bit 31 : Pin 31 */ 7025 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 7026 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 7027 #define GPIO_OUT_PIN31_Low (0x0UL) /*!< Pin driver is low */ 7028 #define GPIO_OUT_PIN31_High (0x1UL) /*!< Pin driver is high */ 7029 7030 /* Bit 30 : Pin 30 */ 7031 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 7032 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 7033 #define GPIO_OUT_PIN30_Low (0x0UL) /*!< Pin driver is low */ 7034 #define GPIO_OUT_PIN30_High (0x1UL) /*!< Pin driver is high */ 7035 7036 /* Bit 29 : Pin 29 */ 7037 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 7038 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 7039 #define GPIO_OUT_PIN29_Low (0x0UL) /*!< Pin driver is low */ 7040 #define GPIO_OUT_PIN29_High (0x1UL) /*!< Pin driver is high */ 7041 7042 /* Bit 28 : Pin 28 */ 7043 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 7044 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 7045 #define GPIO_OUT_PIN28_Low (0x0UL) /*!< Pin driver is low */ 7046 #define GPIO_OUT_PIN28_High (0x1UL) /*!< Pin driver is high */ 7047 7048 /* Bit 27 : Pin 27 */ 7049 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 7050 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 7051 #define GPIO_OUT_PIN27_Low (0x0UL) /*!< Pin driver is low */ 7052 #define GPIO_OUT_PIN27_High (0x1UL) /*!< Pin driver is high */ 7053 7054 /* Bit 26 : Pin 26 */ 7055 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 7056 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 7057 #define GPIO_OUT_PIN26_Low (0x0UL) /*!< Pin driver is low */ 7058 #define GPIO_OUT_PIN26_High (0x1UL) /*!< Pin driver is high */ 7059 7060 /* Bit 25 : Pin 25 */ 7061 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 7062 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 7063 #define GPIO_OUT_PIN25_Low (0x0UL) /*!< Pin driver is low */ 7064 #define GPIO_OUT_PIN25_High (0x1UL) /*!< Pin driver is high */ 7065 7066 /* Bit 24 : Pin 24 */ 7067 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 7068 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 7069 #define GPIO_OUT_PIN24_Low (0x0UL) /*!< Pin driver is low */ 7070 #define GPIO_OUT_PIN24_High (0x1UL) /*!< Pin driver is high */ 7071 7072 /* Bit 23 : Pin 23 */ 7073 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 7074 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 7075 #define GPIO_OUT_PIN23_Low (0x0UL) /*!< Pin driver is low */ 7076 #define GPIO_OUT_PIN23_High (0x1UL) /*!< Pin driver is high */ 7077 7078 /* Bit 22 : Pin 22 */ 7079 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 7080 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 7081 #define GPIO_OUT_PIN22_Low (0x0UL) /*!< Pin driver is low */ 7082 #define GPIO_OUT_PIN22_High (0x1UL) /*!< Pin driver is high */ 7083 7084 /* Bit 21 : Pin 21 */ 7085 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 7086 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 7087 #define GPIO_OUT_PIN21_Low (0x0UL) /*!< Pin driver is low */ 7088 #define GPIO_OUT_PIN21_High (0x1UL) /*!< Pin driver is high */ 7089 7090 /* Bit 20 : Pin 20 */ 7091 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 7092 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 7093 #define GPIO_OUT_PIN20_Low (0x0UL) /*!< Pin driver is low */ 7094 #define GPIO_OUT_PIN20_High (0x1UL) /*!< Pin driver is high */ 7095 7096 /* Bit 19 : Pin 19 */ 7097 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 7098 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 7099 #define GPIO_OUT_PIN19_Low (0x0UL) /*!< Pin driver is low */ 7100 #define GPIO_OUT_PIN19_High (0x1UL) /*!< Pin driver is high */ 7101 7102 /* Bit 18 : Pin 18 */ 7103 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 7104 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 7105 #define GPIO_OUT_PIN18_Low (0x0UL) /*!< Pin driver is low */ 7106 #define GPIO_OUT_PIN18_High (0x1UL) /*!< Pin driver is high */ 7107 7108 /* Bit 17 : Pin 17 */ 7109 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 7110 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 7111 #define GPIO_OUT_PIN17_Low (0x0UL) /*!< Pin driver is low */ 7112 #define GPIO_OUT_PIN17_High (0x1UL) /*!< Pin driver is high */ 7113 7114 /* Bit 16 : Pin 16 */ 7115 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 7116 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 7117 #define GPIO_OUT_PIN16_Low (0x0UL) /*!< Pin driver is low */ 7118 #define GPIO_OUT_PIN16_High (0x1UL) /*!< Pin driver is high */ 7119 7120 /* Bit 15 : Pin 15 */ 7121 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 7122 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 7123 #define GPIO_OUT_PIN15_Low (0x0UL) /*!< Pin driver is low */ 7124 #define GPIO_OUT_PIN15_High (0x1UL) /*!< Pin driver is high */ 7125 7126 /* Bit 14 : Pin 14 */ 7127 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 7128 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 7129 #define GPIO_OUT_PIN14_Low (0x0UL) /*!< Pin driver is low */ 7130 #define GPIO_OUT_PIN14_High (0x1UL) /*!< Pin driver is high */ 7131 7132 /* Bit 13 : Pin 13 */ 7133 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 7134 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 7135 #define GPIO_OUT_PIN13_Low (0x0UL) /*!< Pin driver is low */ 7136 #define GPIO_OUT_PIN13_High (0x1UL) /*!< Pin driver is high */ 7137 7138 /* Bit 12 : Pin 12 */ 7139 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 7140 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 7141 #define GPIO_OUT_PIN12_Low (0x0UL) /*!< Pin driver is low */ 7142 #define GPIO_OUT_PIN12_High (0x1UL) /*!< Pin driver is high */ 7143 7144 /* Bit 11 : Pin 11 */ 7145 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 7146 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 7147 #define GPIO_OUT_PIN11_Low (0x0UL) /*!< Pin driver is low */ 7148 #define GPIO_OUT_PIN11_High (0x1UL) /*!< Pin driver is high */ 7149 7150 /* Bit 10 : Pin 10 */ 7151 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 7152 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 7153 #define GPIO_OUT_PIN10_Low (0x0UL) /*!< Pin driver is low */ 7154 #define GPIO_OUT_PIN10_High (0x1UL) /*!< Pin driver is high */ 7155 7156 /* Bit 9 : Pin 9 */ 7157 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 7158 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 7159 #define GPIO_OUT_PIN9_Low (0x0UL) /*!< Pin driver is low */ 7160 #define GPIO_OUT_PIN9_High (0x1UL) /*!< Pin driver is high */ 7161 7162 /* Bit 8 : Pin 8 */ 7163 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 7164 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 7165 #define GPIO_OUT_PIN8_Low (0x0UL) /*!< Pin driver is low */ 7166 #define GPIO_OUT_PIN8_High (0x1UL) /*!< Pin driver is high */ 7167 7168 /* Bit 7 : Pin 7 */ 7169 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 7170 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 7171 #define GPIO_OUT_PIN7_Low (0x0UL) /*!< Pin driver is low */ 7172 #define GPIO_OUT_PIN7_High (0x1UL) /*!< Pin driver is high */ 7173 7174 /* Bit 6 : Pin 6 */ 7175 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 7176 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 7177 #define GPIO_OUT_PIN6_Low (0x0UL) /*!< Pin driver is low */ 7178 #define GPIO_OUT_PIN6_High (0x1UL) /*!< Pin driver is high */ 7179 7180 /* Bit 5 : Pin 5 */ 7181 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 7182 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 7183 #define GPIO_OUT_PIN5_Low (0x0UL) /*!< Pin driver is low */ 7184 #define GPIO_OUT_PIN5_High (0x1UL) /*!< Pin driver is high */ 7185 7186 /* Bit 4 : Pin 4 */ 7187 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 7188 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 7189 #define GPIO_OUT_PIN4_Low (0x0UL) /*!< Pin driver is low */ 7190 #define GPIO_OUT_PIN4_High (0x1UL) /*!< Pin driver is high */ 7191 7192 /* Bit 3 : Pin 3 */ 7193 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 7194 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 7195 #define GPIO_OUT_PIN3_Low (0x0UL) /*!< Pin driver is low */ 7196 #define GPIO_OUT_PIN3_High (0x1UL) /*!< Pin driver is high */ 7197 7198 /* Bit 2 : Pin 2 */ 7199 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 7200 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 7201 #define GPIO_OUT_PIN2_Low (0x0UL) /*!< Pin driver is low */ 7202 #define GPIO_OUT_PIN2_High (0x1UL) /*!< Pin driver is high */ 7203 7204 /* Bit 1 : Pin 1 */ 7205 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 7206 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 7207 #define GPIO_OUT_PIN1_Low (0x0UL) /*!< Pin driver is low */ 7208 #define GPIO_OUT_PIN1_High (0x1UL) /*!< Pin driver is high */ 7209 7210 /* Bit 0 : Pin 0 */ 7211 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 7212 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 7213 #define GPIO_OUT_PIN0_Low (0x0UL) /*!< Pin driver is low */ 7214 #define GPIO_OUT_PIN0_High (0x1UL) /*!< Pin driver is high */ 7215 7216 /* Register: GPIO_OUTSET */ 7217 /* Description: Set individual bits in GPIO port */ 7218 7219 /* Bit 31 : Pin 31 */ 7220 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 7221 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 7222 #define GPIO_OUTSET_PIN31_Low (0x0UL) /*!< Read: pin driver is low */ 7223 #define GPIO_OUTSET_PIN31_High (0x1UL) /*!< Read: pin driver is high */ 7224 #define GPIO_OUTSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7225 7226 /* Bit 30 : Pin 30 */ 7227 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 7228 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 7229 #define GPIO_OUTSET_PIN30_Low (0x0UL) /*!< Read: pin driver is low */ 7230 #define GPIO_OUTSET_PIN30_High (0x1UL) /*!< Read: pin driver is high */ 7231 #define GPIO_OUTSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7232 7233 /* Bit 29 : Pin 29 */ 7234 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 7235 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 7236 #define GPIO_OUTSET_PIN29_Low (0x0UL) /*!< Read: pin driver is low */ 7237 #define GPIO_OUTSET_PIN29_High (0x1UL) /*!< Read: pin driver is high */ 7238 #define GPIO_OUTSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7239 7240 /* Bit 28 : Pin 28 */ 7241 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 7242 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 7243 #define GPIO_OUTSET_PIN28_Low (0x0UL) /*!< Read: pin driver is low */ 7244 #define GPIO_OUTSET_PIN28_High (0x1UL) /*!< Read: pin driver is high */ 7245 #define GPIO_OUTSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7246 7247 /* Bit 27 : Pin 27 */ 7248 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 7249 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 7250 #define GPIO_OUTSET_PIN27_Low (0x0UL) /*!< Read: pin driver is low */ 7251 #define GPIO_OUTSET_PIN27_High (0x1UL) /*!< Read: pin driver is high */ 7252 #define GPIO_OUTSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7253 7254 /* Bit 26 : Pin 26 */ 7255 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 7256 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 7257 #define GPIO_OUTSET_PIN26_Low (0x0UL) /*!< Read: pin driver is low */ 7258 #define GPIO_OUTSET_PIN26_High (0x1UL) /*!< Read: pin driver is high */ 7259 #define GPIO_OUTSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7260 7261 /* Bit 25 : Pin 25 */ 7262 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 7263 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 7264 #define GPIO_OUTSET_PIN25_Low (0x0UL) /*!< Read: pin driver is low */ 7265 #define GPIO_OUTSET_PIN25_High (0x1UL) /*!< Read: pin driver is high */ 7266 #define GPIO_OUTSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7267 7268 /* Bit 24 : Pin 24 */ 7269 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 7270 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 7271 #define GPIO_OUTSET_PIN24_Low (0x0UL) /*!< Read: pin driver is low */ 7272 #define GPIO_OUTSET_PIN24_High (0x1UL) /*!< Read: pin driver is high */ 7273 #define GPIO_OUTSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7274 7275 /* Bit 23 : Pin 23 */ 7276 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 7277 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 7278 #define GPIO_OUTSET_PIN23_Low (0x0UL) /*!< Read: pin driver is low */ 7279 #define GPIO_OUTSET_PIN23_High (0x1UL) /*!< Read: pin driver is high */ 7280 #define GPIO_OUTSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7281 7282 /* Bit 22 : Pin 22 */ 7283 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 7284 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 7285 #define GPIO_OUTSET_PIN22_Low (0x0UL) /*!< Read: pin driver is low */ 7286 #define GPIO_OUTSET_PIN22_High (0x1UL) /*!< Read: pin driver is high */ 7287 #define GPIO_OUTSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7288 7289 /* Bit 21 : Pin 21 */ 7290 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 7291 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 7292 #define GPIO_OUTSET_PIN21_Low (0x0UL) /*!< Read: pin driver is low */ 7293 #define GPIO_OUTSET_PIN21_High (0x1UL) /*!< Read: pin driver is high */ 7294 #define GPIO_OUTSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7295 7296 /* Bit 20 : Pin 20 */ 7297 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 7298 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 7299 #define GPIO_OUTSET_PIN20_Low (0x0UL) /*!< Read: pin driver is low */ 7300 #define GPIO_OUTSET_PIN20_High (0x1UL) /*!< Read: pin driver is high */ 7301 #define GPIO_OUTSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7302 7303 /* Bit 19 : Pin 19 */ 7304 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 7305 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 7306 #define GPIO_OUTSET_PIN19_Low (0x0UL) /*!< Read: pin driver is low */ 7307 #define GPIO_OUTSET_PIN19_High (0x1UL) /*!< Read: pin driver is high */ 7308 #define GPIO_OUTSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7309 7310 /* Bit 18 : Pin 18 */ 7311 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 7312 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 7313 #define GPIO_OUTSET_PIN18_Low (0x0UL) /*!< Read: pin driver is low */ 7314 #define GPIO_OUTSET_PIN18_High (0x1UL) /*!< Read: pin driver is high */ 7315 #define GPIO_OUTSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7316 7317 /* Bit 17 : Pin 17 */ 7318 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 7319 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 7320 #define GPIO_OUTSET_PIN17_Low (0x0UL) /*!< Read: pin driver is low */ 7321 #define GPIO_OUTSET_PIN17_High (0x1UL) /*!< Read: pin driver is high */ 7322 #define GPIO_OUTSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7323 7324 /* Bit 16 : Pin 16 */ 7325 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 7326 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 7327 #define GPIO_OUTSET_PIN16_Low (0x0UL) /*!< Read: pin driver is low */ 7328 #define GPIO_OUTSET_PIN16_High (0x1UL) /*!< Read: pin driver is high */ 7329 #define GPIO_OUTSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7330 7331 /* Bit 15 : Pin 15 */ 7332 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 7333 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 7334 #define GPIO_OUTSET_PIN15_Low (0x0UL) /*!< Read: pin driver is low */ 7335 #define GPIO_OUTSET_PIN15_High (0x1UL) /*!< Read: pin driver is high */ 7336 #define GPIO_OUTSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7337 7338 /* Bit 14 : Pin 14 */ 7339 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 7340 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 7341 #define GPIO_OUTSET_PIN14_Low (0x0UL) /*!< Read: pin driver is low */ 7342 #define GPIO_OUTSET_PIN14_High (0x1UL) /*!< Read: pin driver is high */ 7343 #define GPIO_OUTSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7344 7345 /* Bit 13 : Pin 13 */ 7346 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 7347 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 7348 #define GPIO_OUTSET_PIN13_Low (0x0UL) /*!< Read: pin driver is low */ 7349 #define GPIO_OUTSET_PIN13_High (0x1UL) /*!< Read: pin driver is high */ 7350 #define GPIO_OUTSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7351 7352 /* Bit 12 : Pin 12 */ 7353 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 7354 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 7355 #define GPIO_OUTSET_PIN12_Low (0x0UL) /*!< Read: pin driver is low */ 7356 #define GPIO_OUTSET_PIN12_High (0x1UL) /*!< Read: pin driver is high */ 7357 #define GPIO_OUTSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7358 7359 /* Bit 11 : Pin 11 */ 7360 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 7361 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 7362 #define GPIO_OUTSET_PIN11_Low (0x0UL) /*!< Read: pin driver is low */ 7363 #define GPIO_OUTSET_PIN11_High (0x1UL) /*!< Read: pin driver is high */ 7364 #define GPIO_OUTSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7365 7366 /* Bit 10 : Pin 10 */ 7367 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 7368 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 7369 #define GPIO_OUTSET_PIN10_Low (0x0UL) /*!< Read: pin driver is low */ 7370 #define GPIO_OUTSET_PIN10_High (0x1UL) /*!< Read: pin driver is high */ 7371 #define GPIO_OUTSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7372 7373 /* Bit 9 : Pin 9 */ 7374 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 7375 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 7376 #define GPIO_OUTSET_PIN9_Low (0x0UL) /*!< Read: pin driver is low */ 7377 #define GPIO_OUTSET_PIN9_High (0x1UL) /*!< Read: pin driver is high */ 7378 #define GPIO_OUTSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7379 7380 /* Bit 8 : Pin 8 */ 7381 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 7382 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 7383 #define GPIO_OUTSET_PIN8_Low (0x0UL) /*!< Read: pin driver is low */ 7384 #define GPIO_OUTSET_PIN8_High (0x1UL) /*!< Read: pin driver is high */ 7385 #define GPIO_OUTSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7386 7387 /* Bit 7 : Pin 7 */ 7388 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 7389 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 7390 #define GPIO_OUTSET_PIN7_Low (0x0UL) /*!< Read: pin driver is low */ 7391 #define GPIO_OUTSET_PIN7_High (0x1UL) /*!< Read: pin driver is high */ 7392 #define GPIO_OUTSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7393 7394 /* Bit 6 : Pin 6 */ 7395 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 7396 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 7397 #define GPIO_OUTSET_PIN6_Low (0x0UL) /*!< Read: pin driver is low */ 7398 #define GPIO_OUTSET_PIN6_High (0x1UL) /*!< Read: pin driver is high */ 7399 #define GPIO_OUTSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7400 7401 /* Bit 5 : Pin 5 */ 7402 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 7403 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 7404 #define GPIO_OUTSET_PIN5_Low (0x0UL) /*!< Read: pin driver is low */ 7405 #define GPIO_OUTSET_PIN5_High (0x1UL) /*!< Read: pin driver is high */ 7406 #define GPIO_OUTSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7407 7408 /* Bit 4 : Pin 4 */ 7409 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 7410 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 7411 #define GPIO_OUTSET_PIN4_Low (0x0UL) /*!< Read: pin driver is low */ 7412 #define GPIO_OUTSET_PIN4_High (0x1UL) /*!< Read: pin driver is high */ 7413 #define GPIO_OUTSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7414 7415 /* Bit 3 : Pin 3 */ 7416 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 7417 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 7418 #define GPIO_OUTSET_PIN3_Low (0x0UL) /*!< Read: pin driver is low */ 7419 #define GPIO_OUTSET_PIN3_High (0x1UL) /*!< Read: pin driver is high */ 7420 #define GPIO_OUTSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7421 7422 /* Bit 2 : Pin 2 */ 7423 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 7424 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 7425 #define GPIO_OUTSET_PIN2_Low (0x0UL) /*!< Read: pin driver is low */ 7426 #define GPIO_OUTSET_PIN2_High (0x1UL) /*!< Read: pin driver is high */ 7427 #define GPIO_OUTSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7428 7429 /* Bit 1 : Pin 1 */ 7430 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 7431 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 7432 #define GPIO_OUTSET_PIN1_Low (0x0UL) /*!< Read: pin driver is low */ 7433 #define GPIO_OUTSET_PIN1_High (0x1UL) /*!< Read: pin driver is high */ 7434 #define GPIO_OUTSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7435 7436 /* Bit 0 : Pin 0 */ 7437 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 7438 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 7439 #define GPIO_OUTSET_PIN0_Low (0x0UL) /*!< Read: pin driver is low */ 7440 #define GPIO_OUTSET_PIN0_High (0x1UL) /*!< Read: pin driver is high */ 7441 #define GPIO_OUTSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 7442 7443 /* Register: GPIO_OUTCLR */ 7444 /* Description: Clear individual bits in GPIO port */ 7445 7446 /* Bit 31 : Pin 31 */ 7447 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 7448 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 7449 #define GPIO_OUTCLR_PIN31_Low (0x0UL) /*!< Read: pin driver is low */ 7450 #define GPIO_OUTCLR_PIN31_High (0x1UL) /*!< Read: pin driver is high */ 7451 #define GPIO_OUTCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7452 7453 /* Bit 30 : Pin 30 */ 7454 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 7455 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 7456 #define GPIO_OUTCLR_PIN30_Low (0x0UL) /*!< Read: pin driver is low */ 7457 #define GPIO_OUTCLR_PIN30_High (0x1UL) /*!< Read: pin driver is high */ 7458 #define GPIO_OUTCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7459 7460 /* Bit 29 : Pin 29 */ 7461 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 7462 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 7463 #define GPIO_OUTCLR_PIN29_Low (0x0UL) /*!< Read: pin driver is low */ 7464 #define GPIO_OUTCLR_PIN29_High (0x1UL) /*!< Read: pin driver is high */ 7465 #define GPIO_OUTCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7466 7467 /* Bit 28 : Pin 28 */ 7468 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 7469 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 7470 #define GPIO_OUTCLR_PIN28_Low (0x0UL) /*!< Read: pin driver is low */ 7471 #define GPIO_OUTCLR_PIN28_High (0x1UL) /*!< Read: pin driver is high */ 7472 #define GPIO_OUTCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7473 7474 /* Bit 27 : Pin 27 */ 7475 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 7476 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 7477 #define GPIO_OUTCLR_PIN27_Low (0x0UL) /*!< Read: pin driver is low */ 7478 #define GPIO_OUTCLR_PIN27_High (0x1UL) /*!< Read: pin driver is high */ 7479 #define GPIO_OUTCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7480 7481 /* Bit 26 : Pin 26 */ 7482 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 7483 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 7484 #define GPIO_OUTCLR_PIN26_Low (0x0UL) /*!< Read: pin driver is low */ 7485 #define GPIO_OUTCLR_PIN26_High (0x1UL) /*!< Read: pin driver is high */ 7486 #define GPIO_OUTCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7487 7488 /* Bit 25 : Pin 25 */ 7489 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 7490 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 7491 #define GPIO_OUTCLR_PIN25_Low (0x0UL) /*!< Read: pin driver is low */ 7492 #define GPIO_OUTCLR_PIN25_High (0x1UL) /*!< Read: pin driver is high */ 7493 #define GPIO_OUTCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7494 7495 /* Bit 24 : Pin 24 */ 7496 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 7497 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 7498 #define GPIO_OUTCLR_PIN24_Low (0x0UL) /*!< Read: pin driver is low */ 7499 #define GPIO_OUTCLR_PIN24_High (0x1UL) /*!< Read: pin driver is high */ 7500 #define GPIO_OUTCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7501 7502 /* Bit 23 : Pin 23 */ 7503 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 7504 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 7505 #define GPIO_OUTCLR_PIN23_Low (0x0UL) /*!< Read: pin driver is low */ 7506 #define GPIO_OUTCLR_PIN23_High (0x1UL) /*!< Read: pin driver is high */ 7507 #define GPIO_OUTCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7508 7509 /* Bit 22 : Pin 22 */ 7510 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 7511 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 7512 #define GPIO_OUTCLR_PIN22_Low (0x0UL) /*!< Read: pin driver is low */ 7513 #define GPIO_OUTCLR_PIN22_High (0x1UL) /*!< Read: pin driver is high */ 7514 #define GPIO_OUTCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7515 7516 /* Bit 21 : Pin 21 */ 7517 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 7518 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 7519 #define GPIO_OUTCLR_PIN21_Low (0x0UL) /*!< Read: pin driver is low */ 7520 #define GPIO_OUTCLR_PIN21_High (0x1UL) /*!< Read: pin driver is high */ 7521 #define GPIO_OUTCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7522 7523 /* Bit 20 : Pin 20 */ 7524 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 7525 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 7526 #define GPIO_OUTCLR_PIN20_Low (0x0UL) /*!< Read: pin driver is low */ 7527 #define GPIO_OUTCLR_PIN20_High (0x1UL) /*!< Read: pin driver is high */ 7528 #define GPIO_OUTCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7529 7530 /* Bit 19 : Pin 19 */ 7531 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 7532 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 7533 #define GPIO_OUTCLR_PIN19_Low (0x0UL) /*!< Read: pin driver is low */ 7534 #define GPIO_OUTCLR_PIN19_High (0x1UL) /*!< Read: pin driver is high */ 7535 #define GPIO_OUTCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7536 7537 /* Bit 18 : Pin 18 */ 7538 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 7539 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 7540 #define GPIO_OUTCLR_PIN18_Low (0x0UL) /*!< Read: pin driver is low */ 7541 #define GPIO_OUTCLR_PIN18_High (0x1UL) /*!< Read: pin driver is high */ 7542 #define GPIO_OUTCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7543 7544 /* Bit 17 : Pin 17 */ 7545 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 7546 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 7547 #define GPIO_OUTCLR_PIN17_Low (0x0UL) /*!< Read: pin driver is low */ 7548 #define GPIO_OUTCLR_PIN17_High (0x1UL) /*!< Read: pin driver is high */ 7549 #define GPIO_OUTCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7550 7551 /* Bit 16 : Pin 16 */ 7552 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 7553 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 7554 #define GPIO_OUTCLR_PIN16_Low (0x0UL) /*!< Read: pin driver is low */ 7555 #define GPIO_OUTCLR_PIN16_High (0x1UL) /*!< Read: pin driver is high */ 7556 #define GPIO_OUTCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7557 7558 /* Bit 15 : Pin 15 */ 7559 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 7560 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 7561 #define GPIO_OUTCLR_PIN15_Low (0x0UL) /*!< Read: pin driver is low */ 7562 #define GPIO_OUTCLR_PIN15_High (0x1UL) /*!< Read: pin driver is high */ 7563 #define GPIO_OUTCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7564 7565 /* Bit 14 : Pin 14 */ 7566 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 7567 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 7568 #define GPIO_OUTCLR_PIN14_Low (0x0UL) /*!< Read: pin driver is low */ 7569 #define GPIO_OUTCLR_PIN14_High (0x1UL) /*!< Read: pin driver is high */ 7570 #define GPIO_OUTCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7571 7572 /* Bit 13 : Pin 13 */ 7573 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 7574 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 7575 #define GPIO_OUTCLR_PIN13_Low (0x0UL) /*!< Read: pin driver is low */ 7576 #define GPIO_OUTCLR_PIN13_High (0x1UL) /*!< Read: pin driver is high */ 7577 #define GPIO_OUTCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7578 7579 /* Bit 12 : Pin 12 */ 7580 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 7581 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 7582 #define GPIO_OUTCLR_PIN12_Low (0x0UL) /*!< Read: pin driver is low */ 7583 #define GPIO_OUTCLR_PIN12_High (0x1UL) /*!< Read: pin driver is high */ 7584 #define GPIO_OUTCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7585 7586 /* Bit 11 : Pin 11 */ 7587 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 7588 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 7589 #define GPIO_OUTCLR_PIN11_Low (0x0UL) /*!< Read: pin driver is low */ 7590 #define GPIO_OUTCLR_PIN11_High (0x1UL) /*!< Read: pin driver is high */ 7591 #define GPIO_OUTCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7592 7593 /* Bit 10 : Pin 10 */ 7594 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 7595 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 7596 #define GPIO_OUTCLR_PIN10_Low (0x0UL) /*!< Read: pin driver is low */ 7597 #define GPIO_OUTCLR_PIN10_High (0x1UL) /*!< Read: pin driver is high */ 7598 #define GPIO_OUTCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7599 7600 /* Bit 9 : Pin 9 */ 7601 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 7602 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 7603 #define GPIO_OUTCLR_PIN9_Low (0x0UL) /*!< Read: pin driver is low */ 7604 #define GPIO_OUTCLR_PIN9_High (0x1UL) /*!< Read: pin driver is high */ 7605 #define GPIO_OUTCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7606 7607 /* Bit 8 : Pin 8 */ 7608 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 7609 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 7610 #define GPIO_OUTCLR_PIN8_Low (0x0UL) /*!< Read: pin driver is low */ 7611 #define GPIO_OUTCLR_PIN8_High (0x1UL) /*!< Read: pin driver is high */ 7612 #define GPIO_OUTCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7613 7614 /* Bit 7 : Pin 7 */ 7615 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 7616 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 7617 #define GPIO_OUTCLR_PIN7_Low (0x0UL) /*!< Read: pin driver is low */ 7618 #define GPIO_OUTCLR_PIN7_High (0x1UL) /*!< Read: pin driver is high */ 7619 #define GPIO_OUTCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7620 7621 /* Bit 6 : Pin 6 */ 7622 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 7623 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 7624 #define GPIO_OUTCLR_PIN6_Low (0x0UL) /*!< Read: pin driver is low */ 7625 #define GPIO_OUTCLR_PIN6_High (0x1UL) /*!< Read: pin driver is high */ 7626 #define GPIO_OUTCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7627 7628 /* Bit 5 : Pin 5 */ 7629 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 7630 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 7631 #define GPIO_OUTCLR_PIN5_Low (0x0UL) /*!< Read: pin driver is low */ 7632 #define GPIO_OUTCLR_PIN5_High (0x1UL) /*!< Read: pin driver is high */ 7633 #define GPIO_OUTCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7634 7635 /* Bit 4 : Pin 4 */ 7636 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 7637 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 7638 #define GPIO_OUTCLR_PIN4_Low (0x0UL) /*!< Read: pin driver is low */ 7639 #define GPIO_OUTCLR_PIN4_High (0x1UL) /*!< Read: pin driver is high */ 7640 #define GPIO_OUTCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7641 7642 /* Bit 3 : Pin 3 */ 7643 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 7644 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 7645 #define GPIO_OUTCLR_PIN3_Low (0x0UL) /*!< Read: pin driver is low */ 7646 #define GPIO_OUTCLR_PIN3_High (0x1UL) /*!< Read: pin driver is high */ 7647 #define GPIO_OUTCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7648 7649 /* Bit 2 : Pin 2 */ 7650 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 7651 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 7652 #define GPIO_OUTCLR_PIN2_Low (0x0UL) /*!< Read: pin driver is low */ 7653 #define GPIO_OUTCLR_PIN2_High (0x1UL) /*!< Read: pin driver is high */ 7654 #define GPIO_OUTCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7655 7656 /* Bit 1 : Pin 1 */ 7657 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 7658 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 7659 #define GPIO_OUTCLR_PIN1_Low (0x0UL) /*!< Read: pin driver is low */ 7660 #define GPIO_OUTCLR_PIN1_High (0x1UL) /*!< Read: pin driver is high */ 7661 #define GPIO_OUTCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7662 7663 /* Bit 0 : Pin 0 */ 7664 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 7665 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 7666 #define GPIO_OUTCLR_PIN0_Low (0x0UL) /*!< Read: pin driver is low */ 7667 #define GPIO_OUTCLR_PIN0_High (0x1UL) /*!< Read: pin driver is high */ 7668 #define GPIO_OUTCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 7669 7670 /* Register: GPIO_IN */ 7671 /* Description: Read GPIO port */ 7672 7673 /* Bit 31 : Pin 31 */ 7674 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 7675 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 7676 #define GPIO_IN_PIN31_Low (0x0UL) /*!< Pin input is low */ 7677 #define GPIO_IN_PIN31_High (0x1UL) /*!< Pin input is high */ 7678 7679 /* Bit 30 : Pin 30 */ 7680 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 7681 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 7682 #define GPIO_IN_PIN30_Low (0x0UL) /*!< Pin input is low */ 7683 #define GPIO_IN_PIN30_High (0x1UL) /*!< Pin input is high */ 7684 7685 /* Bit 29 : Pin 29 */ 7686 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 7687 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 7688 #define GPIO_IN_PIN29_Low (0x0UL) /*!< Pin input is low */ 7689 #define GPIO_IN_PIN29_High (0x1UL) /*!< Pin input is high */ 7690 7691 /* Bit 28 : Pin 28 */ 7692 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 7693 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 7694 #define GPIO_IN_PIN28_Low (0x0UL) /*!< Pin input is low */ 7695 #define GPIO_IN_PIN28_High (0x1UL) /*!< Pin input is high */ 7696 7697 /* Bit 27 : Pin 27 */ 7698 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 7699 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 7700 #define GPIO_IN_PIN27_Low (0x0UL) /*!< Pin input is low */ 7701 #define GPIO_IN_PIN27_High (0x1UL) /*!< Pin input is high */ 7702 7703 /* Bit 26 : Pin 26 */ 7704 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 7705 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 7706 #define GPIO_IN_PIN26_Low (0x0UL) /*!< Pin input is low */ 7707 #define GPIO_IN_PIN26_High (0x1UL) /*!< Pin input is high */ 7708 7709 /* Bit 25 : Pin 25 */ 7710 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 7711 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 7712 #define GPIO_IN_PIN25_Low (0x0UL) /*!< Pin input is low */ 7713 #define GPIO_IN_PIN25_High (0x1UL) /*!< Pin input is high */ 7714 7715 /* Bit 24 : Pin 24 */ 7716 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 7717 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 7718 #define GPIO_IN_PIN24_Low (0x0UL) /*!< Pin input is low */ 7719 #define GPIO_IN_PIN24_High (0x1UL) /*!< Pin input is high */ 7720 7721 /* Bit 23 : Pin 23 */ 7722 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 7723 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 7724 #define GPIO_IN_PIN23_Low (0x0UL) /*!< Pin input is low */ 7725 #define GPIO_IN_PIN23_High (0x1UL) /*!< Pin input is high */ 7726 7727 /* Bit 22 : Pin 22 */ 7728 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 7729 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 7730 #define GPIO_IN_PIN22_Low (0x0UL) /*!< Pin input is low */ 7731 #define GPIO_IN_PIN22_High (0x1UL) /*!< Pin input is high */ 7732 7733 /* Bit 21 : Pin 21 */ 7734 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 7735 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 7736 #define GPIO_IN_PIN21_Low (0x0UL) /*!< Pin input is low */ 7737 #define GPIO_IN_PIN21_High (0x1UL) /*!< Pin input is high */ 7738 7739 /* Bit 20 : Pin 20 */ 7740 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 7741 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 7742 #define GPIO_IN_PIN20_Low (0x0UL) /*!< Pin input is low */ 7743 #define GPIO_IN_PIN20_High (0x1UL) /*!< Pin input is high */ 7744 7745 /* Bit 19 : Pin 19 */ 7746 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 7747 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 7748 #define GPIO_IN_PIN19_Low (0x0UL) /*!< Pin input is low */ 7749 #define GPIO_IN_PIN19_High (0x1UL) /*!< Pin input is high */ 7750 7751 /* Bit 18 : Pin 18 */ 7752 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 7753 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 7754 #define GPIO_IN_PIN18_Low (0x0UL) /*!< Pin input is low */ 7755 #define GPIO_IN_PIN18_High (0x1UL) /*!< Pin input is high */ 7756 7757 /* Bit 17 : Pin 17 */ 7758 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 7759 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 7760 #define GPIO_IN_PIN17_Low (0x0UL) /*!< Pin input is low */ 7761 #define GPIO_IN_PIN17_High (0x1UL) /*!< Pin input is high */ 7762 7763 /* Bit 16 : Pin 16 */ 7764 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 7765 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 7766 #define GPIO_IN_PIN16_Low (0x0UL) /*!< Pin input is low */ 7767 #define GPIO_IN_PIN16_High (0x1UL) /*!< Pin input is high */ 7768 7769 /* Bit 15 : Pin 15 */ 7770 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 7771 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 7772 #define GPIO_IN_PIN15_Low (0x0UL) /*!< Pin input is low */ 7773 #define GPIO_IN_PIN15_High (0x1UL) /*!< Pin input is high */ 7774 7775 /* Bit 14 : Pin 14 */ 7776 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 7777 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 7778 #define GPIO_IN_PIN14_Low (0x0UL) /*!< Pin input is low */ 7779 #define GPIO_IN_PIN14_High (0x1UL) /*!< Pin input is high */ 7780 7781 /* Bit 13 : Pin 13 */ 7782 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 7783 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 7784 #define GPIO_IN_PIN13_Low (0x0UL) /*!< Pin input is low */ 7785 #define GPIO_IN_PIN13_High (0x1UL) /*!< Pin input is high */ 7786 7787 /* Bit 12 : Pin 12 */ 7788 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 7789 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 7790 #define GPIO_IN_PIN12_Low (0x0UL) /*!< Pin input is low */ 7791 #define GPIO_IN_PIN12_High (0x1UL) /*!< Pin input is high */ 7792 7793 /* Bit 11 : Pin 11 */ 7794 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 7795 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 7796 #define GPIO_IN_PIN11_Low (0x0UL) /*!< Pin input is low */ 7797 #define GPIO_IN_PIN11_High (0x1UL) /*!< Pin input is high */ 7798 7799 /* Bit 10 : Pin 10 */ 7800 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 7801 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 7802 #define GPIO_IN_PIN10_Low (0x0UL) /*!< Pin input is low */ 7803 #define GPIO_IN_PIN10_High (0x1UL) /*!< Pin input is high */ 7804 7805 /* Bit 9 : Pin 9 */ 7806 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 7807 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 7808 #define GPIO_IN_PIN9_Low (0x0UL) /*!< Pin input is low */ 7809 #define GPIO_IN_PIN9_High (0x1UL) /*!< Pin input is high */ 7810 7811 /* Bit 8 : Pin 8 */ 7812 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 7813 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 7814 #define GPIO_IN_PIN8_Low (0x0UL) /*!< Pin input is low */ 7815 #define GPIO_IN_PIN8_High (0x1UL) /*!< Pin input is high */ 7816 7817 /* Bit 7 : Pin 7 */ 7818 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 7819 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 7820 #define GPIO_IN_PIN7_Low (0x0UL) /*!< Pin input is low */ 7821 #define GPIO_IN_PIN7_High (0x1UL) /*!< Pin input is high */ 7822 7823 /* Bit 6 : Pin 6 */ 7824 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 7825 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 7826 #define GPIO_IN_PIN6_Low (0x0UL) /*!< Pin input is low */ 7827 #define GPIO_IN_PIN6_High (0x1UL) /*!< Pin input is high */ 7828 7829 /* Bit 5 : Pin 5 */ 7830 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 7831 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 7832 #define GPIO_IN_PIN5_Low (0x0UL) /*!< Pin input is low */ 7833 #define GPIO_IN_PIN5_High (0x1UL) /*!< Pin input is high */ 7834 7835 /* Bit 4 : Pin 4 */ 7836 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 7837 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 7838 #define GPIO_IN_PIN4_Low (0x0UL) /*!< Pin input is low */ 7839 #define GPIO_IN_PIN4_High (0x1UL) /*!< Pin input is high */ 7840 7841 /* Bit 3 : Pin 3 */ 7842 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 7843 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 7844 #define GPIO_IN_PIN3_Low (0x0UL) /*!< Pin input is low */ 7845 #define GPIO_IN_PIN3_High (0x1UL) /*!< Pin input is high */ 7846 7847 /* Bit 2 : Pin 2 */ 7848 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 7849 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 7850 #define GPIO_IN_PIN2_Low (0x0UL) /*!< Pin input is low */ 7851 #define GPIO_IN_PIN2_High (0x1UL) /*!< Pin input is high */ 7852 7853 /* Bit 1 : Pin 1 */ 7854 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 7855 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 7856 #define GPIO_IN_PIN1_Low (0x0UL) /*!< Pin input is low */ 7857 #define GPIO_IN_PIN1_High (0x1UL) /*!< Pin input is high */ 7858 7859 /* Bit 0 : Pin 0 */ 7860 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 7861 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 7862 #define GPIO_IN_PIN0_Low (0x0UL) /*!< Pin input is low */ 7863 #define GPIO_IN_PIN0_High (0x1UL) /*!< Pin input is high */ 7864 7865 /* Register: GPIO_DIR */ 7866 /* Description: Direction of GPIO pins */ 7867 7868 /* Bit 31 : Pin 31 */ 7869 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 7870 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 7871 #define GPIO_DIR_PIN31_Input (0x0UL) /*!< Pin set as input */ 7872 #define GPIO_DIR_PIN31_Output (0x1UL) /*!< Pin set as output */ 7873 7874 /* Bit 30 : Pin 30 */ 7875 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 7876 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 7877 #define GPIO_DIR_PIN30_Input (0x0UL) /*!< Pin set as input */ 7878 #define GPIO_DIR_PIN30_Output (0x1UL) /*!< Pin set as output */ 7879 7880 /* Bit 29 : Pin 29 */ 7881 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 7882 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 7883 #define GPIO_DIR_PIN29_Input (0x0UL) /*!< Pin set as input */ 7884 #define GPIO_DIR_PIN29_Output (0x1UL) /*!< Pin set as output */ 7885 7886 /* Bit 28 : Pin 28 */ 7887 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 7888 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 7889 #define GPIO_DIR_PIN28_Input (0x0UL) /*!< Pin set as input */ 7890 #define GPIO_DIR_PIN28_Output (0x1UL) /*!< Pin set as output */ 7891 7892 /* Bit 27 : Pin 27 */ 7893 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 7894 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 7895 #define GPIO_DIR_PIN27_Input (0x0UL) /*!< Pin set as input */ 7896 #define GPIO_DIR_PIN27_Output (0x1UL) /*!< Pin set as output */ 7897 7898 /* Bit 26 : Pin 26 */ 7899 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 7900 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 7901 #define GPIO_DIR_PIN26_Input (0x0UL) /*!< Pin set as input */ 7902 #define GPIO_DIR_PIN26_Output (0x1UL) /*!< Pin set as output */ 7903 7904 /* Bit 25 : Pin 25 */ 7905 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 7906 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 7907 #define GPIO_DIR_PIN25_Input (0x0UL) /*!< Pin set as input */ 7908 #define GPIO_DIR_PIN25_Output (0x1UL) /*!< Pin set as output */ 7909 7910 /* Bit 24 : Pin 24 */ 7911 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 7912 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 7913 #define GPIO_DIR_PIN24_Input (0x0UL) /*!< Pin set as input */ 7914 #define GPIO_DIR_PIN24_Output (0x1UL) /*!< Pin set as output */ 7915 7916 /* Bit 23 : Pin 23 */ 7917 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 7918 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 7919 #define GPIO_DIR_PIN23_Input (0x0UL) /*!< Pin set as input */ 7920 #define GPIO_DIR_PIN23_Output (0x1UL) /*!< Pin set as output */ 7921 7922 /* Bit 22 : Pin 22 */ 7923 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 7924 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 7925 #define GPIO_DIR_PIN22_Input (0x0UL) /*!< Pin set as input */ 7926 #define GPIO_DIR_PIN22_Output (0x1UL) /*!< Pin set as output */ 7927 7928 /* Bit 21 : Pin 21 */ 7929 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 7930 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 7931 #define GPIO_DIR_PIN21_Input (0x0UL) /*!< Pin set as input */ 7932 #define GPIO_DIR_PIN21_Output (0x1UL) /*!< Pin set as output */ 7933 7934 /* Bit 20 : Pin 20 */ 7935 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 7936 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 7937 #define GPIO_DIR_PIN20_Input (0x0UL) /*!< Pin set as input */ 7938 #define GPIO_DIR_PIN20_Output (0x1UL) /*!< Pin set as output */ 7939 7940 /* Bit 19 : Pin 19 */ 7941 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 7942 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 7943 #define GPIO_DIR_PIN19_Input (0x0UL) /*!< Pin set as input */ 7944 #define GPIO_DIR_PIN19_Output (0x1UL) /*!< Pin set as output */ 7945 7946 /* Bit 18 : Pin 18 */ 7947 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 7948 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 7949 #define GPIO_DIR_PIN18_Input (0x0UL) /*!< Pin set as input */ 7950 #define GPIO_DIR_PIN18_Output (0x1UL) /*!< Pin set as output */ 7951 7952 /* Bit 17 : Pin 17 */ 7953 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 7954 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 7955 #define GPIO_DIR_PIN17_Input (0x0UL) /*!< Pin set as input */ 7956 #define GPIO_DIR_PIN17_Output (0x1UL) /*!< Pin set as output */ 7957 7958 /* Bit 16 : Pin 16 */ 7959 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 7960 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 7961 #define GPIO_DIR_PIN16_Input (0x0UL) /*!< Pin set as input */ 7962 #define GPIO_DIR_PIN16_Output (0x1UL) /*!< Pin set as output */ 7963 7964 /* Bit 15 : Pin 15 */ 7965 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 7966 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 7967 #define GPIO_DIR_PIN15_Input (0x0UL) /*!< Pin set as input */ 7968 #define GPIO_DIR_PIN15_Output (0x1UL) /*!< Pin set as output */ 7969 7970 /* Bit 14 : Pin 14 */ 7971 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 7972 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 7973 #define GPIO_DIR_PIN14_Input (0x0UL) /*!< Pin set as input */ 7974 #define GPIO_DIR_PIN14_Output (0x1UL) /*!< Pin set as output */ 7975 7976 /* Bit 13 : Pin 13 */ 7977 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 7978 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 7979 #define GPIO_DIR_PIN13_Input (0x0UL) /*!< Pin set as input */ 7980 #define GPIO_DIR_PIN13_Output (0x1UL) /*!< Pin set as output */ 7981 7982 /* Bit 12 : Pin 12 */ 7983 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 7984 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 7985 #define GPIO_DIR_PIN12_Input (0x0UL) /*!< Pin set as input */ 7986 #define GPIO_DIR_PIN12_Output (0x1UL) /*!< Pin set as output */ 7987 7988 /* Bit 11 : Pin 11 */ 7989 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 7990 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 7991 #define GPIO_DIR_PIN11_Input (0x0UL) /*!< Pin set as input */ 7992 #define GPIO_DIR_PIN11_Output (0x1UL) /*!< Pin set as output */ 7993 7994 /* Bit 10 : Pin 10 */ 7995 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 7996 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 7997 #define GPIO_DIR_PIN10_Input (0x0UL) /*!< Pin set as input */ 7998 #define GPIO_DIR_PIN10_Output (0x1UL) /*!< Pin set as output */ 7999 8000 /* Bit 9 : Pin 9 */ 8001 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 8002 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 8003 #define GPIO_DIR_PIN9_Input (0x0UL) /*!< Pin set as input */ 8004 #define GPIO_DIR_PIN9_Output (0x1UL) /*!< Pin set as output */ 8005 8006 /* Bit 8 : Pin 8 */ 8007 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 8008 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 8009 #define GPIO_DIR_PIN8_Input (0x0UL) /*!< Pin set as input */ 8010 #define GPIO_DIR_PIN8_Output (0x1UL) /*!< Pin set as output */ 8011 8012 /* Bit 7 : Pin 7 */ 8013 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 8014 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 8015 #define GPIO_DIR_PIN7_Input (0x0UL) /*!< Pin set as input */ 8016 #define GPIO_DIR_PIN7_Output (0x1UL) /*!< Pin set as output */ 8017 8018 /* Bit 6 : Pin 6 */ 8019 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 8020 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 8021 #define GPIO_DIR_PIN6_Input (0x0UL) /*!< Pin set as input */ 8022 #define GPIO_DIR_PIN6_Output (0x1UL) /*!< Pin set as output */ 8023 8024 /* Bit 5 : Pin 5 */ 8025 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 8026 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 8027 #define GPIO_DIR_PIN5_Input (0x0UL) /*!< Pin set as input */ 8028 #define GPIO_DIR_PIN5_Output (0x1UL) /*!< Pin set as output */ 8029 8030 /* Bit 4 : Pin 4 */ 8031 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 8032 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 8033 #define GPIO_DIR_PIN4_Input (0x0UL) /*!< Pin set as input */ 8034 #define GPIO_DIR_PIN4_Output (0x1UL) /*!< Pin set as output */ 8035 8036 /* Bit 3 : Pin 3 */ 8037 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 8038 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 8039 #define GPIO_DIR_PIN3_Input (0x0UL) /*!< Pin set as input */ 8040 #define GPIO_DIR_PIN3_Output (0x1UL) /*!< Pin set as output */ 8041 8042 /* Bit 2 : Pin 2 */ 8043 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 8044 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 8045 #define GPIO_DIR_PIN2_Input (0x0UL) /*!< Pin set as input */ 8046 #define GPIO_DIR_PIN2_Output (0x1UL) /*!< Pin set as output */ 8047 8048 /* Bit 1 : Pin 1 */ 8049 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 8050 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 8051 #define GPIO_DIR_PIN1_Input (0x0UL) /*!< Pin set as input */ 8052 #define GPIO_DIR_PIN1_Output (0x1UL) /*!< Pin set as output */ 8053 8054 /* Bit 0 : Pin 0 */ 8055 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 8056 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 8057 #define GPIO_DIR_PIN0_Input (0x0UL) /*!< Pin set as input */ 8058 #define GPIO_DIR_PIN0_Output (0x1UL) /*!< Pin set as output */ 8059 8060 /* Register: GPIO_DIRSET */ 8061 /* Description: DIR set register */ 8062 8063 /* Bit 31 : Set as output pin 31 */ 8064 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 8065 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 8066 #define GPIO_DIRSET_PIN31_Input (0x0UL) /*!< Read: pin set as input */ 8067 #define GPIO_DIRSET_PIN31_Output (0x1UL) /*!< Read: pin set as output */ 8068 #define GPIO_DIRSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8069 8070 /* Bit 30 : Set as output pin 30 */ 8071 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 8072 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 8073 #define GPIO_DIRSET_PIN30_Input (0x0UL) /*!< Read: pin set as input */ 8074 #define GPIO_DIRSET_PIN30_Output (0x1UL) /*!< Read: pin set as output */ 8075 #define GPIO_DIRSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8076 8077 /* Bit 29 : Set as output pin 29 */ 8078 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 8079 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 8080 #define GPIO_DIRSET_PIN29_Input (0x0UL) /*!< Read: pin set as input */ 8081 #define GPIO_DIRSET_PIN29_Output (0x1UL) /*!< Read: pin set as output */ 8082 #define GPIO_DIRSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8083 8084 /* Bit 28 : Set as output pin 28 */ 8085 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 8086 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 8087 #define GPIO_DIRSET_PIN28_Input (0x0UL) /*!< Read: pin set as input */ 8088 #define GPIO_DIRSET_PIN28_Output (0x1UL) /*!< Read: pin set as output */ 8089 #define GPIO_DIRSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8090 8091 /* Bit 27 : Set as output pin 27 */ 8092 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 8093 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 8094 #define GPIO_DIRSET_PIN27_Input (0x0UL) /*!< Read: pin set as input */ 8095 #define GPIO_DIRSET_PIN27_Output (0x1UL) /*!< Read: pin set as output */ 8096 #define GPIO_DIRSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8097 8098 /* Bit 26 : Set as output pin 26 */ 8099 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 8100 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 8101 #define GPIO_DIRSET_PIN26_Input (0x0UL) /*!< Read: pin set as input */ 8102 #define GPIO_DIRSET_PIN26_Output (0x1UL) /*!< Read: pin set as output */ 8103 #define GPIO_DIRSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8104 8105 /* Bit 25 : Set as output pin 25 */ 8106 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 8107 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 8108 #define GPIO_DIRSET_PIN25_Input (0x0UL) /*!< Read: pin set as input */ 8109 #define GPIO_DIRSET_PIN25_Output (0x1UL) /*!< Read: pin set as output */ 8110 #define GPIO_DIRSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8111 8112 /* Bit 24 : Set as output pin 24 */ 8113 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 8114 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 8115 #define GPIO_DIRSET_PIN24_Input (0x0UL) /*!< Read: pin set as input */ 8116 #define GPIO_DIRSET_PIN24_Output (0x1UL) /*!< Read: pin set as output */ 8117 #define GPIO_DIRSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8118 8119 /* Bit 23 : Set as output pin 23 */ 8120 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 8121 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 8122 #define GPIO_DIRSET_PIN23_Input (0x0UL) /*!< Read: pin set as input */ 8123 #define GPIO_DIRSET_PIN23_Output (0x1UL) /*!< Read: pin set as output */ 8124 #define GPIO_DIRSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8125 8126 /* Bit 22 : Set as output pin 22 */ 8127 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 8128 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 8129 #define GPIO_DIRSET_PIN22_Input (0x0UL) /*!< Read: pin set as input */ 8130 #define GPIO_DIRSET_PIN22_Output (0x1UL) /*!< Read: pin set as output */ 8131 #define GPIO_DIRSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8132 8133 /* Bit 21 : Set as output pin 21 */ 8134 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 8135 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 8136 #define GPIO_DIRSET_PIN21_Input (0x0UL) /*!< Read: pin set as input */ 8137 #define GPIO_DIRSET_PIN21_Output (0x1UL) /*!< Read: pin set as output */ 8138 #define GPIO_DIRSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8139 8140 /* Bit 20 : Set as output pin 20 */ 8141 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 8142 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 8143 #define GPIO_DIRSET_PIN20_Input (0x0UL) /*!< Read: pin set as input */ 8144 #define GPIO_DIRSET_PIN20_Output (0x1UL) /*!< Read: pin set as output */ 8145 #define GPIO_DIRSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8146 8147 /* Bit 19 : Set as output pin 19 */ 8148 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 8149 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 8150 #define GPIO_DIRSET_PIN19_Input (0x0UL) /*!< Read: pin set as input */ 8151 #define GPIO_DIRSET_PIN19_Output (0x1UL) /*!< Read: pin set as output */ 8152 #define GPIO_DIRSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8153 8154 /* Bit 18 : Set as output pin 18 */ 8155 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 8156 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 8157 #define GPIO_DIRSET_PIN18_Input (0x0UL) /*!< Read: pin set as input */ 8158 #define GPIO_DIRSET_PIN18_Output (0x1UL) /*!< Read: pin set as output */ 8159 #define GPIO_DIRSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8160 8161 /* Bit 17 : Set as output pin 17 */ 8162 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 8163 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 8164 #define GPIO_DIRSET_PIN17_Input (0x0UL) /*!< Read: pin set as input */ 8165 #define GPIO_DIRSET_PIN17_Output (0x1UL) /*!< Read: pin set as output */ 8166 #define GPIO_DIRSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8167 8168 /* Bit 16 : Set as output pin 16 */ 8169 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 8170 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 8171 #define GPIO_DIRSET_PIN16_Input (0x0UL) /*!< Read: pin set as input */ 8172 #define GPIO_DIRSET_PIN16_Output (0x1UL) /*!< Read: pin set as output */ 8173 #define GPIO_DIRSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8174 8175 /* Bit 15 : Set as output pin 15 */ 8176 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 8177 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 8178 #define GPIO_DIRSET_PIN15_Input (0x0UL) /*!< Read: pin set as input */ 8179 #define GPIO_DIRSET_PIN15_Output (0x1UL) /*!< Read: pin set as output */ 8180 #define GPIO_DIRSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8181 8182 /* Bit 14 : Set as output pin 14 */ 8183 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 8184 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 8185 #define GPIO_DIRSET_PIN14_Input (0x0UL) /*!< Read: pin set as input */ 8186 #define GPIO_DIRSET_PIN14_Output (0x1UL) /*!< Read: pin set as output */ 8187 #define GPIO_DIRSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8188 8189 /* Bit 13 : Set as output pin 13 */ 8190 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 8191 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 8192 #define GPIO_DIRSET_PIN13_Input (0x0UL) /*!< Read: pin set as input */ 8193 #define GPIO_DIRSET_PIN13_Output (0x1UL) /*!< Read: pin set as output */ 8194 #define GPIO_DIRSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8195 8196 /* Bit 12 : Set as output pin 12 */ 8197 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 8198 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 8199 #define GPIO_DIRSET_PIN12_Input (0x0UL) /*!< Read: pin set as input */ 8200 #define GPIO_DIRSET_PIN12_Output (0x1UL) /*!< Read: pin set as output */ 8201 #define GPIO_DIRSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8202 8203 /* Bit 11 : Set as output pin 11 */ 8204 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 8205 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 8206 #define GPIO_DIRSET_PIN11_Input (0x0UL) /*!< Read: pin set as input */ 8207 #define GPIO_DIRSET_PIN11_Output (0x1UL) /*!< Read: pin set as output */ 8208 #define GPIO_DIRSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8209 8210 /* Bit 10 : Set as output pin 10 */ 8211 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 8212 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 8213 #define GPIO_DIRSET_PIN10_Input (0x0UL) /*!< Read: pin set as input */ 8214 #define GPIO_DIRSET_PIN10_Output (0x1UL) /*!< Read: pin set as output */ 8215 #define GPIO_DIRSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8216 8217 /* Bit 9 : Set as output pin 9 */ 8218 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 8219 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 8220 #define GPIO_DIRSET_PIN9_Input (0x0UL) /*!< Read: pin set as input */ 8221 #define GPIO_DIRSET_PIN9_Output (0x1UL) /*!< Read: pin set as output */ 8222 #define GPIO_DIRSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8223 8224 /* Bit 8 : Set as output pin 8 */ 8225 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 8226 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 8227 #define GPIO_DIRSET_PIN8_Input (0x0UL) /*!< Read: pin set as input */ 8228 #define GPIO_DIRSET_PIN8_Output (0x1UL) /*!< Read: pin set as output */ 8229 #define GPIO_DIRSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8230 8231 /* Bit 7 : Set as output pin 7 */ 8232 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 8233 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 8234 #define GPIO_DIRSET_PIN7_Input (0x0UL) /*!< Read: pin set as input */ 8235 #define GPIO_DIRSET_PIN7_Output (0x1UL) /*!< Read: pin set as output */ 8236 #define GPIO_DIRSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8237 8238 /* Bit 6 : Set as output pin 6 */ 8239 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 8240 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 8241 #define GPIO_DIRSET_PIN6_Input (0x0UL) /*!< Read: pin set as input */ 8242 #define GPIO_DIRSET_PIN6_Output (0x1UL) /*!< Read: pin set as output */ 8243 #define GPIO_DIRSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8244 8245 /* Bit 5 : Set as output pin 5 */ 8246 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 8247 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 8248 #define GPIO_DIRSET_PIN5_Input (0x0UL) /*!< Read: pin set as input */ 8249 #define GPIO_DIRSET_PIN5_Output (0x1UL) /*!< Read: pin set as output */ 8250 #define GPIO_DIRSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8251 8252 /* Bit 4 : Set as output pin 4 */ 8253 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 8254 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 8255 #define GPIO_DIRSET_PIN4_Input (0x0UL) /*!< Read: pin set as input */ 8256 #define GPIO_DIRSET_PIN4_Output (0x1UL) /*!< Read: pin set as output */ 8257 #define GPIO_DIRSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8258 8259 /* Bit 3 : Set as output pin 3 */ 8260 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 8261 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 8262 #define GPIO_DIRSET_PIN3_Input (0x0UL) /*!< Read: pin set as input */ 8263 #define GPIO_DIRSET_PIN3_Output (0x1UL) /*!< Read: pin set as output */ 8264 #define GPIO_DIRSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8265 8266 /* Bit 2 : Set as output pin 2 */ 8267 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 8268 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 8269 #define GPIO_DIRSET_PIN2_Input (0x0UL) /*!< Read: pin set as input */ 8270 #define GPIO_DIRSET_PIN2_Output (0x1UL) /*!< Read: pin set as output */ 8271 #define GPIO_DIRSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8272 8273 /* Bit 1 : Set as output pin 1 */ 8274 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 8275 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 8276 #define GPIO_DIRSET_PIN1_Input (0x0UL) /*!< Read: pin set as input */ 8277 #define GPIO_DIRSET_PIN1_Output (0x1UL) /*!< Read: pin set as output */ 8278 #define GPIO_DIRSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8279 8280 /* Bit 0 : Set as output pin 0 */ 8281 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 8282 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 8283 #define GPIO_DIRSET_PIN0_Input (0x0UL) /*!< Read: pin set as input */ 8284 #define GPIO_DIRSET_PIN0_Output (0x1UL) /*!< Read: pin set as output */ 8285 #define GPIO_DIRSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 8286 8287 /* Register: GPIO_DIRCLR */ 8288 /* Description: DIR clear register */ 8289 8290 /* Bit 31 : Set as input pin 31 */ 8291 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 8292 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 8293 #define GPIO_DIRCLR_PIN31_Input (0x0UL) /*!< Read: pin set as input */ 8294 #define GPIO_DIRCLR_PIN31_Output (0x1UL) /*!< Read: pin set as output */ 8295 #define GPIO_DIRCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8296 8297 /* Bit 30 : Set as input pin 30 */ 8298 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 8299 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 8300 #define GPIO_DIRCLR_PIN30_Input (0x0UL) /*!< Read: pin set as input */ 8301 #define GPIO_DIRCLR_PIN30_Output (0x1UL) /*!< Read: pin set as output */ 8302 #define GPIO_DIRCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8303 8304 /* Bit 29 : Set as input pin 29 */ 8305 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 8306 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 8307 #define GPIO_DIRCLR_PIN29_Input (0x0UL) /*!< Read: pin set as input */ 8308 #define GPIO_DIRCLR_PIN29_Output (0x1UL) /*!< Read: pin set as output */ 8309 #define GPIO_DIRCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8310 8311 /* Bit 28 : Set as input pin 28 */ 8312 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 8313 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 8314 #define GPIO_DIRCLR_PIN28_Input (0x0UL) /*!< Read: pin set as input */ 8315 #define GPIO_DIRCLR_PIN28_Output (0x1UL) /*!< Read: pin set as output */ 8316 #define GPIO_DIRCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8317 8318 /* Bit 27 : Set as input pin 27 */ 8319 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 8320 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 8321 #define GPIO_DIRCLR_PIN27_Input (0x0UL) /*!< Read: pin set as input */ 8322 #define GPIO_DIRCLR_PIN27_Output (0x1UL) /*!< Read: pin set as output */ 8323 #define GPIO_DIRCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8324 8325 /* Bit 26 : Set as input pin 26 */ 8326 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 8327 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 8328 #define GPIO_DIRCLR_PIN26_Input (0x0UL) /*!< Read: pin set as input */ 8329 #define GPIO_DIRCLR_PIN26_Output (0x1UL) /*!< Read: pin set as output */ 8330 #define GPIO_DIRCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8331 8332 /* Bit 25 : Set as input pin 25 */ 8333 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 8334 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 8335 #define GPIO_DIRCLR_PIN25_Input (0x0UL) /*!< Read: pin set as input */ 8336 #define GPIO_DIRCLR_PIN25_Output (0x1UL) /*!< Read: pin set as output */ 8337 #define GPIO_DIRCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8338 8339 /* Bit 24 : Set as input pin 24 */ 8340 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 8341 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 8342 #define GPIO_DIRCLR_PIN24_Input (0x0UL) /*!< Read: pin set as input */ 8343 #define GPIO_DIRCLR_PIN24_Output (0x1UL) /*!< Read: pin set as output */ 8344 #define GPIO_DIRCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8345 8346 /* Bit 23 : Set as input pin 23 */ 8347 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 8348 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 8349 #define GPIO_DIRCLR_PIN23_Input (0x0UL) /*!< Read: pin set as input */ 8350 #define GPIO_DIRCLR_PIN23_Output (0x1UL) /*!< Read: pin set as output */ 8351 #define GPIO_DIRCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8352 8353 /* Bit 22 : Set as input pin 22 */ 8354 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 8355 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 8356 #define GPIO_DIRCLR_PIN22_Input (0x0UL) /*!< Read: pin set as input */ 8357 #define GPIO_DIRCLR_PIN22_Output (0x1UL) /*!< Read: pin set as output */ 8358 #define GPIO_DIRCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8359 8360 /* Bit 21 : Set as input pin 21 */ 8361 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 8362 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 8363 #define GPIO_DIRCLR_PIN21_Input (0x0UL) /*!< Read: pin set as input */ 8364 #define GPIO_DIRCLR_PIN21_Output (0x1UL) /*!< Read: pin set as output */ 8365 #define GPIO_DIRCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8366 8367 /* Bit 20 : Set as input pin 20 */ 8368 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 8369 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 8370 #define GPIO_DIRCLR_PIN20_Input (0x0UL) /*!< Read: pin set as input */ 8371 #define GPIO_DIRCLR_PIN20_Output (0x1UL) /*!< Read: pin set as output */ 8372 #define GPIO_DIRCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8373 8374 /* Bit 19 : Set as input pin 19 */ 8375 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 8376 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 8377 #define GPIO_DIRCLR_PIN19_Input (0x0UL) /*!< Read: pin set as input */ 8378 #define GPIO_DIRCLR_PIN19_Output (0x1UL) /*!< Read: pin set as output */ 8379 #define GPIO_DIRCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8380 8381 /* Bit 18 : Set as input pin 18 */ 8382 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 8383 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 8384 #define GPIO_DIRCLR_PIN18_Input (0x0UL) /*!< Read: pin set as input */ 8385 #define GPIO_DIRCLR_PIN18_Output (0x1UL) /*!< Read: pin set as output */ 8386 #define GPIO_DIRCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8387 8388 /* Bit 17 : Set as input pin 17 */ 8389 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 8390 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 8391 #define GPIO_DIRCLR_PIN17_Input (0x0UL) /*!< Read: pin set as input */ 8392 #define GPIO_DIRCLR_PIN17_Output (0x1UL) /*!< Read: pin set as output */ 8393 #define GPIO_DIRCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8394 8395 /* Bit 16 : Set as input pin 16 */ 8396 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 8397 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 8398 #define GPIO_DIRCLR_PIN16_Input (0x0UL) /*!< Read: pin set as input */ 8399 #define GPIO_DIRCLR_PIN16_Output (0x1UL) /*!< Read: pin set as output */ 8400 #define GPIO_DIRCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8401 8402 /* Bit 15 : Set as input pin 15 */ 8403 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 8404 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 8405 #define GPIO_DIRCLR_PIN15_Input (0x0UL) /*!< Read: pin set as input */ 8406 #define GPIO_DIRCLR_PIN15_Output (0x1UL) /*!< Read: pin set as output */ 8407 #define GPIO_DIRCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8408 8409 /* Bit 14 : Set as input pin 14 */ 8410 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 8411 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 8412 #define GPIO_DIRCLR_PIN14_Input (0x0UL) /*!< Read: pin set as input */ 8413 #define GPIO_DIRCLR_PIN14_Output (0x1UL) /*!< Read: pin set as output */ 8414 #define GPIO_DIRCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8415 8416 /* Bit 13 : Set as input pin 13 */ 8417 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 8418 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 8419 #define GPIO_DIRCLR_PIN13_Input (0x0UL) /*!< Read: pin set as input */ 8420 #define GPIO_DIRCLR_PIN13_Output (0x1UL) /*!< Read: pin set as output */ 8421 #define GPIO_DIRCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8422 8423 /* Bit 12 : Set as input pin 12 */ 8424 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 8425 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 8426 #define GPIO_DIRCLR_PIN12_Input (0x0UL) /*!< Read: pin set as input */ 8427 #define GPIO_DIRCLR_PIN12_Output (0x1UL) /*!< Read: pin set as output */ 8428 #define GPIO_DIRCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8429 8430 /* Bit 11 : Set as input pin 11 */ 8431 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 8432 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 8433 #define GPIO_DIRCLR_PIN11_Input (0x0UL) /*!< Read: pin set as input */ 8434 #define GPIO_DIRCLR_PIN11_Output (0x1UL) /*!< Read: pin set as output */ 8435 #define GPIO_DIRCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8436 8437 /* Bit 10 : Set as input pin 10 */ 8438 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 8439 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 8440 #define GPIO_DIRCLR_PIN10_Input (0x0UL) /*!< Read: pin set as input */ 8441 #define GPIO_DIRCLR_PIN10_Output (0x1UL) /*!< Read: pin set as output */ 8442 #define GPIO_DIRCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8443 8444 /* Bit 9 : Set as input pin 9 */ 8445 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 8446 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 8447 #define GPIO_DIRCLR_PIN9_Input (0x0UL) /*!< Read: pin set as input */ 8448 #define GPIO_DIRCLR_PIN9_Output (0x1UL) /*!< Read: pin set as output */ 8449 #define GPIO_DIRCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8450 8451 /* Bit 8 : Set as input pin 8 */ 8452 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 8453 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 8454 #define GPIO_DIRCLR_PIN8_Input (0x0UL) /*!< Read: pin set as input */ 8455 #define GPIO_DIRCLR_PIN8_Output (0x1UL) /*!< Read: pin set as output */ 8456 #define GPIO_DIRCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8457 8458 /* Bit 7 : Set as input pin 7 */ 8459 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 8460 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 8461 #define GPIO_DIRCLR_PIN7_Input (0x0UL) /*!< Read: pin set as input */ 8462 #define GPIO_DIRCLR_PIN7_Output (0x1UL) /*!< Read: pin set as output */ 8463 #define GPIO_DIRCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8464 8465 /* Bit 6 : Set as input pin 6 */ 8466 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 8467 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 8468 #define GPIO_DIRCLR_PIN6_Input (0x0UL) /*!< Read: pin set as input */ 8469 #define GPIO_DIRCLR_PIN6_Output (0x1UL) /*!< Read: pin set as output */ 8470 #define GPIO_DIRCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8471 8472 /* Bit 5 : Set as input pin 5 */ 8473 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 8474 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 8475 #define GPIO_DIRCLR_PIN5_Input (0x0UL) /*!< Read: pin set as input */ 8476 #define GPIO_DIRCLR_PIN5_Output (0x1UL) /*!< Read: pin set as output */ 8477 #define GPIO_DIRCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8478 8479 /* Bit 4 : Set as input pin 4 */ 8480 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 8481 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 8482 #define GPIO_DIRCLR_PIN4_Input (0x0UL) /*!< Read: pin set as input */ 8483 #define GPIO_DIRCLR_PIN4_Output (0x1UL) /*!< Read: pin set as output */ 8484 #define GPIO_DIRCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8485 8486 /* Bit 3 : Set as input pin 3 */ 8487 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 8488 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 8489 #define GPIO_DIRCLR_PIN3_Input (0x0UL) /*!< Read: pin set as input */ 8490 #define GPIO_DIRCLR_PIN3_Output (0x1UL) /*!< Read: pin set as output */ 8491 #define GPIO_DIRCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8492 8493 /* Bit 2 : Set as input pin 2 */ 8494 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 8495 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 8496 #define GPIO_DIRCLR_PIN2_Input (0x0UL) /*!< Read: pin set as input */ 8497 #define GPIO_DIRCLR_PIN2_Output (0x1UL) /*!< Read: pin set as output */ 8498 #define GPIO_DIRCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8499 8500 /* Bit 1 : Set as input pin 1 */ 8501 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 8502 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 8503 #define GPIO_DIRCLR_PIN1_Input (0x0UL) /*!< Read: pin set as input */ 8504 #define GPIO_DIRCLR_PIN1_Output (0x1UL) /*!< Read: pin set as output */ 8505 #define GPIO_DIRCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8506 8507 /* Bit 0 : Set as input pin 0 */ 8508 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 8509 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 8510 #define GPIO_DIRCLR_PIN0_Input (0x0UL) /*!< Read: pin set as input */ 8511 #define GPIO_DIRCLR_PIN0_Output (0x1UL) /*!< Read: pin set as output */ 8512 #define GPIO_DIRCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 8513 8514 /* Register: GPIO_LATCH */ 8515 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ 8516 8517 /* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */ 8518 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 8519 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 8520 #define GPIO_LATCH_PIN31_NotLatched (0x0UL) /*!< Criteria has not been met */ 8521 #define GPIO_LATCH_PIN31_Latched (0x1UL) /*!< Criteria has been met */ 8522 8523 /* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */ 8524 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 8525 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 8526 #define GPIO_LATCH_PIN30_NotLatched (0x0UL) /*!< Criteria has not been met */ 8527 #define GPIO_LATCH_PIN30_Latched (0x1UL) /*!< Criteria has been met */ 8528 8529 /* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */ 8530 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 8531 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 8532 #define GPIO_LATCH_PIN29_NotLatched (0x0UL) /*!< Criteria has not been met */ 8533 #define GPIO_LATCH_PIN29_Latched (0x1UL) /*!< Criteria has been met */ 8534 8535 /* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */ 8536 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 8537 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 8538 #define GPIO_LATCH_PIN28_NotLatched (0x0UL) /*!< Criteria has not been met */ 8539 #define GPIO_LATCH_PIN28_Latched (0x1UL) /*!< Criteria has been met */ 8540 8541 /* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */ 8542 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 8543 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 8544 #define GPIO_LATCH_PIN27_NotLatched (0x0UL) /*!< Criteria has not been met */ 8545 #define GPIO_LATCH_PIN27_Latched (0x1UL) /*!< Criteria has been met */ 8546 8547 /* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */ 8548 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 8549 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 8550 #define GPIO_LATCH_PIN26_NotLatched (0x0UL) /*!< Criteria has not been met */ 8551 #define GPIO_LATCH_PIN26_Latched (0x1UL) /*!< Criteria has been met */ 8552 8553 /* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */ 8554 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 8555 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 8556 #define GPIO_LATCH_PIN25_NotLatched (0x0UL) /*!< Criteria has not been met */ 8557 #define GPIO_LATCH_PIN25_Latched (0x1UL) /*!< Criteria has been met */ 8558 8559 /* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */ 8560 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 8561 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 8562 #define GPIO_LATCH_PIN24_NotLatched (0x0UL) /*!< Criteria has not been met */ 8563 #define GPIO_LATCH_PIN24_Latched (0x1UL) /*!< Criteria has been met */ 8564 8565 /* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */ 8566 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 8567 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 8568 #define GPIO_LATCH_PIN23_NotLatched (0x0UL) /*!< Criteria has not been met */ 8569 #define GPIO_LATCH_PIN23_Latched (0x1UL) /*!< Criteria has been met */ 8570 8571 /* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */ 8572 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 8573 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 8574 #define GPIO_LATCH_PIN22_NotLatched (0x0UL) /*!< Criteria has not been met */ 8575 #define GPIO_LATCH_PIN22_Latched (0x1UL) /*!< Criteria has been met */ 8576 8577 /* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */ 8578 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 8579 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 8580 #define GPIO_LATCH_PIN21_NotLatched (0x0UL) /*!< Criteria has not been met */ 8581 #define GPIO_LATCH_PIN21_Latched (0x1UL) /*!< Criteria has been met */ 8582 8583 /* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */ 8584 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 8585 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 8586 #define GPIO_LATCH_PIN20_NotLatched (0x0UL) /*!< Criteria has not been met */ 8587 #define GPIO_LATCH_PIN20_Latched (0x1UL) /*!< Criteria has been met */ 8588 8589 /* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */ 8590 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 8591 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 8592 #define GPIO_LATCH_PIN19_NotLatched (0x0UL) /*!< Criteria has not been met */ 8593 #define GPIO_LATCH_PIN19_Latched (0x1UL) /*!< Criteria has been met */ 8594 8595 /* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */ 8596 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 8597 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 8598 #define GPIO_LATCH_PIN18_NotLatched (0x0UL) /*!< Criteria has not been met */ 8599 #define GPIO_LATCH_PIN18_Latched (0x1UL) /*!< Criteria has been met */ 8600 8601 /* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */ 8602 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 8603 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 8604 #define GPIO_LATCH_PIN17_NotLatched (0x0UL) /*!< Criteria has not been met */ 8605 #define GPIO_LATCH_PIN17_Latched (0x1UL) /*!< Criteria has been met */ 8606 8607 /* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */ 8608 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 8609 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 8610 #define GPIO_LATCH_PIN16_NotLatched (0x0UL) /*!< Criteria has not been met */ 8611 #define GPIO_LATCH_PIN16_Latched (0x1UL) /*!< Criteria has been met */ 8612 8613 /* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */ 8614 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 8615 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 8616 #define GPIO_LATCH_PIN15_NotLatched (0x0UL) /*!< Criteria has not been met */ 8617 #define GPIO_LATCH_PIN15_Latched (0x1UL) /*!< Criteria has been met */ 8618 8619 /* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */ 8620 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 8621 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 8622 #define GPIO_LATCH_PIN14_NotLatched (0x0UL) /*!< Criteria has not been met */ 8623 #define GPIO_LATCH_PIN14_Latched (0x1UL) /*!< Criteria has been met */ 8624 8625 /* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */ 8626 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 8627 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 8628 #define GPIO_LATCH_PIN13_NotLatched (0x0UL) /*!< Criteria has not been met */ 8629 #define GPIO_LATCH_PIN13_Latched (0x1UL) /*!< Criteria has been met */ 8630 8631 /* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */ 8632 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 8633 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 8634 #define GPIO_LATCH_PIN12_NotLatched (0x0UL) /*!< Criteria has not been met */ 8635 #define GPIO_LATCH_PIN12_Latched (0x1UL) /*!< Criteria has been met */ 8636 8637 /* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */ 8638 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 8639 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 8640 #define GPIO_LATCH_PIN11_NotLatched (0x0UL) /*!< Criteria has not been met */ 8641 #define GPIO_LATCH_PIN11_Latched (0x1UL) /*!< Criteria has been met */ 8642 8643 /* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */ 8644 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 8645 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 8646 #define GPIO_LATCH_PIN10_NotLatched (0x0UL) /*!< Criteria has not been met */ 8647 #define GPIO_LATCH_PIN10_Latched (0x1UL) /*!< Criteria has been met */ 8648 8649 /* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */ 8650 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 8651 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 8652 #define GPIO_LATCH_PIN9_NotLatched (0x0UL) /*!< Criteria has not been met */ 8653 #define GPIO_LATCH_PIN9_Latched (0x1UL) /*!< Criteria has been met */ 8654 8655 /* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */ 8656 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 8657 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 8658 #define GPIO_LATCH_PIN8_NotLatched (0x0UL) /*!< Criteria has not been met */ 8659 #define GPIO_LATCH_PIN8_Latched (0x1UL) /*!< Criteria has been met */ 8660 8661 /* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */ 8662 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 8663 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 8664 #define GPIO_LATCH_PIN7_NotLatched (0x0UL) /*!< Criteria has not been met */ 8665 #define GPIO_LATCH_PIN7_Latched (0x1UL) /*!< Criteria has been met */ 8666 8667 /* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */ 8668 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 8669 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 8670 #define GPIO_LATCH_PIN6_NotLatched (0x0UL) /*!< Criteria has not been met */ 8671 #define GPIO_LATCH_PIN6_Latched (0x1UL) /*!< Criteria has been met */ 8672 8673 /* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */ 8674 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 8675 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 8676 #define GPIO_LATCH_PIN5_NotLatched (0x0UL) /*!< Criteria has not been met */ 8677 #define GPIO_LATCH_PIN5_Latched (0x1UL) /*!< Criteria has been met */ 8678 8679 /* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */ 8680 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 8681 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 8682 #define GPIO_LATCH_PIN4_NotLatched (0x0UL) /*!< Criteria has not been met */ 8683 #define GPIO_LATCH_PIN4_Latched (0x1UL) /*!< Criteria has been met */ 8684 8685 /* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */ 8686 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 8687 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 8688 #define GPIO_LATCH_PIN3_NotLatched (0x0UL) /*!< Criteria has not been met */ 8689 #define GPIO_LATCH_PIN3_Latched (0x1UL) /*!< Criteria has been met */ 8690 8691 /* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */ 8692 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 8693 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 8694 #define GPIO_LATCH_PIN2_NotLatched (0x0UL) /*!< Criteria has not been met */ 8695 #define GPIO_LATCH_PIN2_Latched (0x1UL) /*!< Criteria has been met */ 8696 8697 /* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */ 8698 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 8699 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 8700 #define GPIO_LATCH_PIN1_NotLatched (0x0UL) /*!< Criteria has not been met */ 8701 #define GPIO_LATCH_PIN1_Latched (0x1UL) /*!< Criteria has been met */ 8702 8703 /* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */ 8704 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 8705 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 8706 #define GPIO_LATCH_PIN0_NotLatched (0x0UL) /*!< Criteria has not been met */ 8707 #define GPIO_LATCH_PIN0_Latched (0x1UL) /*!< Criteria has been met */ 8708 8709 /* Register: GPIO_DETECTMODE */ 8710 /* Description: Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) */ 8711 8712 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ 8713 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ 8714 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ 8715 #define GPIO_DETECTMODE_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */ 8716 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */ 8717 8718 /* Register: GPIO_DETECTMODE_SEC */ 8719 /* Description: Select between default DETECT signal behavior and LDETECT mode (For secure pin only) */ 8720 8721 /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ 8722 #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ 8723 #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ 8724 #define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */ 8725 #define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */ 8726 8727 /* Register: GPIO_PIN_CNF */ 8728 /* Description: Description collection: Configuration of GPIO pins */ 8729 8730 /* Bits 17..16 : Pin sensing mechanism */ 8731 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ 8732 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ 8733 #define GPIO_PIN_CNF_SENSE_Disabled (0x0UL) /*!< Disabled */ 8734 #define GPIO_PIN_CNF_SENSE_High (0x2UL) /*!< Sense for high level */ 8735 #define GPIO_PIN_CNF_SENSE_Low (0x3UL) /*!< Sense for low level */ 8736 8737 /* Bits 10..8 : Drive configuration */ 8738 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ 8739 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ 8740 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x0UL) /*!< Standard '0', standard '1' */ 8741 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x1UL) /*!< High drive '0', standard '1' */ 8742 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x2UL) /*!< Standard '0', high drive '1' */ 8743 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x3UL) /*!< High drive '0', high 'drive '1'' */ 8744 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */ 8745 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ 8746 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */ 8747 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ 8748 8749 /* Bits 3..2 : Pull configuration */ 8750 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ 8751 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ 8752 #define GPIO_PIN_CNF_PULL_Disabled (0x0UL) /*!< No pull */ 8753 #define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull down on pin */ 8754 #define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull up on pin */ 8755 8756 /* Bit 1 : Connect or disconnect input buffer */ 8757 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ 8758 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ 8759 #define GPIO_PIN_CNF_INPUT_Connect (0x0UL) /*!< Connect input buffer */ 8760 #define GPIO_PIN_CNF_INPUT_Disconnect (0x1UL) /*!< Disconnect input buffer */ 8761 8762 /* Bit 0 : Pin direction. Same physical register as DIR register */ 8763 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ 8764 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ 8765 #define GPIO_PIN_CNF_DIR_Input (0x0UL) /*!< Configure pin as an input pin */ 8766 #define GPIO_PIN_CNF_DIR_Output (0x1UL) /*!< Configure pin as an output pin */ 8767 8768 8769 /* Peripheral: PDM */ 8770 /* Description: Pulse Density Modulation (Digital Microphone) Interface 0 */ 8771 8772 /* Register: PDM_TASKS_START */ 8773 /* Description: Starts continuous PDM transfer */ 8774 8775 /* Bit 0 : Starts continuous PDM transfer */ 8776 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 8777 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 8778 #define PDM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ 8779 8780 /* Register: PDM_TASKS_STOP */ 8781 /* Description: Stops PDM transfer */ 8782 8783 /* Bit 0 : Stops PDM transfer */ 8784 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 8785 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 8786 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ 8787 8788 /* Register: PDM_SUBSCRIBE_START */ 8789 /* Description: Subscribe configuration for task START */ 8790 8791 /* Bit 31 : */ 8792 #define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 8793 #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 8794 #define PDM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ 8795 #define PDM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ 8796 8797 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 8798 #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8799 #define PDM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8800 8801 /* Register: PDM_SUBSCRIBE_STOP */ 8802 /* Description: Subscribe configuration for task STOP */ 8803 8804 /* Bit 31 : */ 8805 #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 8806 #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 8807 #define PDM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 8808 #define PDM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 8809 8810 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 8811 #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8812 #define PDM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PDM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8813 8814 /* Register: PDM_EVENTS_STARTED */ 8815 /* Description: PDM transfer has started */ 8816 8817 /* Bit 0 : PDM transfer has started */ 8818 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 8819 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 8820 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ 8821 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ 8822 8823 /* Register: PDM_EVENTS_STOPPED */ 8824 /* Description: PDM transfer has finished */ 8825 8826 /* Bit 0 : PDM transfer has finished */ 8827 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 8828 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 8829 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ 8830 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ 8831 8832 /* Register: PDM_EVENTS_END */ 8833 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ 8834 8835 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ 8836 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 8837 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 8838 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ 8839 #define PDM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ 8840 8841 /* Register: PDM_PUBLISH_STARTED */ 8842 /* Description: Publish configuration for event STARTED */ 8843 8844 /* Bit 31 : */ 8845 #define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ 8846 #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ 8847 #define PDM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 8848 #define PDM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 8849 8850 /* Bits 7..0 : DPPI channel that event STARTED will publish to */ 8851 #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8852 #define PDM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8853 8854 /* Register: PDM_PUBLISH_STOPPED */ 8855 /* Description: Publish configuration for event STOPPED */ 8856 8857 /* Bit 31 : */ 8858 #define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 8859 #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 8860 #define PDM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ 8861 #define PDM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ 8862 8863 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 8864 #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8865 #define PDM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PDM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8866 8867 /* Register: PDM_PUBLISH_END */ 8868 /* Description: Publish configuration for event END */ 8869 8870 /* Bit 31 : */ 8871 #define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 8872 #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 8873 #define PDM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ 8874 #define PDM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ 8875 8876 /* Bits 7..0 : DPPI channel that event END will publish to */ 8877 #define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 8878 #define PDM_PUBLISH_END_CHIDX_Msk (0xFFUL << PDM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 8879 8880 /* Register: PDM_INTEN */ 8881 /* Description: Enable or disable interrupt */ 8882 8883 /* Bit 2 : Enable or disable interrupt for event END */ 8884 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ 8885 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ 8886 #define PDM_INTEN_END_Disabled (0x0UL) /*!< Disable */ 8887 #define PDM_INTEN_END_Enabled (0x1UL) /*!< Enable */ 8888 8889 /* Bit 1 : Enable or disable interrupt for event STOPPED */ 8890 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8891 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8892 #define PDM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ 8893 #define PDM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ 8894 8895 /* Bit 0 : Enable or disable interrupt for event STARTED */ 8896 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 8897 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ 8898 #define PDM_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ 8899 #define PDM_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ 8900 8901 /* Register: PDM_INTENSET */ 8902 /* Description: Enable interrupt */ 8903 8904 /* Bit 2 : Write '1' to enable interrupt for event END */ 8905 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ 8906 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 8907 #define PDM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ 8908 #define PDM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ 8909 #define PDM_INTENSET_END_Set (0x1UL) /*!< Enable */ 8910 8911 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 8912 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8913 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8914 #define PDM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 8915 #define PDM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 8916 #define PDM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ 8917 8918 /* Bit 0 : Write '1' to enable interrupt for event STARTED */ 8919 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 8920 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 8921 #define PDM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ 8922 #define PDM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ 8923 #define PDM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ 8924 8925 /* Register: PDM_INTENCLR */ 8926 /* Description: Disable interrupt */ 8927 8928 /* Bit 2 : Write '1' to disable interrupt for event END */ 8929 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ 8930 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 8931 #define PDM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ 8932 #define PDM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ 8933 #define PDM_INTENCLR_END_Clear (0x1UL) /*!< Disable */ 8934 8935 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 8936 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 8937 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 8938 #define PDM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 8939 #define PDM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 8940 #define PDM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ 8941 8942 /* Bit 0 : Write '1' to disable interrupt for event STARTED */ 8943 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 8944 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 8945 #define PDM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ 8946 #define PDM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ 8947 #define PDM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ 8948 8949 /* Register: PDM_ENABLE */ 8950 /* Description: PDM module enable register */ 8951 8952 /* Bit 0 : Enable or disable PDM module */ 8953 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 8954 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 8955 #define PDM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ 8956 #define PDM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ 8957 8958 /* Register: PDM_PDMCLKCTRL */ 8959 /* Description: PDM clock generator control */ 8960 8961 /* Bits 31..0 : PDM_CLK frequency configuration. */ 8962 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ 8963 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ 8964 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ 8965 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */ 8966 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ 8967 #define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */ 8968 #define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */ 8969 #define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */ 8970 8971 /* Register: PDM_MODE */ 8972 /* Description: Defines the routing of the connected PDM microphones' signals */ 8973 8974 /* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */ 8975 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ 8976 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ 8977 #define PDM_MODE_EDGE_LeftFalling (0x0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ 8978 #define PDM_MODE_EDGE_LeftRising (0x1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ 8979 8980 /* Bit 0 : Mono or stereo operation */ 8981 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ 8982 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ 8983 #define PDM_MODE_OPERATION_Stereo (0x0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */ 8984 #define PDM_MODE_OPERATION_Mono (0x1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */ 8985 8986 /* Register: PDM_GAINL */ 8987 /* Description: Left output gain adjustment */ 8988 8989 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ 8990 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ 8991 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ 8992 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ 8993 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ 8994 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ 8995 8996 /* Register: PDM_GAINR */ 8997 /* Description: Right output gain adjustment */ 8998 8999 /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ 9000 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ 9001 #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ 9002 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ 9003 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ 9004 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ 9005 9006 /* Register: PDM_RATIO */ 9007 /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */ 9008 9009 /* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */ 9010 #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ 9011 #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ 9012 #define PDM_RATIO_RATIO_Ratio64 (0x0UL) /*!< Ratio of 64 */ 9013 #define PDM_RATIO_RATIO_Ratio80 (0x1UL) /*!< Ratio of 80 */ 9014 9015 /* Register: PDM_PSEL_CLK */ 9016 /* Description: Pin number configuration for PDM CLK signal */ 9017 9018 /* Bit 31 : Connection */ 9019 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9020 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9021 #define PDM_PSEL_CLK_CONNECT_Connected (0x0UL) /*!< Connect */ 9022 #define PDM_PSEL_CLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 9023 9024 /* Bits 4..0 : Pin number */ 9025 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ 9026 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ 9027 9028 /* Register: PDM_PSEL_DIN */ 9029 /* Description: Pin number configuration for PDM DIN signal */ 9030 9031 /* Bit 31 : Connection */ 9032 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9033 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9034 #define PDM_PSEL_DIN_CONNECT_Connected (0x0UL) /*!< Connect */ 9035 #define PDM_PSEL_DIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 9036 9037 /* Bits 4..0 : Pin number */ 9038 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ 9039 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ 9040 9041 /* Register: PDM_SAMPLE_PTR */ 9042 /* Description: RAM address pointer to write samples to with EasyDMA */ 9043 9044 /* Bits 31..0 : Address to write PDM samples to over DMA */ 9045 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ 9046 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ 9047 9048 /* Register: PDM_SAMPLE_MAXCNT */ 9049 /* Description: Number of samples to allocate memory for in EasyDMA mode */ 9050 9051 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */ 9052 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ 9053 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ 9054 9055 9056 /* Peripheral: POWER */ 9057 /* Description: Power control 0 */ 9058 9059 /* Register: POWER_TASKS_CONSTLAT */ 9060 /* Description: Enable constant latency mode. */ 9061 9062 /* Bit 0 : Enable constant latency mode. */ 9063 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ 9064 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ 9065 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (0x1UL) /*!< Trigger task */ 9066 9067 /* Register: POWER_TASKS_LOWPWR */ 9068 /* Description: Enable low power mode (variable latency) */ 9069 9070 /* Bit 0 : Enable low power mode (variable latency) */ 9071 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ 9072 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ 9073 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (0x1UL) /*!< Trigger task */ 9074 9075 /* Register: POWER_SUBSCRIBE_CONSTLAT */ 9076 /* Description: Subscribe configuration for task CONSTLAT */ 9077 9078 /* Bit 31 : */ 9079 #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */ 9080 #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */ 9081 #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0x0UL) /*!< Disable subscription */ 9082 #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (0x1UL) /*!< Enable subscription */ 9083 9084 /* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */ 9085 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9086 #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9087 9088 /* Register: POWER_SUBSCRIBE_LOWPWR */ 9089 /* Description: Subscribe configuration for task LOWPWR */ 9090 9091 /* Bit 31 : */ 9092 #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */ 9093 #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */ 9094 #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0x0UL) /*!< Disable subscription */ 9095 #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (0x1UL) /*!< Enable subscription */ 9096 9097 /* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */ 9098 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9099 #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9100 9101 /* Register: POWER_EVENTS_POFWARN */ 9102 /* Description: Power failure warning */ 9103 9104 /* Bit 0 : Power failure warning */ 9105 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ 9106 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ 9107 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0x0UL) /*!< Event not generated */ 9108 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (0x1UL) /*!< Event generated */ 9109 9110 /* Register: POWER_EVENTS_SLEEPENTER */ 9111 /* Description: CPU entered WFI/WFE sleep */ 9112 9113 /* Bit 0 : CPU entered WFI/WFE sleep */ 9114 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ 9115 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ 9116 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0x0UL) /*!< Event not generated */ 9117 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (0x1UL) /*!< Event generated */ 9118 9119 /* Register: POWER_EVENTS_SLEEPEXIT */ 9120 /* Description: CPU exited WFI/WFE sleep */ 9121 9122 /* Bit 0 : CPU exited WFI/WFE sleep */ 9123 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ 9124 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ 9125 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0x0UL) /*!< Event not generated */ 9126 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (0x1UL) /*!< Event generated */ 9127 9128 /* Register: POWER_PUBLISH_POFWARN */ 9129 /* Description: Publish configuration for event POFWARN */ 9130 9131 /* Bit 31 : */ 9132 #define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */ 9133 #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */ 9134 #define POWER_PUBLISH_POFWARN_EN_Disabled (0x0UL) /*!< Disable publishing */ 9135 #define POWER_PUBLISH_POFWARN_EN_Enabled (0x1UL) /*!< Enable publishing */ 9136 9137 /* Bits 7..0 : DPPI channel that event POFWARN will publish to */ 9138 #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9139 #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9140 9141 /* Register: POWER_PUBLISH_SLEEPENTER */ 9142 /* Description: Publish configuration for event SLEEPENTER */ 9143 9144 /* Bit 31 : */ 9145 #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */ 9146 #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */ 9147 #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0x0UL) /*!< Disable publishing */ 9148 #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (0x1UL) /*!< Enable publishing */ 9149 9150 /* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to */ 9151 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9152 #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9153 9154 /* Register: POWER_PUBLISH_SLEEPEXIT */ 9155 /* Description: Publish configuration for event SLEEPEXIT */ 9156 9157 /* Bit 31 : */ 9158 #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */ 9159 #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */ 9160 #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0x0UL) /*!< Disable publishing */ 9161 #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (0x1UL) /*!< Enable publishing */ 9162 9163 /* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to */ 9164 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9165 #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9166 9167 /* Register: POWER_INTEN */ 9168 /* Description: Enable or disable interrupt */ 9169 9170 /* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */ 9171 #define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 9172 #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 9173 #define POWER_INTEN_SLEEPEXIT_Disabled (0x0UL) /*!< Disable */ 9174 #define POWER_INTEN_SLEEPEXIT_Enabled (0x1UL) /*!< Enable */ 9175 9176 /* Bit 5 : Enable or disable interrupt for event SLEEPENTER */ 9177 #define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 9178 #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 9179 #define POWER_INTEN_SLEEPENTER_Disabled (0x0UL) /*!< Disable */ 9180 #define POWER_INTEN_SLEEPENTER_Enabled (0x1UL) /*!< Enable */ 9181 9182 /* Bit 2 : Enable or disable interrupt for event POFWARN */ 9183 #define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 9184 #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 9185 #define POWER_INTEN_POFWARN_Disabled (0x0UL) /*!< Disable */ 9186 #define POWER_INTEN_POFWARN_Enabled (0x1UL) /*!< Enable */ 9187 9188 /* Register: POWER_INTENSET */ 9189 /* Description: Enable interrupt */ 9190 9191 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ 9192 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 9193 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 9194 #define POWER_INTENSET_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */ 9195 #define POWER_INTENSET_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */ 9196 #define POWER_INTENSET_SLEEPEXIT_Set (0x1UL) /*!< Enable */ 9197 9198 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ 9199 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 9200 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 9201 #define POWER_INTENSET_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */ 9202 #define POWER_INTENSET_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */ 9203 #define POWER_INTENSET_SLEEPENTER_Set (0x1UL) /*!< Enable */ 9204 9205 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */ 9206 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 9207 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 9208 #define POWER_INTENSET_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */ 9209 #define POWER_INTENSET_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */ 9210 #define POWER_INTENSET_POFWARN_Set (0x1UL) /*!< Enable */ 9211 9212 /* Register: POWER_INTENCLR */ 9213 /* Description: Disable interrupt */ 9214 9215 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ 9216 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 9217 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 9218 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */ 9219 #define POWER_INTENCLR_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */ 9220 #define POWER_INTENCLR_SLEEPEXIT_Clear (0x1UL) /*!< Disable */ 9221 9222 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ 9223 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 9224 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 9225 #define POWER_INTENCLR_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */ 9226 #define POWER_INTENCLR_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */ 9227 #define POWER_INTENCLR_SLEEPENTER_Clear (0x1UL) /*!< Disable */ 9228 9229 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */ 9230 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 9231 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 9232 #define POWER_INTENCLR_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */ 9233 #define POWER_INTENCLR_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */ 9234 #define POWER_INTENCLR_POFWARN_Clear (0x1UL) /*!< Disable */ 9235 9236 /* Register: POWER_RESETREAS */ 9237 /* Description: Reset reason */ 9238 9239 /* Bit 18 : Reset triggered through CTRL-AP */ 9240 #define POWER_RESETREAS_CTRLAP_Pos (18UL) /*!< Position of CTRLAP field. */ 9241 #define POWER_RESETREAS_CTRLAP_Msk (0x1UL << POWER_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */ 9242 #define POWER_RESETREAS_CTRLAP_NotDetected (0x0UL) /*!< Not detected */ 9243 #define POWER_RESETREAS_CTRLAP_Detected (0x1UL) /*!< Detected */ 9244 9245 /* Bit 17 : Reset from CPU lock-up detected */ 9246 #define POWER_RESETREAS_LOCKUP_Pos (17UL) /*!< Position of LOCKUP field. */ 9247 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ 9248 #define POWER_RESETREAS_LOCKUP_NotDetected (0x0UL) /*!< Not detected */ 9249 #define POWER_RESETREAS_LOCKUP_Detected (0x1UL) /*!< Detected */ 9250 9251 /* Bit 16 : Reset from AIRCR.SYSRESETREQ detected */ 9252 #define POWER_RESETREAS_SREQ_Pos (16UL) /*!< Position of SREQ field. */ 9253 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ 9254 #define POWER_RESETREAS_SREQ_NotDetected (0x0UL) /*!< Not detected */ 9255 #define POWER_RESETREAS_SREQ_Detected (0x1UL) /*!< Detected */ 9256 9257 /* Bit 4 : Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode */ 9258 #define POWER_RESETREAS_DIF_Pos (4UL) /*!< Position of DIF field. */ 9259 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ 9260 #define POWER_RESETREAS_DIF_NotDetected (0x0UL) /*!< Not detected */ 9261 #define POWER_RESETREAS_DIF_Detected (0x1UL) /*!< Detected */ 9262 9263 /* Bit 2 : Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO */ 9264 #define POWER_RESETREAS_OFF_Pos (2UL) /*!< Position of OFF field. */ 9265 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ 9266 #define POWER_RESETREAS_OFF_NotDetected (0x0UL) /*!< Not detected */ 9267 #define POWER_RESETREAS_OFF_Detected (0x1UL) /*!< Detected */ 9268 9269 /* Bit 1 : Reset from global watchdog detected */ 9270 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ 9271 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ 9272 #define POWER_RESETREAS_DOG_NotDetected (0x0UL) /*!< Not detected */ 9273 #define POWER_RESETREAS_DOG_Detected (0x1UL) /*!< Detected */ 9274 9275 /* Bit 0 : Reset from pin reset detected */ 9276 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ 9277 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ 9278 #define POWER_RESETREAS_RESETPIN_NotDetected (0x0UL) /*!< Not detected */ 9279 #define POWER_RESETREAS_RESETPIN_Detected (0x1UL) /*!< Detected */ 9280 9281 /* Register: POWER_POWERSTATUS */ 9282 /* Description: Modem domain power status */ 9283 9284 /* Bit 0 : LTE modem domain status */ 9285 #define POWER_POWERSTATUS_LTEMODEM_Pos (0UL) /*!< Position of LTEMODEM field. */ 9286 #define POWER_POWERSTATUS_LTEMODEM_Msk (0x1UL << POWER_POWERSTATUS_LTEMODEM_Pos) /*!< Bit mask of LTEMODEM field. */ 9287 #define POWER_POWERSTATUS_LTEMODEM_OFF (0x0UL) /*!< LTE modem domain is powered off */ 9288 #define POWER_POWERSTATUS_LTEMODEM_ON (0x1UL) /*!< LTE modem domain is powered on */ 9289 9290 /* Register: POWER_GPREGRET */ 9291 /* Description: Description collection: General purpose retention register */ 9292 9293 /* Bits 7..0 : General purpose retention register */ 9294 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 9295 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 9296 9297 /* Register: POWER_LTEMODEM_STARTN */ 9298 /* Description: Start LTE modem */ 9299 9300 /* Bit 0 : Start LTE modem */ 9301 #define POWER_LTEMODEM_STARTN_STARTN_Pos (0UL) /*!< Position of STARTN field. */ 9302 #define POWER_LTEMODEM_STARTN_STARTN_Msk (0x1UL << POWER_LTEMODEM_STARTN_STARTN_Pos) /*!< Bit mask of STARTN field. */ 9303 #define POWER_LTEMODEM_STARTN_STARTN_Start (0x0UL) /*!< Start LTE modem */ 9304 #define POWER_LTEMODEM_STARTN_STARTN_Hold (0x1UL) /*!< Hold LTE modem disabled */ 9305 9306 /* Register: POWER_LTEMODEM_FORCEOFF */ 9307 /* Description: Force off LTE modem */ 9308 9309 /* Bit 0 : Force off LTE modem */ 9310 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ 9311 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Msk (0x1UL << POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ 9312 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Release (0x0UL) /*!< Release force off */ 9313 #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Hold (0x1UL) /*!< Hold force off active */ 9314 9315 9316 /* Peripheral: PWM */ 9317 /* Description: Pulse width modulation unit 0 */ 9318 9319 /* Register: PWM_TASKS_STOP */ 9320 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ 9321 9322 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ 9323 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 9324 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 9325 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ 9326 9327 /* Register: PWM_TASKS_SEQSTART */ 9328 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ 9329 9330 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ 9331 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ 9332 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ 9333 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (0x1UL) /*!< Trigger task */ 9334 9335 /* Register: PWM_TASKS_NEXTSTEP */ 9336 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ 9337 9338 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ 9339 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ 9340 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ 9341 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (0x1UL) /*!< Trigger task */ 9342 9343 /* Register: PWM_SUBSCRIBE_STOP */ 9344 /* Description: Subscribe configuration for task STOP */ 9345 9346 /* Bit 31 : */ 9347 #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 9348 #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 9349 #define PWM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 9350 #define PWM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 9351 9352 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 9353 #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9354 #define PWM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9355 9356 /* Register: PWM_SUBSCRIBE_SEQSTART */ 9357 /* Description: Description collection: Subscribe configuration for task SEQSTART[n] */ 9358 9359 /* Bit 31 : */ 9360 #define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL) /*!< Position of EN field. */ 9361 #define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field. */ 9362 #define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ 9363 #define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ 9364 9365 /* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */ 9366 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9367 #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9368 9369 /* Register: PWM_SUBSCRIBE_NEXTSTEP */ 9370 /* Description: Subscribe configuration for task NEXTSTEP */ 9371 9372 /* Bit 31 : */ 9373 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */ 9374 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */ 9375 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0x0UL) /*!< Disable subscription */ 9376 #define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (0x1UL) /*!< Enable subscription */ 9377 9378 /* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */ 9379 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9380 #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Msk (0xFFUL << PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9381 9382 /* Register: PWM_EVENTS_STOPPED */ 9383 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ 9384 9385 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ 9386 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 9387 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 9388 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ 9389 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ 9390 9391 /* Register: PWM_EVENTS_SEQSTARTED */ 9392 /* Description: Description collection: First PWM period started on sequence n */ 9393 9394 /* Bit 0 : First PWM period started on sequence n */ 9395 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ 9396 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ 9397 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ 9398 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (0x1UL) /*!< Event generated */ 9399 9400 /* Register: PWM_EVENTS_SEQEND */ 9401 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ 9402 9403 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ 9404 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ 9405 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ 9406 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0x0UL) /*!< Event not generated */ 9407 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (0x1UL) /*!< Event generated */ 9408 9409 /* Register: PWM_EVENTS_PWMPERIODEND */ 9410 /* Description: Emitted at the end of each PWM period */ 9411 9412 /* Bit 0 : Emitted at the end of each PWM period */ 9413 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ 9414 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ 9415 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated */ 9416 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated */ 9417 9418 /* Register: PWM_EVENTS_LOOPSDONE */ 9419 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ 9420 9421 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ 9422 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ 9423 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ 9424 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0x0UL) /*!< Event not generated */ 9425 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (0x1UL) /*!< Event generated */ 9426 9427 /* Register: PWM_PUBLISH_STOPPED */ 9428 /* Description: Publish configuration for event STOPPED */ 9429 9430 /* Bit 31 : */ 9431 #define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 9432 #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 9433 #define PWM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ 9434 #define PWM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ 9435 9436 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 9437 #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9438 #define PWM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9439 9440 /* Register: PWM_PUBLISH_SEQSTARTED */ 9441 /* Description: Description collection: Publish configuration for event SEQSTARTED[n] */ 9442 9443 /* Bit 31 : */ 9444 #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 9445 #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 9446 #define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 9447 #define PWM_PUBLISH_SEQSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 9448 9449 /* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to */ 9450 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9451 #define PWM_PUBLISH_SEQSTARTED_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9452 9453 /* Register: PWM_PUBLISH_SEQEND */ 9454 /* Description: Description collection: Publish configuration for event SEQEND[n] */ 9455 9456 /* Bit 31 : */ 9457 #define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */ 9458 #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */ 9459 #define PWM_PUBLISH_SEQEND_EN_Disabled (0x0UL) /*!< Disable publishing */ 9460 #define PWM_PUBLISH_SEQEND_EN_Enabled (0x1UL) /*!< Enable publishing */ 9461 9462 /* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to */ 9463 #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9464 #define PWM_PUBLISH_SEQEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_SEQEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9465 9466 /* Register: PWM_PUBLISH_PWMPERIODEND */ 9467 /* Description: Publish configuration for event PWMPERIODEND */ 9468 9469 /* Bit 31 : */ 9470 #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */ 9471 #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */ 9472 #define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0x0UL) /*!< Disable publishing */ 9473 #define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (0x1UL) /*!< Enable publishing */ 9474 9475 /* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to */ 9476 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9477 #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Msk (0xFFUL << PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9478 9479 /* Register: PWM_PUBLISH_LOOPSDONE */ 9480 /* Description: Publish configuration for event LOOPSDONE */ 9481 9482 /* Bit 31 : */ 9483 #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */ 9484 #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */ 9485 #define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ 9486 #define PWM_PUBLISH_LOOPSDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ 9487 9488 /* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to */ 9489 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9490 #define PWM_PUBLISH_LOOPSDONE_CHIDX_Msk (0xFFUL << PWM_PUBLISH_LOOPSDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9491 9492 /* Register: PWM_SHORTS */ 9493 /* Description: Shortcuts between local events and tasks */ 9494 9495 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ 9496 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ 9497 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ 9498 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 9499 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 9500 9501 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ 9502 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ 9503 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ 9504 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0x0UL) /*!< Disable shortcut */ 9505 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (0x1UL) /*!< Enable shortcut */ 9506 9507 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ 9508 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ 9509 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ 9510 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0x0UL) /*!< Disable shortcut */ 9511 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (0x1UL) /*!< Enable shortcut */ 9512 9513 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ 9514 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ 9515 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ 9516 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 9517 #define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 9518 9519 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ 9520 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ 9521 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ 9522 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 9523 #define PWM_SHORTS_SEQEND0_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 9524 9525 /* Register: PWM_INTEN */ 9526 /* Description: Enable or disable interrupt */ 9527 9528 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ 9529 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 9530 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 9531 #define PWM_INTEN_LOOPSDONE_Disabled (0x0UL) /*!< Disable */ 9532 #define PWM_INTEN_LOOPSDONE_Enabled (0x1UL) /*!< Enable */ 9533 9534 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ 9535 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 9536 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 9537 #define PWM_INTEN_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ 9538 #define PWM_INTEN_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ 9539 9540 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ 9541 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 9542 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 9543 #define PWM_INTEN_SEQEND1_Disabled (0x0UL) /*!< Disable */ 9544 #define PWM_INTEN_SEQEND1_Enabled (0x1UL) /*!< Enable */ 9545 9546 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ 9547 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 9548 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 9549 #define PWM_INTEN_SEQEND0_Disabled (0x0UL) /*!< Disable */ 9550 #define PWM_INTEN_SEQEND0_Enabled (0x1UL) /*!< Enable */ 9551 9552 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ 9553 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 9554 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 9555 #define PWM_INTEN_SEQSTARTED1_Disabled (0x0UL) /*!< Disable */ 9556 #define PWM_INTEN_SEQSTARTED1_Enabled (0x1UL) /*!< Enable */ 9557 9558 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ 9559 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 9560 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 9561 #define PWM_INTEN_SEQSTARTED0_Disabled (0x0UL) /*!< Disable */ 9562 #define PWM_INTEN_SEQSTARTED0_Enabled (0x1UL) /*!< Enable */ 9563 9564 /* Bit 1 : Enable or disable interrupt for event STOPPED */ 9565 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9566 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9567 #define PWM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ 9568 #define PWM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ 9569 9570 /* Register: PWM_INTENSET */ 9571 /* Description: Enable interrupt */ 9572 9573 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ 9574 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 9575 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 9576 #define PWM_INTENSET_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */ 9577 #define PWM_INTENSET_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */ 9578 #define PWM_INTENSET_LOOPSDONE_Set (0x1UL) /*!< Enable */ 9579 9580 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ 9581 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 9582 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 9583 #define PWM_INTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ 9584 #define PWM_INTENSET_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ 9585 #define PWM_INTENSET_PWMPERIODEND_Set (0x1UL) /*!< Enable */ 9586 9587 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ 9588 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 9589 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 9590 #define PWM_INTENSET_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */ 9591 #define PWM_INTENSET_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */ 9592 #define PWM_INTENSET_SEQEND1_Set (0x1UL) /*!< Enable */ 9593 9594 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ 9595 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 9596 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 9597 #define PWM_INTENSET_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */ 9598 #define PWM_INTENSET_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */ 9599 #define PWM_INTENSET_SEQEND0_Set (0x1UL) /*!< Enable */ 9600 9601 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ 9602 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 9603 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 9604 #define PWM_INTENSET_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */ 9605 #define PWM_INTENSET_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */ 9606 #define PWM_INTENSET_SEQSTARTED1_Set (0x1UL) /*!< Enable */ 9607 9608 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ 9609 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 9610 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 9611 #define PWM_INTENSET_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */ 9612 #define PWM_INTENSET_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */ 9613 #define PWM_INTENSET_SEQSTARTED0_Set (0x1UL) /*!< Enable */ 9614 9615 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 9616 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9617 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9618 #define PWM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 9619 #define PWM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 9620 #define PWM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ 9621 9622 /* Register: PWM_INTENCLR */ 9623 /* Description: Disable interrupt */ 9624 9625 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ 9626 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 9627 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 9628 #define PWM_INTENCLR_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */ 9629 #define PWM_INTENCLR_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */ 9630 #define PWM_INTENCLR_LOOPSDONE_Clear (0x1UL) /*!< Disable */ 9631 9632 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ 9633 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 9634 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 9635 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ 9636 #define PWM_INTENCLR_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ 9637 #define PWM_INTENCLR_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ 9638 9639 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ 9640 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 9641 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 9642 #define PWM_INTENCLR_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */ 9643 #define PWM_INTENCLR_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */ 9644 #define PWM_INTENCLR_SEQEND1_Clear (0x1UL) /*!< Disable */ 9645 9646 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ 9647 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 9648 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 9649 #define PWM_INTENCLR_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */ 9650 #define PWM_INTENCLR_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */ 9651 #define PWM_INTENCLR_SEQEND0_Clear (0x1UL) /*!< Disable */ 9652 9653 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ 9654 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 9655 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 9656 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */ 9657 #define PWM_INTENCLR_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */ 9658 #define PWM_INTENCLR_SEQSTARTED1_Clear (0x1UL) /*!< Disable */ 9659 9660 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ 9661 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 9662 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 9663 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */ 9664 #define PWM_INTENCLR_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */ 9665 #define PWM_INTENCLR_SEQSTARTED0_Clear (0x1UL) /*!< Disable */ 9666 9667 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 9668 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 9669 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 9670 #define PWM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 9671 #define PWM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 9672 #define PWM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ 9673 9674 /* Register: PWM_ENABLE */ 9675 /* Description: PWM module enable register */ 9676 9677 /* Bit 0 : Enable or disable PWM module */ 9678 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 9679 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 9680 #define PWM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disabled */ 9681 #define PWM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ 9682 9683 /* Register: PWM_MODE */ 9684 /* Description: Selects operating mode of the wave counter */ 9685 9686 /* Bit 0 : Selects up mode or up-and-down mode for the counter */ 9687 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ 9688 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ 9689 #define PWM_MODE_UPDOWN_Up (0x0UL) /*!< Up counter, edge-aligned PWM duty cycle */ 9690 #define PWM_MODE_UPDOWN_UpAndDown (0x1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ 9691 9692 /* Register: PWM_COUNTERTOP */ 9693 /* Description: Value up to which the pulse generator counter counts */ 9694 9695 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */ 9696 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ 9697 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ 9698 9699 /* Register: PWM_PRESCALER */ 9700 /* Description: Configuration for PWM_CLK */ 9701 9702 /* Bits 2..0 : Prescaler of PWM_CLK */ 9703 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 9704 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 9705 #define PWM_PRESCALER_PRESCALER_DIV_1 (0x0UL) /*!< Divide by 1 (16 MHz) */ 9706 #define PWM_PRESCALER_PRESCALER_DIV_2 (0x1UL) /*!< Divide by 2 (8 MHz) */ 9707 #define PWM_PRESCALER_PRESCALER_DIV_4 (0x2UL) /*!< Divide by 4 (4 MHz) */ 9708 #define PWM_PRESCALER_PRESCALER_DIV_8 (0x3UL) /*!< Divide by 8 (2 MHz) */ 9709 #define PWM_PRESCALER_PRESCALER_DIV_16 (0x4UL) /*!< Divide by 16 (1 MHz) */ 9710 #define PWM_PRESCALER_PRESCALER_DIV_32 (0x5UL) /*!< Divide by 32 (500 kHz) */ 9711 #define PWM_PRESCALER_PRESCALER_DIV_64 (0x6UL) /*!< Divide by 64 (250 kHz) */ 9712 #define PWM_PRESCALER_PRESCALER_DIV_128 (0x7UL) /*!< Divide by 128 (125 kHz) */ 9713 9714 /* Register: PWM_DECODER */ 9715 /* Description: Configuration of the decoder */ 9716 9717 /* Bit 8 : Selects source for advancing the active sequence */ 9718 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ 9719 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ 9720 #define PWM_DECODER_MODE_RefreshCount (0x0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ 9721 #define PWM_DECODER_MODE_NextStep (0x1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ 9722 9723 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ 9724 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ 9725 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ 9726 #define PWM_DECODER_LOAD_Common (0x0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ 9727 #define PWM_DECODER_LOAD_Grouped (0x1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ 9728 #define PWM_DECODER_LOAD_Individual (0x2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ 9729 #define PWM_DECODER_LOAD_WaveForm (0x3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ 9730 9731 /* Register: PWM_LOOP */ 9732 /* Description: Number of playbacks of a loop */ 9733 9734 /* Bits 15..0 : Number of playbacks of pattern cycles */ 9735 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ 9736 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ 9737 #define PWM_LOOP_CNT_Disabled (0x0000UL) /*!< Looping disabled (stop at the end of the sequence) */ 9738 9739 /* Register: PWM_SEQ_PTR */ 9740 /* Description: Description cluster: Beginning address in RAM of this sequence */ 9741 9742 /* Bits 31..0 : Beginning address in RAM of this sequence */ 9743 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 9744 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 9745 9746 /* Register: PWM_SEQ_CNT */ 9747 /* Description: Description cluster: Number of values (duty cycles) in this sequence */ 9748 9749 /* Bits 14..0 : Number of values (duty cycles) in this sequence */ 9750 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ 9751 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ 9752 #define PWM_SEQ_CNT_CNT_Disabled (0x0000UL) /*!< Sequence is disabled, and shall not be started as it is empty */ 9753 9754 /* Register: PWM_SEQ_REFRESH */ 9755 /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ 9756 9757 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ 9758 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ 9759 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ 9760 #define PWM_SEQ_REFRESH_CNT_Continuous (0x000000UL) /*!< Update every PWM period */ 9761 9762 /* Register: PWM_SEQ_ENDDELAY */ 9763 /* Description: Description cluster: Time added after the sequence */ 9764 9765 /* Bits 23..0 : Time added after the sequence in PWM periods */ 9766 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ 9767 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ 9768 9769 /* Register: PWM_PSEL_OUT */ 9770 /* Description: Description collection: Output pin select for PWM channel n */ 9771 9772 /* Bit 31 : Connection */ 9773 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 9774 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 9775 #define PWM_PSEL_OUT_CONNECT_Connected (0x0UL) /*!< Connect */ 9776 #define PWM_PSEL_OUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 9777 9778 /* Bits 4..0 : Pin number */ 9779 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ 9780 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ 9781 9782 9783 /* Peripheral: REGULATORS */ 9784 /* Description: Voltage regulators control 0 */ 9785 9786 /* Register: REGULATORS_SYSTEMOFF */ 9787 /* Description: System OFF register */ 9788 9789 /* Bit 0 : Enable System OFF mode */ 9790 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ 9791 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ 9792 #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (0x1UL) /*!< Enable System OFF mode */ 9793 9794 /* Register: REGULATORS_EXTPOFCON */ 9795 /* Description: External power failure warning configuration */ 9796 9797 /* Bit 0 : Enable or disable external power failure warning */ 9798 #define REGULATORS_EXTPOFCON_POF_Pos (0UL) /*!< Position of POF field. */ 9799 #define REGULATORS_EXTPOFCON_POF_Msk (0x1UL << REGULATORS_EXTPOFCON_POF_Pos) /*!< Bit mask of POF field. */ 9800 #define REGULATORS_EXTPOFCON_POF_Disabled (0x0UL) /*!< Disable */ 9801 #define REGULATORS_EXTPOFCON_POF_Enabled (0x1UL) /*!< Enable */ 9802 9803 /* Register: REGULATORS_DCDCEN */ 9804 /* Description: Enable a step-down DC/DC voltage regulator. */ 9805 9806 /* Bit 0 : Enable DC/DC buck regulator */ 9807 #define REGULATORS_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ 9808 #define REGULATORS_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ 9809 #define REGULATORS_DCDCEN_DCDCEN_Disabled (0x0UL) /*!< DC/DC buck regulator is disabled */ 9810 #define REGULATORS_DCDCEN_DCDCEN_Enabled (0x1UL) /*!< DC/DC buck regulator is enabled */ 9811 9812 9813 /* Peripheral: RTC */ 9814 /* Description: Real-time counter 0 */ 9815 9816 /* Register: RTC_TASKS_START */ 9817 /* Description: Start RTC counter */ 9818 9819 /* Bit 0 : Start RTC counter */ 9820 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 9821 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 9822 #define RTC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ 9823 9824 /* Register: RTC_TASKS_STOP */ 9825 /* Description: Stop RTC counter */ 9826 9827 /* Bit 0 : Stop RTC counter */ 9828 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 9829 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 9830 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ 9831 9832 /* Register: RTC_TASKS_CLEAR */ 9833 /* Description: Clear RTC counter */ 9834 9835 /* Bit 0 : Clear RTC counter */ 9836 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 9837 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 9838 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */ 9839 9840 /* Register: RTC_TASKS_TRIGOVRFLW */ 9841 /* Description: Set counter to 0xFFFFF0 */ 9842 9843 /* Bit 0 : Set counter to 0xFFFFF0 */ 9844 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ 9845 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ 9846 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (0x1UL) /*!< Trigger task */ 9847 9848 /* Register: RTC_SUBSCRIBE_START */ 9849 /* Description: Subscribe configuration for task START */ 9850 9851 /* Bit 31 : */ 9852 #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 9853 #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 9854 #define RTC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ 9855 #define RTC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ 9856 9857 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 9858 #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9859 #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9860 9861 /* Register: RTC_SUBSCRIBE_STOP */ 9862 /* Description: Subscribe configuration for task STOP */ 9863 9864 /* Bit 31 : */ 9865 #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 9866 #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 9867 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 9868 #define RTC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 9869 9870 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 9871 #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9872 #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9873 9874 /* Register: RTC_SUBSCRIBE_CLEAR */ 9875 /* Description: Subscribe configuration for task CLEAR */ 9876 9877 /* Bit 31 : */ 9878 #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ 9879 #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ 9880 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */ 9881 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */ 9882 9883 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ 9884 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9885 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9886 9887 /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */ 9888 /* Description: Subscribe configuration for task TRIGOVRFLW */ 9889 9890 /* Bit 31 : */ 9891 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ 9892 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */ 9893 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0x0UL) /*!< Disable subscription */ 9894 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (0x1UL) /*!< Enable subscription */ 9895 9896 /* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */ 9897 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9898 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9899 9900 /* Register: RTC_EVENTS_TICK */ 9901 /* Description: Event on counter increment */ 9902 9903 /* Bit 0 : Event on counter increment */ 9904 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ 9905 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ 9906 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0x0UL) /*!< Event not generated */ 9907 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (0x1UL) /*!< Event generated */ 9908 9909 /* Register: RTC_EVENTS_OVRFLW */ 9910 /* Description: Event on counter overflow */ 9911 9912 /* Bit 0 : Event on counter overflow */ 9913 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ 9914 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ 9915 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0x0UL) /*!< Event not generated */ 9916 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (0x1UL) /*!< Event generated */ 9917 9918 /* Register: RTC_EVENTS_COMPARE */ 9919 /* Description: Description collection: Compare event on CC[n] match */ 9920 9921 /* Bit 0 : Compare event on CC[n] match */ 9922 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 9923 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 9924 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */ 9925 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */ 9926 9927 /* Register: RTC_PUBLISH_TICK */ 9928 /* Description: Publish configuration for event TICK */ 9929 9930 /* Bit 31 : */ 9931 #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */ 9932 #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */ 9933 #define RTC_PUBLISH_TICK_EN_Disabled (0x0UL) /*!< Disable publishing */ 9934 #define RTC_PUBLISH_TICK_EN_Enabled (0x1UL) /*!< Enable publishing */ 9935 9936 /* Bits 7..0 : DPPI channel that event TICK will publish to */ 9937 #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9938 #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9939 9940 /* Register: RTC_PUBLISH_OVRFLW */ 9941 /* Description: Publish configuration for event OVRFLW */ 9942 9943 /* Bit 31 : */ 9944 #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ 9945 #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */ 9946 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0x0UL) /*!< Disable publishing */ 9947 #define RTC_PUBLISH_OVRFLW_EN_Enabled (0x1UL) /*!< Enable publishing */ 9948 9949 /* Bits 7..0 : DPPI channel that event OVRFLW will publish to */ 9950 #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9951 #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9952 9953 /* Register: RTC_PUBLISH_COMPARE */ 9954 /* Description: Description collection: Publish configuration for event COMPARE[n] */ 9955 9956 /* Bit 31 : */ 9957 #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ 9958 #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ 9959 #define RTC_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */ 9960 #define RTC_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */ 9961 9962 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */ 9963 #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 9964 #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 9965 9966 /* Register: RTC_INTENSET */ 9967 /* Description: Enable interrupt */ 9968 9969 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ 9970 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 9971 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 9972 #define RTC_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ 9973 #define RTC_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ 9974 #define RTC_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */ 9975 9976 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ 9977 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 9978 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 9979 #define RTC_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ 9980 #define RTC_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ 9981 #define RTC_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */ 9982 9983 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ 9984 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 9985 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 9986 #define RTC_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ 9987 #define RTC_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ 9988 #define RTC_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */ 9989 9990 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ 9991 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 9992 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 9993 #define RTC_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ 9994 #define RTC_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ 9995 #define RTC_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */ 9996 9997 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ 9998 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 9999 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 10000 #define RTC_INTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ 10001 #define RTC_INTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ 10002 #define RTC_INTENSET_OVRFLW_Set (0x1UL) /*!< Enable */ 10003 10004 /* Bit 0 : Write '1' to enable interrupt for event TICK */ 10005 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 10006 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 10007 #define RTC_INTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */ 10008 #define RTC_INTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */ 10009 #define RTC_INTENSET_TICK_Set (0x1UL) /*!< Enable */ 10010 10011 /* Register: RTC_INTENCLR */ 10012 /* Description: Disable interrupt */ 10013 10014 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ 10015 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 10016 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 10017 #define RTC_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ 10018 #define RTC_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ 10019 #define RTC_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */ 10020 10021 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ 10022 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 10023 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 10024 #define RTC_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ 10025 #define RTC_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ 10026 #define RTC_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */ 10027 10028 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ 10029 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 10030 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 10031 #define RTC_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ 10032 #define RTC_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ 10033 #define RTC_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */ 10034 10035 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ 10036 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 10037 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 10038 #define RTC_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ 10039 #define RTC_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ 10040 #define RTC_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */ 10041 10042 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ 10043 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 10044 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 10045 #define RTC_INTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ 10046 #define RTC_INTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ 10047 #define RTC_INTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */ 10048 10049 /* Bit 0 : Write '1' to disable interrupt for event TICK */ 10050 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 10051 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 10052 #define RTC_INTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */ 10053 #define RTC_INTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */ 10054 #define RTC_INTENCLR_TICK_Clear (0x1UL) /*!< Disable */ 10055 10056 /* Register: RTC_EVTEN */ 10057 /* Description: Enable or disable event routing */ 10058 10059 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */ 10060 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 10061 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 10062 #define RTC_EVTEN_COMPARE3_Disabled (0x0UL) /*!< Disable */ 10063 #define RTC_EVTEN_COMPARE3_Enabled (0x1UL) /*!< Enable */ 10064 10065 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */ 10066 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 10067 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 10068 #define RTC_EVTEN_COMPARE2_Disabled (0x0UL) /*!< Disable */ 10069 #define RTC_EVTEN_COMPARE2_Enabled (0x1UL) /*!< Enable */ 10070 10071 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */ 10072 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 10073 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 10074 #define RTC_EVTEN_COMPARE1_Disabled (0x0UL) /*!< Disable */ 10075 #define RTC_EVTEN_COMPARE1_Enabled (0x1UL) /*!< Enable */ 10076 10077 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */ 10078 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 10079 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 10080 #define RTC_EVTEN_COMPARE0_Disabled (0x0UL) /*!< Disable */ 10081 #define RTC_EVTEN_COMPARE0_Enabled (0x1UL) /*!< Enable */ 10082 10083 /* Bit 1 : Enable or disable event routing for event OVRFLW */ 10084 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 10085 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 10086 #define RTC_EVTEN_OVRFLW_Disabled (0x0UL) /*!< Disable */ 10087 #define RTC_EVTEN_OVRFLW_Enabled (0x1UL) /*!< Enable */ 10088 10089 /* Bit 0 : Enable or disable event routing for event TICK */ 10090 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ 10091 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ 10092 #define RTC_EVTEN_TICK_Disabled (0x0UL) /*!< Disable */ 10093 #define RTC_EVTEN_TICK_Enabled (0x1UL) /*!< Enable */ 10094 10095 /* Register: RTC_EVTENSET */ 10096 /* Description: Enable event routing */ 10097 10098 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ 10099 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 10100 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 10101 #define RTC_EVTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ 10102 #define RTC_EVTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ 10103 #define RTC_EVTENSET_COMPARE3_Set (0x1UL) /*!< Enable */ 10104 10105 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ 10106 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 10107 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 10108 #define RTC_EVTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ 10109 #define RTC_EVTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ 10110 #define RTC_EVTENSET_COMPARE2_Set (0x1UL) /*!< Enable */ 10111 10112 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ 10113 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 10114 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 10115 #define RTC_EVTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ 10116 #define RTC_EVTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ 10117 #define RTC_EVTENSET_COMPARE1_Set (0x1UL) /*!< Enable */ 10118 10119 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ 10120 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 10121 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 10122 #define RTC_EVTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ 10123 #define RTC_EVTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ 10124 #define RTC_EVTENSET_COMPARE0_Set (0x1UL) /*!< Enable */ 10125 10126 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */ 10127 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 10128 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 10129 #define RTC_EVTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ 10130 #define RTC_EVTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ 10131 #define RTC_EVTENSET_OVRFLW_Set (0x1UL) /*!< Enable */ 10132 10133 /* Bit 0 : Write '1' to enable event routing for event TICK */ 10134 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 10135 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 10136 #define RTC_EVTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */ 10137 #define RTC_EVTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */ 10138 #define RTC_EVTENSET_TICK_Set (0x1UL) /*!< Enable */ 10139 10140 /* Register: RTC_EVTENCLR */ 10141 /* Description: Disable event routing */ 10142 10143 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ 10144 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 10145 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 10146 #define RTC_EVTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ 10147 #define RTC_EVTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ 10148 #define RTC_EVTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */ 10149 10150 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ 10151 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 10152 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 10153 #define RTC_EVTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ 10154 #define RTC_EVTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ 10155 #define RTC_EVTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */ 10156 10157 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ 10158 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 10159 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 10160 #define RTC_EVTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ 10161 #define RTC_EVTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ 10162 #define RTC_EVTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */ 10163 10164 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ 10165 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 10166 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 10167 #define RTC_EVTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ 10168 #define RTC_EVTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ 10169 #define RTC_EVTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */ 10170 10171 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */ 10172 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 10173 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 10174 #define RTC_EVTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ 10175 #define RTC_EVTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ 10176 #define RTC_EVTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */ 10177 10178 /* Bit 0 : Write '1' to disable event routing for event TICK */ 10179 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 10180 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 10181 #define RTC_EVTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */ 10182 #define RTC_EVTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */ 10183 #define RTC_EVTENCLR_TICK_Clear (0x1UL) /*!< Disable */ 10184 10185 /* Register: RTC_COUNTER */ 10186 /* Description: Current counter value */ 10187 10188 /* Bits 23..0 : Counter value */ 10189 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ 10190 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ 10191 10192 /* Register: RTC_PRESCALER */ 10193 /* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */ 10194 10195 /* Bits 11..0 : Prescaler value */ 10196 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 10197 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 10198 10199 /* Register: RTC_CC */ 10200 /* Description: Description collection: Compare register n */ 10201 10202 /* Bits 23..0 : Compare value */ 10203 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ 10204 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ 10205 10206 10207 /* Peripheral: SAADC */ 10208 /* Description: Analog to Digital Converter 0 */ 10209 10210 /* Register: SAADC_TASKS_START */ 10211 /* Description: Start the ADC and prepare the result buffer in RAM */ 10212 10213 /* Bit 0 : Start the ADC and prepare the result buffer in RAM */ 10214 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 10215 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 10216 #define SAADC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ 10217 10218 /* Register: SAADC_TASKS_SAMPLE */ 10219 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */ 10220 10221 /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */ 10222 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ 10223 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ 10224 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */ 10225 10226 /* Register: SAADC_TASKS_STOP */ 10227 /* Description: Stop the ADC and terminate any on-going conversion */ 10228 10229 /* Bit 0 : Stop the ADC and terminate any on-going conversion */ 10230 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 10231 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 10232 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ 10233 10234 /* Register: SAADC_TASKS_CALIBRATEOFFSET */ 10235 /* Description: Starts offset auto-calibration */ 10236 10237 /* Bit 0 : Starts offset auto-calibration */ 10238 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ 10239 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ 10240 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (0x1UL) /*!< Trigger task */ 10241 10242 /* Register: SAADC_SUBSCRIBE_START */ 10243 /* Description: Subscribe configuration for task START */ 10244 10245 /* Bit 31 : */ 10246 #define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 10247 #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 10248 #define SAADC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ 10249 #define SAADC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ 10250 10251 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 10252 #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10253 #define SAADC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10254 10255 /* Register: SAADC_SUBSCRIBE_SAMPLE */ 10256 /* Description: Subscribe configuration for task SAMPLE */ 10257 10258 /* Bit 31 : */ 10259 #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */ 10260 #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */ 10261 #define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */ 10262 #define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */ 10263 10264 /* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */ 10265 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10266 #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10267 10268 /* Register: SAADC_SUBSCRIBE_STOP */ 10269 /* Description: Subscribe configuration for task STOP */ 10270 10271 /* Bit 31 : */ 10272 #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 10273 #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 10274 #define SAADC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 10275 #define SAADC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 10276 10277 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 10278 #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10279 #define SAADC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10280 10281 /* Register: SAADC_SUBSCRIBE_CALIBRATEOFFSET */ 10282 /* Description: Subscribe configuration for task CALIBRATEOFFSET */ 10283 10284 /* Bit 31 : */ 10285 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */ 10286 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */ 10287 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0x0UL) /*!< Disable subscription */ 10288 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (0x1UL) /*!< Enable subscription */ 10289 10290 /* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */ 10291 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10292 #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Msk (0xFFUL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10293 10294 /* Register: SAADC_EVENTS_STARTED */ 10295 /* Description: The ADC has started */ 10296 10297 /* Bit 0 : The ADC has started */ 10298 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 10299 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 10300 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ 10301 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ 10302 10303 /* Register: SAADC_EVENTS_END */ 10304 /* Description: The ADC has filled up the Result buffer */ 10305 10306 /* Bit 0 : The ADC has filled up the Result buffer */ 10307 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 10308 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 10309 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ 10310 #define SAADC_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ 10311 10312 /* Register: SAADC_EVENTS_DONE */ 10313 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ 10314 10315 /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ 10316 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ 10317 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ 10318 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */ 10319 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */ 10320 10321 /* Register: SAADC_EVENTS_RESULTDONE */ 10322 /* Description: A result is ready to get transferred to RAM. */ 10323 10324 /* Bit 0 : A result is ready to get transferred to RAM. */ 10325 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ 10326 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ 10327 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0x0UL) /*!< Event not generated */ 10328 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (0x1UL) /*!< Event generated */ 10329 10330 /* Register: SAADC_EVENTS_CALIBRATEDONE */ 10331 /* Description: Calibration is complete */ 10332 10333 /* Bit 0 : Calibration is complete */ 10334 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ 10335 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ 10336 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0x0UL) /*!< Event not generated */ 10337 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (0x1UL) /*!< Event generated */ 10338 10339 /* Register: SAADC_EVENTS_STOPPED */ 10340 /* Description: The ADC has stopped */ 10341 10342 /* Bit 0 : The ADC has stopped */ 10343 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 10344 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 10345 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ 10346 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ 10347 10348 /* Register: SAADC_EVENTS_CH_LIMITH */ 10349 /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */ 10350 10351 /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */ 10352 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ 10353 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ 10354 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0x0UL) /*!< Event not generated */ 10355 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (0x1UL) /*!< Event generated */ 10356 10357 /* Register: SAADC_EVENTS_CH_LIMITL */ 10358 /* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */ 10359 10360 /* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */ 10361 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ 10362 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ 10363 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0x0UL) /*!< Event not generated */ 10364 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (0x1UL) /*!< Event generated */ 10365 10366 /* Register: SAADC_PUBLISH_STARTED */ 10367 /* Description: Publish configuration for event STARTED */ 10368 10369 /* Bit 31 : */ 10370 #define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ 10371 #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ 10372 #define SAADC_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 10373 #define SAADC_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 10374 10375 /* Bits 7..0 : DPPI channel that event STARTED will publish to */ 10376 #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10377 #define SAADC_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10378 10379 /* Register: SAADC_PUBLISH_END */ 10380 /* Description: Publish configuration for event END */ 10381 10382 /* Bit 31 : */ 10383 #define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 10384 #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 10385 #define SAADC_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ 10386 #define SAADC_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ 10387 10388 /* Bits 7..0 : DPPI channel that event END will publish to */ 10389 #define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10390 #define SAADC_PUBLISH_END_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10391 10392 /* Register: SAADC_PUBLISH_DONE */ 10393 /* Description: Publish configuration for event DONE */ 10394 10395 /* Bit 31 : */ 10396 #define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */ 10397 #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */ 10398 #define SAADC_PUBLISH_DONE_EN_Disabled (0x0UL) /*!< Disable publishing */ 10399 #define SAADC_PUBLISH_DONE_EN_Enabled (0x1UL) /*!< Enable publishing */ 10400 10401 /* Bits 7..0 : DPPI channel that event DONE will publish to */ 10402 #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10403 #define SAADC_PUBLISH_DONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10404 10405 /* Register: SAADC_PUBLISH_RESULTDONE */ 10406 /* Description: Publish configuration for event RESULTDONE */ 10407 10408 /* Bit 31 : */ 10409 #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */ 10410 #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */ 10411 #define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ 10412 #define SAADC_PUBLISH_RESULTDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ 10413 10414 /* Bits 7..0 : DPPI channel that event RESULTDONE will publish to */ 10415 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10416 #define SAADC_PUBLISH_RESULTDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_RESULTDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10417 10418 /* Register: SAADC_PUBLISH_CALIBRATEDONE */ 10419 /* Description: Publish configuration for event CALIBRATEDONE */ 10420 10421 /* Bit 31 : */ 10422 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */ 10423 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */ 10424 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ 10425 #define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ 10426 10427 /* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to */ 10428 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10429 #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10430 10431 /* Register: SAADC_PUBLISH_STOPPED */ 10432 /* Description: Publish configuration for event STOPPED */ 10433 10434 /* Bit 31 : */ 10435 #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 10436 #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 10437 #define SAADC_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ 10438 #define SAADC_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ 10439 10440 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 10441 #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10442 #define SAADC_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10443 10444 /* Register: SAADC_PUBLISH_CH_LIMITH */ 10445 /* Description: Description cluster: Publish configuration for event CH[n].LIMITH */ 10446 10447 /* Bit 31 : */ 10448 #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */ 10449 #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */ 10450 #define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0x0UL) /*!< Disable publishing */ 10451 #define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (0x1UL) /*!< Enable publishing */ 10452 10453 /* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to */ 10454 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10455 #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10456 10457 /* Register: SAADC_PUBLISH_CH_LIMITL */ 10458 /* Description: Description cluster: Publish configuration for event CH[n].LIMITL */ 10459 10460 /* Bit 31 : */ 10461 #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */ 10462 #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */ 10463 #define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0x0UL) /*!< Disable publishing */ 10464 #define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (0x1UL) /*!< Enable publishing */ 10465 10466 /* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to */ 10467 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 10468 #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Msk (0xFFUL << SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 10469 10470 /* Register: SAADC_INTEN */ 10471 /* Description: Enable or disable interrupt */ 10472 10473 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ 10474 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 10475 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 10476 #define SAADC_INTEN_CH7LIMITL_Disabled (0x0UL) /*!< Disable */ 10477 #define SAADC_INTEN_CH7LIMITL_Enabled (0x1UL) /*!< Enable */ 10478 10479 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ 10480 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 10481 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 10482 #define SAADC_INTEN_CH7LIMITH_Disabled (0x0UL) /*!< Disable */ 10483 #define SAADC_INTEN_CH7LIMITH_Enabled (0x1UL) /*!< Enable */ 10484 10485 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ 10486 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 10487 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 10488 #define SAADC_INTEN_CH6LIMITL_Disabled (0x0UL) /*!< Disable */ 10489 #define SAADC_INTEN_CH6LIMITL_Enabled (0x1UL) /*!< Enable */ 10490 10491 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ 10492 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 10493 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 10494 #define SAADC_INTEN_CH6LIMITH_Disabled (0x0UL) /*!< Disable */ 10495 #define SAADC_INTEN_CH6LIMITH_Enabled (0x1UL) /*!< Enable */ 10496 10497 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ 10498 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 10499 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 10500 #define SAADC_INTEN_CH5LIMITL_Disabled (0x0UL) /*!< Disable */ 10501 #define SAADC_INTEN_CH5LIMITL_Enabled (0x1UL) /*!< Enable */ 10502 10503 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ 10504 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 10505 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 10506 #define SAADC_INTEN_CH5LIMITH_Disabled (0x0UL) /*!< Disable */ 10507 #define SAADC_INTEN_CH5LIMITH_Enabled (0x1UL) /*!< Enable */ 10508 10509 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ 10510 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 10511 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 10512 #define SAADC_INTEN_CH4LIMITL_Disabled (0x0UL) /*!< Disable */ 10513 #define SAADC_INTEN_CH4LIMITL_Enabled (0x1UL) /*!< Enable */ 10514 10515 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ 10516 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 10517 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 10518 #define SAADC_INTEN_CH4LIMITH_Disabled (0x0UL) /*!< Disable */ 10519 #define SAADC_INTEN_CH4LIMITH_Enabled (0x1UL) /*!< Enable */ 10520 10521 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ 10522 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 10523 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 10524 #define SAADC_INTEN_CH3LIMITL_Disabled (0x0UL) /*!< Disable */ 10525 #define SAADC_INTEN_CH3LIMITL_Enabled (0x1UL) /*!< Enable */ 10526 10527 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ 10528 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 10529 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 10530 #define SAADC_INTEN_CH3LIMITH_Disabled (0x0UL) /*!< Disable */ 10531 #define SAADC_INTEN_CH3LIMITH_Enabled (0x1UL) /*!< Enable */ 10532 10533 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ 10534 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 10535 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 10536 #define SAADC_INTEN_CH2LIMITL_Disabled (0x0UL) /*!< Disable */ 10537 #define SAADC_INTEN_CH2LIMITL_Enabled (0x1UL) /*!< Enable */ 10538 10539 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ 10540 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 10541 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 10542 #define SAADC_INTEN_CH2LIMITH_Disabled (0x0UL) /*!< Disable */ 10543 #define SAADC_INTEN_CH2LIMITH_Enabled (0x1UL) /*!< Enable */ 10544 10545 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ 10546 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 10547 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 10548 #define SAADC_INTEN_CH1LIMITL_Disabled (0x0UL) /*!< Disable */ 10549 #define SAADC_INTEN_CH1LIMITL_Enabled (0x1UL) /*!< Enable */ 10550 10551 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ 10552 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 10553 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 10554 #define SAADC_INTEN_CH1LIMITH_Disabled (0x0UL) /*!< Disable */ 10555 #define SAADC_INTEN_CH1LIMITH_Enabled (0x1UL) /*!< Enable */ 10556 10557 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ 10558 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 10559 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 10560 #define SAADC_INTEN_CH0LIMITL_Disabled (0x0UL) /*!< Disable */ 10561 #define SAADC_INTEN_CH0LIMITL_Enabled (0x1UL) /*!< Enable */ 10562 10563 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ 10564 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 10565 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 10566 #define SAADC_INTEN_CH0LIMITH_Disabled (0x0UL) /*!< Disable */ 10567 #define SAADC_INTEN_CH0LIMITH_Enabled (0x1UL) /*!< Enable */ 10568 10569 /* Bit 5 : Enable or disable interrupt for event STOPPED */ 10570 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 10571 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 10572 #define SAADC_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ 10573 #define SAADC_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ 10574 10575 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ 10576 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 10577 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 10578 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0x0UL) /*!< Disable */ 10579 #define SAADC_INTEN_CALIBRATEDONE_Enabled (0x1UL) /*!< Enable */ 10580 10581 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */ 10582 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 10583 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 10584 #define SAADC_INTEN_RESULTDONE_Disabled (0x0UL) /*!< Disable */ 10585 #define SAADC_INTEN_RESULTDONE_Enabled (0x1UL) /*!< Enable */ 10586 10587 /* Bit 2 : Enable or disable interrupt for event DONE */ 10588 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ 10589 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ 10590 #define SAADC_INTEN_DONE_Disabled (0x0UL) /*!< Disable */ 10591 #define SAADC_INTEN_DONE_Enabled (0x1UL) /*!< Enable */ 10592 10593 /* Bit 1 : Enable or disable interrupt for event END */ 10594 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ 10595 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ 10596 #define SAADC_INTEN_END_Disabled (0x0UL) /*!< Disable */ 10597 #define SAADC_INTEN_END_Enabled (0x1UL) /*!< Enable */ 10598 10599 /* Bit 0 : Enable or disable interrupt for event STARTED */ 10600 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 10601 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ 10602 #define SAADC_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ 10603 #define SAADC_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ 10604 10605 /* Register: SAADC_INTENSET */ 10606 /* Description: Enable interrupt */ 10607 10608 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ 10609 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 10610 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 10611 #define SAADC_INTENSET_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10612 #define SAADC_INTENSET_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10613 #define SAADC_INTENSET_CH7LIMITL_Set (0x1UL) /*!< Enable */ 10614 10615 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ 10616 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 10617 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 10618 #define SAADC_INTENSET_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10619 #define SAADC_INTENSET_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10620 #define SAADC_INTENSET_CH7LIMITH_Set (0x1UL) /*!< Enable */ 10621 10622 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ 10623 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 10624 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 10625 #define SAADC_INTENSET_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10626 #define SAADC_INTENSET_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10627 #define SAADC_INTENSET_CH6LIMITL_Set (0x1UL) /*!< Enable */ 10628 10629 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ 10630 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 10631 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 10632 #define SAADC_INTENSET_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10633 #define SAADC_INTENSET_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10634 #define SAADC_INTENSET_CH6LIMITH_Set (0x1UL) /*!< Enable */ 10635 10636 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ 10637 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 10638 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 10639 #define SAADC_INTENSET_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10640 #define SAADC_INTENSET_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10641 #define SAADC_INTENSET_CH5LIMITL_Set (0x1UL) /*!< Enable */ 10642 10643 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ 10644 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 10645 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 10646 #define SAADC_INTENSET_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10647 #define SAADC_INTENSET_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10648 #define SAADC_INTENSET_CH5LIMITH_Set (0x1UL) /*!< Enable */ 10649 10650 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ 10651 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 10652 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 10653 #define SAADC_INTENSET_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10654 #define SAADC_INTENSET_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10655 #define SAADC_INTENSET_CH4LIMITL_Set (0x1UL) /*!< Enable */ 10656 10657 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ 10658 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 10659 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 10660 #define SAADC_INTENSET_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10661 #define SAADC_INTENSET_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10662 #define SAADC_INTENSET_CH4LIMITH_Set (0x1UL) /*!< Enable */ 10663 10664 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ 10665 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 10666 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 10667 #define SAADC_INTENSET_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10668 #define SAADC_INTENSET_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10669 #define SAADC_INTENSET_CH3LIMITL_Set (0x1UL) /*!< Enable */ 10670 10671 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ 10672 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 10673 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 10674 #define SAADC_INTENSET_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10675 #define SAADC_INTENSET_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10676 #define SAADC_INTENSET_CH3LIMITH_Set (0x1UL) /*!< Enable */ 10677 10678 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ 10679 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 10680 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 10681 #define SAADC_INTENSET_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10682 #define SAADC_INTENSET_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10683 #define SAADC_INTENSET_CH2LIMITL_Set (0x1UL) /*!< Enable */ 10684 10685 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ 10686 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 10687 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 10688 #define SAADC_INTENSET_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10689 #define SAADC_INTENSET_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10690 #define SAADC_INTENSET_CH2LIMITH_Set (0x1UL) /*!< Enable */ 10691 10692 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ 10693 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 10694 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 10695 #define SAADC_INTENSET_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10696 #define SAADC_INTENSET_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10697 #define SAADC_INTENSET_CH1LIMITL_Set (0x1UL) /*!< Enable */ 10698 10699 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ 10700 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 10701 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 10702 #define SAADC_INTENSET_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10703 #define SAADC_INTENSET_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10704 #define SAADC_INTENSET_CH1LIMITH_Set (0x1UL) /*!< Enable */ 10705 10706 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ 10707 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 10708 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 10709 #define SAADC_INTENSET_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10710 #define SAADC_INTENSET_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10711 #define SAADC_INTENSET_CH0LIMITL_Set (0x1UL) /*!< Enable */ 10712 10713 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ 10714 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 10715 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 10716 #define SAADC_INTENSET_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10717 #define SAADC_INTENSET_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10718 #define SAADC_INTENSET_CH0LIMITH_Set (0x1UL) /*!< Enable */ 10719 10720 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */ 10721 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 10722 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 10723 #define SAADC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 10724 #define SAADC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 10725 #define SAADC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ 10726 10727 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ 10728 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 10729 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 10730 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */ 10731 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */ 10732 #define SAADC_INTENSET_CALIBRATEDONE_Set (0x1UL) /*!< Enable */ 10733 10734 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ 10735 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 10736 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 10737 #define SAADC_INTENSET_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */ 10738 #define SAADC_INTENSET_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */ 10739 #define SAADC_INTENSET_RESULTDONE_Set (0x1UL) /*!< Enable */ 10740 10741 /* Bit 2 : Write '1' to enable interrupt for event DONE */ 10742 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ 10743 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 10744 #define SAADC_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */ 10745 #define SAADC_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */ 10746 #define SAADC_INTENSET_DONE_Set (0x1UL) /*!< Enable */ 10747 10748 /* Bit 1 : Write '1' to enable interrupt for event END */ 10749 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 10750 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ 10751 #define SAADC_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ 10752 #define SAADC_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ 10753 #define SAADC_INTENSET_END_Set (0x1UL) /*!< Enable */ 10754 10755 /* Bit 0 : Write '1' to enable interrupt for event STARTED */ 10756 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 10757 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 10758 #define SAADC_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ 10759 #define SAADC_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ 10760 #define SAADC_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ 10761 10762 /* Register: SAADC_INTENCLR */ 10763 /* Description: Disable interrupt */ 10764 10765 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ 10766 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 10767 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 10768 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10769 #define SAADC_INTENCLR_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10770 #define SAADC_INTENCLR_CH7LIMITL_Clear (0x1UL) /*!< Disable */ 10771 10772 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ 10773 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 10774 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 10775 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10776 #define SAADC_INTENCLR_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10777 #define SAADC_INTENCLR_CH7LIMITH_Clear (0x1UL) /*!< Disable */ 10778 10779 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ 10780 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 10781 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 10782 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10783 #define SAADC_INTENCLR_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10784 #define SAADC_INTENCLR_CH6LIMITL_Clear (0x1UL) /*!< Disable */ 10785 10786 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ 10787 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 10788 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 10789 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10790 #define SAADC_INTENCLR_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10791 #define SAADC_INTENCLR_CH6LIMITH_Clear (0x1UL) /*!< Disable */ 10792 10793 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ 10794 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 10795 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 10796 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10797 #define SAADC_INTENCLR_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10798 #define SAADC_INTENCLR_CH5LIMITL_Clear (0x1UL) /*!< Disable */ 10799 10800 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ 10801 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 10802 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 10803 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10804 #define SAADC_INTENCLR_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10805 #define SAADC_INTENCLR_CH5LIMITH_Clear (0x1UL) /*!< Disable */ 10806 10807 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ 10808 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 10809 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 10810 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10811 #define SAADC_INTENCLR_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10812 #define SAADC_INTENCLR_CH4LIMITL_Clear (0x1UL) /*!< Disable */ 10813 10814 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ 10815 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 10816 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 10817 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10818 #define SAADC_INTENCLR_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10819 #define SAADC_INTENCLR_CH4LIMITH_Clear (0x1UL) /*!< Disable */ 10820 10821 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ 10822 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 10823 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 10824 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10825 #define SAADC_INTENCLR_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10826 #define SAADC_INTENCLR_CH3LIMITL_Clear (0x1UL) /*!< Disable */ 10827 10828 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ 10829 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 10830 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 10831 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10832 #define SAADC_INTENCLR_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10833 #define SAADC_INTENCLR_CH3LIMITH_Clear (0x1UL) /*!< Disable */ 10834 10835 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ 10836 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 10837 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 10838 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10839 #define SAADC_INTENCLR_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10840 #define SAADC_INTENCLR_CH2LIMITL_Clear (0x1UL) /*!< Disable */ 10841 10842 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ 10843 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 10844 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 10845 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10846 #define SAADC_INTENCLR_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10847 #define SAADC_INTENCLR_CH2LIMITH_Clear (0x1UL) /*!< Disable */ 10848 10849 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ 10850 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 10851 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 10852 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10853 #define SAADC_INTENCLR_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10854 #define SAADC_INTENCLR_CH1LIMITL_Clear (0x1UL) /*!< Disable */ 10855 10856 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ 10857 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 10858 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 10859 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10860 #define SAADC_INTENCLR_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10861 #define SAADC_INTENCLR_CH1LIMITH_Clear (0x1UL) /*!< Disable */ 10862 10863 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ 10864 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 10865 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 10866 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ 10867 #define SAADC_INTENCLR_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ 10868 #define SAADC_INTENCLR_CH0LIMITL_Clear (0x1UL) /*!< Disable */ 10869 10870 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ 10871 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 10872 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 10873 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ 10874 #define SAADC_INTENCLR_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ 10875 #define SAADC_INTENCLR_CH0LIMITH_Clear (0x1UL) /*!< Disable */ 10876 10877 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */ 10878 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 10879 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 10880 #define SAADC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 10881 #define SAADC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 10882 #define SAADC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ 10883 10884 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ 10885 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 10886 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 10887 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */ 10888 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */ 10889 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (0x1UL) /*!< Disable */ 10890 10891 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ 10892 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 10893 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 10894 #define SAADC_INTENCLR_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */ 10895 #define SAADC_INTENCLR_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */ 10896 #define SAADC_INTENCLR_RESULTDONE_Clear (0x1UL) /*!< Disable */ 10897 10898 /* Bit 2 : Write '1' to disable interrupt for event DONE */ 10899 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ 10900 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 10901 #define SAADC_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */ 10902 #define SAADC_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */ 10903 #define SAADC_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */ 10904 10905 /* Bit 1 : Write '1' to disable interrupt for event END */ 10906 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 10907 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 10908 #define SAADC_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ 10909 #define SAADC_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ 10910 #define SAADC_INTENCLR_END_Clear (0x1UL) /*!< Disable */ 10911 10912 /* Bit 0 : Write '1' to disable interrupt for event STARTED */ 10913 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 10914 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 10915 #define SAADC_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ 10916 #define SAADC_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ 10917 #define SAADC_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ 10918 10919 /* Register: SAADC_STATUS */ 10920 /* Description: Status */ 10921 10922 /* Bit 0 : Status */ 10923 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 10924 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 10925 #define SAADC_STATUS_STATUS_Ready (0x0UL) /*!< ADC is ready. No on-going conversion. */ 10926 #define SAADC_STATUS_STATUS_Busy (0x1UL) /*!< ADC is busy. Single conversion in progress. */ 10927 10928 /* Register: SAADC_ENABLE */ 10929 /* Description: Enable or disable ADC */ 10930 10931 /* Bit 0 : Enable or disable ADC */ 10932 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 10933 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 10934 #define SAADC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable ADC */ 10935 #define SAADC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable ADC */ 10936 10937 /* Register: SAADC_CH_PSELP */ 10938 /* Description: Description cluster: Input positive pin selection for CH[n] */ 10939 10940 /* Bits 4..0 : Analog positive input channel */ 10941 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ 10942 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ 10943 #define SAADC_CH_PSELP_PSELP_NC (0x00UL) /*!< Not connected */ 10944 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (0x01UL) /*!< AIN0 */ 10945 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (0x02UL) /*!< AIN1 */ 10946 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (0x03UL) /*!< AIN2 */ 10947 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (0x04UL) /*!< AIN3 */ 10948 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (0x05UL) /*!< AIN4 */ 10949 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (0x06UL) /*!< AIN5 */ 10950 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (0x07UL) /*!< AIN6 */ 10951 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (0x08UL) /*!< AIN7 */ 10952 #define SAADC_CH_PSELP_PSELP_VDDGPIO (0x09UL) /*!< VDD_GPIO */ 10953 10954 /* Register: SAADC_CH_PSELN */ 10955 /* Description: Description cluster: Input negative pin selection for CH[n] */ 10956 10957 /* Bits 4..0 : Analog negative input, enables differential channel */ 10958 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ 10959 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ 10960 #define SAADC_CH_PSELN_PSELN_NC (0x00UL) /*!< Not connected */ 10961 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (0x01UL) /*!< AIN0 */ 10962 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (0x02UL) /*!< AIN1 */ 10963 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (0x03UL) /*!< AIN2 */ 10964 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (0x04UL) /*!< AIN3 */ 10965 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (0x05UL) /*!< AIN4 */ 10966 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (0x06UL) /*!< AIN5 */ 10967 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (0x07UL) /*!< AIN6 */ 10968 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (0x08UL) /*!< AIN7 */ 10969 #define SAADC_CH_PSELN_PSELN_VDD_GPIO (0x09UL) /*!< VDD_GPIO */ 10970 10971 /* Register: SAADC_CH_CONFIG */ 10972 /* Description: Description cluster: Input configuration for CH[n] */ 10973 10974 /* Bit 24 : Enable burst mode */ 10975 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ 10976 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ 10977 #define SAADC_CH_CONFIG_BURST_Disabled (0x0UL) /*!< Burst mode is disabled (normal operation) */ 10978 #define SAADC_CH_CONFIG_BURST_Enabled (0x1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ 10979 10980 /* Bit 20 : Enable differential mode */ 10981 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ 10982 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 10983 #define SAADC_CH_CONFIG_MODE_SE (0x0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ 10984 #define SAADC_CH_CONFIG_MODE_Diff (0x1UL) /*!< Differential */ 10985 10986 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ 10987 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ 10988 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ 10989 #define SAADC_CH_CONFIG_TACQ_3us (0x0UL) /*!< 3 us */ 10990 #define SAADC_CH_CONFIG_TACQ_5us (0x1UL) /*!< 5 us */ 10991 #define SAADC_CH_CONFIG_TACQ_10us (0x2UL) /*!< 10 us */ 10992 #define SAADC_CH_CONFIG_TACQ_15us (0x3UL) /*!< 15 us */ 10993 #define SAADC_CH_CONFIG_TACQ_20us (0x4UL) /*!< 20 us */ 10994 #define SAADC_CH_CONFIG_TACQ_40us (0x5UL) /*!< 40 us */ 10995 10996 /* Bit 12 : Reference control */ 10997 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ 10998 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 10999 #define SAADC_CH_CONFIG_REFSEL_Internal (0x0UL) /*!< Internal reference (0.6 V) */ 11000 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (0x1UL) /*!< VDD_GPIO/4 as reference */ 11001 11002 /* Bits 10..8 : Gain control */ 11003 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ 11004 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ 11005 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0x0UL) /*!< 1/6 */ 11006 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (0x1UL) /*!< 1/5 */ 11007 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (0x2UL) /*!< 1/4 */ 11008 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (0x3UL) /*!< 1/3 */ 11009 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (0x4UL) /*!< 1/2 */ 11010 #define SAADC_CH_CONFIG_GAIN_Gain1 (0x5UL) /*!< 1 */ 11011 #define SAADC_CH_CONFIG_GAIN_Gain2 (0x6UL) /*!< 2 */ 11012 #define SAADC_CH_CONFIG_GAIN_Gain4 (0x7UL) /*!< 4 */ 11013 11014 /* Bits 5..4 : Negative channel resistor control */ 11015 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ 11016 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ 11017 #define SAADC_CH_CONFIG_RESN_Bypass (0x0UL) /*!< Bypass resistor ladder */ 11018 #define SAADC_CH_CONFIG_RESN_Pulldown (0x1UL) /*!< Pull-down to GND */ 11019 #define SAADC_CH_CONFIG_RESN_Pullup (0x2UL) /*!< Pull-up to VDD_GPIO */ 11020 #define SAADC_CH_CONFIG_RESN_VDD1_2 (0x3UL) /*!< Set input at VDD_GPIO/2 */ 11021 11022 /* Bits 1..0 : Positive channel resistor control */ 11023 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ 11024 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ 11025 #define SAADC_CH_CONFIG_RESP_Bypass (0x0UL) /*!< Bypass resistor ladder */ 11026 #define SAADC_CH_CONFIG_RESP_Pulldown (0x1UL) /*!< Pull-down to GND */ 11027 #define SAADC_CH_CONFIG_RESP_Pullup (0x2UL) /*!< Pull-up to VDD_GPIO */ 11028 #define SAADC_CH_CONFIG_RESP_VDD1_2 (0x3UL) /*!< Set input at VDD_GPIO/2 */ 11029 11030 /* Register: SAADC_CH_LIMIT */ 11031 /* Description: Description cluster: High/low limits for event monitoring a channel */ 11032 11033 /* Bits 31..16 : High level limit */ 11034 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ 11035 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ 11036 11037 /* Bits 15..0 : Low level limit */ 11038 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ 11039 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ 11040 11041 /* Register: SAADC_RESOLUTION */ 11042 /* Description: Resolution configuration */ 11043 11044 /* Bits 2..0 : Set the resolution */ 11045 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ 11046 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ 11047 #define SAADC_RESOLUTION_VAL_8bit (0x0UL) /*!< 8 bit */ 11048 #define SAADC_RESOLUTION_VAL_10bit (0x1UL) /*!< 10 bit */ 11049 #define SAADC_RESOLUTION_VAL_12bit (0x2UL) /*!< 12 bit */ 11050 #define SAADC_RESOLUTION_VAL_14bit (0x3UL) /*!< 14 bit */ 11051 11052 /* Register: SAADC_OVERSAMPLE */ 11053 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ 11054 11055 /* Bits 3..0 : Oversample control */ 11056 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ 11057 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ 11058 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0x0UL) /*!< Bypass oversampling */ 11059 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (0x1UL) /*!< Oversample 2x */ 11060 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (0x2UL) /*!< Oversample 4x */ 11061 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (0x3UL) /*!< Oversample 8x */ 11062 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (0x4UL) /*!< Oversample 16x */ 11063 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (0x5UL) /*!< Oversample 32x */ 11064 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (0x6UL) /*!< Oversample 64x */ 11065 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (0x7UL) /*!< Oversample 128x */ 11066 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (0x8UL) /*!< Oversample 256x */ 11067 11068 /* Register: SAADC_SAMPLERATE */ 11069 /* Description: Controls normal or continuous sample rate */ 11070 11071 /* Bit 12 : Select mode for sample rate control */ 11072 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ 11073 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ 11074 #define SAADC_SAMPLERATE_MODE_Task (0x0UL) /*!< Rate is controlled from SAMPLE task */ 11075 #define SAADC_SAMPLERATE_MODE_Timers (0x1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ 11076 11077 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ 11078 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ 11079 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ 11080 11081 /* Register: SAADC_RESULT_PTR */ 11082 /* Description: Data pointer */ 11083 11084 /* Bits 31..0 : Data pointer */ 11085 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 11086 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 11087 11088 /* Register: SAADC_RESULT_MAXCNT */ 11089 /* Description: Maximum number of buffer words to transfer */ 11090 11091 /* Bits 14..0 : Maximum number of buffer words to transfer */ 11092 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 11093 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 11094 11095 /* Register: SAADC_RESULT_AMOUNT */ 11096 /* Description: Number of buffer words transferred since last START */ 11097 11098 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ 11099 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 11100 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 11101 11102 11103 /* Peripheral: SPIM */ 11104 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */ 11105 11106 /* Register: SPIM_TASKS_START */ 11107 /* Description: Start SPI transaction */ 11108 11109 /* Bit 0 : Start SPI transaction */ 11110 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 11111 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 11112 #define SPIM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ 11113 11114 /* Register: SPIM_TASKS_STOP */ 11115 /* Description: Stop SPI transaction */ 11116 11117 /* Bit 0 : Stop SPI transaction */ 11118 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 11119 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 11120 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ 11121 11122 /* Register: SPIM_TASKS_SUSPEND */ 11123 /* Description: Suspend SPI transaction */ 11124 11125 /* Bit 0 : Suspend SPI transaction */ 11126 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 11127 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 11128 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ 11129 11130 /* Register: SPIM_TASKS_RESUME */ 11131 /* Description: Resume SPI transaction */ 11132 11133 /* Bit 0 : Resume SPI transaction */ 11134 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 11135 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 11136 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ 11137 11138 /* Register: SPIM_SUBSCRIBE_START */ 11139 /* Description: Subscribe configuration for task START */ 11140 11141 /* Bit 31 : */ 11142 #define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 11143 #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 11144 #define SPIM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ 11145 #define SPIM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ 11146 11147 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 11148 #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11149 #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11150 11151 /* Register: SPIM_SUBSCRIBE_STOP */ 11152 /* Description: Subscribe configuration for task STOP */ 11153 11154 /* Bit 31 : */ 11155 #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 11156 #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 11157 #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 11158 #define SPIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 11159 11160 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 11161 #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11162 #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11163 11164 /* Register: SPIM_SUBSCRIBE_SUSPEND */ 11165 /* Description: Subscribe configuration for task SUSPEND */ 11166 11167 /* Bit 31 : */ 11168 #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ 11169 #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ 11170 #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ 11171 #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ 11172 11173 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ 11174 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11175 #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11176 11177 /* Register: SPIM_SUBSCRIBE_RESUME */ 11178 /* Description: Subscribe configuration for task RESUME */ 11179 11180 /* Bit 31 : */ 11181 #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ 11182 #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ 11183 #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ 11184 #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ 11185 11186 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ 11187 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11188 #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11189 11190 /* Register: SPIM_EVENTS_STOPPED */ 11191 /* Description: SPI transaction has stopped */ 11192 11193 /* Bit 0 : SPI transaction has stopped */ 11194 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 11195 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 11196 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ 11197 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ 11198 11199 /* Register: SPIM_EVENTS_ENDRX */ 11200 /* Description: End of RXD buffer reached */ 11201 11202 /* Bit 0 : End of RXD buffer reached */ 11203 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 11204 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 11205 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */ 11206 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */ 11207 11208 /* Register: SPIM_EVENTS_END */ 11209 /* Description: End of RXD buffer and TXD buffer reached */ 11210 11211 /* Bit 0 : End of RXD buffer and TXD buffer reached */ 11212 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 11213 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 11214 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ 11215 #define SPIM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ 11216 11217 /* Register: SPIM_EVENTS_ENDTX */ 11218 /* Description: End of TXD buffer reached */ 11219 11220 /* Bit 0 : End of TXD buffer reached */ 11221 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ 11222 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ 11223 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */ 11224 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */ 11225 11226 /* Register: SPIM_EVENTS_STARTED */ 11227 /* Description: Transaction started */ 11228 11229 /* Bit 0 : Transaction started */ 11230 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ 11231 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ 11232 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ 11233 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ 11234 11235 /* Register: SPIM_PUBLISH_STOPPED */ 11236 /* Description: Publish configuration for event STOPPED */ 11237 11238 /* Bit 31 : */ 11239 #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 11240 #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 11241 #define SPIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ 11242 #define SPIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ 11243 11244 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 11245 #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11246 #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11247 11248 /* Register: SPIM_PUBLISH_ENDRX */ 11249 /* Description: Publish configuration for event ENDRX */ 11250 11251 /* Bit 31 : */ 11252 #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ 11253 #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ 11254 #define SPIM_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */ 11255 #define SPIM_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */ 11256 11257 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */ 11258 #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11259 #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11260 11261 /* Register: SPIM_PUBLISH_END */ 11262 /* Description: Publish configuration for event END */ 11263 11264 /* Bit 31 : */ 11265 #define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 11266 #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 11267 #define SPIM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ 11268 #define SPIM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ 11269 11270 /* Bits 7..0 : DPPI channel that event END will publish to */ 11271 #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11272 #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11273 11274 /* Register: SPIM_PUBLISH_ENDTX */ 11275 /* Description: Publish configuration for event ENDTX */ 11276 11277 /* Bit 31 : */ 11278 #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */ 11279 #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */ 11280 #define SPIM_PUBLISH_ENDTX_EN_Disabled (0x0UL) /*!< Disable publishing */ 11281 #define SPIM_PUBLISH_ENDTX_EN_Enabled (0x1UL) /*!< Enable publishing */ 11282 11283 /* Bits 7..0 : DPPI channel that event ENDTX will publish to */ 11284 #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11285 #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11286 11287 /* Register: SPIM_PUBLISH_STARTED */ 11288 /* Description: Publish configuration for event STARTED */ 11289 11290 /* Bit 31 : */ 11291 #define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ 11292 #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ 11293 #define SPIM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 11294 #define SPIM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 11295 11296 /* Bits 7..0 : DPPI channel that event STARTED will publish to */ 11297 #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11298 #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11299 11300 /* Register: SPIM_SHORTS */ 11301 /* Description: Shortcuts between local events and tasks */ 11302 11303 /* Bit 17 : Shortcut between event END and task START */ 11304 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ 11305 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 11306 #define SPIM_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */ 11307 #define SPIM_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */ 11308 11309 /* Register: SPIM_INTENSET */ 11310 /* Description: Enable interrupt */ 11311 11312 /* Bit 19 : Write '1' to enable interrupt for event STARTED */ 11313 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 11314 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 11315 #define SPIM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ 11316 #define SPIM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ 11317 #define SPIM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ 11318 11319 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */ 11320 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 11321 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 11322 #define SPIM_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */ 11323 #define SPIM_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */ 11324 #define SPIM_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */ 11325 11326 /* Bit 6 : Write '1' to enable interrupt for event END */ 11327 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ 11328 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 11329 #define SPIM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ 11330 #define SPIM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ 11331 #define SPIM_INTENSET_END_Set (0x1UL) /*!< Enable */ 11332 11333 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ 11334 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 11335 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 11336 #define SPIM_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ 11337 #define SPIM_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ 11338 #define SPIM_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */ 11339 11340 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 11341 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 11342 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 11343 #define SPIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 11344 #define SPIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 11345 #define SPIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ 11346 11347 /* Register: SPIM_INTENCLR */ 11348 /* Description: Disable interrupt */ 11349 11350 /* Bit 19 : Write '1' to disable interrupt for event STARTED */ 11351 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 11352 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 11353 #define SPIM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ 11354 #define SPIM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ 11355 #define SPIM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ 11356 11357 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */ 11358 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 11359 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 11360 #define SPIM_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */ 11361 #define SPIM_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */ 11362 #define SPIM_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */ 11363 11364 /* Bit 6 : Write '1' to disable interrupt for event END */ 11365 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ 11366 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 11367 #define SPIM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ 11368 #define SPIM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ 11369 #define SPIM_INTENCLR_END_Clear (0x1UL) /*!< Disable */ 11370 11371 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ 11372 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 11373 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 11374 #define SPIM_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ 11375 #define SPIM_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ 11376 #define SPIM_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */ 11377 11378 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 11379 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 11380 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 11381 #define SPIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 11382 #define SPIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 11383 #define SPIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ 11384 11385 /* Register: SPIM_ENABLE */ 11386 /* Description: Enable SPIM */ 11387 11388 /* Bits 3..0 : Enable or disable SPIM */ 11389 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 11390 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 11391 #define SPIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPIM */ 11392 #define SPIM_ENABLE_ENABLE_Enabled (0x7UL) /*!< Enable SPIM */ 11393 11394 /* Register: SPIM_PSEL_SCK */ 11395 /* Description: Pin select for SCK */ 11396 11397 /* Bit 31 : Connection */ 11398 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 11399 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 11400 #define SPIM_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ 11401 #define SPIM_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 11402 11403 /* Bits 4..0 : Pin number */ 11404 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 11405 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 11406 11407 /* Register: SPIM_PSEL_MOSI */ 11408 /* Description: Pin select for MOSI signal */ 11409 11410 /* Bit 31 : Connection */ 11411 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 11412 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 11413 #define SPIM_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */ 11414 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 11415 11416 /* Bits 4..0 : Pin number */ 11417 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 11418 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 11419 11420 /* Register: SPIM_PSEL_MISO */ 11421 /* Description: Pin select for MISO signal */ 11422 11423 /* Bit 31 : Connection */ 11424 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 11425 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 11426 #define SPIM_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */ 11427 #define SPIM_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 11428 11429 /* Bits 4..0 : Pin number */ 11430 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 11431 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 11432 11433 /* Register: SPIM_FREQUENCY */ 11434 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ 11435 11436 /* Bits 31..0 : SPI master data rate */ 11437 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 11438 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 11439 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ 11440 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 11441 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ 11442 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ 11443 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ 11444 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ 11445 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ 11446 11447 /* Register: SPIM_RXD_PTR */ 11448 /* Description: Data pointer */ 11449 11450 /* Bits 31..0 : Data pointer */ 11451 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 11452 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 11453 11454 /* Register: SPIM_RXD_MAXCNT */ 11455 /* Description: Maximum number of bytes in receive buffer */ 11456 11457 /* Bits 12..0 : Maximum number of bytes in receive buffer */ 11458 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 11459 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 11460 11461 /* Register: SPIM_RXD_AMOUNT */ 11462 /* Description: Number of bytes transferred in the last transaction */ 11463 11464 /* Bits 12..0 : Number of bytes transferred in the last transaction */ 11465 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 11466 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 11467 11468 /* Register: SPIM_RXD_LIST */ 11469 /* Description: EasyDMA list type */ 11470 11471 /* Bits 1..0 : List type */ 11472 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 11473 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 11474 #define SPIM_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ 11475 #define SPIM_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ 11476 11477 /* Register: SPIM_TXD_PTR */ 11478 /* Description: Data pointer */ 11479 11480 /* Bits 31..0 : Data pointer */ 11481 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 11482 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 11483 11484 /* Register: SPIM_TXD_MAXCNT */ 11485 /* Description: Maximum number of bytes in transmit buffer */ 11486 11487 /* Bits 12..0 : Maximum number of bytes in transmit buffer */ 11488 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 11489 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 11490 11491 /* Register: SPIM_TXD_AMOUNT */ 11492 /* Description: Number of bytes transferred in the last transaction */ 11493 11494 /* Bits 12..0 : Number of bytes transferred in the last transaction */ 11495 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 11496 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 11497 11498 /* Register: SPIM_TXD_LIST */ 11499 /* Description: EasyDMA list type */ 11500 11501 /* Bits 1..0 : List type */ 11502 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 11503 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 11504 #define SPIM_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ 11505 #define SPIM_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ 11506 11507 /* Register: SPIM_CONFIG */ 11508 /* Description: Configuration register */ 11509 11510 /* Bit 2 : Serial clock (SCK) polarity */ 11511 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 11512 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 11513 #define SPIM_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */ 11514 #define SPIM_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */ 11515 11516 /* Bit 1 : Serial clock (SCK) phase */ 11517 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 11518 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 11519 #define SPIM_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 11520 #define SPIM_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 11521 11522 /* Bit 0 : Bit order */ 11523 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 11524 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 11525 #define SPIM_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */ 11526 #define SPIM_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */ 11527 11528 /* Register: SPIM_ORC */ 11529 /* Description: Over-read character. Character clocked out in case an over-read of the TXD buffer. */ 11530 11531 /* Bits 7..0 : Over-read character. Character clocked out in case an over-read of the TXD buffer. */ 11532 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 11533 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 11534 11535 11536 /* Peripheral: SPIS */ 11537 /* Description: SPI Slave 0 */ 11538 11539 /* Register: SPIS_TASKS_ACQUIRE */ 11540 /* Description: Acquire SPI semaphore */ 11541 11542 /* Bit 0 : Acquire SPI semaphore */ 11543 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ 11544 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ 11545 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (0x1UL) /*!< Trigger task */ 11546 11547 /* Register: SPIS_TASKS_RELEASE */ 11548 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ 11549 11550 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ 11551 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ 11552 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ 11553 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (0x1UL) /*!< Trigger task */ 11554 11555 /* Register: SPIS_SUBSCRIBE_ACQUIRE */ 11556 /* Description: Subscribe configuration for task ACQUIRE */ 11557 11558 /* Bit 31 : */ 11559 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */ 11560 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */ 11561 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0x0UL) /*!< Disable subscription */ 11562 #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (0x1UL) /*!< Enable subscription */ 11563 11564 /* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */ 11565 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11566 #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11567 11568 /* Register: SPIS_SUBSCRIBE_RELEASE */ 11569 /* Description: Subscribe configuration for task RELEASE */ 11570 11571 /* Bit 31 : */ 11572 #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */ 11573 #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */ 11574 #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0x0UL) /*!< Disable subscription */ 11575 #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (0x1UL) /*!< Enable subscription */ 11576 11577 /* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */ 11578 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11579 #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11580 11581 /* Register: SPIS_EVENTS_END */ 11582 /* Description: Granted transaction completed */ 11583 11584 /* Bit 0 : Granted transaction completed */ 11585 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 11586 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 11587 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ 11588 #define SPIS_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ 11589 11590 /* Register: SPIS_EVENTS_ENDRX */ 11591 /* Description: End of RXD buffer reached */ 11592 11593 /* Bit 0 : End of RXD buffer reached */ 11594 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 11595 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 11596 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */ 11597 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */ 11598 11599 /* Register: SPIS_EVENTS_ACQUIRED */ 11600 /* Description: Semaphore acquired */ 11601 11602 /* Bit 0 : Semaphore acquired */ 11603 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ 11604 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ 11605 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0x0UL) /*!< Event not generated */ 11606 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (0x1UL) /*!< Event generated */ 11607 11608 /* Register: SPIS_PUBLISH_END */ 11609 /* Description: Publish configuration for event END */ 11610 11611 /* Bit 31 : */ 11612 #define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 11613 #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 11614 #define SPIS_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ 11615 #define SPIS_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ 11616 11617 /* Bits 7..0 : DPPI channel that event END will publish to */ 11618 #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11619 #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11620 11621 /* Register: SPIS_PUBLISH_ENDRX */ 11622 /* Description: Publish configuration for event ENDRX */ 11623 11624 /* Bit 31 : */ 11625 #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ 11626 #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ 11627 #define SPIS_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */ 11628 #define SPIS_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */ 11629 11630 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */ 11631 #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11632 #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11633 11634 /* Register: SPIS_PUBLISH_ACQUIRED */ 11635 /* Description: Publish configuration for event ACQUIRED */ 11636 11637 /* Bit 31 : */ 11638 #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */ 11639 #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */ 11640 #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0x0UL) /*!< Disable publishing */ 11641 #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (0x1UL) /*!< Enable publishing */ 11642 11643 /* Bits 7..0 : DPPI channel that event ACQUIRED will publish to */ 11644 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11645 #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11646 11647 /* Register: SPIS_SHORTS */ 11648 /* Description: Shortcuts between local events and tasks */ 11649 11650 /* Bit 2 : Shortcut between event END and task ACQUIRE */ 11651 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ 11652 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ 11653 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0x0UL) /*!< Disable shortcut */ 11654 #define SPIS_SHORTS_END_ACQUIRE_Enabled (0x1UL) /*!< Enable shortcut */ 11655 11656 /* Register: SPIS_INTENSET */ 11657 /* Description: Enable interrupt */ 11658 11659 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ 11660 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 11661 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 11662 #define SPIS_INTENSET_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */ 11663 #define SPIS_INTENSET_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */ 11664 #define SPIS_INTENSET_ACQUIRED_Set (0x1UL) /*!< Enable */ 11665 11666 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ 11667 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 11668 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 11669 #define SPIS_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ 11670 #define SPIS_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ 11671 #define SPIS_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */ 11672 11673 /* Bit 1 : Write '1' to enable interrupt for event END */ 11674 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 11675 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ 11676 #define SPIS_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ 11677 #define SPIS_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ 11678 #define SPIS_INTENSET_END_Set (0x1UL) /*!< Enable */ 11679 11680 /* Register: SPIS_INTENCLR */ 11681 /* Description: Disable interrupt */ 11682 11683 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ 11684 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 11685 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 11686 #define SPIS_INTENCLR_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */ 11687 #define SPIS_INTENCLR_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */ 11688 #define SPIS_INTENCLR_ACQUIRED_Clear (0x1UL) /*!< Disable */ 11689 11690 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ 11691 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 11692 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 11693 #define SPIS_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ 11694 #define SPIS_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ 11695 #define SPIS_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */ 11696 11697 /* Bit 1 : Write '1' to disable interrupt for event END */ 11698 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 11699 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 11700 #define SPIS_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ 11701 #define SPIS_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ 11702 #define SPIS_INTENCLR_END_Clear (0x1UL) /*!< Disable */ 11703 11704 /* Register: SPIS_SEMSTAT */ 11705 /* Description: Semaphore status register */ 11706 11707 /* Bits 1..0 : Semaphore status */ 11708 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ 11709 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ 11710 #define SPIS_SEMSTAT_SEMSTAT_Free (0x0UL) /*!< Semaphore is free */ 11711 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x1UL) /*!< Semaphore is assigned to CPU */ 11712 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x2UL) /*!< Semaphore is assigned to SPI slave */ 11713 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ 11714 11715 /* Register: SPIS_STATUS */ 11716 /* Description: Status from last transaction */ 11717 11718 /* Bit 1 : RX buffer overflow detected, and prevented */ 11719 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ 11720 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 11721 #define SPIS_STATUS_OVERFLOW_NotPresent (0x0UL) /*!< Read: error not present */ 11722 #define SPIS_STATUS_OVERFLOW_Present (0x1UL) /*!< Read: error present */ 11723 #define SPIS_STATUS_OVERFLOW_Clear (0x1UL) /*!< Write: clear error on writing '1' */ 11724 11725 /* Bit 0 : TX buffer over-read detected, and prevented */ 11726 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ 11727 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 11728 #define SPIS_STATUS_OVERREAD_NotPresent (0x0UL) /*!< Read: error not present */ 11729 #define SPIS_STATUS_OVERREAD_Present (0x1UL) /*!< Read: error present */ 11730 #define SPIS_STATUS_OVERREAD_Clear (0x1UL) /*!< Write: clear error on writing '1' */ 11731 11732 /* Register: SPIS_ENABLE */ 11733 /* Description: Enable SPI slave */ 11734 11735 /* Bits 3..0 : Enable or disable SPI slave */ 11736 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 11737 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 11738 #define SPIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPI slave */ 11739 #define SPIS_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable SPI slave */ 11740 11741 /* Register: SPIS_PSEL_SCK */ 11742 /* Description: Pin select for SCK */ 11743 11744 /* Bit 31 : Connection */ 11745 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 11746 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 11747 #define SPIS_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ 11748 #define SPIS_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 11749 11750 /* Bits 4..0 : Pin number */ 11751 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 11752 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 11753 11754 /* Register: SPIS_PSEL_MISO */ 11755 /* Description: Pin select for MISO signal */ 11756 11757 /* Bit 31 : Connection */ 11758 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 11759 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 11760 #define SPIS_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */ 11761 #define SPIS_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 11762 11763 /* Bits 4..0 : Pin number */ 11764 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 11765 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 11766 11767 /* Register: SPIS_PSEL_MOSI */ 11768 /* Description: Pin select for MOSI signal */ 11769 11770 /* Bit 31 : Connection */ 11771 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 11772 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 11773 #define SPIS_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */ 11774 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 11775 11776 /* Bits 4..0 : Pin number */ 11777 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 11778 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 11779 11780 /* Register: SPIS_PSEL_CSN */ 11781 /* Description: Pin select for CSN signal */ 11782 11783 /* Bit 31 : Connection */ 11784 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 11785 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 11786 #define SPIS_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */ 11787 #define SPIS_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 11788 11789 /* Bits 4..0 : Pin number */ 11790 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ 11791 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ 11792 11793 /* Register: SPIS_RXD_PTR */ 11794 /* Description: RXD data pointer */ 11795 11796 /* Bits 31..0 : RXD data pointer */ 11797 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 11798 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 11799 11800 /* Register: SPIS_RXD_MAXCNT */ 11801 /* Description: Maximum number of bytes in receive buffer */ 11802 11803 /* Bits 12..0 : Maximum number of bytes in receive buffer */ 11804 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 11805 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 11806 11807 /* Register: SPIS_RXD_AMOUNT */ 11808 /* Description: Number of bytes received in last granted transaction */ 11809 11810 /* Bits 12..0 : Number of bytes received in the last granted transaction */ 11811 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 11812 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 11813 11814 /* Register: SPIS_RXD_LIST */ 11815 /* Description: EasyDMA list type */ 11816 11817 /* Bits 1..0 : List type */ 11818 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 11819 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 11820 #define SPIS_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ 11821 #define SPIS_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ 11822 11823 /* Register: SPIS_TXD_PTR */ 11824 /* Description: TXD data pointer */ 11825 11826 /* Bits 31..0 : TXD data pointer */ 11827 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 11828 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 11829 11830 /* Register: SPIS_TXD_MAXCNT */ 11831 /* Description: Maximum number of bytes in transmit buffer */ 11832 11833 /* Bits 12..0 : Maximum number of bytes in transmit buffer */ 11834 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 11835 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 11836 11837 /* Register: SPIS_TXD_AMOUNT */ 11838 /* Description: Number of bytes transmitted in last granted transaction */ 11839 11840 /* Bits 12..0 : Number of bytes transmitted in last granted transaction */ 11841 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 11842 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 11843 11844 /* Register: SPIS_TXD_LIST */ 11845 /* Description: EasyDMA list type */ 11846 11847 /* Bits 1..0 : List type */ 11848 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 11849 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 11850 #define SPIS_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ 11851 #define SPIS_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ 11852 11853 /* Register: SPIS_CONFIG */ 11854 /* Description: Configuration register */ 11855 11856 /* Bit 2 : Serial clock (SCK) polarity */ 11857 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 11858 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 11859 #define SPIS_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */ 11860 #define SPIS_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */ 11861 11862 /* Bit 1 : Serial clock (SCK) phase */ 11863 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 11864 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 11865 #define SPIS_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 11866 #define SPIS_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 11867 11868 /* Bit 0 : Bit order */ 11869 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 11870 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 11871 #define SPIS_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */ 11872 #define SPIS_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */ 11873 11874 /* Register: SPIS_DEF */ 11875 /* Description: Default character. Character clocked out in case of an ignored transaction. */ 11876 11877 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ 11878 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ 11879 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ 11880 11881 /* Register: SPIS_ORC */ 11882 /* Description: Over-read character */ 11883 11884 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ 11885 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 11886 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 11887 11888 11889 /* Peripheral: SPU */ 11890 /* Description: System protection unit */ 11891 11892 /* Register: SPU_EVENTS_RAMACCERR */ 11893 /* Description: A security violation has been detected for the RAM memory space */ 11894 11895 /* Bit 0 : A security violation has been detected for the RAM memory space */ 11896 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL) /*!< Position of EVENTS_RAMACCERR field. */ 11897 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos) /*!< Bit mask of EVENTS_RAMACCERR field. */ 11898 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0x0UL) /*!< Event not generated */ 11899 #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (0x1UL) /*!< Event generated */ 11900 11901 /* Register: SPU_EVENTS_FLASHACCERR */ 11902 /* Description: A security violation has been detected for the flash memory space */ 11903 11904 /* Bit 0 : A security violation has been detected for the flash memory space */ 11905 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL) /*!< Position of EVENTS_FLASHACCERR field. */ 11906 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos) /*!< Bit mask of EVENTS_FLASHACCERR field. */ 11907 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0x0UL) /*!< Event not generated */ 11908 #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (0x1UL) /*!< Event generated */ 11909 11910 /* Register: SPU_EVENTS_PERIPHACCERR */ 11911 /* Description: A security violation has been detected on one or several peripherals */ 11912 11913 /* Bit 0 : A security violation has been detected on one or several peripherals */ 11914 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */ 11915 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit mask of EVENTS_PERIPHACCERR field. */ 11916 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0x0UL) /*!< Event not generated */ 11917 #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (0x1UL) /*!< Event generated */ 11918 11919 /* Register: SPU_PUBLISH_RAMACCERR */ 11920 /* Description: Publish configuration for event RAMACCERR */ 11921 11922 /* Bit 31 : */ 11923 #define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL) /*!< Position of EN field. */ 11924 #define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos) /*!< Bit mask of EN field. */ 11925 #define SPU_PUBLISH_RAMACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */ 11926 #define SPU_PUBLISH_RAMACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */ 11927 11928 /* Bits 7..0 : DPPI channel that event RAMACCERR will publish to */ 11929 #define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11930 #define SPU_PUBLISH_RAMACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_RAMACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11931 11932 /* Register: SPU_PUBLISH_FLASHACCERR */ 11933 /* Description: Publish configuration for event FLASHACCERR */ 11934 11935 /* Bit 31 : */ 11936 #define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL) /*!< Position of EN field. */ 11937 #define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos) /*!< Bit mask of EN field. */ 11938 #define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */ 11939 #define SPU_PUBLISH_FLASHACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */ 11940 11941 /* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to */ 11942 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11943 #define SPU_PUBLISH_FLASHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_FLASHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11944 11945 /* Register: SPU_PUBLISH_PERIPHACCERR */ 11946 /* Description: Publish configuration for event PERIPHACCERR */ 11947 11948 /* Bit 31 : */ 11949 #define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL) /*!< Position of EN field. */ 11950 #define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos) /*!< Bit mask of EN field. */ 11951 #define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */ 11952 #define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */ 11953 11954 /* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to */ 11955 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 11956 #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Msk (0xFFUL << SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 11957 11958 /* Register: SPU_INTEN */ 11959 /* Description: Enable or disable interrupt */ 11960 11961 /* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */ 11962 #define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ 11963 #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ 11964 #define SPU_INTEN_PERIPHACCERR_Disabled (0x0UL) /*!< Disable */ 11965 #define SPU_INTEN_PERIPHACCERR_Enabled (0x1UL) /*!< Enable */ 11966 11967 /* Bit 1 : Enable or disable interrupt for event FLASHACCERR */ 11968 #define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ 11969 #define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ 11970 #define SPU_INTEN_FLASHACCERR_Disabled (0x0UL) /*!< Disable */ 11971 #define SPU_INTEN_FLASHACCERR_Enabled (0x1UL) /*!< Enable */ 11972 11973 /* Bit 0 : Enable or disable interrupt for event RAMACCERR */ 11974 #define SPU_INTEN_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ 11975 #define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ 11976 #define SPU_INTEN_RAMACCERR_Disabled (0x0UL) /*!< Disable */ 11977 #define SPU_INTEN_RAMACCERR_Enabled (0x1UL) /*!< Enable */ 11978 11979 /* Register: SPU_INTENSET */ 11980 /* Description: Enable interrupt */ 11981 11982 /* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */ 11983 #define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ 11984 #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ 11985 #define SPU_INTENSET_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ 11986 #define SPU_INTENSET_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ 11987 #define SPU_INTENSET_PERIPHACCERR_Set (0x1UL) /*!< Enable */ 11988 11989 /* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */ 11990 #define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ 11991 #define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ 11992 #define SPU_INTENSET_FLASHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ 11993 #define SPU_INTENSET_FLASHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ 11994 #define SPU_INTENSET_FLASHACCERR_Set (0x1UL) /*!< Enable */ 11995 11996 /* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */ 11997 #define SPU_INTENSET_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ 11998 #define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ 11999 #define SPU_INTENSET_RAMACCERR_Disabled (0x0UL) /*!< Read: Disabled */ 12000 #define SPU_INTENSET_RAMACCERR_Enabled (0x1UL) /*!< Read: Enabled */ 12001 #define SPU_INTENSET_RAMACCERR_Set (0x1UL) /*!< Enable */ 12002 12003 /* Register: SPU_INTENCLR */ 12004 /* Description: Disable interrupt */ 12005 12006 /* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */ 12007 #define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ 12008 #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ 12009 #define SPU_INTENCLR_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ 12010 #define SPU_INTENCLR_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ 12011 #define SPU_INTENCLR_PERIPHACCERR_Clear (0x1UL) /*!< Disable */ 12012 12013 /* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */ 12014 #define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ 12015 #define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ 12016 #define SPU_INTENCLR_FLASHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ 12017 #define SPU_INTENCLR_FLASHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ 12018 #define SPU_INTENCLR_FLASHACCERR_Clear (0x1UL) /*!< Disable */ 12019 12020 /* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */ 12021 #define SPU_INTENCLR_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ 12022 #define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ 12023 #define SPU_INTENCLR_RAMACCERR_Disabled (0x0UL) /*!< Read: Disabled */ 12024 #define SPU_INTENCLR_RAMACCERR_Enabled (0x1UL) /*!< Read: Enabled */ 12025 #define SPU_INTENCLR_RAMACCERR_Clear (0x1UL) /*!< Disable */ 12026 12027 /* Register: SPU_CAP */ 12028 /* Description: Show implemented features for the current device */ 12029 12030 /* Bit 0 : Show ARM TrustZone status */ 12031 #define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */ 12032 #define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */ 12033 #define SPU_CAP_TZM_NotAvailable (0x0UL) /*!< ARM TrustZone support not available */ 12034 #define SPU_CAP_TZM_Enabled (0x1UL) /*!< ARM TrustZone support is available */ 12035 12036 /* Register: SPU_EXTDOMAIN_PERM */ 12037 /* Description: Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n */ 12038 12039 /* Bit 8 : */ 12040 #define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 12041 #define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ 12042 #define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ 12043 #define SPU_EXTDOMAIN_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ 12044 12045 /* Bit 4 : Peripheral security mapping */ 12046 #define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ 12047 #define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ 12048 #define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0x0UL) /*!< Bus accesses from this domain have the non-secure attribute set */ 12049 #define SPU_EXTDOMAIN_PERM_SECATTR_Secure (0x1UL) /*!< Bus accesses from this domain have secure attribute set */ 12050 12051 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ 12052 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ 12053 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ 12054 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< The bus access from this external domain always have the non-secure attribute set */ 12055 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (0x1UL) /*!< The bus access from this external domain always have the secure attribute set */ 12056 #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */ 12057 12058 /* Register: SPU_DPPI_PERM */ 12059 /* Description: Description cluster: Select between secure and non-secure attribute for the DPPI channels. */ 12060 12061 /* Bit 15 : Select secure attribute. */ 12062 #define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */ 12063 #define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */ 12064 #define SPU_DPPI_PERM_CHANNEL15_NonSecure (0x0UL) /*!< Channel15 has its non-secure attribute set */ 12065 #define SPU_DPPI_PERM_CHANNEL15_Secure (0x1UL) /*!< Channel15 has its secure attribute set */ 12066 12067 /* Bit 14 : Select secure attribute. */ 12068 #define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */ 12069 #define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */ 12070 #define SPU_DPPI_PERM_CHANNEL14_NonSecure (0x0UL) /*!< Channel14 has its non-secure attribute set */ 12071 #define SPU_DPPI_PERM_CHANNEL14_Secure (0x1UL) /*!< Channel14 has its secure attribute set */ 12072 12073 /* Bit 13 : Select secure attribute. */ 12074 #define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */ 12075 #define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */ 12076 #define SPU_DPPI_PERM_CHANNEL13_NonSecure (0x0UL) /*!< Channel13 has its non-secure attribute set */ 12077 #define SPU_DPPI_PERM_CHANNEL13_Secure (0x1UL) /*!< Channel13 has its secure attribute set */ 12078 12079 /* Bit 12 : Select secure attribute. */ 12080 #define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */ 12081 #define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */ 12082 #define SPU_DPPI_PERM_CHANNEL12_NonSecure (0x0UL) /*!< Channel12 has its non-secure attribute set */ 12083 #define SPU_DPPI_PERM_CHANNEL12_Secure (0x1UL) /*!< Channel12 has its secure attribute set */ 12084 12085 /* Bit 11 : Select secure attribute. */ 12086 #define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */ 12087 #define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */ 12088 #define SPU_DPPI_PERM_CHANNEL11_NonSecure (0x0UL) /*!< Channel11 has its non-secure attribute set */ 12089 #define SPU_DPPI_PERM_CHANNEL11_Secure (0x1UL) /*!< Channel11 has its secure attribute set */ 12090 12091 /* Bit 10 : Select secure attribute. */ 12092 #define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */ 12093 #define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */ 12094 #define SPU_DPPI_PERM_CHANNEL10_NonSecure (0x0UL) /*!< Channel10 has its non-secure attribute set */ 12095 #define SPU_DPPI_PERM_CHANNEL10_Secure (0x1UL) /*!< Channel10 has its secure attribute set */ 12096 12097 /* Bit 9 : Select secure attribute. */ 12098 #define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */ 12099 #define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */ 12100 #define SPU_DPPI_PERM_CHANNEL9_NonSecure (0x0UL) /*!< Channel9 has its non-secure attribute set */ 12101 #define SPU_DPPI_PERM_CHANNEL9_Secure (0x1UL) /*!< Channel9 has its secure attribute set */ 12102 12103 /* Bit 8 : Select secure attribute. */ 12104 #define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */ 12105 #define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */ 12106 #define SPU_DPPI_PERM_CHANNEL8_NonSecure (0x0UL) /*!< Channel8 has its non-secure attribute set */ 12107 #define SPU_DPPI_PERM_CHANNEL8_Secure (0x1UL) /*!< Channel8 has its secure attribute set */ 12108 12109 /* Bit 7 : Select secure attribute. */ 12110 #define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */ 12111 #define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */ 12112 #define SPU_DPPI_PERM_CHANNEL7_NonSecure (0x0UL) /*!< Channel7 has its non-secure attribute set */ 12113 #define SPU_DPPI_PERM_CHANNEL7_Secure (0x1UL) /*!< Channel7 has its secure attribute set */ 12114 12115 /* Bit 6 : Select secure attribute. */ 12116 #define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */ 12117 #define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */ 12118 #define SPU_DPPI_PERM_CHANNEL6_NonSecure (0x0UL) /*!< Channel6 has its non-secure attribute set */ 12119 #define SPU_DPPI_PERM_CHANNEL6_Secure (0x1UL) /*!< Channel6 has its secure attribute set */ 12120 12121 /* Bit 5 : Select secure attribute. */ 12122 #define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */ 12123 #define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */ 12124 #define SPU_DPPI_PERM_CHANNEL5_NonSecure (0x0UL) /*!< Channel5 has its non-secure attribute set */ 12125 #define SPU_DPPI_PERM_CHANNEL5_Secure (0x1UL) /*!< Channel5 has its secure attribute set */ 12126 12127 /* Bit 4 : Select secure attribute. */ 12128 #define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */ 12129 #define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */ 12130 #define SPU_DPPI_PERM_CHANNEL4_NonSecure (0x0UL) /*!< Channel4 has its non-secure attribute set */ 12131 #define SPU_DPPI_PERM_CHANNEL4_Secure (0x1UL) /*!< Channel4 has its secure attribute set */ 12132 12133 /* Bit 3 : Select secure attribute. */ 12134 #define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */ 12135 #define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */ 12136 #define SPU_DPPI_PERM_CHANNEL3_NonSecure (0x0UL) /*!< Channel3 has its non-secure attribute set */ 12137 #define SPU_DPPI_PERM_CHANNEL3_Secure (0x1UL) /*!< Channel3 has its secure attribute set */ 12138 12139 /* Bit 2 : Select secure attribute. */ 12140 #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */ 12141 #define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */ 12142 #define SPU_DPPI_PERM_CHANNEL2_NonSecure (0x0UL) /*!< Channel2 has its non-secure attribute set */ 12143 #define SPU_DPPI_PERM_CHANNEL2_Secure (0x1UL) /*!< Channel2 has its secure attribute set */ 12144 12145 /* Bit 1 : Select secure attribute. */ 12146 #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */ 12147 #define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */ 12148 #define SPU_DPPI_PERM_CHANNEL1_NonSecure (0x0UL) /*!< Channel1 has its non-secure attribute set */ 12149 #define SPU_DPPI_PERM_CHANNEL1_Secure (0x1UL) /*!< Channel1 has its secure attribute set */ 12150 12151 /* Bit 0 : Select secure attribute. */ 12152 #define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */ 12153 #define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */ 12154 #define SPU_DPPI_PERM_CHANNEL0_NonSecure (0x0UL) /*!< Channel0 has its non-secure attribute set */ 12155 #define SPU_DPPI_PERM_CHANNEL0_Secure (0x1UL) /*!< Channel0 has its secure attribute set */ 12156 12157 /* Register: SPU_DPPI_LOCK */ 12158 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */ 12159 12160 /* Bit 0 : */ 12161 #define SPU_DPPI_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ 12162 #define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ 12163 #define SPU_DPPI_LOCK_LOCK_Unlocked (0x0UL) /*!< DPPI[n].PERM register content can be changed */ 12164 #define SPU_DPPI_LOCK_LOCK_Locked (0x1UL) /*!< DPPI[n].PERM register can't be changed until next reset */ 12165 12166 /* Register: SPU_GPIOPORT_PERM */ 12167 /* Description: Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. */ 12168 12169 /* Bit 31 : Select secure attribute attribute for PIN 31. */ 12170 #define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 12171 #define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 12172 #define SPU_GPIOPORT_PERM_PIN31_NonSecure (0x0UL) /*!< Pin 31 has its non-secure attribute set */ 12173 #define SPU_GPIOPORT_PERM_PIN31_Secure (0x1UL) /*!< Pin 31 has its secure attribute set */ 12174 12175 /* Bit 30 : Select secure attribute attribute for PIN 30. */ 12176 #define SPU_GPIOPORT_PERM_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 12177 #define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 12178 #define SPU_GPIOPORT_PERM_PIN30_NonSecure (0x0UL) /*!< Pin 30 has its non-secure attribute set */ 12179 #define SPU_GPIOPORT_PERM_PIN30_Secure (0x1UL) /*!< Pin 30 has its secure attribute set */ 12180 12181 /* Bit 29 : Select secure attribute attribute for PIN 29. */ 12182 #define SPU_GPIOPORT_PERM_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 12183 #define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 12184 #define SPU_GPIOPORT_PERM_PIN29_NonSecure (0x0UL) /*!< Pin 29 has its non-secure attribute set */ 12185 #define SPU_GPIOPORT_PERM_PIN29_Secure (0x1UL) /*!< Pin 29 has its secure attribute set */ 12186 12187 /* Bit 28 : Select secure attribute attribute for PIN 28. */ 12188 #define SPU_GPIOPORT_PERM_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 12189 #define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 12190 #define SPU_GPIOPORT_PERM_PIN28_NonSecure (0x0UL) /*!< Pin 28 has its non-secure attribute set */ 12191 #define SPU_GPIOPORT_PERM_PIN28_Secure (0x1UL) /*!< Pin 28 has its secure attribute set */ 12192 12193 /* Bit 27 : Select secure attribute attribute for PIN 27. */ 12194 #define SPU_GPIOPORT_PERM_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 12195 #define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 12196 #define SPU_GPIOPORT_PERM_PIN27_NonSecure (0x0UL) /*!< Pin 27 has its non-secure attribute set */ 12197 #define SPU_GPIOPORT_PERM_PIN27_Secure (0x1UL) /*!< Pin 27 has its secure attribute set */ 12198 12199 /* Bit 26 : Select secure attribute attribute for PIN 26. */ 12200 #define SPU_GPIOPORT_PERM_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 12201 #define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 12202 #define SPU_GPIOPORT_PERM_PIN26_NonSecure (0x0UL) /*!< Pin 26 has its non-secure attribute set */ 12203 #define SPU_GPIOPORT_PERM_PIN26_Secure (0x1UL) /*!< Pin 26 has its secure attribute set */ 12204 12205 /* Bit 25 : Select secure attribute attribute for PIN 25. */ 12206 #define SPU_GPIOPORT_PERM_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 12207 #define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 12208 #define SPU_GPIOPORT_PERM_PIN25_NonSecure (0x0UL) /*!< Pin 25 has its non-secure attribute set */ 12209 #define SPU_GPIOPORT_PERM_PIN25_Secure (0x1UL) /*!< Pin 25 has its secure attribute set */ 12210 12211 /* Bit 24 : Select secure attribute attribute for PIN 24. */ 12212 #define SPU_GPIOPORT_PERM_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 12213 #define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 12214 #define SPU_GPIOPORT_PERM_PIN24_NonSecure (0x0UL) /*!< Pin 24 has its non-secure attribute set */ 12215 #define SPU_GPIOPORT_PERM_PIN24_Secure (0x1UL) /*!< Pin 24 has its secure attribute set */ 12216 12217 /* Bit 23 : Select secure attribute attribute for PIN 23. */ 12218 #define SPU_GPIOPORT_PERM_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 12219 #define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 12220 #define SPU_GPIOPORT_PERM_PIN23_NonSecure (0x0UL) /*!< Pin 23 has its non-secure attribute set */ 12221 #define SPU_GPIOPORT_PERM_PIN23_Secure (0x1UL) /*!< Pin 23 has its secure attribute set */ 12222 12223 /* Bit 22 : Select secure attribute attribute for PIN 22. */ 12224 #define SPU_GPIOPORT_PERM_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 12225 #define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 12226 #define SPU_GPIOPORT_PERM_PIN22_NonSecure (0x0UL) /*!< Pin 22 has its non-secure attribute set */ 12227 #define SPU_GPIOPORT_PERM_PIN22_Secure (0x1UL) /*!< Pin 22 has its secure attribute set */ 12228 12229 /* Bit 21 : Select secure attribute attribute for PIN 21. */ 12230 #define SPU_GPIOPORT_PERM_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 12231 #define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 12232 #define SPU_GPIOPORT_PERM_PIN21_NonSecure (0x0UL) /*!< Pin 21 has its non-secure attribute set */ 12233 #define SPU_GPIOPORT_PERM_PIN21_Secure (0x1UL) /*!< Pin 21 has its secure attribute set */ 12234 12235 /* Bit 20 : Select secure attribute attribute for PIN 20. */ 12236 #define SPU_GPIOPORT_PERM_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 12237 #define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 12238 #define SPU_GPIOPORT_PERM_PIN20_NonSecure (0x0UL) /*!< Pin 20 has its non-secure attribute set */ 12239 #define SPU_GPIOPORT_PERM_PIN20_Secure (0x1UL) /*!< Pin 20 has its secure attribute set */ 12240 12241 /* Bit 19 : Select secure attribute attribute for PIN 19. */ 12242 #define SPU_GPIOPORT_PERM_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 12243 #define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 12244 #define SPU_GPIOPORT_PERM_PIN19_NonSecure (0x0UL) /*!< Pin 19 has its non-secure attribute set */ 12245 #define SPU_GPIOPORT_PERM_PIN19_Secure (0x1UL) /*!< Pin 19 has its secure attribute set */ 12246 12247 /* Bit 18 : Select secure attribute attribute for PIN 18. */ 12248 #define SPU_GPIOPORT_PERM_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 12249 #define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 12250 #define SPU_GPIOPORT_PERM_PIN18_NonSecure (0x0UL) /*!< Pin 18 has its non-secure attribute set */ 12251 #define SPU_GPIOPORT_PERM_PIN18_Secure (0x1UL) /*!< Pin 18 has its secure attribute set */ 12252 12253 /* Bit 17 : Select secure attribute attribute for PIN 17. */ 12254 #define SPU_GPIOPORT_PERM_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 12255 #define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 12256 #define SPU_GPIOPORT_PERM_PIN17_NonSecure (0x0UL) /*!< Pin 17 has its non-secure attribute set */ 12257 #define SPU_GPIOPORT_PERM_PIN17_Secure (0x1UL) /*!< Pin 17 has its secure attribute set */ 12258 12259 /* Bit 16 : Select secure attribute attribute for PIN 16. */ 12260 #define SPU_GPIOPORT_PERM_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 12261 #define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 12262 #define SPU_GPIOPORT_PERM_PIN16_NonSecure (0x0UL) /*!< Pin 16 has its non-secure attribute set */ 12263 #define SPU_GPIOPORT_PERM_PIN16_Secure (0x1UL) /*!< Pin 16 has its secure attribute set */ 12264 12265 /* Bit 15 : Select secure attribute attribute for PIN 15. */ 12266 #define SPU_GPIOPORT_PERM_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 12267 #define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 12268 #define SPU_GPIOPORT_PERM_PIN15_NonSecure (0x0UL) /*!< Pin 15 has its non-secure attribute set */ 12269 #define SPU_GPIOPORT_PERM_PIN15_Secure (0x1UL) /*!< Pin 15 has its secure attribute set */ 12270 12271 /* Bit 14 : Select secure attribute attribute for PIN 14. */ 12272 #define SPU_GPIOPORT_PERM_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 12273 #define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 12274 #define SPU_GPIOPORT_PERM_PIN14_NonSecure (0x0UL) /*!< Pin 14 has its non-secure attribute set */ 12275 #define SPU_GPIOPORT_PERM_PIN14_Secure (0x1UL) /*!< Pin 14 has its secure attribute set */ 12276 12277 /* Bit 13 : Select secure attribute attribute for PIN 13. */ 12278 #define SPU_GPIOPORT_PERM_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 12279 #define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 12280 #define SPU_GPIOPORT_PERM_PIN13_NonSecure (0x0UL) /*!< Pin 13 has its non-secure attribute set */ 12281 #define SPU_GPIOPORT_PERM_PIN13_Secure (0x1UL) /*!< Pin 13 has its secure attribute set */ 12282 12283 /* Bit 12 : Select secure attribute attribute for PIN 12. */ 12284 #define SPU_GPIOPORT_PERM_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 12285 #define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 12286 #define SPU_GPIOPORT_PERM_PIN12_NonSecure (0x0UL) /*!< Pin 12 has its non-secure attribute set */ 12287 #define SPU_GPIOPORT_PERM_PIN12_Secure (0x1UL) /*!< Pin 12 has its secure attribute set */ 12288 12289 /* Bit 11 : Select secure attribute attribute for PIN 11. */ 12290 #define SPU_GPIOPORT_PERM_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 12291 #define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 12292 #define SPU_GPIOPORT_PERM_PIN11_NonSecure (0x0UL) /*!< Pin 11 has its non-secure attribute set */ 12293 #define SPU_GPIOPORT_PERM_PIN11_Secure (0x1UL) /*!< Pin 11 has its secure attribute set */ 12294 12295 /* Bit 10 : Select secure attribute attribute for PIN 10. */ 12296 #define SPU_GPIOPORT_PERM_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 12297 #define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 12298 #define SPU_GPIOPORT_PERM_PIN10_NonSecure (0x0UL) /*!< Pin 10 has its non-secure attribute set */ 12299 #define SPU_GPIOPORT_PERM_PIN10_Secure (0x1UL) /*!< Pin 10 has its secure attribute set */ 12300 12301 /* Bit 9 : Select secure attribute attribute for PIN 9. */ 12302 #define SPU_GPIOPORT_PERM_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 12303 #define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 12304 #define SPU_GPIOPORT_PERM_PIN9_NonSecure (0x0UL) /*!< Pin 9 has its non-secure attribute set */ 12305 #define SPU_GPIOPORT_PERM_PIN9_Secure (0x1UL) /*!< Pin 9 has its secure attribute set */ 12306 12307 /* Bit 8 : Select secure attribute attribute for PIN 8. */ 12308 #define SPU_GPIOPORT_PERM_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 12309 #define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 12310 #define SPU_GPIOPORT_PERM_PIN8_NonSecure (0x0UL) /*!< Pin 8 has its non-secure attribute set */ 12311 #define SPU_GPIOPORT_PERM_PIN8_Secure (0x1UL) /*!< Pin 8 has its secure attribute set */ 12312 12313 /* Bit 7 : Select secure attribute attribute for PIN 7. */ 12314 #define SPU_GPIOPORT_PERM_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 12315 #define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 12316 #define SPU_GPIOPORT_PERM_PIN7_NonSecure (0x0UL) /*!< Pin 7 has its non-secure attribute set */ 12317 #define SPU_GPIOPORT_PERM_PIN7_Secure (0x1UL) /*!< Pin 7 has its secure attribute set */ 12318 12319 /* Bit 6 : Select secure attribute attribute for PIN 6. */ 12320 #define SPU_GPIOPORT_PERM_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 12321 #define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 12322 #define SPU_GPIOPORT_PERM_PIN6_NonSecure (0x0UL) /*!< Pin 6 has its non-secure attribute set */ 12323 #define SPU_GPIOPORT_PERM_PIN6_Secure (0x1UL) /*!< Pin 6 has its secure attribute set */ 12324 12325 /* Bit 5 : Select secure attribute attribute for PIN 5. */ 12326 #define SPU_GPIOPORT_PERM_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 12327 #define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 12328 #define SPU_GPIOPORT_PERM_PIN5_NonSecure (0x0UL) /*!< Pin 5 has its non-secure attribute set */ 12329 #define SPU_GPIOPORT_PERM_PIN5_Secure (0x1UL) /*!< Pin 5 has its secure attribute set */ 12330 12331 /* Bit 4 : Select secure attribute attribute for PIN 4. */ 12332 #define SPU_GPIOPORT_PERM_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 12333 #define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 12334 #define SPU_GPIOPORT_PERM_PIN4_NonSecure (0x0UL) /*!< Pin 4 has its non-secure attribute set */ 12335 #define SPU_GPIOPORT_PERM_PIN4_Secure (0x1UL) /*!< Pin 4 has its secure attribute set */ 12336 12337 /* Bit 3 : Select secure attribute attribute for PIN 3. */ 12338 #define SPU_GPIOPORT_PERM_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 12339 #define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 12340 #define SPU_GPIOPORT_PERM_PIN3_NonSecure (0x0UL) /*!< Pin 3 has its non-secure attribute set */ 12341 #define SPU_GPIOPORT_PERM_PIN3_Secure (0x1UL) /*!< Pin 3 has its secure attribute set */ 12342 12343 /* Bit 2 : Select secure attribute attribute for PIN 2. */ 12344 #define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 12345 #define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 12346 #define SPU_GPIOPORT_PERM_PIN2_NonSecure (0x0UL) /*!< Pin 2 has its non-secure attribute set */ 12347 #define SPU_GPIOPORT_PERM_PIN2_Secure (0x1UL) /*!< Pin 2 has its secure attribute set */ 12348 12349 /* Bit 1 : Select secure attribute attribute for PIN 1. */ 12350 #define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 12351 #define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 12352 #define SPU_GPIOPORT_PERM_PIN1_NonSecure (0x0UL) /*!< Pin 1 has its non-secure attribute set */ 12353 #define SPU_GPIOPORT_PERM_PIN1_Secure (0x1UL) /*!< Pin 1 has its secure attribute set */ 12354 12355 /* Bit 0 : Select secure attribute attribute for PIN 0. */ 12356 #define SPU_GPIOPORT_PERM_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 12357 #define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 12358 #define SPU_GPIOPORT_PERM_PIN0_NonSecure (0x0UL) /*!< Pin 0 has its non-secure attribute set */ 12359 #define SPU_GPIOPORT_PERM_PIN0_Secure (0x1UL) /*!< Pin 0 has its secure attribute set */ 12360 12361 /* Register: SPU_GPIOPORT_LOCK */ 12362 /* Description: Description cluster: Prevent further modification of the corresponding PERM register */ 12363 12364 /* Bit 0 : */ 12365 #define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ 12366 #define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ 12367 #define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0x0UL) /*!< GPIOPORT[n].PERM register content can be changed */ 12368 #define SPU_GPIOPORT_LOCK_LOCK_Locked (0x1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */ 12369 12370 /* Register: SPU_FLASHNSC_REGION */ 12371 /* Description: Description cluster: Define which flash region can contain the non-secure callable (NSC) region n */ 12372 12373 /* Bit 8 : */ 12374 #define SPU_FLASHNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 12375 #define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */ 12376 #define SPU_FLASHNSC_REGION_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ 12377 #define SPU_FLASHNSC_REGION_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ 12378 12379 /* Bits 4..0 : Region number */ 12380 #define SPU_FLASHNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */ 12381 #define SPU_FLASHNSC_REGION_REGION_Msk (0x1FUL << SPU_FLASHNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */ 12382 12383 /* Register: SPU_FLASHNSC_SIZE */ 12384 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */ 12385 12386 /* Bit 8 : */ 12387 #define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 12388 #define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */ 12389 #define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ 12390 #define SPU_FLASHNSC_SIZE_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ 12391 12392 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */ 12393 #define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ 12394 #define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ 12395 #define SPU_FLASHNSC_SIZE_SIZE_Disabled (0x0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ 12396 #define SPU_FLASHNSC_SIZE_SIZE_32 (0x1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ 12397 #define SPU_FLASHNSC_SIZE_SIZE_64 (0x2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ 12398 #define SPU_FLASHNSC_SIZE_SIZE_128 (0x3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ 12399 #define SPU_FLASHNSC_SIZE_SIZE_256 (0x4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ 12400 #define SPU_FLASHNSC_SIZE_SIZE_512 (0x5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ 12401 #define SPU_FLASHNSC_SIZE_SIZE_1024 (0x6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ 12402 #define SPU_FLASHNSC_SIZE_SIZE_2048 (0x7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ 12403 #define SPU_FLASHNSC_SIZE_SIZE_4096 (0x8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ 12404 12405 /* Register: SPU_RAMNSC_REGION */ 12406 /* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */ 12407 12408 /* Bit 8 : */ 12409 #define SPU_RAMNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 12410 #define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */ 12411 #define SPU_RAMNSC_REGION_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ 12412 #define SPU_RAMNSC_REGION_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ 12413 12414 /* Bits 4..0 : Region number */ 12415 #define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */ 12416 #define SPU_RAMNSC_REGION_REGION_Msk (0x1FUL << SPU_RAMNSC_REGION_REGION_Pos) /*!< Bit mask of REGION field. */ 12417 12418 /* Register: SPU_RAMNSC_SIZE */ 12419 /* Description: Description cluster: Define the size of the non-secure callable (NSC) region n */ 12420 12421 /* Bit 8 : */ 12422 #define SPU_RAMNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 12423 #define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */ 12424 #define SPU_RAMNSC_SIZE_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ 12425 #define SPU_RAMNSC_SIZE_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ 12426 12427 /* Bits 3..0 : Size of the non-secure callable (NSC) region n */ 12428 #define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ 12429 #define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ 12430 #define SPU_RAMNSC_SIZE_SIZE_Disabled (0x0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ 12431 #define SPU_RAMNSC_SIZE_SIZE_32 (0x1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ 12432 #define SPU_RAMNSC_SIZE_SIZE_64 (0x2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ 12433 #define SPU_RAMNSC_SIZE_SIZE_128 (0x3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ 12434 #define SPU_RAMNSC_SIZE_SIZE_256 (0x4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ 12435 #define SPU_RAMNSC_SIZE_SIZE_512 (0x5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ 12436 #define SPU_RAMNSC_SIZE_SIZE_1024 (0x6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ 12437 #define SPU_RAMNSC_SIZE_SIZE_2048 (0x7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ 12438 #define SPU_RAMNSC_SIZE_SIZE_4096 (0x8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ 12439 12440 /* Register: SPU_FLASHREGION_PERM */ 12441 /* Description: Description cluster: Access permissions for flash region n */ 12442 12443 /* Bit 8 : */ 12444 #define SPU_FLASHREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 12445 #define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ 12446 #define SPU_FLASHREGION_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ 12447 #define SPU_FLASHREGION_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ 12448 12449 /* Bit 4 : Security attribute for flash region n */ 12450 #define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ 12451 #define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ 12452 #define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0x0UL) /*!< Flash region n security attribute is non-secure */ 12453 #define SPU_FLASHREGION_PERM_SECATTR_Secure (0x1UL) /*!< Flash region n security attribute is secure */ 12454 12455 /* Bit 2 : Configure read permissions for flash region n */ 12456 #define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */ 12457 #define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */ 12458 #define SPU_FLASHREGION_PERM_READ_Disable (0x0UL) /*!< Block read operation from flash region n */ 12459 #define SPU_FLASHREGION_PERM_READ_Enable (0x1UL) /*!< Allow read operation from flash region n */ 12460 12461 /* Bit 1 : Configure write permission for flash region n */ 12462 #define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ 12463 #define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ 12464 #define SPU_FLASHREGION_PERM_WRITE_Disable (0x0UL) /*!< Block write operation to region n */ 12465 #define SPU_FLASHREGION_PERM_WRITE_Enable (0x1UL) /*!< Allow write operation to region n */ 12466 12467 /* Bit 0 : Configure instruction fetch permissions from flash region n */ 12468 #define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */ 12469 #define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ 12470 #define SPU_FLASHREGION_PERM_EXECUTE_Disable (0x0UL) /*!< Block instruction fetches from flash region n */ 12471 #define SPU_FLASHREGION_PERM_EXECUTE_Enable (0x1UL) /*!< Allow instruction fetches from flash region n */ 12472 12473 /* Register: SPU_RAMREGION_PERM */ 12474 /* Description: Description cluster: Access permissions for RAM region n */ 12475 12476 /* Bit 8 : */ 12477 #define SPU_RAMREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 12478 #define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ 12479 #define SPU_RAMREGION_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ 12480 #define SPU_RAMREGION_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ 12481 12482 /* Bit 4 : Security attribute for RAM region n */ 12483 #define SPU_RAMREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ 12484 #define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ 12485 #define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0x0UL) /*!< RAM region n security attribute is non-secure */ 12486 #define SPU_RAMREGION_PERM_SECATTR_Secure (0x1UL) /*!< RAM region n security attribute is secure */ 12487 12488 /* Bit 2 : Configure read permissions for RAM region n */ 12489 #define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */ 12490 #define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */ 12491 #define SPU_RAMREGION_PERM_READ_Disable (0x0UL) /*!< Block read operation from RAM region n */ 12492 #define SPU_RAMREGION_PERM_READ_Enable (0x1UL) /*!< Allow read operation from RAM region n */ 12493 12494 /* Bit 1 : Configure write permission for RAM region n */ 12495 #define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ 12496 #define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ 12497 #define SPU_RAMREGION_PERM_WRITE_Disable (0x0UL) /*!< Block write operation to RAM region n */ 12498 #define SPU_RAMREGION_PERM_WRITE_Enable (0x1UL) /*!< Allow write operation to RAM region n */ 12499 12500 /* Bit 0 : Configure instruction fetch permissions from RAM region n */ 12501 #define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */ 12502 #define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ 12503 #define SPU_RAMREGION_PERM_EXECUTE_Disable (0x0UL) /*!< Block instruction fetches from RAM region n */ 12504 #define SPU_RAMREGION_PERM_EXECUTE_Enable (0x1UL) /*!< Allow instruction fetches from RAM region n */ 12505 12506 /* Register: SPU_PERIPHID_PERM */ 12507 /* Description: Description cluster: List capabilities and access permissions for the peripheral with ID n */ 12508 12509 /* Bit 31 : Indicate if a peripheral is present with ID n */ 12510 #define SPU_PERIPHID_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */ 12511 #define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ 12512 #define SPU_PERIPHID_PERM_PRESENT_NotPresent (0x0UL) /*!< Peripheral is not present */ 12513 #define SPU_PERIPHID_PERM_PRESENT_IsPresent (0x1UL) /*!< Peripheral is present */ 12514 12515 /* Bit 8 : */ 12516 #define SPU_PERIPHID_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ 12517 #define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ 12518 #define SPU_PERIPHID_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ 12519 #define SPU_PERIPHID_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ 12520 12521 /* Bit 5 : Security attribution for the DMA transfer */ 12522 #define SPU_PERIPHID_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */ 12523 #define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */ 12524 #define SPU_PERIPHID_PERM_DMASEC_NonSecure (0x0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */ 12525 #define SPU_PERIPHID_PERM_DMASEC_Secure (0x1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */ 12526 12527 /* Bit 4 : Peripheral security mapping */ 12528 #define SPU_PERIPHID_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ 12529 #define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ 12530 #define SPU_PERIPHID_PERM_SECATTR_NonSecure (0x0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */ 12531 #define SPU_PERIPHID_PERM_SECATTR_Secure (0x1UL) /*!< Peripheral is mapped in secure peripheral address space */ 12532 12533 /* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */ 12534 #define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */ 12535 #define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */ 12536 #define SPU_PERIPHID_PERM_DMA_NoDMA (0x0UL) /*!< Peripheral has no DMA capability */ 12537 #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (0x1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */ 12538 #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (0x2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */ 12539 12540 /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ 12541 #define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ 12542 #define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ 12543 #define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< This peripheral is always accessible as a non-secure peripheral */ 12544 #define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (0x1UL) /*!< This peripheral is always accessible as a secure peripheral */ 12545 #define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */ 12546 #define SPU_PERIPHID_PERM_SECUREMAPPING_Split (0x3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */ 12547 12548 12549 /* Peripheral: TAD */ 12550 /* Description: Trace and debug control */ 12551 12552 /* Register: TAD_TASKS_CLOCKSTART */ 12553 /* Description: Start all trace and debug clocks. */ 12554 12555 /* Bit 0 : Start all trace and debug clocks. */ 12556 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos (0UL) /*!< Position of TASKS_CLOCKSTART field. */ 12557 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk (0x1UL << TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos) /*!< Bit mask of TASKS_CLOCKSTART field. */ 12558 #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger (0x1UL) /*!< Trigger task */ 12559 12560 /* Register: TAD_TASKS_CLOCKSTOP */ 12561 /* Description: Stop all trace and debug clocks. */ 12562 12563 /* Bit 0 : Stop all trace and debug clocks. */ 12564 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos (0UL) /*!< Position of TASKS_CLOCKSTOP field. */ 12565 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk (0x1UL << TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos) /*!< Bit mask of TASKS_CLOCKSTOP field. */ 12566 #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger (0x1UL) /*!< Trigger task */ 12567 12568 /* Register: TAD_ENABLE */ 12569 /* Description: Enable debug domain and aquire selected GPIOs */ 12570 12571 /* Bit 0 : */ 12572 #define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 12573 #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 12574 #define TAD_ENABLE_ENABLE_DISABLED (0x0UL) /*!< Disable debug domain and release selected GPIOs */ 12575 #define TAD_ENABLE_ENABLE_ENABLED (0x1UL) /*!< Enable debug domain and aquire selected GPIOs */ 12576 12577 /* Register: TAD_PSEL_TRACECLK */ 12578 /* Description: Pin configuration for TRACECLK */ 12579 12580 /* Bit 31 : Connection */ 12581 #define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12582 #define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12583 #define TAD_PSEL_TRACECLK_CONNECT_Connected (0x0UL) /*!< Connect */ 12584 #define TAD_PSEL_TRACECLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 12585 12586 /* Bits 4..0 : Pin number */ 12587 #define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */ 12588 #define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */ 12589 #define TAD_PSEL_TRACECLK_PIN_Traceclk (0x15UL) /*!< TRACECLK pin */ 12590 12591 /* Register: TAD_PSEL_TRACEDATA0 */ 12592 /* Description: Pin configuration for TRACEDATA[0] */ 12593 12594 /* Bit 31 : Connection */ 12595 #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12596 #define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12597 #define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0x0UL) /*!< Connect */ 12598 #define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 12599 12600 /* Bits 4..0 : Pin number */ 12601 #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */ 12602 #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */ 12603 #define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (0x16UL) /*!< TRACEDATA0 pin */ 12604 12605 /* Register: TAD_PSEL_TRACEDATA1 */ 12606 /* Description: Pin configuration for TRACEDATA[1] */ 12607 12608 /* Bit 31 : Connection */ 12609 #define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12610 #define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12611 #define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0x0UL) /*!< Connect */ 12612 #define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 12613 12614 /* Bits 4..0 : Pin number */ 12615 #define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */ 12616 #define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */ 12617 #define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (0x17UL) /*!< TRACEDATA1 pin */ 12618 12619 /* Register: TAD_PSEL_TRACEDATA2 */ 12620 /* Description: Pin configuration for TRACEDATA[2] */ 12621 12622 /* Bit 31 : Connection */ 12623 #define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12624 #define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12625 #define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0x0UL) /*!< Connect */ 12626 #define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 12627 12628 /* Bits 4..0 : Pin number */ 12629 #define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */ 12630 #define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */ 12631 #define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (0x18UL) /*!< TRACEDATA2 pin */ 12632 12633 /* Register: TAD_PSEL_TRACEDATA3 */ 12634 /* Description: Pin configuration for TRACEDATA[3] */ 12635 12636 /* Bit 31 : Connection */ 12637 #define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12638 #define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12639 #define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0x0UL) /*!< Connect */ 12640 #define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 12641 12642 /* Bits 4..0 : Pin number */ 12643 #define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */ 12644 #define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */ 12645 #define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (0x19UL) /*!< TRACEDATA3 pin */ 12646 12647 /* Register: TAD_TRACEPORTSPEED */ 12648 /* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */ 12649 12650 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */ 12651 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ 12652 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ 12653 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0x0UL) /*!< Trace Port clock is: 32MHz */ 12654 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (0x1UL) /*!< Trace Port clock is: 16MHz */ 12655 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (0x2UL) /*!< Trace Port clock is: 8MHz */ 12656 #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (0x3UL) /*!< Trace Port clock is: 4MHz */ 12657 12658 12659 /* Peripheral: TIMER */ 12660 /* Description: Timer/Counter 0 */ 12661 12662 /* Register: TIMER_TASKS_START */ 12663 /* Description: Start Timer */ 12664 12665 /* Bit 0 : Start Timer */ 12666 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 12667 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 12668 #define TIMER_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ 12669 12670 /* Register: TIMER_TASKS_STOP */ 12671 /* Description: Stop Timer */ 12672 12673 /* Bit 0 : Stop Timer */ 12674 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 12675 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 12676 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ 12677 12678 /* Register: TIMER_TASKS_COUNT */ 12679 /* Description: Increment Timer (Counter mode only) */ 12680 12681 /* Bit 0 : Increment Timer (Counter mode only) */ 12682 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ 12683 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ 12684 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (0x1UL) /*!< Trigger task */ 12685 12686 /* Register: TIMER_TASKS_CLEAR */ 12687 /* Description: Clear time */ 12688 12689 /* Bit 0 : Clear time */ 12690 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 12691 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 12692 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */ 12693 12694 /* Register: TIMER_TASKS_SHUTDOWN */ 12695 /* Description: Deprecated register - Shut down timer */ 12696 12697 /* Bit 0 : Deprecated field - Shut down timer */ 12698 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ 12699 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ 12700 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (0x1UL) /*!< Trigger task */ 12701 12702 /* Register: TIMER_TASKS_CAPTURE */ 12703 /* Description: Description collection: Capture Timer value to CC[n] register */ 12704 12705 /* Bit 0 : Capture Timer value to CC[n] register */ 12706 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ 12707 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ 12708 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */ 12709 12710 /* Register: TIMER_SUBSCRIBE_START */ 12711 /* Description: Subscribe configuration for task START */ 12712 12713 /* Bit 31 : */ 12714 #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 12715 #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 12716 #define TIMER_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ 12717 #define TIMER_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ 12718 12719 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 12720 #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 12721 #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 12722 12723 /* Register: TIMER_SUBSCRIBE_STOP */ 12724 /* Description: Subscribe configuration for task STOP */ 12725 12726 /* Bit 31 : */ 12727 #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 12728 #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 12729 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 12730 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 12731 12732 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 12733 #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 12734 #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 12735 12736 /* Register: TIMER_SUBSCRIBE_COUNT */ 12737 /* Description: Subscribe configuration for task COUNT */ 12738 12739 /* Bit 31 : */ 12740 #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */ 12741 #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */ 12742 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0x0UL) /*!< Disable subscription */ 12743 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (0x1UL) /*!< Enable subscription */ 12744 12745 /* Bits 7..0 : DPPI channel that task COUNT will subscribe to */ 12746 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 12747 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 12748 12749 /* Register: TIMER_SUBSCRIBE_CLEAR */ 12750 /* Description: Subscribe configuration for task CLEAR */ 12751 12752 /* Bit 31 : */ 12753 #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ 12754 #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ 12755 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */ 12756 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */ 12757 12758 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ 12759 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 12760 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 12761 12762 /* Register: TIMER_SUBSCRIBE_SHUTDOWN */ 12763 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */ 12764 12765 /* Bit 31 : */ 12766 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */ 12767 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */ 12768 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0x0UL) /*!< Disable subscription */ 12769 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (0x1UL) /*!< Enable subscription */ 12770 12771 /* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */ 12772 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 12773 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 12774 12775 /* Register: TIMER_SUBSCRIBE_CAPTURE */ 12776 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */ 12777 12778 /* Bit 31 : */ 12779 #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ 12780 #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ 12781 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription */ 12782 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription */ 12783 12784 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ 12785 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 12786 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 12787 12788 /* Register: TIMER_EVENTS_COMPARE */ 12789 /* Description: Description collection: Compare event on CC[n] match */ 12790 12791 /* Bit 0 : Compare event on CC[n] match */ 12792 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 12793 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 12794 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */ 12795 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */ 12796 12797 /* Register: TIMER_PUBLISH_COMPARE */ 12798 /* Description: Description collection: Publish configuration for event COMPARE[n] */ 12799 12800 /* Bit 31 : */ 12801 #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ 12802 #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ 12803 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */ 12804 #define TIMER_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */ 12805 12806 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */ 12807 #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 12808 #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 12809 12810 /* Register: TIMER_SHORTS */ 12811 /* Description: Shortcuts between local events and tasks */ 12812 12813 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ 12814 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ 12815 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ 12816 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 12817 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 12818 12819 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ 12820 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ 12821 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ 12822 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 12823 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 12824 12825 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ 12826 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ 12827 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ 12828 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 12829 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 12830 12831 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ 12832 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ 12833 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ 12834 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 12835 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 12836 12837 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ 12838 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ 12839 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ 12840 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 12841 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 12842 12843 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ 12844 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ 12845 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ 12846 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 12847 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 12848 12849 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ 12850 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ 12851 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ 12852 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ 12853 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ 12854 12855 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ 12856 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ 12857 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ 12858 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ 12859 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ 12860 12861 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ 12862 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ 12863 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ 12864 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ 12865 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ 12866 12867 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ 12868 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ 12869 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ 12870 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ 12871 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ 12872 12873 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ 12874 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ 12875 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ 12876 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ 12877 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ 12878 12879 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ 12880 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 12881 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 12882 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ 12883 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ 12884 12885 /* Register: TIMER_INTENSET */ 12886 /* Description: Enable interrupt */ 12887 12888 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ 12889 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ 12890 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ 12891 #define TIMER_INTENSET_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ 12892 #define TIMER_INTENSET_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ 12893 #define TIMER_INTENSET_COMPARE5_Set (0x1UL) /*!< Enable */ 12894 12895 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ 12896 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ 12897 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ 12898 #define TIMER_INTENSET_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ 12899 #define TIMER_INTENSET_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ 12900 #define TIMER_INTENSET_COMPARE4_Set (0x1UL) /*!< Enable */ 12901 12902 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ 12903 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 12904 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 12905 #define TIMER_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ 12906 #define TIMER_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ 12907 #define TIMER_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */ 12908 12909 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ 12910 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 12911 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 12912 #define TIMER_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ 12913 #define TIMER_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ 12914 #define TIMER_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */ 12915 12916 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ 12917 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 12918 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 12919 #define TIMER_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ 12920 #define TIMER_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ 12921 #define TIMER_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */ 12922 12923 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ 12924 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 12925 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 12926 #define TIMER_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ 12927 #define TIMER_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ 12928 #define TIMER_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */ 12929 12930 /* Register: TIMER_INTENCLR */ 12931 /* Description: Disable interrupt */ 12932 12933 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ 12934 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ 12935 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ 12936 #define TIMER_INTENCLR_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ 12937 #define TIMER_INTENCLR_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ 12938 #define TIMER_INTENCLR_COMPARE5_Clear (0x1UL) /*!< Disable */ 12939 12940 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ 12941 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ 12942 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ 12943 #define TIMER_INTENCLR_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ 12944 #define TIMER_INTENCLR_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ 12945 #define TIMER_INTENCLR_COMPARE4_Clear (0x1UL) /*!< Disable */ 12946 12947 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ 12948 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 12949 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 12950 #define TIMER_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ 12951 #define TIMER_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ 12952 #define TIMER_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */ 12953 12954 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ 12955 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 12956 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 12957 #define TIMER_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ 12958 #define TIMER_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ 12959 #define TIMER_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */ 12960 12961 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ 12962 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 12963 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 12964 #define TIMER_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ 12965 #define TIMER_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ 12966 #define TIMER_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */ 12967 12968 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ 12969 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 12970 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 12971 #define TIMER_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ 12972 #define TIMER_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ 12973 #define TIMER_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */ 12974 12975 /* Register: TIMER_MODE */ 12976 /* Description: Timer mode selection */ 12977 12978 /* Bits 1..0 : Timer mode */ 12979 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 12980 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 12981 #define TIMER_MODE_MODE_Timer (0x0UL) /*!< Select Timer mode */ 12982 #define TIMER_MODE_MODE_Counter (0x1UL) /*!< Deprecated enumerator - Select Counter mode */ 12983 #define TIMER_MODE_MODE_LowPowerCounter (0x2UL) /*!< Select Low Power Counter mode */ 12984 12985 /* Register: TIMER_BITMODE */ 12986 /* Description: Configure the number of bits used by the TIMER */ 12987 12988 /* Bits 1..0 : Timer bit width */ 12989 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ 12990 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ 12991 #define TIMER_BITMODE_BITMODE_16Bit (0x0UL) /*!< 16 bit timer bit width */ 12992 #define TIMER_BITMODE_BITMODE_08Bit (0x1UL) /*!< 8 bit timer bit width */ 12993 #define TIMER_BITMODE_BITMODE_24Bit (0x2UL) /*!< 24 bit timer bit width */ 12994 #define TIMER_BITMODE_BITMODE_32Bit (0x3UL) /*!< 32 bit timer bit width */ 12995 12996 /* Register: TIMER_PRESCALER */ 12997 /* Description: Timer prescaler register */ 12998 12999 /* Bits 3..0 : Prescaler value */ 13000 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 13001 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 13002 13003 /* Register: TIMER_ONESHOTEN */ 13004 /* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */ 13005 13006 /* Bit 0 : Enable one-shot operation */ 13007 #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */ 13008 #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */ 13009 #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0x0UL) /*!< Disable one-shot operation */ 13010 #define TIMER_ONESHOTEN_ONESHOTEN_Enable (0x1UL) /*!< Enable one-shot operation */ 13011 13012 /* Register: TIMER_CC */ 13013 /* Description: Description collection: Capture/Compare register n */ 13014 13015 /* Bits 31..0 : Capture/Compare value */ 13016 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ 13017 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ 13018 13019 13020 /* Peripheral: TPIU */ 13021 /* Description: Trace Port Interface Unit */ 13022 13023 /* Register: TPIU_SUPPORTEDPORTSIZES */ 13024 /* Description: Each bit location is a single port size that is supported on the device. */ 13025 13026 /* Bit 31 : Indicates whether the TPIU supports port size of 32-bit. */ 13027 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Pos (31UL) /*!< Position of PORT_SIZE_32 field. */ 13028 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Pos) /*!< Bit mask of PORT_SIZE_32 field. */ 13029 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_NotSupported (0x0UL) /*!< Port size 32 is not supported. */ 13030 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_32_Supported (0x1UL) /*!< Port size 32 is supported. */ 13031 13032 /* Bit 30 : Indicates whether the TPIU supports port size of 31-bit. */ 13033 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Pos (30UL) /*!< Position of PORT_SIZE_31 field. */ 13034 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Pos) /*!< Bit mask of PORT_SIZE_31 field. */ 13035 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_NotSupported (0x0UL) /*!< Port size 31 is not supported. */ 13036 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_31_Supported (0x1UL) /*!< Port size 31 is supported. */ 13037 13038 /* Bit 29 : Indicates whether the TPIU supports port size of 30-bit. */ 13039 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Pos (29UL) /*!< Position of PORT_SIZE_30 field. */ 13040 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Pos) /*!< Bit mask of PORT_SIZE_30 field. */ 13041 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_NotSupported (0x0UL) /*!< Port size 30 is not supported. */ 13042 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_30_Supported (0x1UL) /*!< Port size 30 is supported. */ 13043 13044 /* Bit 28 : Indicates whether the TPIU supports port size of 29-bit. */ 13045 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Pos (28UL) /*!< Position of PORT_SIZE_29 field. */ 13046 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Pos) /*!< Bit mask of PORT_SIZE_29 field. */ 13047 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_NotSupported (0x0UL) /*!< Port size 29 is not supported. */ 13048 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_29_Supported (0x1UL) /*!< Port size 29 is supported. */ 13049 13050 /* Bit 27 : Indicates whether the TPIU supports port size of 28-bit. */ 13051 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Pos (27UL) /*!< Position of PORT_SIZE_28 field. */ 13052 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Pos) /*!< Bit mask of PORT_SIZE_28 field. */ 13053 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_NotSupported (0x0UL) /*!< Port size 28 is not supported. */ 13054 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_28_Supported (0x1UL) /*!< Port size 28 is supported. */ 13055 13056 /* Bit 26 : Indicates whether the TPIU supports port size of 27-bit. */ 13057 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Pos (26UL) /*!< Position of PORT_SIZE_27 field. */ 13058 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Pos) /*!< Bit mask of PORT_SIZE_27 field. */ 13059 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_NotSupported (0x0UL) /*!< Port size 27 is not supported. */ 13060 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_27_Supported (0x1UL) /*!< Port size 27 is supported. */ 13061 13062 /* Bit 25 : Indicates whether the TPIU supports port size of 26-bit. */ 13063 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Pos (25UL) /*!< Position of PORT_SIZE_26 field. */ 13064 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Pos) /*!< Bit mask of PORT_SIZE_26 field. */ 13065 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_NotSupported (0x0UL) /*!< Port size 26 is not supported. */ 13066 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_26_Supported (0x1UL) /*!< Port size 26 is supported. */ 13067 13068 /* Bit 24 : Indicates whether the TPIU supports port size of 25-bit. */ 13069 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Pos (24UL) /*!< Position of PORT_SIZE_25 field. */ 13070 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Pos) /*!< Bit mask of PORT_SIZE_25 field. */ 13071 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_NotSupported (0x0UL) /*!< Port size 25 is not supported. */ 13072 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_25_Supported (0x1UL) /*!< Port size 25 is supported. */ 13073 13074 /* Bit 23 : Indicates whether the TPIU supports port size of 24-bit. */ 13075 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Pos (23UL) /*!< Position of PORT_SIZE_24 field. */ 13076 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Pos) /*!< Bit mask of PORT_SIZE_24 field. */ 13077 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_NotSupported (0x0UL) /*!< Port size 24 is not supported. */ 13078 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_24_Supported (0x1UL) /*!< Port size 24 is supported. */ 13079 13080 /* Bit 22 : Indicates whether the TPIU supports port size of 23-bit. */ 13081 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Pos (22UL) /*!< Position of PORT_SIZE_23 field. */ 13082 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Pos) /*!< Bit mask of PORT_SIZE_23 field. */ 13083 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_NotSupported (0x0UL) /*!< Port size 23 is not supported. */ 13084 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_23_Supported (0x1UL) /*!< Port size 23 is supported. */ 13085 13086 /* Bit 21 : Indicates whether the TPIU supports port size of 22-bit. */ 13087 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Pos (21UL) /*!< Position of PORT_SIZE_22 field. */ 13088 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Pos) /*!< Bit mask of PORT_SIZE_22 field. */ 13089 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_NotSupported (0x0UL) /*!< Port size 22 is not supported. */ 13090 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_22_Supported (0x1UL) /*!< Port size 22 is supported. */ 13091 13092 /* Bit 20 : Indicates whether the TPIU supports port size of 21-bit. */ 13093 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Pos (20UL) /*!< Position of PORT_SIZE_21 field. */ 13094 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Pos) /*!< Bit mask of PORT_SIZE_21 field. */ 13095 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_NotSupported (0x0UL) /*!< Port size 21 is not supported. */ 13096 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_21_Supported (0x1UL) /*!< Port size 21 is supported. */ 13097 13098 /* Bit 19 : Indicates whether the TPIU supports port size of 20-bit. */ 13099 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Pos (19UL) /*!< Position of PORT_SIZE_20 field. */ 13100 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Pos) /*!< Bit mask of PORT_SIZE_20 field. */ 13101 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_NotSupported (0x0UL) /*!< Port size 20 is not supported. */ 13102 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_20_Supported (0x1UL) /*!< Port size 20 is supported. */ 13103 13104 /* Bit 18 : Indicates whether the TPIU supports port size of 19-bit. */ 13105 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Pos (18UL) /*!< Position of PORT_SIZE_19 field. */ 13106 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Pos) /*!< Bit mask of PORT_SIZE_19 field. */ 13107 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_NotSupported (0x0UL) /*!< Port size 19 is not supported. */ 13108 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_19_Supported (0x1UL) /*!< Port size 19 is supported. */ 13109 13110 /* Bit 17 : Indicates whether the TPIU supports port size of 18-bit. */ 13111 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Pos (17UL) /*!< Position of PORT_SIZE_18 field. */ 13112 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Pos) /*!< Bit mask of PORT_SIZE_18 field. */ 13113 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_NotSupported (0x0UL) /*!< Port size 18 is not supported. */ 13114 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_18_Supported (0x1UL) /*!< Port size 18 is supported. */ 13115 13116 /* Bit 16 : Indicates whether the TPIU supports port size of 17-bit. */ 13117 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Pos (16UL) /*!< Position of PORT_SIZE_17 field. */ 13118 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Pos) /*!< Bit mask of PORT_SIZE_17 field. */ 13119 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_NotSupported (0x0UL) /*!< Port size 17 is not supported. */ 13120 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_17_Supported (0x1UL) /*!< Port size 17 is supported. */ 13121 13122 /* Bit 15 : Indicates whether the TPIU supports port size of 16-bit. */ 13123 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Pos (15UL) /*!< Position of PORT_SIZE_16 field. */ 13124 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Pos) /*!< Bit mask of PORT_SIZE_16 field. */ 13125 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_NotSupported (0x0UL) /*!< Port size 16 is not supported. */ 13126 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_16_Supported (0x1UL) /*!< Port size 16 is supported. */ 13127 13128 /* Bit 14 : Indicates whether the TPIU supports port size of 15-bit. */ 13129 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Pos (14UL) /*!< Position of PORT_SIZE_15 field. */ 13130 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Pos) /*!< Bit mask of PORT_SIZE_15 field. */ 13131 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_NotSupported (0x0UL) /*!< Port size 15 is not supported. */ 13132 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_15_Supported (0x1UL) /*!< Port size 15 is supported. */ 13133 13134 /* Bit 13 : Indicates whether the TPIU supports port size of 14-bit. */ 13135 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Pos (13UL) /*!< Position of PORT_SIZE_14 field. */ 13136 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Pos) /*!< Bit mask of PORT_SIZE_14 field. */ 13137 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_NotSupported (0x0UL) /*!< Port size 14 is not supported. */ 13138 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_14_Supported (0x1UL) /*!< Port size 14 is supported. */ 13139 13140 /* Bit 12 : Indicates whether the TPIU supports port size of 13-bit. */ 13141 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Pos (12UL) /*!< Position of PORT_SIZE_13 field. */ 13142 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Pos) /*!< Bit mask of PORT_SIZE_13 field. */ 13143 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_NotSupported (0x0UL) /*!< Port size 13 is not supported. */ 13144 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_13_Supported (0x1UL) /*!< Port size 13 is supported. */ 13145 13146 /* Bit 11 : Indicates whether the TPIU supports port size of 12-bit. */ 13147 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Pos (11UL) /*!< Position of PORT_SIZE_12 field. */ 13148 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Pos) /*!< Bit mask of PORT_SIZE_12 field. */ 13149 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_NotSupported (0x0UL) /*!< Port size 12 is not supported. */ 13150 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_12_Supported (0x1UL) /*!< Port size 12 is supported. */ 13151 13152 /* Bit 10 : Indicates whether the TPIU supports port size of 11-bit. */ 13153 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Pos (10UL) /*!< Position of PORT_SIZE_11 field. */ 13154 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Pos) /*!< Bit mask of PORT_SIZE_11 field. */ 13155 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_NotSupported (0x0UL) /*!< Port size 11 is not supported. */ 13156 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_11_Supported (0x1UL) /*!< Port size 11 is supported. */ 13157 13158 /* Bit 9 : Indicates whether the TPIU supports port size of 10-bit. */ 13159 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Pos (9UL) /*!< Position of PORT_SIZE_10 field. */ 13160 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Pos) /*!< Bit mask of PORT_SIZE_10 field. */ 13161 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_NotSupported (0x0UL) /*!< Port size 10 is not supported. */ 13162 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_10_Supported (0x1UL) /*!< Port size 10 is supported. */ 13163 13164 /* Bit 8 : Indicates whether the TPIU supports port size of 9-bit. */ 13165 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Pos (8UL) /*!< Position of PORT_SIZE_9 field. */ 13166 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Pos) /*!< Bit mask of PORT_SIZE_9 field. */ 13167 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_NotSupported (0x0UL) /*!< Port size 9 is not supported. */ 13168 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_9_Supported (0x1UL) /*!< Port size 9 is supported. */ 13169 13170 /* Bit 7 : Indicates whether the TPIU supports port size of 8-bit. */ 13171 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Pos (7UL) /*!< Position of PORT_SIZE_8 field. */ 13172 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Pos) /*!< Bit mask of PORT_SIZE_8 field. */ 13173 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_NotSupported (0x0UL) /*!< Port size 8 is not supported. */ 13174 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_8_Supported (0x1UL) /*!< Port size 8 is supported. */ 13175 13176 /* Bit 6 : Indicates whether the TPIU supports port size of 7-bit. */ 13177 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Pos (6UL) /*!< Position of PORT_SIZE_7 field. */ 13178 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Pos) /*!< Bit mask of PORT_SIZE_7 field. */ 13179 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_NotSupported (0x0UL) /*!< Port size 7 is not supported. */ 13180 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_7_Supported (0x1UL) /*!< Port size 7 is supported. */ 13181 13182 /* Bit 5 : Indicates whether the TPIU supports port size of 6-bit. */ 13183 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Pos (5UL) /*!< Position of PORT_SIZE_6 field. */ 13184 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Pos) /*!< Bit mask of PORT_SIZE_6 field. */ 13185 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_NotSupported (0x0UL) /*!< Port size 6 is not supported. */ 13186 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_6_Supported (0x1UL) /*!< Port size 6 is supported. */ 13187 13188 /* Bit 4 : Indicates whether the TPIU supports port size of 5-bit. */ 13189 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Pos (4UL) /*!< Position of PORT_SIZE_5 field. */ 13190 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Pos) /*!< Bit mask of PORT_SIZE_5 field. */ 13191 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_NotSupported (0x0UL) /*!< Port size 5 is not supported. */ 13192 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_5_Supported (0x1UL) /*!< Port size 5 is supported. */ 13193 13194 /* Bit 3 : Indicates whether the TPIU supports port size of 4-bit. */ 13195 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Pos (3UL) /*!< Position of PORT_SIZE_4 field. */ 13196 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Pos) /*!< Bit mask of PORT_SIZE_4 field. */ 13197 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_NotSupported (0x0UL) /*!< Port size 4 is not supported. */ 13198 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_4_Supported (0x1UL) /*!< Port size 4 is supported. */ 13199 13200 /* Bit 2 : Indicates whether the TPIU supports port size of 3-bit. */ 13201 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Pos (2UL) /*!< Position of PORT_SIZE_3 field. */ 13202 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Pos) /*!< Bit mask of PORT_SIZE_3 field. */ 13203 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_NotSupported (0x0UL) /*!< Port size 3 is not supported. */ 13204 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_3_Supported (0x1UL) /*!< Port size 3 is supported. */ 13205 13206 /* Bit 1 : Indicates whether the TPIU supports port size of 2-bit. */ 13207 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Pos (1UL) /*!< Position of PORT_SIZE_2 field. */ 13208 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Pos) /*!< Bit mask of PORT_SIZE_2 field. */ 13209 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_NotSupported (0x0UL) /*!< Port size 2 is not supported. */ 13210 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_2_Supported (0x1UL) /*!< Port size 2 is supported. */ 13211 13212 /* Bit 0 : Indicates whether the TPIU supports port size of 1-bit. */ 13213 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Pos (0UL) /*!< Position of PORT_SIZE_1 field. */ 13214 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Msk (0x1UL << TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Pos) /*!< Bit mask of PORT_SIZE_1 field. */ 13215 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_NotSupported (0x0UL) /*!< Port size 1 is not supported. */ 13216 #define TPIU_SUPPORTEDPORTSIZES_PORT_SIZE_1_Supported (0x1UL) /*!< Port size 1 is supported. */ 13217 13218 /* Register: TPIU_CURRENTPORTSIZE */ 13219 /* Description: Each bit location is a single port size. One bit can be set, and indicates the current port size. */ 13220 13221 /* Bit 31 : Indicates which port size is currently selected. */ 13222 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Pos (31UL) /*!< Position of PORT_SIZE_32 field. */ 13223 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Pos) /*!< Bit mask of PORT_SIZE_32 field. */ 13224 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_NotSelected (0x0UL) /*!< Port size 32 is not selected. */ 13225 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_32_Selected (0x1UL) /*!< Port size 32 is selected. */ 13226 13227 /* Bit 30 : Indicates which port size is currently selected. */ 13228 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Pos (30UL) /*!< Position of PORT_SIZE_31 field. */ 13229 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Pos) /*!< Bit mask of PORT_SIZE_31 field. */ 13230 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_NotSelected (0x0UL) /*!< Port size 31 is not selected. */ 13231 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_31_Selected (0x1UL) /*!< Port size 31 is selected. */ 13232 13233 /* Bit 29 : Indicates which port size is currently selected. */ 13234 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Pos (29UL) /*!< Position of PORT_SIZE_30 field. */ 13235 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Pos) /*!< Bit mask of PORT_SIZE_30 field. */ 13236 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_NotSelected (0x0UL) /*!< Port size 30 is not selected. */ 13237 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_30_Selected (0x1UL) /*!< Port size 30 is selected. */ 13238 13239 /* Bit 28 : Indicates which port size is currently selected. */ 13240 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Pos (28UL) /*!< Position of PORT_SIZE_29 field. */ 13241 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Pos) /*!< Bit mask of PORT_SIZE_29 field. */ 13242 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_NotSelected (0x0UL) /*!< Port size 29 is not selected. */ 13243 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_29_Selected (0x1UL) /*!< Port size 29 is selected. */ 13244 13245 /* Bit 27 : Indicates which port size is currently selected. */ 13246 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Pos (27UL) /*!< Position of PORT_SIZE_28 field. */ 13247 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Pos) /*!< Bit mask of PORT_SIZE_28 field. */ 13248 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_NotSelected (0x0UL) /*!< Port size 28 is not selected. */ 13249 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_28_Selected (0x1UL) /*!< Port size 28 is selected. */ 13250 13251 /* Bit 26 : Indicates which port size is currently selected. */ 13252 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Pos (26UL) /*!< Position of PORT_SIZE_27 field. */ 13253 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Pos) /*!< Bit mask of PORT_SIZE_27 field. */ 13254 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_NotSelected (0x0UL) /*!< Port size 27 is not selected. */ 13255 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_27_Selected (0x1UL) /*!< Port size 27 is selected. */ 13256 13257 /* Bit 25 : Indicates which port size is currently selected. */ 13258 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Pos (25UL) /*!< Position of PORT_SIZE_26 field. */ 13259 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Pos) /*!< Bit mask of PORT_SIZE_26 field. */ 13260 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_NotSelected (0x0UL) /*!< Port size 26 is not selected. */ 13261 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_26_Selected (0x1UL) /*!< Port size 26 is selected. */ 13262 13263 /* Bit 24 : Indicates which port size is currently selected. */ 13264 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Pos (24UL) /*!< Position of PORT_SIZE_25 field. */ 13265 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Pos) /*!< Bit mask of PORT_SIZE_25 field. */ 13266 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_NotSelected (0x0UL) /*!< Port size 25 is not selected. */ 13267 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_25_Selected (0x1UL) /*!< Port size 25 is selected. */ 13268 13269 /* Bit 23 : Indicates which port size is currently selected. */ 13270 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Pos (23UL) /*!< Position of PORT_SIZE_24 field. */ 13271 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Pos) /*!< Bit mask of PORT_SIZE_24 field. */ 13272 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_NotSelected (0x0UL) /*!< Port size 24 is not selected. */ 13273 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_24_Selected (0x1UL) /*!< Port size 24 is selected. */ 13274 13275 /* Bit 22 : Indicates which port size is currently selected. */ 13276 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Pos (22UL) /*!< Position of PORT_SIZE_23 field. */ 13277 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Pos) /*!< Bit mask of PORT_SIZE_23 field. */ 13278 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_NotSelected (0x0UL) /*!< Port size 23 is not selected. */ 13279 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_23_Selected (0x1UL) /*!< Port size 23 is selected. */ 13280 13281 /* Bit 21 : Indicates which port size is currently selected. */ 13282 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Pos (21UL) /*!< Position of PORT_SIZE_22 field. */ 13283 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Pos) /*!< Bit mask of PORT_SIZE_22 field. */ 13284 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_NotSelected (0x0UL) /*!< Port size 22 is not selected. */ 13285 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_22_Selected (0x1UL) /*!< Port size 22 is selected. */ 13286 13287 /* Bit 20 : Indicates which port size is currently selected. */ 13288 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Pos (20UL) /*!< Position of PORT_SIZE_21 field. */ 13289 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Pos) /*!< Bit mask of PORT_SIZE_21 field. */ 13290 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_NotSelected (0x0UL) /*!< Port size 21 is not selected. */ 13291 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_21_Selected (0x1UL) /*!< Port size 21 is selected. */ 13292 13293 /* Bit 19 : Indicates which port size is currently selected. */ 13294 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Pos (19UL) /*!< Position of PORT_SIZE_20 field. */ 13295 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Pos) /*!< Bit mask of PORT_SIZE_20 field. */ 13296 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_NotSelected (0x0UL) /*!< Port size 20 is not selected. */ 13297 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_20_Selected (0x1UL) /*!< Port size 20 is selected. */ 13298 13299 /* Bit 18 : Indicates which port size is currently selected. */ 13300 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Pos (18UL) /*!< Position of PORT_SIZE_19 field. */ 13301 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Pos) /*!< Bit mask of PORT_SIZE_19 field. */ 13302 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_NotSelected (0x0UL) /*!< Port size 19 is not selected. */ 13303 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_19_Selected (0x1UL) /*!< Port size 19 is selected. */ 13304 13305 /* Bit 17 : Indicates which port size is currently selected. */ 13306 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Pos (17UL) /*!< Position of PORT_SIZE_18 field. */ 13307 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Pos) /*!< Bit mask of PORT_SIZE_18 field. */ 13308 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_NotSelected (0x0UL) /*!< Port size 18 is not selected. */ 13309 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_18_Selected (0x1UL) /*!< Port size 18 is selected. */ 13310 13311 /* Bit 16 : Indicates which port size is currently selected. */ 13312 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Pos (16UL) /*!< Position of PORT_SIZE_17 field. */ 13313 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Pos) /*!< Bit mask of PORT_SIZE_17 field. */ 13314 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_NotSelected (0x0UL) /*!< Port size 17 is not selected. */ 13315 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_17_Selected (0x1UL) /*!< Port size 17 is selected. */ 13316 13317 /* Bit 15 : Indicates which port size is currently selected. */ 13318 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Pos (15UL) /*!< Position of PORT_SIZE_16 field. */ 13319 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Pos) /*!< Bit mask of PORT_SIZE_16 field. */ 13320 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_NotSelected (0x0UL) /*!< Port size 16 is not selected. */ 13321 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_16_Selected (0x1UL) /*!< Port size 16 is selected. */ 13322 13323 /* Bit 14 : Indicates which port size is currently selected. */ 13324 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Pos (14UL) /*!< Position of PORT_SIZE_15 field. */ 13325 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Pos) /*!< Bit mask of PORT_SIZE_15 field. */ 13326 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_NotSelected (0x0UL) /*!< Port size 15 is not selected. */ 13327 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_15_Selected (0x1UL) /*!< Port size 15 is selected. */ 13328 13329 /* Bit 13 : Indicates which port size is currently selected. */ 13330 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Pos (13UL) /*!< Position of PORT_SIZE_14 field. */ 13331 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Pos) /*!< Bit mask of PORT_SIZE_14 field. */ 13332 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_NotSelected (0x0UL) /*!< Port size 14 is not selected. */ 13333 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_14_Selected (0x1UL) /*!< Port size 14 is selected. */ 13334 13335 /* Bit 12 : Indicates which port size is currently selected. */ 13336 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Pos (12UL) /*!< Position of PORT_SIZE_13 field. */ 13337 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Pos) /*!< Bit mask of PORT_SIZE_13 field. */ 13338 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_NotSelected (0x0UL) /*!< Port size 13 is not selected. */ 13339 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_13_Selected (0x1UL) /*!< Port size 13 is selected. */ 13340 13341 /* Bit 11 : Indicates which port size is currently selected. */ 13342 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Pos (11UL) /*!< Position of PORT_SIZE_12 field. */ 13343 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Pos) /*!< Bit mask of PORT_SIZE_12 field. */ 13344 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_NotSelected (0x0UL) /*!< Port size 12 is not selected. */ 13345 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_12_Selected (0x1UL) /*!< Port size 12 is selected. */ 13346 13347 /* Bit 10 : Indicates which port size is currently selected. */ 13348 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Pos (10UL) /*!< Position of PORT_SIZE_11 field. */ 13349 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Pos) /*!< Bit mask of PORT_SIZE_11 field. */ 13350 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_NotSelected (0x0UL) /*!< Port size 11 is not selected. */ 13351 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_11_Selected (0x1UL) /*!< Port size 11 is selected. */ 13352 13353 /* Bit 9 : Indicates which port size is currently selected. */ 13354 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Pos (9UL) /*!< Position of PORT_SIZE_10 field. */ 13355 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Pos) /*!< Bit mask of PORT_SIZE_10 field. */ 13356 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_NotSelected (0x0UL) /*!< Port size 10 is not selected. */ 13357 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_10_Selected (0x1UL) /*!< Port size 10 is selected. */ 13358 13359 /* Bit 8 : Indicates which port size is currently selected. */ 13360 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Pos (8UL) /*!< Position of PORT_SIZE_9 field. */ 13361 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Pos) /*!< Bit mask of PORT_SIZE_9 field. */ 13362 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_NotSelected (0x0UL) /*!< Port size 9 is not selected. */ 13363 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_9_Selected (0x1UL) /*!< Port size 9 is selected. */ 13364 13365 /* Bit 7 : Indicates which port size is currently selected. */ 13366 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Pos (7UL) /*!< Position of PORT_SIZE_8 field. */ 13367 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Pos) /*!< Bit mask of PORT_SIZE_8 field. */ 13368 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_NotSelected (0x0UL) /*!< Port size 8 is not selected. */ 13369 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_8_Selected (0x1UL) /*!< Port size 8 is selected. */ 13370 13371 /* Bit 6 : Indicates which port size is currently selected. */ 13372 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Pos (6UL) /*!< Position of PORT_SIZE_7 field. */ 13373 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Pos) /*!< Bit mask of PORT_SIZE_7 field. */ 13374 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_NotSelected (0x0UL) /*!< Port size 7 is not selected. */ 13375 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_7_Selected (0x1UL) /*!< Port size 7 is selected. */ 13376 13377 /* Bit 5 : Indicates which port size is currently selected. */ 13378 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Pos (5UL) /*!< Position of PORT_SIZE_6 field. */ 13379 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Pos) /*!< Bit mask of PORT_SIZE_6 field. */ 13380 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_NotSelected (0x0UL) /*!< Port size 6 is not selected. */ 13381 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_6_Selected (0x1UL) /*!< Port size 6 is selected. */ 13382 13383 /* Bit 4 : Indicates which port size is currently selected. */ 13384 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Pos (4UL) /*!< Position of PORT_SIZE_5 field. */ 13385 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Pos) /*!< Bit mask of PORT_SIZE_5 field. */ 13386 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_NotSelected (0x0UL) /*!< Port size 5 is not selected. */ 13387 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_5_Selected (0x1UL) /*!< Port size 5 is selected. */ 13388 13389 /* Bit 3 : Indicates which port size is currently selected. */ 13390 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Pos (3UL) /*!< Position of PORT_SIZE_4 field. */ 13391 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Pos) /*!< Bit mask of PORT_SIZE_4 field. */ 13392 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_NotSelected (0x0UL) /*!< Port size 4 is not selected. */ 13393 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_4_Selected (0x1UL) /*!< Port size 4 is selected. */ 13394 13395 /* Bit 2 : Indicates which port size is currently selected. */ 13396 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Pos (2UL) /*!< Position of PORT_SIZE_3 field. */ 13397 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Pos) /*!< Bit mask of PORT_SIZE_3 field. */ 13398 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_NotSelected (0x0UL) /*!< Port size 3 is not selected. */ 13399 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_3_Selected (0x1UL) /*!< Port size 3 is selected. */ 13400 13401 /* Bit 1 : Indicates which port size is currently selected. */ 13402 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Pos (1UL) /*!< Position of PORT_SIZE_2 field. */ 13403 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Pos) /*!< Bit mask of PORT_SIZE_2 field. */ 13404 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_NotSelected (0x0UL) /*!< Port size 2 is not selected. */ 13405 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_2_Selected (0x1UL) /*!< Port size 2 is selected. */ 13406 13407 /* Bit 0 : Indicates which port size is currently selected. */ 13408 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Pos (0UL) /*!< Position of PORT_SIZE_1 field. */ 13409 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Msk (0x1UL << TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Pos) /*!< Bit mask of PORT_SIZE_1 field. */ 13410 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_NotSelected (0x0UL) /*!< Port size 1 is not selected. */ 13411 #define TPIU_CURRENTPORTSIZE_PORT_SIZE_1_Selected (0x1UL) /*!< Port size 1 is selected. */ 13412 13413 /* Register: TPIU_SUPPORTEDTRIGGERMODES */ 13414 /* Description: The Supported_trigger_modes register indicates the implemented trigger counter multipliers and other supported features of the trigger system. */ 13415 13416 /* Bit 17 : A trigger has occurred but the counter is not at 0. */ 13417 #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Pos (17UL) /*!< Position of TRGRUN field. */ 13418 #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Pos) /*!< Bit mask of TRGRUN field. */ 13419 #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_NotOccured (0x0UL) /*!< Either a trigger has not occurred or the counter is at 0. */ 13420 #define TPIU_SUPPORTEDTRIGGERMODES_TRGRUN_Occured (0x1UL) /*!< A trigger has occurred but the counter is not at 0. */ 13421 13422 /* Bit 16 : A trigger has occurred and the counter has reached 0. */ 13423 #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Pos (16UL) /*!< Position of TRIGGERED field. */ 13424 #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Pos) /*!< Bit mask of TRIGGERED field. */ 13425 #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_NotOccured (0x0UL) /*!< Trigger has not occurred. */ 13426 #define TPIU_SUPPORTEDTRIGGERMODES_TRIGGERED_Occured (0x1UL) /*!< Trigger has occurred. */ 13427 13428 /* Bit 8 : Indicates whether an 8-bit wide counter register is implemented. */ 13429 #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Pos (8UL) /*!< Position of TCOUNT8 field. */ 13430 #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Pos) /*!< Bit mask of TCOUNT8 field. */ 13431 #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_NotImplemented (0x0UL) /*!< An 8-bit wide counter register is implemented. */ 13432 #define TPIU_SUPPORTEDTRIGGERMODES_TCOUNT8_Implemented (0x1UL) /*!< An 8-bit wide counter register is implemented. */ 13433 13434 /* Bit 4 : Indicates whether multiplying the trigger counter by 2^(4+1) is supported. */ 13435 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_4_Pos (4UL) /*!< Position of MULT_4 field. */ 13436 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_4_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT_4_Pos) /*!< Bit mask of MULT_4 field. */ 13437 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_4_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(4+1) is supported. */ 13438 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_4_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(4+1) is supported. */ 13439 13440 /* Bit 3 : Indicates whether multiplying the trigger counter by 2^(3+1) is supported. */ 13441 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_3_Pos (3UL) /*!< Position of MULT_3 field. */ 13442 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_3_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT_3_Pos) /*!< Bit mask of MULT_3 field. */ 13443 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_3_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(3+1) is supported. */ 13444 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_3_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(3+1) is supported. */ 13445 13446 /* Bit 2 : Indicates whether multiplying the trigger counter by 2^(2+1) is supported. */ 13447 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_2_Pos (2UL) /*!< Position of MULT_2 field. */ 13448 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_2_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT_2_Pos) /*!< Bit mask of MULT_2 field. */ 13449 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_2_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(2+1) is supported. */ 13450 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_2_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(2+1) is supported. */ 13451 13452 /* Bit 1 : Indicates whether multiplying the trigger counter by 2^(1+1) is supported. */ 13453 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_1_Pos (1UL) /*!< Position of MULT_1 field. */ 13454 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_1_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT_1_Pos) /*!< Bit mask of MULT_1 field. */ 13455 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_1_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(1+1) is supported. */ 13456 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_1_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(1+1) is supported. */ 13457 13458 /* Bit 0 : Indicates whether multiplying the trigger counter by 2^(0+1) is supported. */ 13459 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_0_Pos (0UL) /*!< Position of MULT_0 field. */ 13460 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_0_Msk (0x1UL << TPIU_SUPPORTEDTRIGGERMODES_MULT_0_Pos) /*!< Bit mask of MULT_0 field. */ 13461 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_0_NotSelected (0x0UL) /*!< Multiplying the trigger counter by 2^(0+1) is supported. */ 13462 #define TPIU_SUPPORTEDTRIGGERMODES_MULT_0_Selected (0x1UL) /*!< Multiplying the trigger counter by 2^(0+1) is supported. */ 13463 13464 /* Register: TPIU_TRIGGERCOUNTERVALUE */ 13465 /* Description: The Trigger_counter_value register enables delaying the indication of triggers to any external connected trace capture or storage devices. */ 13466 13467 /* Bits 7..0 : 8-bit counter value for the number of words to be output from the formatter before a trigger is inserted. */ 13468 #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Pos (0UL) /*!< Position of TrigCount field. */ 13469 #define TPIU_TRIGGERCOUNTERVALUE_TrigCount_Msk (0xFFUL << TPIU_TRIGGERCOUNTERVALUE_TrigCount_Pos) /*!< Bit mask of TrigCount field. */ 13470 13471 /* Register: TPIU_TRIGGERMULTIPLIER */ 13472 /* Description: The Trigger_multiplier register contains the selectors for the trigger counter multiplier. */ 13473 13474 /* Bit 4 : Multiply the Trigger Counter by 2^n. */ 13475 #define TPIU_TRIGGERMULTIPLIER_MULT_4_Pos (4UL) /*!< Position of MULT_4 field. */ 13476 #define TPIU_TRIGGERMULTIPLIER_MULT_4_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT_4_Pos) /*!< Bit mask of MULT_4 field. */ 13477 #define TPIU_TRIGGERMULTIPLIER_MULT_4_Disabled (0x0UL) /*!< Multiplier disabled. */ 13478 #define TPIU_TRIGGERMULTIPLIER_MULT_4_Enabled (0x1UL) /*!< Multiplier enabled. */ 13479 13480 /* Bit 3 : Multiply the Trigger Counter by 2^n. */ 13481 #define TPIU_TRIGGERMULTIPLIER_MULT_3_Pos (3UL) /*!< Position of MULT_3 field. */ 13482 #define TPIU_TRIGGERMULTIPLIER_MULT_3_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT_3_Pos) /*!< Bit mask of MULT_3 field. */ 13483 #define TPIU_TRIGGERMULTIPLIER_MULT_3_Disabled (0x0UL) /*!< Multiplier disabled. */ 13484 #define TPIU_TRIGGERMULTIPLIER_MULT_3_Enabled (0x1UL) /*!< Multiplier enabled. */ 13485 13486 /* Bit 2 : Multiply the Trigger Counter by 2^n. */ 13487 #define TPIU_TRIGGERMULTIPLIER_MULT_2_Pos (2UL) /*!< Position of MULT_2 field. */ 13488 #define TPIU_TRIGGERMULTIPLIER_MULT_2_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT_2_Pos) /*!< Bit mask of MULT_2 field. */ 13489 #define TPIU_TRIGGERMULTIPLIER_MULT_2_Disabled (0x0UL) /*!< Multiplier disabled. */ 13490 #define TPIU_TRIGGERMULTIPLIER_MULT_2_Enabled (0x1UL) /*!< Multiplier enabled. */ 13491 13492 /* Bit 1 : Multiply the Trigger Counter by 2^n. */ 13493 #define TPIU_TRIGGERMULTIPLIER_MULT_1_Pos (1UL) /*!< Position of MULT_1 field. */ 13494 #define TPIU_TRIGGERMULTIPLIER_MULT_1_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT_1_Pos) /*!< Bit mask of MULT_1 field. */ 13495 #define TPIU_TRIGGERMULTIPLIER_MULT_1_Disabled (0x0UL) /*!< Multiplier disabled. */ 13496 #define TPIU_TRIGGERMULTIPLIER_MULT_1_Enabled (0x1UL) /*!< Multiplier enabled. */ 13497 13498 /* Bit 0 : Multiply the Trigger Counter by 2^n. */ 13499 #define TPIU_TRIGGERMULTIPLIER_MULT_0_Pos (0UL) /*!< Position of MULT_0 field. */ 13500 #define TPIU_TRIGGERMULTIPLIER_MULT_0_Msk (0x1UL << TPIU_TRIGGERMULTIPLIER_MULT_0_Pos) /*!< Bit mask of MULT_0 field. */ 13501 #define TPIU_TRIGGERMULTIPLIER_MULT_0_Disabled (0x0UL) /*!< Multiplier disabled. */ 13502 #define TPIU_TRIGGERMULTIPLIER_MULT_0_Enabled (0x1UL) /*!< Multiplier enabled. */ 13503 13504 /* Register: TPIU_SUPPPORTEDTESTPATTERNMODES */ 13505 /* Description: The Supported_test_pattern_modes register provides a set of known bit sequences or patterns that can be output over the trace port and can be detected by the TPA or other associated trace capture device. */ 13506 13507 /* Bit 17 : Indicates whether continuous mode is supported. */ 13508 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Pos (17UL) /*!< Position of PCONTEN field. */ 13509 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Pos) /*!< Bit mask of PCONTEN field. */ 13510 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_NotSupported (0x0UL) /*!< Mode is not supported. */ 13511 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PCONTEN_Supported (0x1UL) /*!< Mode is supported. */ 13512 13513 /* Bit 16 : Indicates whether timed mode is supported. */ 13514 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Pos (16UL) /*!< Position of PTIMEEN field. */ 13515 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Pos) /*!< Bit mask of PTIMEEN field. */ 13516 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_NotSupported (0x0UL) /*!< Mode is not supported. */ 13517 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PTIMEEN_Supported (0x1UL) /*!< Mode is supported. */ 13518 13519 /* Bit 3 : Indicates whether the FF/00 pattern is supported as output over the trace port. */ 13520 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Pos (3UL) /*!< Position of PATF0 field. */ 13521 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Pos) /*!< Bit mask of PATF0 field. */ 13522 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_NotSupported (0x0UL) /*!< Test pattern is not supported. */ 13523 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATF0_Supported (0x1UL) /*!< Test pattern is supported. */ 13524 13525 /* Bit 2 : Indicates whether the AA/55 pattern is supported as output over the trace port. */ 13526 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Pos (2UL) /*!< Position of PATA5 field. */ 13527 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Pos) /*!< Bit mask of PATA5 field. */ 13528 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_NotSupported (0x0UL) /*!< Test pattern is not supported. */ 13529 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATA5_Supported (0x1UL) /*!< Test pattern is supported. */ 13530 13531 /* Bit 1 : Indicates whether the walking 0s pattern is supported as output over the trace port. */ 13532 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Pos (1UL) /*!< Position of PATW0 field. */ 13533 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Pos) /*!< Bit mask of PATW0 field. */ 13534 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_NotSupported (0x0UL) /*!< Test pattern is not supported. */ 13535 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW0_Supported (0x1UL) /*!< Test pattern is supported. */ 13536 13537 /* Bit 0 : Indicates whether the walking 1s pattern is supported as output over the trace port. */ 13538 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Pos (0UL) /*!< Position of PATW1 field. */ 13539 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Msk (0x1UL << TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Pos) /*!< Bit mask of PATW1 field. */ 13540 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_NotSupported (0x0UL) /*!< Test pattern is not supported. */ 13541 #define TPIU_SUPPPORTEDTESTPATTERNMODES_PATW1_Supported (0x1UL) /*!< Test pattern is supported. */ 13542 13543 /* Register: TPIU_CURRENTTESTPATTERNMODES */ 13544 /* Description: Current_test_pattern_mode indicates the current test pattern or mode selected. */ 13545 13546 /* Bit 17 : Indicates whether continuous mode is supported. */ 13547 #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Pos (17UL) /*!< Position of PCONTEN field. */ 13548 #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Pos) /*!< Bit mask of PCONTEN field. */ 13549 #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Disabled (0x0UL) /*!< Mode is disabled. */ 13550 #define TPIU_CURRENTTESTPATTERNMODES_PCONTEN_Enabled (0x1UL) /*!< Mode is enabled. */ 13551 13552 /* Bit 16 : Indicates whether timed mode is supported. */ 13553 #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Pos (16UL) /*!< Position of PTIMEEN field. */ 13554 #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Pos) /*!< Bit mask of PTIMEEN field. */ 13555 #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Disabled (0x0UL) /*!< Mode is disabled. */ 13556 #define TPIU_CURRENTTESTPATTERNMODES_PTIMEEN_Enabled (0x1UL) /*!< Mode is enabled. */ 13557 13558 /* Bit 3 : Indicates whether the FF/00 pattern is supported as output over the trace port. */ 13559 #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Pos (3UL) /*!< Position of PATF0 field. */ 13560 #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATF0_Pos) /*!< Bit mask of PATF0 field. */ 13561 #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Disabled (0x0UL) /*!< Test pattern is disabled. */ 13562 #define TPIU_CURRENTTESTPATTERNMODES_PATF0_Enabled (0x1UL) /*!< Test pattern is enabled. */ 13563 13564 /* Bit 2 : Indicates whether the AA/55 pattern is supported as output over the trace port. */ 13565 #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Pos (2UL) /*!< Position of PATA5 field. */ 13566 #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATA5_Pos) /*!< Bit mask of PATA5 field. */ 13567 #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Disabled (0x0UL) /*!< Test pattern is disabled. */ 13568 #define TPIU_CURRENTTESTPATTERNMODES_PATA5_Enabled (0x1UL) /*!< Test pattern is enabled. */ 13569 13570 /* Bit 1 : Indicates whether the walking 0s pattern is supported as output over the trace port. */ 13571 #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Pos (1UL) /*!< Position of PATW0 field. */ 13572 #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATW0_Pos) /*!< Bit mask of PATW0 field. */ 13573 #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Disabled (0x0UL) /*!< Test pattern is disabled. */ 13574 #define TPIU_CURRENTTESTPATTERNMODES_PATW0_Enabled (0x1UL) /*!< Test pattern is enabled. */ 13575 13576 /* Bit 0 : Indicates whether the walking 1s pattern is supported as output over the trace port. */ 13577 #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Pos (0UL) /*!< Position of PATW1 field. */ 13578 #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Msk (0x1UL << TPIU_CURRENTTESTPATTERNMODES_PATW1_Pos) /*!< Bit mask of PATW1 field. */ 13579 #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Disabled (0x0UL) /*!< Test pattern is disabled. */ 13580 #define TPIU_CURRENTTESTPATTERNMODES_PATW1_Enabled (0x1UL) /*!< Test pattern is enabled. */ 13581 13582 /* Register: TPIU_TPRCR */ 13583 /* Description: The TPRCR register is an 8-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value. */ 13584 13585 /* Bits 7..0 : 8-bit counter value to indicate the number of traceclkin cycles for which a pattern runs before it switches to the next pattern. */ 13586 #define TPIU_TPRCR_PATTCOUNT_Pos (0UL) /*!< Position of PATTCOUNT field. */ 13587 #define TPIU_TPRCR_PATTCOUNT_Msk (0xFFUL << TPIU_TPRCR_PATTCOUNT_Pos) /*!< Bit mask of PATTCOUNT field. */ 13588 13589 /* Register: TPIU_FFSR */ 13590 /* Description: The FFSR register indicates the current status of the formatter and flush features available in the TPIU. */ 13591 13592 /* Bit 2 : Indicates whether the TRACECTL pin is available for use. */ 13593 #define TPIU_FFSR_TCPRESENT_Pos (2UL) /*!< Position of TCPRESENT field. */ 13594 #define TPIU_FFSR_TCPRESENT_Msk (0x1UL << TPIU_FFSR_TCPRESENT_Pos) /*!< Bit mask of TCPRESENT field. */ 13595 #define TPIU_FFSR_TCPRESENT_NotPresent (0x0UL) /*!< TRACECTL pin is not present. */ 13596 #define TPIU_FFSR_TCPRESENT_Present (0x1UL) /*!< TRACECTL pin is present. */ 13597 13598 /* Bit 1 : The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes HIGH. */ 13599 #define TPIU_FFSR_FTSTOPPED_Pos (1UL) /*!< Position of FTSTOPPED field. */ 13600 #define TPIU_FFSR_FTSTOPPED_Msk (0x1UL << TPIU_FFSR_FTSTOPPED_Pos) /*!< Bit mask of FTSTOPPED field. */ 13601 #define TPIU_FFSR_FTSTOPPED_Running (0x0UL) /*!< Formatter has not stopped. */ 13602 #define TPIU_FFSR_FTSTOPPED_Stopped (0x1UL) /*!< Formatter has stopped. */ 13603 13604 /* Bit 0 : Flush in progress. */ 13605 #define TPIU_FFSR_FLINPROG_Pos (0UL) /*!< Position of FLINPROG field. */ 13606 #define TPIU_FFSR_FLINPROG_Msk (0x1UL << TPIU_FFSR_FLINPROG_Pos) /*!< Bit mask of FLINPROG field. */ 13607 #define TPIU_FFSR_FLINPROG_NotInProgress (0x0UL) /*!< A flush is not in progress. */ 13608 #define TPIU_FFSR_FLINPROG_InProgress (0x1UL) /*!< A flush is in progress. */ 13609 13610 /* Register: TPIU_FFCR */ 13611 /* Description: The FFCR register controls the generation of stop, trigger, and flush events. */ 13612 13613 /* Bit 13 : Stops the formatter after a trigger event is observed. Reset to disabled or 0. */ 13614 #define TPIU_FFCR_STOPTRIG_Pos (13UL) /*!< Position of STOPTRIG field. */ 13615 #define TPIU_FFCR_STOPTRIG_Msk (0x1UL << TPIU_FFCR_STOPTRIG_Pos) /*!< Bit mask of STOPTRIG field. */ 13616 #define TPIU_FFCR_STOPTRIG_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13617 #define TPIU_FFCR_STOPTRIG_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13618 13619 /* Bit 12 : Forces the FIFO to drain off any part-completed packets. */ 13620 #define TPIU_FFCR_STOPFL_Pos (12UL) /*!< Position of STOPFL field. */ 13621 #define TPIU_FFCR_STOPFL_Msk (0x1UL << TPIU_FFCR_STOPFL_Pos) /*!< Bit mask of STOPFL field. */ 13622 #define TPIU_FFCR_STOPFL_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13623 #define TPIU_FFCR_STOPFL_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13624 13625 /* Bit 10 : Indicates a trigger when flush completion on afreadys is returned. */ 13626 #define TPIU_FFCR_TRIGFL_Pos (10UL) /*!< Position of TRIGFL field. */ 13627 #define TPIU_FFCR_TRIGFL_Msk (0x1UL << TPIU_FFCR_TRIGFL_Pos) /*!< Bit mask of TRIGFL field. */ 13628 #define TPIU_FFCR_TRIGFL_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13629 #define TPIU_FFCR_TRIGFL_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13630 13631 /* Bit 9 : Indicates a trigger on a trigger event. */ 13632 #define TPIU_FFCR_TRIGEVT_Pos (9UL) /*!< Position of TRIGEVT field. */ 13633 #define TPIU_FFCR_TRIGEVT_Msk (0x1UL << TPIU_FFCR_TRIGEVT_Pos) /*!< Bit mask of TRIGEVT field. */ 13634 #define TPIU_FFCR_TRIGEVT_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13635 #define TPIU_FFCR_TRIGEVT_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13636 13637 /* Bit 8 : Indicates a trigger when trigin is asserted. */ 13638 #define TPIU_FFCR_TRIGIN_Pos (8UL) /*!< Position of TRIGIN field. */ 13639 #define TPIU_FFCR_TRIGIN_Msk (0x1UL << TPIU_FFCR_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */ 13640 #define TPIU_FFCR_TRIGIN_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13641 #define TPIU_FFCR_TRIGIN_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13642 13643 /* Bit 7 : Generates a flush. This bit is set to 1 when this flush is serviced. */ 13644 #define TPIU_FFCR_FONMANW_Pos (7UL) /*!< Position of FONMANW field. */ 13645 #define TPIU_FFCR_FONMANW_Msk (0x1UL << TPIU_FFCR_FONMANW_Pos) /*!< Bit mask of FONMANW field. */ 13646 #define TPIU_FFCR_FONMANW_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13647 #define TPIU_FFCR_FONMANW_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13648 13649 /* Bit 6 : Generates a flush. This bit is set to 0 when this flush is serviced. */ 13650 #define TPIU_FFCR_FONMANR_Pos (6UL) /*!< Position of FONMANR field. */ 13651 #define TPIU_FFCR_FONMANR_Msk (0x1UL << TPIU_FFCR_FONMANR_Pos) /*!< Bit mask of FONMANR field. */ 13652 #define TPIU_FFCR_FONMANR_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13653 #define TPIU_FFCR_FONMANR_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13654 13655 /* Bit 5 : Initiates a manual flush of data in the system when a trigger event occurs. */ 13656 #define TPIU_FFCR_FONTRIG_Pos (5UL) /*!< Position of FONTRIG field. */ 13657 #define TPIU_FFCR_FONTRIG_Msk (0x1UL << TPIU_FFCR_FONTRIG_Pos) /*!< Bit mask of FONTRIG field. */ 13658 #define TPIU_FFCR_FONTRIG_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13659 #define TPIU_FFCR_FONTRIG_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13660 13661 /* Bit 4 : Enables the use of the flushin connection. */ 13662 #define TPIU_FFCR_FONFLIN_Pos (4UL) /*!< Position of FONFLIN field. */ 13663 #define TPIU_FFCR_FONFLIN_Msk (0x1UL << TPIU_FFCR_FONFLIN_Pos) /*!< Bit mask of FONFLIN field. */ 13664 #define TPIU_FFCR_FONFLIN_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13665 #define TPIU_FFCR_FONFLIN_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13666 13667 /* Bit 1 : Is embedded in trigger packets and indicates that no cycle is using sync packets. */ 13668 #define TPIU_FFCR_ENFCONT_Pos (1UL) /*!< Position of ENFCONT field. */ 13669 #define TPIU_FFCR_ENFCONT_Msk (0x1UL << TPIU_FFCR_ENFCONT_Pos) /*!< Bit mask of ENFCONT field. */ 13670 #define TPIU_FFCR_ENFCONT_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13671 #define TPIU_FFCR_ENFCONT_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13672 13673 /* Bit 0 : Do not embed triggers into the formatted stream. Trace disable cycles and triggers are indicated by tracectl, where present. */ 13674 #define TPIU_FFCR_ENFTC_Pos (0UL) /*!< Position of ENFTC field. */ 13675 #define TPIU_FFCR_ENFTC_Msk (0x1UL << TPIU_FFCR_ENFTC_Pos) /*!< Bit mask of ENFTC field. */ 13676 #define TPIU_FFCR_ENFTC_Disabled (0x0UL) /*!< The formatting feature is disabled. */ 13677 #define TPIU_FFCR_ENFTC_Enabled (0x1UL) /*!< The formatting feature is enabled. */ 13678 13679 /* Register: TPIU_FSCR */ 13680 /* Description: The FSCR register enables the frequency of synchronization information to be optimized to suit the Trace Port Analyzer (TPA) capture buffer size. */ 13681 13682 /* Bits 11..0 : 12-bit counter reload value. Indicates the number of complete frames between full synchronization packets. */ 13683 #define TPIU_FSCR_CYCCOUNT_Pos (0UL) /*!< Position of CYCCOUNT field. */ 13684 #define TPIU_FSCR_CYCCOUNT_Msk (0xFFFUL << TPIU_FSCR_CYCCOUNT_Pos) /*!< Bit mask of CYCCOUNT field. */ 13685 13686 /* Register: TPIU_EXTCTLINPORT */ 13687 /* Description: Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high-speed trace port solution. */ 13688 13689 /* Bit 7 : EXTCTL inputs. */ 13690 #define TPIU_EXTCTLINPORT_EXTCTLIN_7_Pos (7UL) /*!< Position of EXTCTLIN_7 field. */ 13691 #define TPIU_EXTCTLINPORT_EXTCTLIN_7_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_7_Pos) /*!< Bit mask of EXTCTLIN_7 field. */ 13692 #define TPIU_EXTCTLINPORT_EXTCTLIN_7_Low (0x0UL) /*!< Input EXTCTL7 is low. */ 13693 #define TPIU_EXTCTLINPORT_EXTCTLIN_7_High (0x1UL) /*!< Input EXTCTL7 is high. */ 13694 13695 /* Bit 6 : EXTCTL inputs. */ 13696 #define TPIU_EXTCTLINPORT_EXTCTLIN_6_Pos (6UL) /*!< Position of EXTCTLIN_6 field. */ 13697 #define TPIU_EXTCTLINPORT_EXTCTLIN_6_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_6_Pos) /*!< Bit mask of EXTCTLIN_6 field. */ 13698 #define TPIU_EXTCTLINPORT_EXTCTLIN_6_Low (0x0UL) /*!< Input EXTCTL6 is low. */ 13699 #define TPIU_EXTCTLINPORT_EXTCTLIN_6_High (0x1UL) /*!< Input EXTCTL6 is high. */ 13700 13701 /* Bit 5 : EXTCTL inputs. */ 13702 #define TPIU_EXTCTLINPORT_EXTCTLIN_5_Pos (5UL) /*!< Position of EXTCTLIN_5 field. */ 13703 #define TPIU_EXTCTLINPORT_EXTCTLIN_5_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_5_Pos) /*!< Bit mask of EXTCTLIN_5 field. */ 13704 #define TPIU_EXTCTLINPORT_EXTCTLIN_5_Low (0x0UL) /*!< Input EXTCTL5 is low. */ 13705 #define TPIU_EXTCTLINPORT_EXTCTLIN_5_High (0x1UL) /*!< Input EXTCTL5 is high. */ 13706 13707 /* Bit 4 : EXTCTL inputs. */ 13708 #define TPIU_EXTCTLINPORT_EXTCTLIN_4_Pos (4UL) /*!< Position of EXTCTLIN_4 field. */ 13709 #define TPIU_EXTCTLINPORT_EXTCTLIN_4_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_4_Pos) /*!< Bit mask of EXTCTLIN_4 field. */ 13710 #define TPIU_EXTCTLINPORT_EXTCTLIN_4_Low (0x0UL) /*!< Input EXTCTL4 is low. */ 13711 #define TPIU_EXTCTLINPORT_EXTCTLIN_4_High (0x1UL) /*!< Input EXTCTL4 is high. */ 13712 13713 /* Bit 3 : EXTCTL inputs. */ 13714 #define TPIU_EXTCTLINPORT_EXTCTLIN_3_Pos (3UL) /*!< Position of EXTCTLIN_3 field. */ 13715 #define TPIU_EXTCTLINPORT_EXTCTLIN_3_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_3_Pos) /*!< Bit mask of EXTCTLIN_3 field. */ 13716 #define TPIU_EXTCTLINPORT_EXTCTLIN_3_Low (0x0UL) /*!< Input EXTCTL3 is low. */ 13717 #define TPIU_EXTCTLINPORT_EXTCTLIN_3_High (0x1UL) /*!< Input EXTCTL3 is high. */ 13718 13719 /* Bit 2 : EXTCTL inputs. */ 13720 #define TPIU_EXTCTLINPORT_EXTCTLIN_2_Pos (2UL) /*!< Position of EXTCTLIN_2 field. */ 13721 #define TPIU_EXTCTLINPORT_EXTCTLIN_2_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_2_Pos) /*!< Bit mask of EXTCTLIN_2 field. */ 13722 #define TPIU_EXTCTLINPORT_EXTCTLIN_2_Low (0x0UL) /*!< Input EXTCTL2 is low. */ 13723 #define TPIU_EXTCTLINPORT_EXTCTLIN_2_High (0x1UL) /*!< Input EXTCTL2 is high. */ 13724 13725 /* Bit 1 : EXTCTL inputs. */ 13726 #define TPIU_EXTCTLINPORT_EXTCTLIN_1_Pos (1UL) /*!< Position of EXTCTLIN_1 field. */ 13727 #define TPIU_EXTCTLINPORT_EXTCTLIN_1_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_1_Pos) /*!< Bit mask of EXTCTLIN_1 field. */ 13728 #define TPIU_EXTCTLINPORT_EXTCTLIN_1_Low (0x0UL) /*!< Input EXTCTL1 is low. */ 13729 #define TPIU_EXTCTLINPORT_EXTCTLIN_1_High (0x1UL) /*!< Input EXTCTL1 is high. */ 13730 13731 /* Bit 0 : EXTCTL inputs. */ 13732 #define TPIU_EXTCTLINPORT_EXTCTLIN_0_Pos (0UL) /*!< Position of EXTCTLIN_0 field. */ 13733 #define TPIU_EXTCTLINPORT_EXTCTLIN_0_Msk (0x1UL << TPIU_EXTCTLINPORT_EXTCTLIN_0_Pos) /*!< Bit mask of EXTCTLIN_0 field. */ 13734 #define TPIU_EXTCTLINPORT_EXTCTLIN_0_Low (0x0UL) /*!< Input EXTCTL0 is low. */ 13735 #define TPIU_EXTCTLINPORT_EXTCTLIN_0_High (0x1UL) /*!< Input EXTCTL0 is high. */ 13736 13737 /* Register: TPIU_EXTCTLOUTPORT */ 13738 /* Description: Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexers, or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. */ 13739 13740 /* Bit 7 : EXTCTL outputs. */ 13741 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_7_Pos (7UL) /*!< Position of EXTCTLOUT_7 field. */ 13742 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_7_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_7_Pos) /*!< Bit mask of EXTCTLOUT_7 field. */ 13743 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_7_Low (0x0UL) /*!< Output EXTCTL7 is low. */ 13744 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_7_High (0x1UL) /*!< Output EXTCTL7 is high. */ 13745 13746 /* Bit 6 : EXTCTL outputs. */ 13747 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_6_Pos (6UL) /*!< Position of EXTCTLOUT_6 field. */ 13748 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_6_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_6_Pos) /*!< Bit mask of EXTCTLOUT_6 field. */ 13749 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_6_Low (0x0UL) /*!< Output EXTCTL6 is low. */ 13750 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_6_High (0x1UL) /*!< Output EXTCTL6 is high. */ 13751 13752 /* Bit 5 : EXTCTL outputs. */ 13753 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_5_Pos (5UL) /*!< Position of EXTCTLOUT_5 field. */ 13754 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_5_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_5_Pos) /*!< Bit mask of EXTCTLOUT_5 field. */ 13755 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_5_Low (0x0UL) /*!< Output EXTCTL5 is low. */ 13756 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_5_High (0x1UL) /*!< Output EXTCTL5 is high. */ 13757 13758 /* Bit 4 : EXTCTL outputs. */ 13759 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_4_Pos (4UL) /*!< Position of EXTCTLOUT_4 field. */ 13760 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_4_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_4_Pos) /*!< Bit mask of EXTCTLOUT_4 field. */ 13761 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_4_Low (0x0UL) /*!< Output EXTCTL4 is low. */ 13762 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_4_High (0x1UL) /*!< Output EXTCTL4 is high. */ 13763 13764 /* Bit 3 : EXTCTL outputs. */ 13765 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_3_Pos (3UL) /*!< Position of EXTCTLOUT_3 field. */ 13766 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_3_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_3_Pos) /*!< Bit mask of EXTCTLOUT_3 field. */ 13767 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_3_Low (0x0UL) /*!< Output EXTCTL3 is low. */ 13768 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_3_High (0x1UL) /*!< Output EXTCTL3 is high. */ 13769 13770 /* Bit 2 : EXTCTL outputs. */ 13771 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_2_Pos (2UL) /*!< Position of EXTCTLOUT_2 field. */ 13772 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_2_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_2_Pos) /*!< Bit mask of EXTCTLOUT_2 field. */ 13773 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_2_Low (0x0UL) /*!< Output EXTCTL2 is low. */ 13774 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_2_High (0x1UL) /*!< Output EXTCTL2 is high. */ 13775 13776 /* Bit 1 : EXTCTL outputs. */ 13777 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_1_Pos (1UL) /*!< Position of EXTCTLOUT_1 field. */ 13778 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_1_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_1_Pos) /*!< Bit mask of EXTCTLOUT_1 field. */ 13779 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_1_Low (0x0UL) /*!< Output EXTCTL1 is low. */ 13780 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_1_High (0x1UL) /*!< Output EXTCTL1 is high. */ 13781 13782 /* Bit 0 : EXTCTL outputs. */ 13783 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_0_Pos (0UL) /*!< Position of EXTCTLOUT_0 field. */ 13784 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_0_Msk (0x1UL << TPIU_EXTCTLOUTPORT_EXTCTLOUT_0_Pos) /*!< Bit mask of EXTCTLOUT_0 field. */ 13785 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_0_Low (0x0UL) /*!< Output EXTCTL0 is low. */ 13786 #define TPIU_EXTCTLOUTPORT_EXTCTLOUT_0_High (0x1UL) /*!< Output EXTCTL0 is high. */ 13787 13788 /* Register: TPIU_ITTRFLINACK */ 13789 /* Description: The ITTRFLINACK register enables control of the triginack and flushinack outputs from the TPIU. */ 13790 13791 /* Bit 1 : Sets the value of flushinack. */ 13792 #define TPIU_ITTRFLINACK_FLUSHINACK_Pos (1UL) /*!< Position of FLUSHINACK field. */ 13793 #define TPIU_ITTRFLINACK_FLUSHINACK_Msk (0x1UL << TPIU_ITTRFLINACK_FLUSHINACK_Pos) /*!< Bit mask of FLUSHINACK field. */ 13794 #define TPIU_ITTRFLINACK_FLUSHINACK_Low (0x0UL) /*!< Pin is logic 0. */ 13795 #define TPIU_ITTRFLINACK_FLUSHINACK_High (0x1UL) /*!< Pin is logic 1. */ 13796 13797 /* Bit 0 : Sets the value of triginack. */ 13798 #define TPIU_ITTRFLINACK_TRIGINACK_Pos (0UL) /*!< Position of TRIGINACK field. */ 13799 #define TPIU_ITTRFLINACK_TRIGINACK_Msk (0x1UL << TPIU_ITTRFLINACK_TRIGINACK_Pos) /*!< Bit mask of TRIGINACK field. */ 13800 #define TPIU_ITTRFLINACK_TRIGINACK_Low (0x0UL) /*!< Pin is logic 0. */ 13801 #define TPIU_ITTRFLINACK_TRIGINACK_High (0x1UL) /*!< Pin is logic 1. */ 13802 13803 /* Register: TPIU_ITTRFLIN */ 13804 /* Description: The ITTRFLIN register contains the values of the flushin and trigin inputs to the TPIU. */ 13805 13806 /* Bit 1 : Reads the value of flushin. */ 13807 #define TPIU_ITTRFLIN_FLUSHIN_Pos (1UL) /*!< Position of FLUSHIN field. */ 13808 #define TPIU_ITTRFLIN_FLUSHIN_Msk (0x1UL << TPIU_ITTRFLIN_FLUSHIN_Pos) /*!< Bit mask of FLUSHIN field. */ 13809 #define TPIU_ITTRFLIN_FLUSHIN_Low (0x0UL) /*!< Pin is logic 0. */ 13810 #define TPIU_ITTRFLIN_FLUSHIN_High (0x1UL) /*!< Pin is logic 1. */ 13811 13812 /* Bit 0 : Reads the value of trigin. */ 13813 #define TPIU_ITTRFLIN_TRIGIN_Pos (0UL) /*!< Position of TRIGIN field. */ 13814 #define TPIU_ITTRFLIN_TRIGIN_Msk (0x1UL << TPIU_ITTRFLIN_TRIGIN_Pos) /*!< Bit mask of TRIGIN field. */ 13815 #define TPIU_ITTRFLIN_TRIGIN_Low (0x0UL) /*!< Pin is logic 0. */ 13816 #define TPIU_ITTRFLIN_TRIGIN_High (0x1UL) /*!< Pin is logic 1. */ 13817 13818 /* Register: TPIU_ITATBDATA0 */ 13819 /* Description: The ITATBDATA0 register contains the value of the atdatas inputs to the TPIU. The values are valid only when atvalids is HIGH. */ 13820 13821 /* Bit 4 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 13822 #define TPIU_ITATBDATA0_ATDATA_4_Pos (4UL) /*!< Position of ATDATA_4 field. */ 13823 #define TPIU_ITATBDATA0_ATDATA_4_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA_4_Pos) /*!< Bit mask of ATDATA_4 field. */ 13824 #define TPIU_ITATBDATA0_ATDATA_4_Low (0x0UL) /*!< Pin is logic 0. */ 13825 #define TPIU_ITATBDATA0_ATDATA_4_High (0x1UL) /*!< Pin is logic 1. */ 13826 13827 /* Bit 3 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 13828 #define TPIU_ITATBDATA0_ATDATA_3_Pos (3UL) /*!< Position of ATDATA_3 field. */ 13829 #define TPIU_ITATBDATA0_ATDATA_3_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA_3_Pos) /*!< Bit mask of ATDATA_3 field. */ 13830 #define TPIU_ITATBDATA0_ATDATA_3_Low (0x0UL) /*!< Pin is logic 0. */ 13831 #define TPIU_ITATBDATA0_ATDATA_3_High (0x1UL) /*!< Pin is logic 1. */ 13832 13833 /* Bit 2 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 13834 #define TPIU_ITATBDATA0_ATDATA_2_Pos (2UL) /*!< Position of ATDATA_2 field. */ 13835 #define TPIU_ITATBDATA0_ATDATA_2_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA_2_Pos) /*!< Bit mask of ATDATA_2 field. */ 13836 #define TPIU_ITATBDATA0_ATDATA_2_Low (0x0UL) /*!< Pin is logic 0. */ 13837 #define TPIU_ITATBDATA0_ATDATA_2_High (0x1UL) /*!< Pin is logic 1. */ 13838 13839 /* Bit 1 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 13840 #define TPIU_ITATBDATA0_ATDATA_1_Pos (1UL) /*!< Position of ATDATA_1 field. */ 13841 #define TPIU_ITATBDATA0_ATDATA_1_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA_1_Pos) /*!< Bit mask of ATDATA_1 field. */ 13842 #define TPIU_ITATBDATA0_ATDATA_1_Low (0x0UL) /*!< Pin is logic 0. */ 13843 #define TPIU_ITATBDATA0_ATDATA_1_High (0x1UL) /*!< Pin is logic 1. */ 13844 13845 /* Bit 0 : A read access returns the value of a pin on atdatas_x of the enabled port. A write access writes to the corresponding atdatam pin of the enabled port. */ 13846 #define TPIU_ITATBDATA0_ATDATA_0_Pos (0UL) /*!< Position of ATDATA_0 field. */ 13847 #define TPIU_ITATBDATA0_ATDATA_0_Msk (0x1UL << TPIU_ITATBDATA0_ATDATA_0_Pos) /*!< Bit mask of ATDATA_0 field. */ 13848 #define TPIU_ITATBDATA0_ATDATA_0_Low (0x0UL) /*!< Pin is logic 0. */ 13849 #define TPIU_ITATBDATA0_ATDATA_0_High (0x1UL) /*!< Pin is logic 1. */ 13850 13851 /* Register: TPIU_ITATBCTR2 */ 13852 /* Description: Enables control of the atreadys and afvalids outputs of the TPIU. */ 13853 13854 /* Bit 1 : Sets the value of atready. */ 13855 #define TPIU_ITATBCTR2_AFVALID_Pos (1UL) /*!< Position of AFVALID field. */ 13856 #define TPIU_ITATBCTR2_AFVALID_Msk (0x1UL << TPIU_ITATBCTR2_AFVALID_Pos) /*!< Bit mask of AFVALID field. */ 13857 #define TPIU_ITATBCTR2_AFVALID_Low (0x0UL) /*!< Pin is logic 0. */ 13858 #define TPIU_ITATBCTR2_AFVALID_High (0x1UL) /*!< Pin is logic 1. */ 13859 13860 /* Bit 0 : Sets the value of afvalid. */ 13861 #define TPIU_ITATBCTR2_ATREADY_Pos (0UL) /*!< Position of ATREADY field. */ 13862 #define TPIU_ITATBCTR2_ATREADY_Msk (0x1UL << TPIU_ITATBCTR2_ATREADY_Pos) /*!< Bit mask of ATREADY field. */ 13863 #define TPIU_ITATBCTR2_ATREADY_Low (0x0UL) /*!< Pin is logic 0. */ 13864 #define TPIU_ITATBCTR2_ATREADY_High (0x1UL) /*!< Pin is logic 1. */ 13865 13866 /* Register: TPIU_ITATBCTR1 */ 13867 /* Description: The ITATBCTR1 register contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH. */ 13868 13869 /* Bits 6..0 : Reads the value of atids. */ 13870 #define TPIU_ITATBCTR1_ATID_Pos (0UL) /*!< Position of ATID field. */ 13871 #define TPIU_ITATBCTR1_ATID_Msk (0x7FUL << TPIU_ITATBCTR1_ATID_Pos) /*!< Bit mask of ATID field. */ 13872 #define TPIU_ITATBCTR1_ATID_Low (0x00UL) /*!< Pin is logic 0. */ 13873 #define TPIU_ITATBCTR1_ATID_High (0x01UL) /*!< Pin is logic 1. */ 13874 13875 /* Register: TPIU_ITATBCTR0 */ 13876 /* Description: The ITATBCTR0 register captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. 13877 To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit[0], is HIGH. */ 13878 13879 /* Bits 9..8 : Reads the value of atbytess. */ 13880 #define TPIU_ITATBCTR0_ATBYTES_Pos (8UL) /*!< Position of ATBYTES field. */ 13881 #define TPIU_ITATBCTR0_ATBYTES_Msk (0x3UL << TPIU_ITATBCTR0_ATBYTES_Pos) /*!< Bit mask of ATBYTES field. */ 13882 #define TPIU_ITATBCTR0_ATBYTES_Low (0x0UL) /*!< Pin is logic 0. */ 13883 #define TPIU_ITATBCTR0_ATBYTES_High (0x1UL) /*!< Pin is logic 1. */ 13884 13885 /* Bit 2 : Reads the value of afreadys. */ 13886 #define TPIU_ITATBCTR0_AFREADY_Pos (2UL) /*!< Position of AFREADY field. */ 13887 #define TPIU_ITATBCTR0_AFREADY_Msk (0x1UL << TPIU_ITATBCTR0_AFREADY_Pos) /*!< Bit mask of AFREADY field. */ 13888 #define TPIU_ITATBCTR0_AFREADY_Low (0x0UL) /*!< Pin is logic 0. */ 13889 #define TPIU_ITATBCTR0_AFREADY_High (0x1UL) /*!< Pin is logic 1. */ 13890 13891 /* Bit 0 : Reads the value of atvalids. */ 13892 #define TPIU_ITATBCTR0_ATVALID_Pos (0UL) /*!< Position of ATVALID field. */ 13893 #define TPIU_ITATBCTR0_ATVALID_Msk (0x1UL << TPIU_ITATBCTR0_ATVALID_Pos) /*!< Bit mask of ATVALID field. */ 13894 #define TPIU_ITATBCTR0_ATVALID_Low (0x0UL) /*!< Pin is logic 0. */ 13895 #define TPIU_ITATBCTR0_ATVALID_High (0x1UL) /*!< Pin is logic 1. */ 13896 13897 /* Register: TPIU_ITCTRL */ 13898 /* Description: Used to enable topology detection. 13899 This register enables the component to switch from a functional mode, the default behavior, 13900 to integration mode where the inputs and outputs of the component can be directly controlled for integration testing and topology solving. */ 13901 13902 /* Bit 0 : Enables the component to switch from functional mode to integration mode and back. If no integration functionality is implemented, this register must read as zero. */ 13903 #define TPIU_ITCTRL_INTEGRATIONMODE_Pos (0UL) /*!< Position of INTEGRATIONMODE field. */ 13904 #define TPIU_ITCTRL_INTEGRATIONMODE_Msk (0x1UL << TPIU_ITCTRL_INTEGRATIONMODE_Pos) /*!< Bit mask of INTEGRATIONMODE field. */ 13905 #define TPIU_ITCTRL_INTEGRATIONMODE_Disabled (0x0UL) /*!< Integration mode is disabled. */ 13906 #define TPIU_ITCTRL_INTEGRATIONMODE_Enabled (0x1UL) /*!< Integration mode is Enabled. */ 13907 13908 /* Register: TPIU_CLAIMSET */ 13909 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. 13910 The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented. */ 13911 13912 /* Bit 3 : Set claim bit 3 and check if bit is implemented or not. */ 13913 #define TPIU_CLAIMSET_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */ 13914 #define TPIU_CLAIMSET_BIT_3_Msk (0x1UL << TPIU_CLAIMSET_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */ 13915 #define TPIU_CLAIMSET_BIT_3_NotImplemented (0x0UL) /*!< Claim bit 3 is not implemented. */ 13916 #define TPIU_CLAIMSET_BIT_3_Implemented (0x1UL) /*!< Claim bit 3 is implemented. */ 13917 #define TPIU_CLAIMSET_BIT_3_Set (0x1UL) /*!< Set claim bit 3. */ 13918 13919 /* Bit 2 : Set claim bit 2 and check if bit is implemented or not. */ 13920 #define TPIU_CLAIMSET_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */ 13921 #define TPIU_CLAIMSET_BIT_2_Msk (0x1UL << TPIU_CLAIMSET_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */ 13922 #define TPIU_CLAIMSET_BIT_2_NotImplemented (0x0UL) /*!< Claim bit 2 is not implemented. */ 13923 #define TPIU_CLAIMSET_BIT_2_Implemented (0x1UL) /*!< Claim bit 2 is implemented. */ 13924 #define TPIU_CLAIMSET_BIT_2_Set (0x1UL) /*!< Set claim bit 2. */ 13925 13926 /* Bit 1 : Set claim bit 1 and check if bit is implemented or not. */ 13927 #define TPIU_CLAIMSET_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */ 13928 #define TPIU_CLAIMSET_BIT_1_Msk (0x1UL << TPIU_CLAIMSET_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */ 13929 #define TPIU_CLAIMSET_BIT_1_NotImplemented (0x0UL) /*!< Claim bit 1 is not implemented. */ 13930 #define TPIU_CLAIMSET_BIT_1_Implemented (0x1UL) /*!< Claim bit 1 is implemented. */ 13931 #define TPIU_CLAIMSET_BIT_1_Set (0x1UL) /*!< Set claim bit 1. */ 13932 13933 /* Bit 0 : Set claim bit 0 and check if bit is implemented or not. */ 13934 #define TPIU_CLAIMSET_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */ 13935 #define TPIU_CLAIMSET_BIT_0_Msk (0x1UL << TPIU_CLAIMSET_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */ 13936 #define TPIU_CLAIMSET_BIT_0_NotImplemented (0x0UL) /*!< Claim bit 0 is not implemented. */ 13937 #define TPIU_CLAIMSET_BIT_0_Implemented (0x1UL) /*!< Claim bit 0 is implemented. */ 13938 #define TPIU_CLAIMSET_BIT_0_Set (0x1UL) /*!< Set claim bit 0. */ 13939 13940 /* Register: TPIU_CLAIMCLR */ 13941 /* Description: Software can use the claim tag to coordinate application and debugger access to trace unit functionality. 13942 The claim tags have no effect on the operation of the component. 13943 The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag. */ 13944 13945 /* Bit 3 : Read or clear claim bit 3. */ 13946 #define TPIU_CLAIMCLR_BIT_3_Pos (3UL) /*!< Position of BIT_3 field. */ 13947 #define TPIU_CLAIMCLR_BIT_3_Msk (0x1UL << TPIU_CLAIMCLR_BIT_3_Pos) /*!< Bit mask of BIT_3 field. */ 13948 #define TPIU_CLAIMCLR_BIT_3_Cleared (0x0UL) /*!< Claim bit 3 is not set. */ 13949 #define TPIU_CLAIMCLR_BIT_3_Set (0x1UL) /*!< Claim bit 3 is set. */ 13950 #define TPIU_CLAIMCLR_BIT_3_Clear (0x1UL) /*!< Clear claim bit 3. */ 13951 13952 /* Bit 2 : Read or clear claim bit 2. */ 13953 #define TPIU_CLAIMCLR_BIT_2_Pos (2UL) /*!< Position of BIT_2 field. */ 13954 #define TPIU_CLAIMCLR_BIT_2_Msk (0x1UL << TPIU_CLAIMCLR_BIT_2_Pos) /*!< Bit mask of BIT_2 field. */ 13955 #define TPIU_CLAIMCLR_BIT_2_Cleared (0x0UL) /*!< Claim bit 2 is not set. */ 13956 #define TPIU_CLAIMCLR_BIT_2_Set (0x1UL) /*!< Claim bit 2 is set. */ 13957 #define TPIU_CLAIMCLR_BIT_2_Clear (0x1UL) /*!< Clear claim bit 2. */ 13958 13959 /* Bit 1 : Read or clear claim bit 1. */ 13960 #define TPIU_CLAIMCLR_BIT_1_Pos (1UL) /*!< Position of BIT_1 field. */ 13961 #define TPIU_CLAIMCLR_BIT_1_Msk (0x1UL << TPIU_CLAIMCLR_BIT_1_Pos) /*!< Bit mask of BIT_1 field. */ 13962 #define TPIU_CLAIMCLR_BIT_1_Cleared (0x0UL) /*!< Claim bit 1 is not set. */ 13963 #define TPIU_CLAIMCLR_BIT_1_Set (0x1UL) /*!< Claim bit 1 is set. */ 13964 #define TPIU_CLAIMCLR_BIT_1_Clear (0x1UL) /*!< Clear claim bit 1. */ 13965 13966 /* Bit 0 : Read or clear claim bit 0. */ 13967 #define TPIU_CLAIMCLR_BIT_0_Pos (0UL) /*!< Position of BIT_0 field. */ 13968 #define TPIU_CLAIMCLR_BIT_0_Msk (0x1UL << TPIU_CLAIMCLR_BIT_0_Pos) /*!< Bit mask of BIT_0 field. */ 13969 #define TPIU_CLAIMCLR_BIT_0_Cleared (0x0UL) /*!< Claim bit 0 is not set. */ 13970 #define TPIU_CLAIMCLR_BIT_0_Set (0x1UL) /*!< Claim bit 0 is set. */ 13971 #define TPIU_CLAIMCLR_BIT_0_Clear (0x1UL) /*!< Clear claim bit 0. */ 13972 13973 /* Register: TPIU_LAR */ 13974 /* Description: This is used to enable write access to device registers. */ 13975 13976 /* Bits 31..0 : A write of 0xC5ACCE55 enables further write access to this device. Any other write removes write access. */ 13977 #define TPIU_LAR_ACCESS_Pos (0UL) /*!< Position of ACCESS field. */ 13978 #define TPIU_LAR_ACCESS_Msk (0xFFFFFFFFUL << TPIU_LAR_ACCESS_Pos) /*!< Bit mask of ACCESS field. */ 13979 #define TPIU_LAR_ACCESS_UnLock (0xC5ACCE55UL) /*!< Unlock register interface. */ 13980 13981 /* Register: TPIU_LSR */ 13982 /* Description: This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. 13983 Accesses to the extended stimulus port registers are not affected by the lock mechanism. 13984 This register must always be present although there might not be any lock access control mechanism. 13985 The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. 13986 For most components this covers all registers except for the Lock Access Register. */ 13987 13988 /* Bit 2 : Indicates if the Lock Access Register is implemented as 8-bit or 32-bit. */ 13989 #define TPIU_LSR_TYPE_Pos (2UL) /*!< Position of TYPE field. */ 13990 #define TPIU_LSR_TYPE_Msk (0x1UL << TPIU_LSR_TYPE_Pos) /*!< Bit mask of TYPE field. */ 13991 #define TPIU_LSR_TYPE_Bits32 (0x0UL) /*!< This component implements a 32-bit Lock Access Register. */ 13992 #define TPIU_LSR_TYPE_Bits8 (0x1UL) /*!< This component implements an 8-bit Lock Access Register. */ 13993 13994 /* Bit 1 : Returns the current status of the Lock. */ 13995 #define TPIU_LSR_LOCKED_Pos (1UL) /*!< Position of LOCKED field. */ 13996 #define TPIU_LSR_LOCKED_Msk (0x1UL << TPIU_LSR_LOCKED_Pos) /*!< Bit mask of LOCKED field. */ 13997 #define TPIU_LSR_LOCKED_UnLocked (0x0UL) /*!< Write access is allowed to this device. */ 13998 #define TPIU_LSR_LOCKED_Locked (0x1UL) /*!< Write access to the component is blocked. All writes to control registers are ignored. Reads are permitted. */ 13999 14000 /* Bit 0 : Indicates that a lock control mechanism exists for this device. */ 14001 #define TPIU_LSR_PRESENT_Pos (0UL) /*!< Position of PRESENT field. */ 14002 #define TPIU_LSR_PRESENT_Msk (0x1UL << TPIU_LSR_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ 14003 #define TPIU_LSR_PRESENT_NotImplemented (0x0UL) /*!< No lock control mechanism exists, writes to the Lock Access Register are ignored. */ 14004 #define TPIU_LSR_PRESENT_Implemented (0x1UL) /*!< Lock control mechanism is present. */ 14005 14006 /* Register: TPIU_AUTHSTATUS */ 14007 /* Description: Indicates the current level of tracing permitted by the system */ 14008 14009 /* Bits 7..6 : Secure Non-Invasive Debug */ 14010 #define TPIU_AUTHSTATUS_SNID_Pos (6UL) /*!< Position of SNID field. */ 14011 #define TPIU_AUTHSTATUS_SNID_Msk (0x3UL << TPIU_AUTHSTATUS_SNID_Pos) /*!< Bit mask of SNID field. */ 14012 #define TPIU_AUTHSTATUS_SNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 14013 #define TPIU_AUTHSTATUS_SNID_Implemented (0x1UL) /*!< The feature is implemented. */ 14014 14015 /* Bits 5..4 : Secure Invasive Debug */ 14016 #define TPIU_AUTHSTATUS_SID_Pos (4UL) /*!< Position of SID field. */ 14017 #define TPIU_AUTHSTATUS_SID_Msk (0x3UL << TPIU_AUTHSTATUS_SID_Pos) /*!< Bit mask of SID field. */ 14018 #define TPIU_AUTHSTATUS_SID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 14019 #define TPIU_AUTHSTATUS_SID_Implemented (0x1UL) /*!< The feature is implemented. */ 14020 14021 /* Bits 3..2 : Non-secure Non-Invasive Debug */ 14022 #define TPIU_AUTHSTATUS_NSNID_Pos (2UL) /*!< Position of NSNID field. */ 14023 #define TPIU_AUTHSTATUS_NSNID_Msk (0x3UL << TPIU_AUTHSTATUS_NSNID_Pos) /*!< Bit mask of NSNID field. */ 14024 #define TPIU_AUTHSTATUS_NSNID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 14025 #define TPIU_AUTHSTATUS_NSNID_Implemented (0x1UL) /*!< The feature is implemented. */ 14026 14027 /* Bits 1..0 : Non-secure Invasive Debug */ 14028 #define TPIU_AUTHSTATUS_NSID_Pos (0UL) /*!< Position of NSID field. */ 14029 #define TPIU_AUTHSTATUS_NSID_Msk (0x3UL << TPIU_AUTHSTATUS_NSID_Pos) /*!< Bit mask of NSID field. */ 14030 #define TPIU_AUTHSTATUS_NSID_NotImplemented (0x0UL) /*!< The feature is not implemented. */ 14031 #define TPIU_AUTHSTATUS_NSID_Implemented (0x1UL) /*!< The feature is implemented. */ 14032 14033 /* Register: TPIU_DEVID */ 14034 /* Description: Indicates the capabilities of the component. */ 14035 14036 /* Bit 11 : Indicates whether Serial Wire Output, UART or NRZ, is supported. */ 14037 #define TPIU_DEVID_SWOUARTNRZ_Pos (11UL) /*!< Position of SWOUARTNRZ field. */ 14038 #define TPIU_DEVID_SWOUARTNRZ_Msk (0x1UL << TPIU_DEVID_SWOUARTNRZ_Pos) /*!< Bit mask of SWOUARTNRZ field. */ 14039 #define TPIU_DEVID_SWOUARTNRZ_NotSupported (0x0UL) /*!< Serial Wire Output, UART or NRZ, is not supported. */ 14040 #define TPIU_DEVID_SWOUARTNRZ_Supported (0x1UL) /*!< Serial Wire Output, UART or NRZ, is supported. */ 14041 14042 /* Bit 10 : Indicates whether Serial Wire Output, Manchester encoded format, is supported. */ 14043 #define TPIU_DEVID_SWOMAN_Pos (10UL) /*!< Position of SWOMAN field. */ 14044 #define TPIU_DEVID_SWOMAN_Msk (0x1UL << TPIU_DEVID_SWOMAN_Pos) /*!< Bit mask of SWOMAN field. */ 14045 #define TPIU_DEVID_SWOMAN_NotSupported (0x0UL) /*!< Serial Wire Output, Manchester encoded format, is not supported. */ 14046 #define TPIU_DEVID_SWOMAN_Supported (0x1UL) /*!< Serial Wire Output, Manchester encoded format, is supported. */ 14047 14048 /* Bit 9 : Indicates whether trace clock plus data is supported. */ 14049 #define TPIU_DEVID_TCLKDATA_Pos (9UL) /*!< Position of TCLKDATA field. */ 14050 #define TPIU_DEVID_TCLKDATA_Msk (0x1UL << TPIU_DEVID_TCLKDATA_Pos) /*!< Bit mask of TCLKDATA field. */ 14051 #define TPIU_DEVID_TCLKDATA_Supported (0x0UL) /*!< Trace clock and data is supported. */ 14052 #define TPIU_DEVID_TCLKDATA_NotSupported (0x1UL) /*!< Trace clock and data is not supported. */ 14053 14054 /* Bits 8..6 : FIFO size in powers of 2. */ 14055 #define TPIU_DEVID_FIFOSIZE_Pos (6UL) /*!< Position of FIFOSIZE field. */ 14056 #define TPIU_DEVID_FIFOSIZE_Msk (0x7UL << TPIU_DEVID_FIFOSIZE_Pos) /*!< Bit mask of FIFOSIZE field. */ 14057 #define TPIU_DEVID_FIFOSIZE_Entries4 (0x2UL) /*!< FIFO size of 4 entries, that is, 16 bytes. */ 14058 14059 /* Bit 5 : Indicates the relationship between atclk and traceclkin. */ 14060 #define TPIU_DEVID_CLKRELAT_Pos (5UL) /*!< Position of CLKRELAT field. */ 14061 #define TPIU_DEVID_CLKRELAT_Msk (0x1UL << TPIU_DEVID_CLKRELAT_Pos) /*!< Bit mask of CLKRELAT field. */ 14062 #define TPIU_DEVID_CLKRELAT_Synchronous (0x0UL) /*!< atclk and traceclkin are synchronous. */ 14063 #define TPIU_DEVID_CLKRELAT_ASynchronous (0x1UL) /*!< atclk and traceclkin are asynchronous. */ 14064 14065 /* Bits 4..0 : Indicates the hidden level of input multiplexing. When non-zero, this value indicates the type of multiplexing on the input to the ATB. 14066 Currently only 0x00 is supported, that is, no multiplexing is present. This value helps detect the ATB structure. */ 14067 #define TPIU_DEVID_MUXNUM_Pos (0UL) /*!< Position of MUXNUM field. */ 14068 #define TPIU_DEVID_MUXNUM_Msk (0x1FUL << TPIU_DEVID_MUXNUM_Pos) /*!< Bit mask of MUXNUM field. */ 14069 14070 /* Register: TPIU_DEVTYPE */ 14071 /* Description: The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. */ 14072 14073 /* Bits 7..4 : The sub-type of the component */ 14074 #define TPIU_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ 14075 #define TPIU_DEVTYPE_SUB_Msk (0xFUL << TPIU_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ 14076 #define TPIU_DEVTYPE_SUB_TracePort (0x1UL) /*!< Indicates that this component is a trace port component. */ 14077 14078 /* Bits 3..0 : The main type of the component */ 14079 #define TPIU_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ 14080 #define TPIU_DEVTYPE_MAJOR_Msk (0xFUL << TPIU_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ 14081 #define TPIU_DEVTYPE_MAJOR_TraceSource (0x1UL) /*!< Peripheral is a trace sink. */ 14082 14083 14084 /* Peripheral: TWIM */ 14085 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ 14086 14087 /* Register: TWIM_TASKS_STARTRX */ 14088 /* Description: Start TWI receive sequence */ 14089 14090 /* Bit 0 : Start TWI receive sequence */ 14091 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ 14092 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ 14093 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */ 14094 14095 /* Register: TWIM_TASKS_STARTTX */ 14096 /* Description: Start TWI transmit sequence */ 14097 14098 /* Bit 0 : Start TWI transmit sequence */ 14099 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ 14100 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ 14101 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */ 14102 14103 /* Register: TWIM_TASKS_STOP */ 14104 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ 14105 14106 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ 14107 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 14108 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 14109 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ 14110 14111 /* Register: TWIM_TASKS_SUSPEND */ 14112 /* Description: Suspend TWI transaction */ 14113 14114 /* Bit 0 : Suspend TWI transaction */ 14115 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 14116 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 14117 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ 14118 14119 /* Register: TWIM_TASKS_RESUME */ 14120 /* Description: Resume TWI transaction */ 14121 14122 /* Bit 0 : Resume TWI transaction */ 14123 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 14124 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 14125 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ 14126 14127 /* Register: TWIM_SUBSCRIBE_STARTRX */ 14128 /* Description: Subscribe configuration for task STARTRX */ 14129 14130 /* Bit 31 : */ 14131 #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */ 14132 #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */ 14133 #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0x0UL) /*!< Disable subscription */ 14134 #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (0x1UL) /*!< Enable subscription */ 14135 14136 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ 14137 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14138 #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14139 14140 /* Register: TWIM_SUBSCRIBE_STARTTX */ 14141 /* Description: Subscribe configuration for task STARTTX */ 14142 14143 /* Bit 31 : */ 14144 #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */ 14145 #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */ 14146 #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription */ 14147 #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription */ 14148 14149 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ 14150 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14151 #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14152 14153 /* Register: TWIM_SUBSCRIBE_STOP */ 14154 /* Description: Subscribe configuration for task STOP */ 14155 14156 /* Bit 31 : */ 14157 #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 14158 #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 14159 #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 14160 #define TWIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 14161 14162 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 14163 #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14164 #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14165 14166 /* Register: TWIM_SUBSCRIBE_SUSPEND */ 14167 /* Description: Subscribe configuration for task SUSPEND */ 14168 14169 /* Bit 31 : */ 14170 #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ 14171 #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ 14172 #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ 14173 #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ 14174 14175 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ 14176 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14177 #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14178 14179 /* Register: TWIM_SUBSCRIBE_RESUME */ 14180 /* Description: Subscribe configuration for task RESUME */ 14181 14182 /* Bit 31 : */ 14183 #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ 14184 #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ 14185 #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ 14186 #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ 14187 14188 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ 14189 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14190 #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14191 14192 /* Register: TWIM_EVENTS_STOPPED */ 14193 /* Description: TWI stopped */ 14194 14195 /* Bit 0 : TWI stopped */ 14196 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 14197 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 14198 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ 14199 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ 14200 14201 /* Register: TWIM_EVENTS_ERROR */ 14202 /* Description: TWI error */ 14203 14204 /* Bit 0 : TWI error */ 14205 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 14206 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 14207 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ 14208 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ 14209 14210 /* Register: TWIM_EVENTS_SUSPENDED */ 14211 /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ 14212 14213 /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ 14214 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ 14215 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ 14216 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0x0UL) /*!< Event not generated */ 14217 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (0x1UL) /*!< Event generated */ 14218 14219 /* Register: TWIM_EVENTS_RXSTARTED */ 14220 /* Description: Receive sequence started */ 14221 14222 /* Bit 0 : Receive sequence started */ 14223 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 14224 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 14225 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ 14226 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */ 14227 14228 /* Register: TWIM_EVENTS_TXSTARTED */ 14229 /* Description: Transmit sequence started */ 14230 14231 /* Bit 0 : Transmit sequence started */ 14232 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 14233 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 14234 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ 14235 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */ 14236 14237 /* Register: TWIM_EVENTS_LASTRX */ 14238 /* Description: Byte boundary, starting to receive the last byte */ 14239 14240 /* Bit 0 : Byte boundary, starting to receive the last byte */ 14241 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ 14242 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ 14243 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0x0UL) /*!< Event not generated */ 14244 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (0x1UL) /*!< Event generated */ 14245 14246 /* Register: TWIM_EVENTS_LASTTX */ 14247 /* Description: Byte boundary, starting to transmit the last byte */ 14248 14249 /* Bit 0 : Byte boundary, starting to transmit the last byte */ 14250 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ 14251 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ 14252 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0x0UL) /*!< Event not generated */ 14253 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (0x1UL) /*!< Event generated */ 14254 14255 /* Register: TWIM_PUBLISH_STOPPED */ 14256 /* Description: Publish configuration for event STOPPED */ 14257 14258 /* Bit 31 : */ 14259 #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 14260 #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 14261 #define TWIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ 14262 #define TWIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ 14263 14264 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 14265 #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14266 #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14267 14268 /* Register: TWIM_PUBLISH_ERROR */ 14269 /* Description: Publish configuration for event ERROR */ 14270 14271 /* Bit 31 : */ 14272 #define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ 14273 #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ 14274 #define TWIM_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ 14275 #define TWIM_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ 14276 14277 /* Bits 7..0 : DPPI channel that event ERROR will publish to */ 14278 #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14279 #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14280 14281 /* Register: TWIM_PUBLISH_SUSPENDED */ 14282 /* Description: Publish configuration for event SUSPENDED */ 14283 14284 /* Bit 31 : */ 14285 #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */ 14286 #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */ 14287 #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0x0UL) /*!< Disable publishing */ 14288 #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (0x1UL) /*!< Enable publishing */ 14289 14290 /* Bits 7..0 : DPPI channel that event SUSPENDED will publish to */ 14291 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14292 #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14293 14294 /* Register: TWIM_PUBLISH_RXSTARTED */ 14295 /* Description: Publish configuration for event RXSTARTED */ 14296 14297 /* Bit 31 : */ 14298 #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 14299 #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 14300 #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 14301 #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 14302 14303 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ 14304 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14305 #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14306 14307 /* Register: TWIM_PUBLISH_TXSTARTED */ 14308 /* Description: Publish configuration for event TXSTARTED */ 14309 14310 /* Bit 31 : */ 14311 #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 14312 #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 14313 #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 14314 #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 14315 14316 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ 14317 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14318 #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14319 14320 /* Register: TWIM_PUBLISH_LASTRX */ 14321 /* Description: Publish configuration for event LASTRX */ 14322 14323 /* Bit 31 : */ 14324 #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */ 14325 #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */ 14326 #define TWIM_PUBLISH_LASTRX_EN_Disabled (0x0UL) /*!< Disable publishing */ 14327 #define TWIM_PUBLISH_LASTRX_EN_Enabled (0x1UL) /*!< Enable publishing */ 14328 14329 /* Bits 7..0 : DPPI channel that event LASTRX will publish to */ 14330 #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14331 #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14332 14333 /* Register: TWIM_PUBLISH_LASTTX */ 14334 /* Description: Publish configuration for event LASTTX */ 14335 14336 /* Bit 31 : */ 14337 #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */ 14338 #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */ 14339 #define TWIM_PUBLISH_LASTTX_EN_Disabled (0x0UL) /*!< Disable publishing */ 14340 #define TWIM_PUBLISH_LASTTX_EN_Enabled (0x1UL) /*!< Enable publishing */ 14341 14342 /* Bits 7..0 : DPPI channel that event LASTTX will publish to */ 14343 #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14344 #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14345 14346 /* Register: TWIM_SHORTS */ 14347 /* Description: Shortcuts between local events and tasks */ 14348 14349 /* Bit 12 : Shortcut between event LASTRX and task STOP */ 14350 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ 14351 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ 14352 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 14353 #define TWIM_SHORTS_LASTRX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 14354 14355 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */ 14356 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ 14357 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ 14358 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0x0UL) /*!< Disable shortcut */ 14359 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (0x1UL) /*!< Enable shortcut */ 14360 14361 /* Bit 9 : Shortcut between event LASTTX and task STOP */ 14362 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ 14363 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ 14364 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ 14365 #define TWIM_SHORTS_LASTTX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ 14366 14367 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ 14368 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ 14369 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ 14370 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ 14371 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ 14372 14373 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */ 14374 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ 14375 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ 14376 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */ 14377 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */ 14378 14379 /* Register: TWIM_INTEN */ 14380 /* Description: Enable or disable interrupt */ 14381 14382 /* Bit 24 : Enable or disable interrupt for event LASTTX */ 14383 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 14384 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 14385 #define TWIM_INTEN_LASTTX_Disabled (0x0UL) /*!< Disable */ 14386 #define TWIM_INTEN_LASTTX_Enabled (0x1UL) /*!< Enable */ 14387 14388 /* Bit 23 : Enable or disable interrupt for event LASTRX */ 14389 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 14390 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 14391 #define TWIM_INTEN_LASTRX_Disabled (0x0UL) /*!< Disable */ 14392 #define TWIM_INTEN_LASTRX_Enabled (0x1UL) /*!< Enable */ 14393 14394 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ 14395 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 14396 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 14397 #define TWIM_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */ 14398 #define TWIM_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */ 14399 14400 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ 14401 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 14402 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 14403 #define TWIM_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */ 14404 #define TWIM_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */ 14405 14406 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */ 14407 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 14408 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 14409 #define TWIM_INTEN_SUSPENDED_Disabled (0x0UL) /*!< Disable */ 14410 #define TWIM_INTEN_SUSPENDED_Enabled (0x1UL) /*!< Enable */ 14411 14412 /* Bit 9 : Enable or disable interrupt for event ERROR */ 14413 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 14414 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 14415 #define TWIM_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ 14416 #define TWIM_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ 14417 14418 /* Bit 1 : Enable or disable interrupt for event STOPPED */ 14419 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 14420 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 14421 #define TWIM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ 14422 #define TWIM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ 14423 14424 /* Register: TWIM_INTENSET */ 14425 /* Description: Enable interrupt */ 14426 14427 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */ 14428 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 14429 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 14430 #define TWIM_INTENSET_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */ 14431 #define TWIM_INTENSET_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */ 14432 #define TWIM_INTENSET_LASTTX_Set (0x1UL) /*!< Enable */ 14433 14434 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */ 14435 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 14436 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 14437 #define TWIM_INTENSET_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */ 14438 #define TWIM_INTENSET_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */ 14439 #define TWIM_INTENSET_LASTRX_Set (0x1UL) /*!< Enable */ 14440 14441 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ 14442 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 14443 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 14444 #define TWIM_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 14445 #define TWIM_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 14446 #define TWIM_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */ 14447 14448 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ 14449 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 14450 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 14451 #define TWIM_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 14452 #define TWIM_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 14453 #define TWIM_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */ 14454 14455 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ 14456 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 14457 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 14458 #define TWIM_INTENSET_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */ 14459 #define TWIM_INTENSET_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */ 14460 #define TWIM_INTENSET_SUSPENDED_Set (0x1UL) /*!< Enable */ 14461 14462 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 14463 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 14464 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 14465 #define TWIM_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ 14466 #define TWIM_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ 14467 #define TWIM_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ 14468 14469 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 14470 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 14471 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 14472 #define TWIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 14473 #define TWIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 14474 #define TWIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ 14475 14476 /* Register: TWIM_INTENCLR */ 14477 /* Description: Disable interrupt */ 14478 14479 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */ 14480 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 14481 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 14482 #define TWIM_INTENCLR_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */ 14483 #define TWIM_INTENCLR_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */ 14484 #define TWIM_INTENCLR_LASTTX_Clear (0x1UL) /*!< Disable */ 14485 14486 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */ 14487 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 14488 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 14489 #define TWIM_INTENCLR_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */ 14490 #define TWIM_INTENCLR_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */ 14491 #define TWIM_INTENCLR_LASTRX_Clear (0x1UL) /*!< Disable */ 14492 14493 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ 14494 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 14495 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 14496 #define TWIM_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 14497 #define TWIM_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 14498 #define TWIM_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */ 14499 14500 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ 14501 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 14502 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 14503 #define TWIM_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 14504 #define TWIM_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 14505 #define TWIM_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */ 14506 14507 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ 14508 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 14509 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 14510 #define TWIM_INTENCLR_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */ 14511 #define TWIM_INTENCLR_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */ 14512 #define TWIM_INTENCLR_SUSPENDED_Clear (0x1UL) /*!< Disable */ 14513 14514 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 14515 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 14516 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 14517 #define TWIM_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ 14518 #define TWIM_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ 14519 #define TWIM_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ 14520 14521 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 14522 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 14523 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 14524 #define TWIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 14525 #define TWIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 14526 #define TWIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ 14527 14528 /* Register: TWIM_ERRORSRC */ 14529 /* Description: Error source */ 14530 14531 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ 14532 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 14533 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 14534 #define TWIM_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */ 14535 #define TWIM_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */ 14536 14537 /* Bit 1 : NACK received after sending the address (write '1' to clear) */ 14538 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ 14539 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ 14540 #define TWIM_ERRORSRC_ANACK_NotReceived (0x0UL) /*!< Error did not occur */ 14541 #define TWIM_ERRORSRC_ANACK_Received (0x1UL) /*!< Error occurred */ 14542 14543 /* Bit 0 : Overrun error */ 14544 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 14545 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 14546 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0x0UL) /*!< Error did not occur */ 14547 #define TWIM_ERRORSRC_OVERRUN_Received (0x1UL) /*!< Error occurred */ 14548 14549 /* Register: TWIM_ENABLE */ 14550 /* Description: Enable TWIM */ 14551 14552 /* Bits 3..0 : Enable or disable TWIM */ 14553 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 14554 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 14555 #define TWIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIM */ 14556 #define TWIM_ENABLE_ENABLE_Enabled (0x6UL) /*!< Enable TWIM */ 14557 14558 /* Register: TWIM_PSEL_SCL */ 14559 /* Description: Pin select for SCL signal */ 14560 14561 /* Bit 31 : Connection */ 14562 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 14563 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 14564 #define TWIM_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */ 14565 #define TWIM_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 14566 14567 /* Bits 4..0 : Pin number */ 14568 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 14569 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 14570 14571 /* Register: TWIM_PSEL_SDA */ 14572 /* Description: Pin select for SDA signal */ 14573 14574 /* Bit 31 : Connection */ 14575 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 14576 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 14577 #define TWIM_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */ 14578 #define TWIM_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 14579 14580 /* Bits 4..0 : Pin number */ 14581 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 14582 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 14583 14584 /* Register: TWIM_FREQUENCY */ 14585 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ 14586 14587 /* Bits 31..0 : TWI master clock frequency */ 14588 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 14589 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 14590 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ 14591 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 14592 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ 14593 14594 /* Register: TWIM_RXD_PTR */ 14595 /* Description: Data pointer */ 14596 14597 /* Bits 31..0 : Data pointer */ 14598 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 14599 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 14600 14601 /* Register: TWIM_RXD_MAXCNT */ 14602 /* Description: Maximum number of bytes in receive buffer */ 14603 14604 /* Bits 12..0 : Maximum number of bytes in receive buffer */ 14605 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 14606 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 14607 14608 /* Register: TWIM_RXD_AMOUNT */ 14609 /* Description: Number of bytes transferred in the last transaction */ 14610 14611 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ 14612 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 14613 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 14614 14615 /* Register: TWIM_RXD_LIST */ 14616 /* Description: EasyDMA list type */ 14617 14618 /* Bits 1..0 : List type */ 14619 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 14620 #define TWIM_RXD_LIST_LIST_Msk (0x3UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 14621 #define TWIM_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ 14622 #define TWIM_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ 14623 14624 /* Register: TWIM_TXD_PTR */ 14625 /* Description: Data pointer */ 14626 14627 /* Bits 31..0 : Data pointer */ 14628 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 14629 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 14630 14631 /* Register: TWIM_TXD_MAXCNT */ 14632 /* Description: Maximum number of bytes in transmit buffer */ 14633 14634 /* Bits 12..0 : Maximum number of bytes in transmit buffer */ 14635 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 14636 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 14637 14638 /* Register: TWIM_TXD_AMOUNT */ 14639 /* Description: Number of bytes transferred in the last transaction */ 14640 14641 /* Bits 12..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ 14642 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 14643 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 14644 14645 /* Register: TWIM_TXD_LIST */ 14646 /* Description: EasyDMA list type */ 14647 14648 /* Bits 1..0 : List type */ 14649 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 14650 #define TWIM_TXD_LIST_LIST_Msk (0x3UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 14651 #define TWIM_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ 14652 #define TWIM_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ 14653 14654 /* Register: TWIM_ADDRESS */ 14655 /* Description: Address used in the TWI transfer */ 14656 14657 /* Bits 6..0 : Address used in the TWI transfer */ 14658 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 14659 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 14660 14661 14662 /* Peripheral: TWIS */ 14663 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ 14664 14665 /* Register: TWIS_TASKS_STOP */ 14666 /* Description: Stop TWI transaction */ 14667 14668 /* Bit 0 : Stop TWI transaction */ 14669 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 14670 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 14671 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ 14672 14673 /* Register: TWIS_TASKS_SUSPEND */ 14674 /* Description: Suspend TWI transaction */ 14675 14676 /* Bit 0 : Suspend TWI transaction */ 14677 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ 14678 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ 14679 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ 14680 14681 /* Register: TWIS_TASKS_RESUME */ 14682 /* Description: Resume TWI transaction */ 14683 14684 /* Bit 0 : Resume TWI transaction */ 14685 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ 14686 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ 14687 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ 14688 14689 /* Register: TWIS_TASKS_PREPARERX */ 14690 /* Description: Prepare the TWI slave to respond to a write command */ 14691 14692 /* Bit 0 : Prepare the TWI slave to respond to a write command */ 14693 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ 14694 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ 14695 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (0x1UL) /*!< Trigger task */ 14696 14697 /* Register: TWIS_TASKS_PREPARETX */ 14698 /* Description: Prepare the TWI slave to respond to a read command */ 14699 14700 /* Bit 0 : Prepare the TWI slave to respond to a read command */ 14701 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ 14702 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ 14703 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (0x1UL) /*!< Trigger task */ 14704 14705 /* Register: TWIS_SUBSCRIBE_STOP */ 14706 /* Description: Subscribe configuration for task STOP */ 14707 14708 /* Bit 31 : */ 14709 #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 14710 #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 14711 #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ 14712 #define TWIS_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ 14713 14714 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 14715 #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14716 #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14717 14718 /* Register: TWIS_SUBSCRIBE_SUSPEND */ 14719 /* Description: Subscribe configuration for task SUSPEND */ 14720 14721 /* Bit 31 : */ 14722 #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ 14723 #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ 14724 #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ 14725 #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ 14726 14727 /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ 14728 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14729 #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14730 14731 /* Register: TWIS_SUBSCRIBE_RESUME */ 14732 /* Description: Subscribe configuration for task RESUME */ 14733 14734 /* Bit 31 : */ 14735 #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ 14736 #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ 14737 #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ 14738 #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ 14739 14740 /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ 14741 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14742 #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14743 14744 /* Register: TWIS_SUBSCRIBE_PREPARERX */ 14745 /* Description: Subscribe configuration for task PREPARERX */ 14746 14747 /* Bit 31 : */ 14748 #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */ 14749 #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */ 14750 #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0x0UL) /*!< Disable subscription */ 14751 #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (0x1UL) /*!< Enable subscription */ 14752 14753 /* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */ 14754 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14755 #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14756 14757 /* Register: TWIS_SUBSCRIBE_PREPARETX */ 14758 /* Description: Subscribe configuration for task PREPARETX */ 14759 14760 /* Bit 31 : */ 14761 #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */ 14762 #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */ 14763 #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0x0UL) /*!< Disable subscription */ 14764 #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (0x1UL) /*!< Enable subscription */ 14765 14766 /* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */ 14767 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14768 #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14769 14770 /* Register: TWIS_EVENTS_STOPPED */ 14771 /* Description: TWI stopped */ 14772 14773 /* Bit 0 : TWI stopped */ 14774 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ 14775 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ 14776 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ 14777 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ 14778 14779 /* Register: TWIS_EVENTS_ERROR */ 14780 /* Description: TWI error */ 14781 14782 /* Bit 0 : TWI error */ 14783 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 14784 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 14785 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ 14786 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ 14787 14788 /* Register: TWIS_EVENTS_RXSTARTED */ 14789 /* Description: Receive sequence started */ 14790 14791 /* Bit 0 : Receive sequence started */ 14792 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 14793 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 14794 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ 14795 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */ 14796 14797 /* Register: TWIS_EVENTS_TXSTARTED */ 14798 /* Description: Transmit sequence started */ 14799 14800 /* Bit 0 : Transmit sequence started */ 14801 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 14802 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 14803 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ 14804 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */ 14805 14806 /* Register: TWIS_EVENTS_WRITE */ 14807 /* Description: Write command received */ 14808 14809 /* Bit 0 : Write command received */ 14810 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ 14811 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ 14812 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0x0UL) /*!< Event not generated */ 14813 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (0x1UL) /*!< Event generated */ 14814 14815 /* Register: TWIS_EVENTS_READ */ 14816 /* Description: Read command received */ 14817 14818 /* Bit 0 : Read command received */ 14819 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ 14820 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ 14821 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0x0UL) /*!< Event not generated */ 14822 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (0x1UL) /*!< Event generated */ 14823 14824 /* Register: TWIS_PUBLISH_STOPPED */ 14825 /* Description: Publish configuration for event STOPPED */ 14826 14827 /* Bit 31 : */ 14828 #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 14829 #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ 14830 #define TWIS_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ 14831 #define TWIS_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ 14832 14833 /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ 14834 #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14835 #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14836 14837 /* Register: TWIS_PUBLISH_ERROR */ 14838 /* Description: Publish configuration for event ERROR */ 14839 14840 /* Bit 31 : */ 14841 #define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ 14842 #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ 14843 #define TWIS_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ 14844 #define TWIS_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ 14845 14846 /* Bits 7..0 : DPPI channel that event ERROR will publish to */ 14847 #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14848 #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14849 14850 /* Register: TWIS_PUBLISH_RXSTARTED */ 14851 /* Description: Publish configuration for event RXSTARTED */ 14852 14853 /* Bit 31 : */ 14854 #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 14855 #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 14856 #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 14857 #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 14858 14859 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ 14860 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14861 #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14862 14863 /* Register: TWIS_PUBLISH_TXSTARTED */ 14864 /* Description: Publish configuration for event TXSTARTED */ 14865 14866 /* Bit 31 : */ 14867 #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 14868 #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 14869 #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 14870 #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 14871 14872 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ 14873 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14874 #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14875 14876 /* Register: TWIS_PUBLISH_WRITE */ 14877 /* Description: Publish configuration for event WRITE */ 14878 14879 /* Bit 31 : */ 14880 #define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */ 14881 #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */ 14882 #define TWIS_PUBLISH_WRITE_EN_Disabled (0x0UL) /*!< Disable publishing */ 14883 #define TWIS_PUBLISH_WRITE_EN_Enabled (0x1UL) /*!< Enable publishing */ 14884 14885 /* Bits 7..0 : DPPI channel that event WRITE will publish to */ 14886 #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14887 #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14888 14889 /* Register: TWIS_PUBLISH_READ */ 14890 /* Description: Publish configuration for event READ */ 14891 14892 /* Bit 31 : */ 14893 #define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */ 14894 #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */ 14895 #define TWIS_PUBLISH_READ_EN_Disabled (0x0UL) /*!< Disable publishing */ 14896 #define TWIS_PUBLISH_READ_EN_Enabled (0x1UL) /*!< Enable publishing */ 14897 14898 /* Bits 7..0 : DPPI channel that event READ will publish to */ 14899 #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 14900 #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 14901 14902 /* Register: TWIS_SHORTS */ 14903 /* Description: Shortcuts between local events and tasks */ 14904 14905 /* Bit 14 : Shortcut between event READ and task SUSPEND */ 14906 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ 14907 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ 14908 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ 14909 #define TWIS_SHORTS_READ_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ 14910 14911 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */ 14912 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ 14913 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ 14914 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ 14915 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ 14916 14917 /* Register: TWIS_INTEN */ 14918 /* Description: Enable or disable interrupt */ 14919 14920 /* Bit 26 : Enable or disable interrupt for event READ */ 14921 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ 14922 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ 14923 #define TWIS_INTEN_READ_Disabled (0x0UL) /*!< Disable */ 14924 #define TWIS_INTEN_READ_Enabled (0x1UL) /*!< Enable */ 14925 14926 /* Bit 25 : Enable or disable interrupt for event WRITE */ 14927 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 14928 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ 14929 #define TWIS_INTEN_WRITE_Disabled (0x0UL) /*!< Disable */ 14930 #define TWIS_INTEN_WRITE_Enabled (0x1UL) /*!< Enable */ 14931 14932 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ 14933 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 14934 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 14935 #define TWIS_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */ 14936 #define TWIS_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */ 14937 14938 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ 14939 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 14940 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 14941 #define TWIS_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */ 14942 #define TWIS_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */ 14943 14944 /* Bit 9 : Enable or disable interrupt for event ERROR */ 14945 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 14946 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 14947 #define TWIS_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ 14948 #define TWIS_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ 14949 14950 /* Bit 1 : Enable or disable interrupt for event STOPPED */ 14951 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 14952 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 14953 #define TWIS_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ 14954 #define TWIS_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ 14955 14956 /* Register: TWIS_INTENSET */ 14957 /* Description: Enable interrupt */ 14958 14959 /* Bit 26 : Write '1' to enable interrupt for event READ */ 14960 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ 14961 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ 14962 #define TWIS_INTENSET_READ_Disabled (0x0UL) /*!< Read: Disabled */ 14963 #define TWIS_INTENSET_READ_Enabled (0x1UL) /*!< Read: Enabled */ 14964 #define TWIS_INTENSET_READ_Set (0x1UL) /*!< Enable */ 14965 14966 /* Bit 25 : Write '1' to enable interrupt for event WRITE */ 14967 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 14968 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ 14969 #define TWIS_INTENSET_WRITE_Disabled (0x0UL) /*!< Read: Disabled */ 14970 #define TWIS_INTENSET_WRITE_Enabled (0x1UL) /*!< Read: Enabled */ 14971 #define TWIS_INTENSET_WRITE_Set (0x1UL) /*!< Enable */ 14972 14973 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ 14974 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 14975 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 14976 #define TWIS_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 14977 #define TWIS_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 14978 #define TWIS_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */ 14979 14980 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ 14981 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 14982 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 14983 #define TWIS_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 14984 #define TWIS_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 14985 #define TWIS_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */ 14986 14987 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 14988 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 14989 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 14990 #define TWIS_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ 14991 #define TWIS_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ 14992 #define TWIS_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ 14993 14994 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ 14995 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 14996 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 14997 #define TWIS_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 14998 #define TWIS_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 14999 #define TWIS_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ 15000 15001 /* Register: TWIS_INTENCLR */ 15002 /* Description: Disable interrupt */ 15003 15004 /* Bit 26 : Write '1' to disable interrupt for event READ */ 15005 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ 15006 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ 15007 #define TWIS_INTENCLR_READ_Disabled (0x0UL) /*!< Read: Disabled */ 15008 #define TWIS_INTENCLR_READ_Enabled (0x1UL) /*!< Read: Enabled */ 15009 #define TWIS_INTENCLR_READ_Clear (0x1UL) /*!< Disable */ 15010 15011 /* Bit 25 : Write '1' to disable interrupt for event WRITE */ 15012 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 15013 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ 15014 #define TWIS_INTENCLR_WRITE_Disabled (0x0UL) /*!< Read: Disabled */ 15015 #define TWIS_INTENCLR_WRITE_Enabled (0x1UL) /*!< Read: Enabled */ 15016 #define TWIS_INTENCLR_WRITE_Clear (0x1UL) /*!< Disable */ 15017 15018 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ 15019 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 15020 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 15021 #define TWIS_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 15022 #define TWIS_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 15023 #define TWIS_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */ 15024 15025 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ 15026 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 15027 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 15028 #define TWIS_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 15029 #define TWIS_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 15030 #define TWIS_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */ 15031 15032 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 15033 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 15034 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 15035 #define TWIS_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ 15036 #define TWIS_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ 15037 #define TWIS_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ 15038 15039 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ 15040 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 15041 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 15042 #define TWIS_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 15043 #define TWIS_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 15044 #define TWIS_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ 15045 15046 /* Register: TWIS_ERRORSRC */ 15047 /* Description: Error source */ 15048 15049 /* Bit 3 : TX buffer over-read detected, and prevented */ 15050 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ 15051 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 15052 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0x0UL) /*!< Error did not occur */ 15053 #define TWIS_ERRORSRC_OVERREAD_Detected (0x1UL) /*!< Error occurred */ 15054 15055 /* Bit 2 : NACK sent after receiving a data byte */ 15056 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 15057 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 15058 #define TWIS_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */ 15059 #define TWIS_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */ 15060 15061 /* Bit 0 : RX buffer overflow detected, and prevented */ 15062 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ 15063 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 15064 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0x0UL) /*!< Error did not occur */ 15065 #define TWIS_ERRORSRC_OVERFLOW_Detected (0x1UL) /*!< Error occurred */ 15066 15067 /* Register: TWIS_MATCH */ 15068 /* Description: Status register indicating which address had a match */ 15069 15070 /* Bit 0 : Indication of which address in ADDRESS that matched the incoming address */ 15071 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ 15072 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ 15073 15074 /* Register: TWIS_ENABLE */ 15075 /* Description: Enable TWIS */ 15076 15077 /* Bits 3..0 : Enable or disable TWIS */ 15078 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 15079 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 15080 #define TWIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIS */ 15081 #define TWIS_ENABLE_ENABLE_Enabled (0x9UL) /*!< Enable TWIS */ 15082 15083 /* Register: TWIS_PSEL_SCL */ 15084 /* Description: Pin select for SCL signal */ 15085 15086 /* Bit 31 : Connection */ 15087 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 15088 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 15089 #define TWIS_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */ 15090 #define TWIS_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 15091 15092 /* Bits 4..0 : Pin number */ 15093 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 15094 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 15095 15096 /* Register: TWIS_PSEL_SDA */ 15097 /* Description: Pin select for SDA signal */ 15098 15099 /* Bit 31 : Connection */ 15100 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 15101 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 15102 #define TWIS_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */ 15103 #define TWIS_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 15104 15105 /* Bits 4..0 : Pin number */ 15106 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 15107 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 15108 15109 /* Register: TWIS_RXD_PTR */ 15110 /* Description: RXD Data pointer */ 15111 15112 /* Bits 31..0 : RXD Data pointer */ 15113 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 15114 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 15115 15116 /* Register: TWIS_RXD_MAXCNT */ 15117 /* Description: Maximum number of bytes in RXD buffer */ 15118 15119 /* Bits 12..0 : Maximum number of bytes in RXD buffer */ 15120 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 15121 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 15122 15123 /* Register: TWIS_RXD_AMOUNT */ 15124 /* Description: Number of bytes transferred in the last RXD transaction */ 15125 15126 /* Bits 12..0 : Number of bytes transferred in the last RXD transaction */ 15127 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 15128 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 15129 15130 /* Register: TWIS_RXD_LIST */ 15131 /* Description: EasyDMA list type */ 15132 15133 /* Bits 1..0 : List type */ 15134 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 15135 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 15136 #define TWIS_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ 15137 #define TWIS_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ 15138 15139 /* Register: TWIS_TXD_PTR */ 15140 /* Description: TXD Data pointer */ 15141 15142 /* Bits 31..0 : TXD Data pointer */ 15143 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 15144 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 15145 15146 /* Register: TWIS_TXD_MAXCNT */ 15147 /* Description: Maximum number of bytes in TXD buffer */ 15148 15149 /* Bits 12..0 : Maximum number of bytes in TXD buffer */ 15150 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 15151 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 15152 15153 /* Register: TWIS_TXD_AMOUNT */ 15154 /* Description: Number of bytes transferred in the last TXD transaction */ 15155 15156 /* Bits 12..0 : Number of bytes transferred in the last TXD transaction */ 15157 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 15158 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 15159 15160 /* Register: TWIS_TXD_LIST */ 15161 /* Description: EasyDMA list type */ 15162 15163 /* Bits 1..0 : List type */ 15164 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 15165 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 15166 #define TWIS_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ 15167 #define TWIS_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ 15168 15169 /* Register: TWIS_ADDRESS */ 15170 /* Description: Description collection: TWI slave address n */ 15171 15172 /* Bits 6..0 : TWI slave address */ 15173 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 15174 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 15175 15176 /* Register: TWIS_CONFIG */ 15177 /* Description: Configuration register for the address match mechanism */ 15178 15179 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */ 15180 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ 15181 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ 15182 #define TWIS_CONFIG_ADDRESS1_Disabled (0x0UL) /*!< Disabled */ 15183 #define TWIS_CONFIG_ADDRESS1_Enabled (0x1UL) /*!< Enabled */ 15184 15185 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */ 15186 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ 15187 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ 15188 #define TWIS_CONFIG_ADDRESS0_Disabled (0x0UL) /*!< Disabled */ 15189 #define TWIS_CONFIG_ADDRESS0_Enabled (0x1UL) /*!< Enabled */ 15190 15191 /* Register: TWIS_ORC */ 15192 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ 15193 15194 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ 15195 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 15196 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 15197 15198 15199 /* Peripheral: UARTE */ 15200 /* Description: UART with EasyDMA 0 */ 15201 15202 /* Register: UARTE_TASKS_STARTRX */ 15203 /* Description: Start UART receiver */ 15204 15205 /* Bit 0 : Start UART receiver */ 15206 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ 15207 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ 15208 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */ 15209 15210 /* Register: UARTE_TASKS_STOPRX */ 15211 /* Description: Stop UART receiver */ 15212 15213 /* Bit 0 : Stop UART receiver */ 15214 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ 15215 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ 15216 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (0x1UL) /*!< Trigger task */ 15217 15218 /* Register: UARTE_TASKS_STARTTX */ 15219 /* Description: Start UART transmitter */ 15220 15221 /* Bit 0 : Start UART transmitter */ 15222 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ 15223 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ 15224 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */ 15225 15226 /* Register: UARTE_TASKS_STOPTX */ 15227 /* Description: Stop UART transmitter */ 15228 15229 /* Bit 0 : Stop UART transmitter */ 15230 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ 15231 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ 15232 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (0x1UL) /*!< Trigger task */ 15233 15234 /* Register: UARTE_TASKS_FLUSHRX */ 15235 /* Description: Flush RX FIFO into RX buffer */ 15236 15237 /* Bit 0 : Flush RX FIFO into RX buffer */ 15238 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ 15239 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ 15240 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (0x1UL) /*!< Trigger task */ 15241 15242 /* Register: UARTE_SUBSCRIBE_STARTRX */ 15243 /* Description: Subscribe configuration for task STARTRX */ 15244 15245 /* Bit 31 : */ 15246 #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */ 15247 #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */ 15248 #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0x0UL) /*!< Disable subscription */ 15249 #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (0x1UL) /*!< Enable subscription */ 15250 15251 /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ 15252 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15253 #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15254 15255 /* Register: UARTE_SUBSCRIBE_STOPRX */ 15256 /* Description: Subscribe configuration for task STOPRX */ 15257 15258 /* Bit 31 : */ 15259 #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */ 15260 #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */ 15261 #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0x0UL) /*!< Disable subscription */ 15262 #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (0x1UL) /*!< Enable subscription */ 15263 15264 /* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */ 15265 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15266 #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15267 15268 /* Register: UARTE_SUBSCRIBE_STARTTX */ 15269 /* Description: Subscribe configuration for task STARTTX */ 15270 15271 /* Bit 31 : */ 15272 #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */ 15273 #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */ 15274 #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription */ 15275 #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription */ 15276 15277 /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ 15278 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15279 #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15280 15281 /* Register: UARTE_SUBSCRIBE_STOPTX */ 15282 /* Description: Subscribe configuration for task STOPTX */ 15283 15284 /* Bit 31 : */ 15285 #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */ 15286 #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */ 15287 #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0x0UL) /*!< Disable subscription */ 15288 #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (0x1UL) /*!< Enable subscription */ 15289 15290 /* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */ 15291 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15292 #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15293 15294 /* Register: UARTE_SUBSCRIBE_FLUSHRX */ 15295 /* Description: Subscribe configuration for task FLUSHRX */ 15296 15297 /* Bit 31 : */ 15298 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */ 15299 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */ 15300 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0x0UL) /*!< Disable subscription */ 15301 #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (0x1UL) /*!< Enable subscription */ 15302 15303 /* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */ 15304 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15305 #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15306 15307 /* Register: UARTE_EVENTS_CTS */ 15308 /* Description: CTS is activated (set low). Clear To Send. */ 15309 15310 /* Bit 0 : CTS is activated (set low). Clear To Send. */ 15311 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ 15312 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ 15313 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0x0UL) /*!< Event not generated */ 15314 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (0x1UL) /*!< Event generated */ 15315 15316 /* Register: UARTE_EVENTS_NCTS */ 15317 /* Description: CTS is deactivated (set high). Not Clear To Send. */ 15318 15319 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ 15320 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ 15321 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ 15322 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0x0UL) /*!< Event not generated */ 15323 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (0x1UL) /*!< Event generated */ 15324 15325 /* Register: UARTE_EVENTS_RXDRDY */ 15326 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ 15327 15328 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ 15329 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ 15330 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ 15331 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0x0UL) /*!< Event not generated */ 15332 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (0x1UL) /*!< Event generated */ 15333 15334 /* Register: UARTE_EVENTS_ENDRX */ 15335 /* Description: Receive buffer is filled up */ 15336 15337 /* Bit 0 : Receive buffer is filled up */ 15338 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ 15339 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ 15340 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */ 15341 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */ 15342 15343 /* Register: UARTE_EVENTS_TXDRDY */ 15344 /* Description: Data sent from TXD */ 15345 15346 /* Bit 0 : Data sent from TXD */ 15347 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ 15348 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ 15349 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0x0UL) /*!< Event not generated */ 15350 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (0x1UL) /*!< Event generated */ 15351 15352 /* Register: UARTE_EVENTS_ENDTX */ 15353 /* Description: Last TX byte transmitted */ 15354 15355 /* Bit 0 : Last TX byte transmitted */ 15356 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ 15357 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ 15358 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */ 15359 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */ 15360 15361 /* Register: UARTE_EVENTS_ERROR */ 15362 /* Description: Error detected */ 15363 15364 /* Bit 0 : Error detected */ 15365 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 15366 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 15367 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ 15368 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ 15369 15370 /* Register: UARTE_EVENTS_RXTO */ 15371 /* Description: Receiver timeout */ 15372 15373 /* Bit 0 : Receiver timeout */ 15374 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ 15375 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ 15376 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0x0UL) /*!< Event not generated */ 15377 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (0x1UL) /*!< Event generated */ 15378 15379 /* Register: UARTE_EVENTS_RXSTARTED */ 15380 /* Description: UART receiver has started */ 15381 15382 /* Bit 0 : UART receiver has started */ 15383 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ 15384 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ 15385 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ 15386 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */ 15387 15388 /* Register: UARTE_EVENTS_TXSTARTED */ 15389 /* Description: UART transmitter has started */ 15390 15391 /* Bit 0 : UART transmitter has started */ 15392 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ 15393 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ 15394 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ 15395 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */ 15396 15397 /* Register: UARTE_EVENTS_TXSTOPPED */ 15398 /* Description: Transmitter stopped */ 15399 15400 /* Bit 0 : Transmitter stopped */ 15401 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ 15402 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ 15403 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */ 15404 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (0x1UL) /*!< Event generated */ 15405 15406 /* Register: UARTE_PUBLISH_CTS */ 15407 /* Description: Publish configuration for event CTS */ 15408 15409 /* Bit 31 : */ 15410 #define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */ 15411 #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */ 15412 #define UARTE_PUBLISH_CTS_EN_Disabled (0x0UL) /*!< Disable publishing */ 15413 #define UARTE_PUBLISH_CTS_EN_Enabled (0x1UL) /*!< Enable publishing */ 15414 15415 /* Bits 7..0 : DPPI channel that event CTS will publish to */ 15416 #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15417 #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15418 15419 /* Register: UARTE_PUBLISH_NCTS */ 15420 /* Description: Publish configuration for event NCTS */ 15421 15422 /* Bit 31 : */ 15423 #define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */ 15424 #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */ 15425 #define UARTE_PUBLISH_NCTS_EN_Disabled (0x0UL) /*!< Disable publishing */ 15426 #define UARTE_PUBLISH_NCTS_EN_Enabled (0x1UL) /*!< Enable publishing */ 15427 15428 /* Bits 7..0 : DPPI channel that event NCTS will publish to */ 15429 #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15430 #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15431 15432 /* Register: UARTE_PUBLISH_RXDRDY */ 15433 /* Description: Publish configuration for event RXDRDY */ 15434 15435 /* Bit 31 : */ 15436 #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ 15437 #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */ 15438 #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ 15439 #define UARTE_PUBLISH_RXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ 15440 15441 /* Bits 7..0 : DPPI channel that event RXDRDY will publish to */ 15442 #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15443 #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15444 15445 /* Register: UARTE_PUBLISH_ENDRX */ 15446 /* Description: Publish configuration for event ENDRX */ 15447 15448 /* Bit 31 : */ 15449 #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ 15450 #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ 15451 #define UARTE_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */ 15452 #define UARTE_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */ 15453 15454 /* Bits 7..0 : DPPI channel that event ENDRX will publish to */ 15455 #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15456 #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15457 15458 /* Register: UARTE_PUBLISH_TXDRDY */ 15459 /* Description: Publish configuration for event TXDRDY */ 15460 15461 /* Bit 31 : */ 15462 #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ 15463 #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */ 15464 #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ 15465 #define UARTE_PUBLISH_TXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ 15466 15467 /* Bits 7..0 : DPPI channel that event TXDRDY will publish to */ 15468 #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15469 #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15470 15471 /* Register: UARTE_PUBLISH_ENDTX */ 15472 /* Description: Publish configuration for event ENDTX */ 15473 15474 /* Bit 31 : */ 15475 #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */ 15476 #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */ 15477 #define UARTE_PUBLISH_ENDTX_EN_Disabled (0x0UL) /*!< Disable publishing */ 15478 #define UARTE_PUBLISH_ENDTX_EN_Enabled (0x1UL) /*!< Enable publishing */ 15479 15480 /* Bits 7..0 : DPPI channel that event ENDTX will publish to */ 15481 #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15482 #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15483 15484 /* Register: UARTE_PUBLISH_ERROR */ 15485 /* Description: Publish configuration for event ERROR */ 15486 15487 /* Bit 31 : */ 15488 #define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ 15489 #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ 15490 #define UARTE_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ 15491 #define UARTE_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ 15492 15493 /* Bits 7..0 : DPPI channel that event ERROR will publish to */ 15494 #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15495 #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15496 15497 /* Register: UARTE_PUBLISH_RXTO */ 15498 /* Description: Publish configuration for event RXTO */ 15499 15500 /* Bit 31 : */ 15501 #define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */ 15502 #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */ 15503 #define UARTE_PUBLISH_RXTO_EN_Disabled (0x0UL) /*!< Disable publishing */ 15504 #define UARTE_PUBLISH_RXTO_EN_Enabled (0x1UL) /*!< Enable publishing */ 15505 15506 /* Bits 7..0 : DPPI channel that event RXTO will publish to */ 15507 #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15508 #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15509 15510 /* Register: UARTE_PUBLISH_RXSTARTED */ 15511 /* Description: Publish configuration for event RXSTARTED */ 15512 15513 /* Bit 31 : */ 15514 #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 15515 #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 15516 #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 15517 #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 15518 15519 /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ 15520 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15521 #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15522 15523 /* Register: UARTE_PUBLISH_TXSTARTED */ 15524 /* Description: Publish configuration for event TXSTARTED */ 15525 15526 /* Bit 31 : */ 15527 #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 15528 #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 15529 #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ 15530 #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ 15531 15532 /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ 15533 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15534 #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15535 15536 /* Register: UARTE_PUBLISH_TXSTOPPED */ 15537 /* Description: Publish configuration for event TXSTOPPED */ 15538 15539 /* Bit 31 : */ 15540 #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 15541 #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */ 15542 #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ 15543 #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ 15544 15545 /* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to */ 15546 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 15547 #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 15548 15549 /* Register: UARTE_SHORTS */ 15550 /* Description: Shortcuts between local events and tasks */ 15551 15552 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */ 15553 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ 15554 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ 15555 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0x0UL) /*!< Disable shortcut */ 15556 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (0x1UL) /*!< Enable shortcut */ 15557 15558 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */ 15559 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ 15560 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ 15561 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */ 15562 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */ 15563 15564 /* Register: UARTE_INTEN */ 15565 /* Description: Enable or disable interrupt */ 15566 15567 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ 15568 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 15569 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 15570 #define UARTE_INTEN_TXSTOPPED_Disabled (0x0UL) /*!< Disable */ 15571 #define UARTE_INTEN_TXSTOPPED_Enabled (0x1UL) /*!< Enable */ 15572 15573 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ 15574 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 15575 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 15576 #define UARTE_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */ 15577 #define UARTE_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */ 15578 15579 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ 15580 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 15581 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 15582 #define UARTE_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */ 15583 #define UARTE_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */ 15584 15585 /* Bit 17 : Enable or disable interrupt for event RXTO */ 15586 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 15587 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ 15588 #define UARTE_INTEN_RXTO_Disabled (0x0UL) /*!< Disable */ 15589 #define UARTE_INTEN_RXTO_Enabled (0x1UL) /*!< Enable */ 15590 15591 /* Bit 9 : Enable or disable interrupt for event ERROR */ 15592 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 15593 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 15594 #define UARTE_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ 15595 #define UARTE_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ 15596 15597 /* Bit 8 : Enable or disable interrupt for event ENDTX */ 15598 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 15599 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 15600 #define UARTE_INTEN_ENDTX_Disabled (0x0UL) /*!< Disable */ 15601 #define UARTE_INTEN_ENDTX_Enabled (0x1UL) /*!< Enable */ 15602 15603 /* Bit 7 : Enable or disable interrupt for event TXDRDY */ 15604 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 15605 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 15606 #define UARTE_INTEN_TXDRDY_Disabled (0x0UL) /*!< Disable */ 15607 #define UARTE_INTEN_TXDRDY_Enabled (0x1UL) /*!< Enable */ 15608 15609 /* Bit 4 : Enable or disable interrupt for event ENDRX */ 15610 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 15611 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 15612 #define UARTE_INTEN_ENDRX_Disabled (0x0UL) /*!< Disable */ 15613 #define UARTE_INTEN_ENDRX_Enabled (0x1UL) /*!< Enable */ 15614 15615 /* Bit 2 : Enable or disable interrupt for event RXDRDY */ 15616 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 15617 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 15618 #define UARTE_INTEN_RXDRDY_Disabled (0x0UL) /*!< Disable */ 15619 #define UARTE_INTEN_RXDRDY_Enabled (0x1UL) /*!< Enable */ 15620 15621 /* Bit 1 : Enable or disable interrupt for event NCTS */ 15622 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 15623 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ 15624 #define UARTE_INTEN_NCTS_Disabled (0x0UL) /*!< Disable */ 15625 #define UARTE_INTEN_NCTS_Enabled (0x1UL) /*!< Enable */ 15626 15627 /* Bit 0 : Enable or disable interrupt for event CTS */ 15628 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ 15629 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ 15630 #define UARTE_INTEN_CTS_Disabled (0x0UL) /*!< Disable */ 15631 #define UARTE_INTEN_CTS_Enabled (0x1UL) /*!< Enable */ 15632 15633 /* Register: UARTE_INTENSET */ 15634 /* Description: Enable interrupt */ 15635 15636 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ 15637 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 15638 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 15639 #define UARTE_INTENSET_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 15640 #define UARTE_INTENSET_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 15641 #define UARTE_INTENSET_TXSTOPPED_Set (0x1UL) /*!< Enable */ 15642 15643 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ 15644 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 15645 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 15646 #define UARTE_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 15647 #define UARTE_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 15648 #define UARTE_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */ 15649 15650 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ 15651 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 15652 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 15653 #define UARTE_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 15654 #define UARTE_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 15655 #define UARTE_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */ 15656 15657 /* Bit 17 : Write '1' to enable interrupt for event RXTO */ 15658 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 15659 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 15660 #define UARTE_INTENSET_RXTO_Disabled (0x0UL) /*!< Read: Disabled */ 15661 #define UARTE_INTENSET_RXTO_Enabled (0x1UL) /*!< Read: Enabled */ 15662 #define UARTE_INTENSET_RXTO_Set (0x1UL) /*!< Enable */ 15663 15664 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 15665 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 15666 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 15667 #define UARTE_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ 15668 #define UARTE_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ 15669 #define UARTE_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ 15670 15671 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */ 15672 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 15673 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 15674 #define UARTE_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */ 15675 #define UARTE_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */ 15676 #define UARTE_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */ 15677 15678 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ 15679 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 15680 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 15681 #define UARTE_INTENSET_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ 15682 #define UARTE_INTENSET_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ 15683 #define UARTE_INTENSET_TXDRDY_Set (0x1UL) /*!< Enable */ 15684 15685 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ 15686 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 15687 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 15688 #define UARTE_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ 15689 #define UARTE_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ 15690 #define UARTE_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */ 15691 15692 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ 15693 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 15694 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 15695 #define UARTE_INTENSET_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ 15696 #define UARTE_INTENSET_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ 15697 #define UARTE_INTENSET_RXDRDY_Set (0x1UL) /*!< Enable */ 15698 15699 /* Bit 1 : Write '1' to enable interrupt for event NCTS */ 15700 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 15701 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 15702 #define UARTE_INTENSET_NCTS_Disabled (0x0UL) /*!< Read: Disabled */ 15703 #define UARTE_INTENSET_NCTS_Enabled (0x1UL) /*!< Read: Enabled */ 15704 #define UARTE_INTENSET_NCTS_Set (0x1UL) /*!< Enable */ 15705 15706 /* Bit 0 : Write '1' to enable interrupt for event CTS */ 15707 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 15708 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 15709 #define UARTE_INTENSET_CTS_Disabled (0x0UL) /*!< Read: Disabled */ 15710 #define UARTE_INTENSET_CTS_Enabled (0x1UL) /*!< Read: Enabled */ 15711 #define UARTE_INTENSET_CTS_Set (0x1UL) /*!< Enable */ 15712 15713 /* Register: UARTE_INTENCLR */ 15714 /* Description: Disable interrupt */ 15715 15716 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ 15717 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 15718 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 15719 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ 15720 #define UARTE_INTENCLR_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ 15721 #define UARTE_INTENCLR_TXSTOPPED_Clear (0x1UL) /*!< Disable */ 15722 15723 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ 15724 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 15725 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 15726 #define UARTE_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 15727 #define UARTE_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 15728 #define UARTE_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */ 15729 15730 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ 15731 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 15732 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 15733 #define UARTE_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ 15734 #define UARTE_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ 15735 #define UARTE_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */ 15736 15737 /* Bit 17 : Write '1' to disable interrupt for event RXTO */ 15738 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 15739 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ 15740 #define UARTE_INTENCLR_RXTO_Disabled (0x0UL) /*!< Read: Disabled */ 15741 #define UARTE_INTENCLR_RXTO_Enabled (0x1UL) /*!< Read: Enabled */ 15742 #define UARTE_INTENCLR_RXTO_Clear (0x1UL) /*!< Disable */ 15743 15744 /* Bit 9 : Write '1' to disable interrupt for event ERROR */ 15745 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 15746 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 15747 #define UARTE_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ 15748 #define UARTE_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ 15749 #define UARTE_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ 15750 15751 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */ 15752 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 15753 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 15754 #define UARTE_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */ 15755 #define UARTE_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */ 15756 #define UARTE_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */ 15757 15758 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ 15759 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 15760 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 15761 #define UARTE_INTENCLR_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ 15762 #define UARTE_INTENCLR_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ 15763 #define UARTE_INTENCLR_TXDRDY_Clear (0x1UL) /*!< Disable */ 15764 15765 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ 15766 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 15767 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 15768 #define UARTE_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ 15769 #define UARTE_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ 15770 #define UARTE_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */ 15771 15772 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ 15773 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 15774 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 15775 #define UARTE_INTENCLR_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ 15776 #define UARTE_INTENCLR_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ 15777 #define UARTE_INTENCLR_RXDRDY_Clear (0x1UL) /*!< Disable */ 15778 15779 /* Bit 1 : Write '1' to disable interrupt for event NCTS */ 15780 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 15781 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ 15782 #define UARTE_INTENCLR_NCTS_Disabled (0x0UL) /*!< Read: Disabled */ 15783 #define UARTE_INTENCLR_NCTS_Enabled (0x1UL) /*!< Read: Enabled */ 15784 #define UARTE_INTENCLR_NCTS_Clear (0x1UL) /*!< Disable */ 15785 15786 /* Bit 0 : Write '1' to disable interrupt for event CTS */ 15787 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ 15788 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ 15789 #define UARTE_INTENCLR_CTS_Disabled (0x0UL) /*!< Read: Disabled */ 15790 #define UARTE_INTENCLR_CTS_Enabled (0x1UL) /*!< Read: Enabled */ 15791 #define UARTE_INTENCLR_CTS_Clear (0x1UL) /*!< Disable */ 15792 15793 /* Register: UARTE_ERRORSRC */ 15794 /* Description: Error source This register is read/write one to clear. */ 15795 15796 /* Bit 3 : Break condition */ 15797 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 15798 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 15799 #define UARTE_ERRORSRC_BREAK_NotPresent (0x0UL) /*!< Read: error not present */ 15800 #define UARTE_ERRORSRC_BREAK_Present (0x1UL) /*!< Read: error present */ 15801 15802 /* Bit 2 : Framing error occurred */ 15803 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 15804 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 15805 #define UARTE_ERRORSRC_FRAMING_NotPresent (0x0UL) /*!< Read: error not present */ 15806 #define UARTE_ERRORSRC_FRAMING_Present (0x1UL) /*!< Read: error present */ 15807 15808 /* Bit 1 : Parity error */ 15809 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 15810 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 15811 #define UARTE_ERRORSRC_PARITY_NotPresent (0x0UL) /*!< Read: error not present */ 15812 #define UARTE_ERRORSRC_PARITY_Present (0x1UL) /*!< Read: error present */ 15813 15814 /* Bit 0 : Overrun error */ 15815 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 15816 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 15817 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0x0UL) /*!< Read: error not present */ 15818 #define UARTE_ERRORSRC_OVERRUN_Present (0x1UL) /*!< Read: error present */ 15819 15820 /* Register: UARTE_ENABLE */ 15821 /* Description: Enable UART */ 15822 15823 /* Bits 3..0 : Enable or disable UARTE */ 15824 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 15825 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 15826 #define UARTE_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable UARTE */ 15827 #define UARTE_ENABLE_ENABLE_Enabled (0x8UL) /*!< Enable UARTE */ 15828 15829 /* Register: UARTE_PSEL_RTS */ 15830 /* Description: Pin select for RTS signal */ 15831 15832 /* Bit 31 : Connection */ 15833 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 15834 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 15835 #define UARTE_PSEL_RTS_CONNECT_Connected (0x0UL) /*!< Connect */ 15836 #define UARTE_PSEL_RTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 15837 15838 /* Bits 4..0 : Pin number */ 15839 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 15840 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ 15841 15842 /* Register: UARTE_PSEL_TXD */ 15843 /* Description: Pin select for TXD signal */ 15844 15845 /* Bit 31 : Connection */ 15846 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 15847 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 15848 #define UARTE_PSEL_TXD_CONNECT_Connected (0x0UL) /*!< Connect */ 15849 #define UARTE_PSEL_TXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 15850 15851 /* Bits 4..0 : Pin number */ 15852 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 15853 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ 15854 15855 /* Register: UARTE_PSEL_CTS */ 15856 /* Description: Pin select for CTS signal */ 15857 15858 /* Bit 31 : Connection */ 15859 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 15860 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 15861 #define UARTE_PSEL_CTS_CONNECT_Connected (0x0UL) /*!< Connect */ 15862 #define UARTE_PSEL_CTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 15863 15864 /* Bits 4..0 : Pin number */ 15865 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 15866 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ 15867 15868 /* Register: UARTE_PSEL_RXD */ 15869 /* Description: Pin select for RXD signal */ 15870 15871 /* Bit 31 : Connection */ 15872 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 15873 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 15874 #define UARTE_PSEL_RXD_CONNECT_Connected (0x0UL) /*!< Connect */ 15875 #define UARTE_PSEL_RXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ 15876 15877 /* Bits 4..0 : Pin number */ 15878 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 15879 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ 15880 15881 /* Register: UARTE_BAUDRATE */ 15882 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ 15883 15884 /* Bits 31..0 : Baud rate */ 15885 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 15886 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 15887 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ 15888 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ 15889 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ 15890 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ 15891 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ 15892 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ 15893 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ 15894 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ 15895 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ 15896 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ 15897 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ 15898 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ 15899 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ 15900 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ 15901 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ 15902 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ 15903 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ 15904 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ 15905 15906 /* Register: UARTE_RXD_PTR */ 15907 /* Description: Data pointer */ 15908 15909 /* Bits 31..0 : Data pointer */ 15910 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 15911 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 15912 15913 /* Register: UARTE_RXD_MAXCNT */ 15914 /* Description: Maximum number of bytes in receive buffer */ 15915 15916 /* Bits 12..0 : Maximum number of bytes in receive buffer */ 15917 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 15918 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 15919 15920 /* Register: UARTE_RXD_AMOUNT */ 15921 /* Description: Number of bytes transferred in the last transaction */ 15922 15923 /* Bits 12..0 : Number of bytes transferred in the last transaction */ 15924 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 15925 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 15926 15927 /* Register: UARTE_TXD_PTR */ 15928 /* Description: Data pointer */ 15929 15930 /* Bits 31..0 : Data pointer */ 15931 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 15932 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 15933 15934 /* Register: UARTE_TXD_MAXCNT */ 15935 /* Description: Maximum number of bytes in transmit buffer */ 15936 15937 /* Bits 12..0 : Maximum number of bytes in transmit buffer */ 15938 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 15939 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x1FFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 15940 15941 /* Register: UARTE_TXD_AMOUNT */ 15942 /* Description: Number of bytes transferred in the last transaction */ 15943 15944 /* Bits 12..0 : Number of bytes transferred in the last transaction */ 15945 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 15946 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x1FFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 15947 15948 /* Register: UARTE_CONFIG */ 15949 /* Description: Configuration of parity and hardware flow control */ 15950 15951 /* Bit 4 : Stop bits */ 15952 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ 15953 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ 15954 #define UARTE_CONFIG_STOP_One (0x0UL) /*!< One stop bit */ 15955 #define UARTE_CONFIG_STOP_Two (0x1UL) /*!< Two stop bits */ 15956 15957 /* Bits 3..1 : Parity */ 15958 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 15959 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 15960 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ 15961 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ 15962 15963 /* Bit 0 : Hardware flow control */ 15964 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 15965 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 15966 #define UARTE_CONFIG_HWFC_Disabled (0x0UL) /*!< Disabled */ 15967 #define UARTE_CONFIG_HWFC_Enabled (0x1UL) /*!< Enabled */ 15968 15969 15970 /* Peripheral: UICR */ 15971 /* Description: User information configuration registers User information configuration registers */ 15972 15973 /* Register: UICR_APPROTECT */ 15974 /* Description: Access port protection */ 15975 15976 /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and 15977 memory mapped addresses */ 15978 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ 15979 #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ 15980 #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ 15981 #define UICR_APPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */ 15982 15983 /* Register: UICR_XOSC32M */ 15984 /* Description: Oscillator control */ 15985 15986 /* Bits 5..0 : Pierce current DAC control signals */ 15987 #define UICR_XOSC32M_CTRL_Pos (0UL) /*!< Position of CTRL field. */ 15988 #define UICR_XOSC32M_CTRL_Msk (0x3FUL << UICR_XOSC32M_CTRL_Pos) /*!< Bit mask of CTRL field. */ 15989 15990 /* Register: UICR_HFXOSRC */ 15991 /* Description: HFXO clock source selection */ 15992 15993 /* Bit 0 : HFXO clock source selection */ 15994 #define UICR_HFXOSRC_HFXOSRC_Pos (0UL) /*!< Position of HFXOSRC field. */ 15995 #define UICR_HFXOSRC_HFXOSRC_Msk (0x1UL << UICR_HFXOSRC_HFXOSRC_Pos) /*!< Bit mask of HFXOSRC field. */ 15996 #define UICR_HFXOSRC_HFXOSRC_TCXO (0x0UL) /*!< 32 MHz temperature compensated crystal oscillator (TCXO) */ 15997 #define UICR_HFXOSRC_HFXOSRC_XTAL (0x1UL) /*!< 32 MHz crystal oscillator */ 15998 15999 /* Register: UICR_HFXOCNT */ 16000 /* Description: HFXO startup counter */ 16001 16002 /* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */ 16003 #define UICR_HFXOCNT_HFXOCNT_Pos (0UL) /*!< Position of HFXOCNT field. */ 16004 #define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos) /*!< Bit mask of HFXOCNT field. */ 16005 #define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0x00UL) /*!< Min debounce time = (0*64 us + 0.5 us) */ 16006 #define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (0xFFUL) /*!< Max debounce time = (255*64 us + 0.5 us) */ 16007 16008 /* Register: UICR_APPNVMCPOFGUARD */ 16009 /* Description: Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition. */ 16010 16011 /* Bit 0 : Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition */ 16012 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos (0UL) /*!< Position of NVMCPOFGUARDEN field. */ 16013 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Msk (0x1UL << UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos) /*!< Bit mask of NVMCPOFGUARDEN field. */ 16014 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Disabled (0x0UL) /*!< NVM WRITE and NVM ERASE are not blocked in POFWARN condition */ 16015 #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Enabled (0x1UL) /*!< NVM WRITE and NVM ERASE are blocked in POFWARN condition */ 16016 16017 /* Register: UICR_SECUREAPPROTECT */ 16018 /* Description: Secure access port protection */ 16019 16020 /* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure 16021 memory mapped addresses */ 16022 #define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ 16023 #define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ 16024 #define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ 16025 #define UICR_SECUREAPPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */ 16026 16027 /* Register: UICR_ERASEPROTECT */ 16028 /* Description: Erase protection */ 16029 16030 /* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality */ 16031 #define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ 16032 #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ 16033 #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ 16034 #define UICR_ERASEPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */ 16035 16036 /* Register: UICR_OTP */ 16037 /* Description: Description collection: One time programmable memory */ 16038 16039 /* Bits 31..16 : Upper half word */ 16040 #define UICR_OTP_UPPER_Pos (16UL) /*!< Position of UPPER field. */ 16041 #define UICR_OTP_UPPER_Msk (0xFFFFUL << UICR_OTP_UPPER_Pos) /*!< Bit mask of UPPER field. */ 16042 16043 /* Bits 15..0 : Lower half word */ 16044 #define UICR_OTP_LOWER_Pos (0UL) /*!< Position of LOWER field. */ 16045 #define UICR_OTP_LOWER_Msk (0xFFFFUL << UICR_OTP_LOWER_Pos) /*!< Bit mask of LOWER field. */ 16046 16047 /* Register: UICR_KEYSLOT_CONFIG_DEST */ 16048 /* Description: Description cluster: Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) 16049 will be pushed by KMU. Note that this address must match that of a peripheral's 16050 APB mapped write-only key registers, otherwise the KMU can push this key value into 16051 an address range which the CPU can potentially read. */ 16052 16053 /* Bits 31..0 : Secure APB destination address */ 16054 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Pos (0UL) /*!< Position of DEST field. */ 16055 #define UICR_KEYSLOT_CONFIG_DEST_DEST_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_CONFIG_DEST_DEST_Pos) /*!< Bit mask of DEST field. */ 16056 16057 /* Register: UICR_KEYSLOT_CONFIG_PERM */ 16058 /* Description: Description cluster: Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. */ 16059 16060 /* Bit 16 : Revocation state for the key slot */ 16061 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */ 16062 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos) /*!< Bit mask of STATE field. */ 16063 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0x0UL) /*!< Key value registers can no longer be read or pushed */ 16064 #define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (0x1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */ 16065 16066 /* Bit 2 : Push permission for key slot */ 16067 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */ 16068 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos) /*!< Bit mask of PUSH field. */ 16069 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0x0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */ 16070 #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (0x1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */ 16071 16072 /* Bit 1 : Read permission for key slot */ 16073 #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */ 16074 #define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */ 16075 #define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0x0UL) /*!< Disable read from key value registers */ 16076 #define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (0x1UL) /*!< Enable read from key value registers */ 16077 16078 /* Bit 0 : Write permission for key slot */ 16079 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL) /*!< Position of WRITE field. */ 16080 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ 16081 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0x0UL) /*!< Disable write to the key value registers */ 16082 #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (0x1UL) /*!< Enable write to the key value registers */ 16083 16084 /* Register: UICR_KEYSLOT_KEY_VALUE */ 16085 /* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */ 16086 16087 /* Bits 31..0 : Define bits [31+o*32:0+o*32] of value assigned to KMU key slot */ 16088 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 16089 #define UICR_KEYSLOT_KEY_VALUE_VALUE_Msk (0xFFFFFFFFUL << UICR_KEYSLOT_KEY_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 16090 16091 16092 /* Peripheral: VMC */ 16093 /* Description: Volatile Memory controller 0 */ 16094 16095 /* Register: VMC_RAM_POWER */ 16096 /* Description: Description cluster: RAMn power control register */ 16097 16098 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ 16099 #define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ 16100 #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ 16101 #define VMC_RAM_POWER_S3RETENTION_Off (0x0UL) /*!< Off */ 16102 #define VMC_RAM_POWER_S3RETENTION_On (0x1UL) /*!< On */ 16103 16104 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ 16105 #define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ 16106 #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ 16107 #define VMC_RAM_POWER_S2RETENTION_Off (0x0UL) /*!< Off */ 16108 #define VMC_RAM_POWER_S2RETENTION_On (0x1UL) /*!< On */ 16109 16110 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ 16111 #define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 16112 #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 16113 #define VMC_RAM_POWER_S1RETENTION_Off (0x0UL) /*!< Off */ 16114 #define VMC_RAM_POWER_S1RETENTION_On (0x1UL) /*!< On */ 16115 16116 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ 16117 #define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 16118 #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 16119 #define VMC_RAM_POWER_S0RETENTION_Off (0x0UL) /*!< Off */ 16120 #define VMC_RAM_POWER_S0RETENTION_On (0x1UL) /*!< On */ 16121 16122 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ 16123 #define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ 16124 #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ 16125 #define VMC_RAM_POWER_S3POWER_Off (0x0UL) /*!< Off */ 16126 #define VMC_RAM_POWER_S3POWER_On (0x1UL) /*!< On */ 16127 16128 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ 16129 #define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ 16130 #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ 16131 #define VMC_RAM_POWER_S2POWER_Off (0x0UL) /*!< Off */ 16132 #define VMC_RAM_POWER_S2POWER_On (0x1UL) /*!< On */ 16133 16134 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ 16135 #define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 16136 #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 16137 #define VMC_RAM_POWER_S1POWER_Off (0x0UL) /*!< Off */ 16138 #define VMC_RAM_POWER_S1POWER_On (0x1UL) /*!< On */ 16139 16140 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ 16141 #define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 16142 #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 16143 #define VMC_RAM_POWER_S0POWER_Off (0x0UL) /*!< Off */ 16144 #define VMC_RAM_POWER_S0POWER_On (0x1UL) /*!< On */ 16145 16146 /* Register: VMC_RAM_POWERSET */ 16147 /* Description: Description cluster: RAMn power control set register */ 16148 16149 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ 16150 #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ 16151 #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ 16152 #define VMC_RAM_POWERSET_S3RETENTION_On (0x1UL) /*!< On */ 16153 16154 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ 16155 #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ 16156 #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ 16157 #define VMC_RAM_POWERSET_S2RETENTION_On (0x1UL) /*!< On */ 16158 16159 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ 16160 #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 16161 #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 16162 #define VMC_RAM_POWERSET_S1RETENTION_On (0x1UL) /*!< On */ 16163 16164 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ 16165 #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 16166 #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 16167 #define VMC_RAM_POWERSET_S0RETENTION_On (0x1UL) /*!< On */ 16168 16169 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ 16170 #define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ 16171 #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ 16172 #define VMC_RAM_POWERSET_S3POWER_On (0x1UL) /*!< On */ 16173 16174 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ 16175 #define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ 16176 #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ 16177 #define VMC_RAM_POWERSET_S2POWER_On (0x1UL) /*!< On */ 16178 16179 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ 16180 #define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 16181 #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 16182 #define VMC_RAM_POWERSET_S1POWER_On (0x1UL) /*!< On */ 16183 16184 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ 16185 #define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 16186 #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 16187 #define VMC_RAM_POWERSET_S0POWER_On (0x1UL) /*!< On */ 16188 16189 /* Register: VMC_RAM_POWERCLR */ 16190 /* Description: Description cluster: RAMn power control clear register */ 16191 16192 /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ 16193 #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ 16194 #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ 16195 #define VMC_RAM_POWERCLR_S3RETENTION_Off (0x1UL) /*!< Off */ 16196 16197 /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ 16198 #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ 16199 #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ 16200 #define VMC_RAM_POWERCLR_S2RETENTION_Off (0x1UL) /*!< Off */ 16201 16202 /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ 16203 #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 16204 #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 16205 #define VMC_RAM_POWERCLR_S1RETENTION_Off (0x1UL) /*!< Off */ 16206 16207 /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ 16208 #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 16209 #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 16210 #define VMC_RAM_POWERCLR_S0RETENTION_Off (0x1UL) /*!< Off */ 16211 16212 /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ 16213 #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ 16214 #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ 16215 #define VMC_RAM_POWERCLR_S3POWER_Off (0x1UL) /*!< Off */ 16216 16217 /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ 16218 #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ 16219 #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ 16220 #define VMC_RAM_POWERCLR_S2POWER_Off (0x1UL) /*!< Off */ 16221 16222 /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ 16223 #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 16224 #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 16225 #define VMC_RAM_POWERCLR_S1POWER_Off (0x1UL) /*!< Off */ 16226 16227 /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ 16228 #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 16229 #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 16230 #define VMC_RAM_POWERCLR_S0POWER_Off (0x1UL) /*!< Off */ 16231 16232 16233 /* Peripheral: WDT */ 16234 /* Description: Watchdog Timer 0 */ 16235 16236 /* Register: WDT_TASKS_START */ 16237 /* Description: Start the watchdog */ 16238 16239 /* Bit 0 : Start the watchdog */ 16240 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 16241 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 16242 #define WDT_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ 16243 16244 /* Register: WDT_SUBSCRIBE_START */ 16245 /* Description: Subscribe configuration for task START */ 16246 16247 /* Bit 31 : */ 16248 #define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 16249 #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 16250 #define WDT_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ 16251 #define WDT_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ 16252 16253 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 16254 #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 16255 #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 16256 16257 /* Register: WDT_EVENTS_TIMEOUT */ 16258 /* Description: Watchdog timeout */ 16259 16260 /* Bit 0 : Watchdog timeout */ 16261 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ 16262 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ 16263 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0x0UL) /*!< Event not generated */ 16264 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (0x1UL) /*!< Event generated */ 16265 16266 /* Register: WDT_PUBLISH_TIMEOUT */ 16267 /* Description: Publish configuration for event TIMEOUT */ 16268 16269 /* Bit 31 : */ 16270 #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */ 16271 #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */ 16272 #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0x0UL) /*!< Disable publishing */ 16273 #define WDT_PUBLISH_TIMEOUT_EN_Enabled (0x1UL) /*!< Enable publishing */ 16274 16275 /* Bits 7..0 : DPPI channel that event TIMEOUT will publish to */ 16276 #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 16277 #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 16278 16279 /* Register: WDT_INTENSET */ 16280 /* Description: Enable interrupt */ 16281 16282 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ 16283 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 16284 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 16285 #define WDT_INTENSET_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ 16286 #define WDT_INTENSET_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ 16287 #define WDT_INTENSET_TIMEOUT_Set (0x1UL) /*!< Enable */ 16288 16289 /* Register: WDT_INTENCLR */ 16290 /* Description: Disable interrupt */ 16291 16292 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ 16293 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 16294 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 16295 #define WDT_INTENCLR_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ 16296 #define WDT_INTENCLR_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ 16297 #define WDT_INTENCLR_TIMEOUT_Clear (0x1UL) /*!< Disable */ 16298 16299 /* Register: WDT_RUNSTATUS */ 16300 /* Description: Run status */ 16301 16302 /* Bit 0 : Indicates whether or not the watchdog is running */ 16303 #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */ 16304 #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */ 16305 #define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0x0UL) /*!< Watchdog not running */ 16306 #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (0x1UL) /*!< Watchdog is running */ 16307 16308 /* Register: WDT_REQSTATUS */ 16309 /* Description: Request status */ 16310 16311 /* Bit 7 : Request status for RR[7] register */ 16312 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ 16313 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ 16314 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0x0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ 16315 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (0x1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ 16316 16317 /* Bit 6 : Request status for RR[6] register */ 16318 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ 16319 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ 16320 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0x0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ 16321 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (0x1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ 16322 16323 /* Bit 5 : Request status for RR[5] register */ 16324 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ 16325 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ 16326 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0x0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ 16327 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (0x1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ 16328 16329 /* Bit 4 : Request status for RR[4] register */ 16330 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ 16331 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ 16332 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0x0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ 16333 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (0x1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ 16334 16335 /* Bit 3 : Request status for RR[3] register */ 16336 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ 16337 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ 16338 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0x0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ 16339 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (0x1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ 16340 16341 /* Bit 2 : Request status for RR[2] register */ 16342 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ 16343 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ 16344 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0x0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ 16345 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (0x1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ 16346 16347 /* Bit 1 : Request status for RR[1] register */ 16348 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ 16349 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ 16350 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0x0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ 16351 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (0x1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ 16352 16353 /* Bit 0 : Request status for RR[0] register */ 16354 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ 16355 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ 16356 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0x0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ 16357 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (0x1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ 16358 16359 /* Register: WDT_CRV */ 16360 /* Description: Counter reload value */ 16361 16362 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ 16363 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ 16364 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ 16365 16366 /* Register: WDT_RREN */ 16367 /* Description: Enable register for reload request registers */ 16368 16369 /* Bit 7 : Enable or disable RR[7] register */ 16370 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ 16371 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ 16372 #define WDT_RREN_RR7_Disabled (0x0UL) /*!< Disable RR[7] register */ 16373 #define WDT_RREN_RR7_Enabled (0x1UL) /*!< Enable RR[7] register */ 16374 16375 /* Bit 6 : Enable or disable RR[6] register */ 16376 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ 16377 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ 16378 #define WDT_RREN_RR6_Disabled (0x0UL) /*!< Disable RR[6] register */ 16379 #define WDT_RREN_RR6_Enabled (0x1UL) /*!< Enable RR[6] register */ 16380 16381 /* Bit 5 : Enable or disable RR[5] register */ 16382 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ 16383 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ 16384 #define WDT_RREN_RR5_Disabled (0x0UL) /*!< Disable RR[5] register */ 16385 #define WDT_RREN_RR5_Enabled (0x1UL) /*!< Enable RR[5] register */ 16386 16387 /* Bit 4 : Enable or disable RR[4] register */ 16388 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ 16389 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ 16390 #define WDT_RREN_RR4_Disabled (0x0UL) /*!< Disable RR[4] register */ 16391 #define WDT_RREN_RR4_Enabled (0x1UL) /*!< Enable RR[4] register */ 16392 16393 /* Bit 3 : Enable or disable RR[3] register */ 16394 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ 16395 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ 16396 #define WDT_RREN_RR3_Disabled (0x0UL) /*!< Disable RR[3] register */ 16397 #define WDT_RREN_RR3_Enabled (0x1UL) /*!< Enable RR[3] register */ 16398 16399 /* Bit 2 : Enable or disable RR[2] register */ 16400 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ 16401 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ 16402 #define WDT_RREN_RR2_Disabled (0x0UL) /*!< Disable RR[2] register */ 16403 #define WDT_RREN_RR2_Enabled (0x1UL) /*!< Enable RR[2] register */ 16404 16405 /* Bit 1 : Enable or disable RR[1] register */ 16406 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ 16407 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ 16408 #define WDT_RREN_RR1_Disabled (0x0UL) /*!< Disable RR[1] register */ 16409 #define WDT_RREN_RR1_Enabled (0x1UL) /*!< Enable RR[1] register */ 16410 16411 /* Bit 0 : Enable or disable RR[0] register */ 16412 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ 16413 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ 16414 #define WDT_RREN_RR0_Disabled (0x0UL) /*!< Disable RR[0] register */ 16415 #define WDT_RREN_RR0_Enabled (0x1UL) /*!< Enable RR[0] register */ 16416 16417 /* Register: WDT_CONFIG */ 16418 /* Description: Configuration register */ 16419 16420 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ 16421 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ 16422 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ 16423 #define WDT_CONFIG_HALT_Pause (0x0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ 16424 #define WDT_CONFIG_HALT_Run (0x1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ 16425 16426 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ 16427 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ 16428 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ 16429 #define WDT_CONFIG_SLEEP_Pause (0x0UL) /*!< Pause watchdog while the CPU is sleeping */ 16430 #define WDT_CONFIG_SLEEP_Run (0x1UL) /*!< Keep the watchdog running while the CPU is sleeping */ 16431 16432 /* Register: WDT_RR */ 16433 /* Description: Description collection: Reload request n */ 16434 16435 /* Bits 31..0 : Reload request register */ 16436 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ 16437 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ 16438 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ 16439 16440 16441 /*lint --flb "Leave library region" */ 16442 #endif 16443
