1 /* 2 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 3 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, this 10 list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its 17 contributors may be used to endorse or promote products derived from this 18 software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 * 32 * @file nrf9160.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 07. January 2025 36 * @note Generated by SVDConv V3.3.35 on Tuesday, 07.01.2025 15:34:34 37 * from File 'nrf9160.svd', 38 * last modified on Friday, 13.12.2024 08:41:27 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf9160 49 * @{ 50 */ 51 52 53 #ifndef NRF9160_H 54 #define NRF9160_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 82 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 83 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 84 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 85 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 86 /* ========================================== nrf9160 Specific Interrupt Numbers =========================================== */ 87 SPU_IRQn = 3, /*!< 3 SPU */ 88 CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 89 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 8, /*!< 8 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */ 90 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn= 9, /*!< 9 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 */ 91 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn= 10, /*!< 10 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 */ 92 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn= 11, /*!< 11 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 */ 93 GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ 94 SAADC_IRQn = 14, /*!< 14 SAADC */ 95 TIMER0_IRQn = 15, /*!< 15 TIMER0 */ 96 TIMER1_IRQn = 16, /*!< 16 TIMER1 */ 97 TIMER2_IRQn = 17, /*!< 17 TIMER2 */ 98 RTC0_IRQn = 20, /*!< 20 RTC0 */ 99 RTC1_IRQn = 21, /*!< 21 RTC1 */ 100 WDT_IRQn = 24, /*!< 24 WDT */ 101 EGU0_IRQn = 27, /*!< 27 EGU0 */ 102 EGU1_IRQn = 28, /*!< 28 EGU1 */ 103 EGU2_IRQn = 29, /*!< 29 EGU2 */ 104 EGU3_IRQn = 30, /*!< 30 EGU3 */ 105 EGU4_IRQn = 31, /*!< 31 EGU4 */ 106 EGU5_IRQn = 32, /*!< 32 EGU5 */ 107 PWM0_IRQn = 33, /*!< 33 PWM0 */ 108 PWM1_IRQn = 34, /*!< 34 PWM1 */ 109 PWM2_IRQn = 35, /*!< 35 PWM2 */ 110 PWM3_IRQn = 36, /*!< 36 PWM3 */ 111 PDM_IRQn = 38, /*!< 38 PDM */ 112 I2S_IRQn = 40, /*!< 40 I2S */ 113 IPC_IRQn = 42, /*!< 42 IPC */ 114 FPU_IRQn = 44, /*!< 44 FPU */ 115 GPIOTE1_IRQn = 49, /*!< 49 GPIOTE1 */ 116 KMU_IRQn = 57, /*!< 57 KMU */ 117 CRYPTOCELL_IRQn = 64 /*!< 64 CRYPTOCELL */ 118 } IRQn_Type; 119 120 121 122 /* =========================================================================================================================== */ 123 /* ================ Processor and Core Peripheral Section ================ */ 124 /* =========================================================================================================================== */ 125 126 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 127 #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 128 #define __INTERRUPTS_MAX 240 /*!< Top interrupt number */ 129 #define __DSP_PRESENT 1 /*!< DSP present or not */ 130 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 131 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 132 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 133 #define __MPU_PRESENT 1 /*!< MPU present */ 134 #define __FPU_PRESENT 1 /*!< FPU present */ 135 #define __FPU_DP 0 /*!< Double Precision FPU */ 136 #define __SAUREGION_PRESENT 0 /*!< SAU region present */ 137 138 139 /** @} */ /* End of group Configuration_of_CMSIS */ 140 141 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 142 #include "system_nrf9160.h" /*!< nrf9160 System */ 143 144 #ifndef __IM /*!< Fallback for older CMSIS versions */ 145 #define __IM __I 146 #endif 147 #ifndef __OM /*!< Fallback for older CMSIS versions */ 148 #define __OM __O 149 #endif 150 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 151 #define __IOM __IO 152 #endif 153 154 155 /* =========================================================================================================================== */ 156 /* ================ Device Specific Cluster Section ================ */ 157 /* =========================================================================================================================== */ 158 159 160 /** @addtogroup Device_Peripheral_clusters 161 * @{ 162 */ 163 164 165 /** 166 * @brief FICR_SIPINFO [SIPINFO] (SIP-specific device information is provided in the following chapters.) 167 */ 168 typedef struct { 169 __IM uint32_t PARTNO; /*!< (@ 0x00000000) SIP part number */ 170 __IM uint8_t HWREVISION[4]; /*!< (@ 0x00000004) Description collection: SIP hardware revision, 171 encoded in ASCII, for example B0A or B1A */ 172 __IM uint8_t VARIANT[4]; /*!< (@ 0x00000008) Description collection: SIP VARIANT, encoded 173 in ASCII, for example SIAA, SIBA or SICA. 174 See Ordering information for details. */ 175 } FICR_SIPINFO_Type; /*!< Size = 12 (0xc) */ 176 177 178 /** 179 * @brief FICR_INFO [INFO] (Device info) 180 */ 181 typedef struct { 182 __IM uint32_t RESERVED; 183 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 184 __IM uint32_t RESERVED1[3]; 185 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 186 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 187 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size */ 188 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 189 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 190 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 191 192 193 /** 194 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 195 */ 196 typedef struct { 197 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 198 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 199 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 200 201 202 /** 203 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 204 */ 205 typedef struct { 206 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 207 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 208 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 209 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 210 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator configuration 211 1 */ 212 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator configuration 213 2 */ 214 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator configuration 215 3 */ 216 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator configuration 217 4 */ 218 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 219 220 221 /** 222 * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified) 223 */ 224 typedef struct { 225 __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where 226 content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 227 ) will be pushed by KMU. Note that this 228 address must match that of a peripheral's 229 APB mapped write-only key registers, otherwise 230 the KMU can push this key value into an 231 address range which the CPU can potentially 232 read. */ 233 __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the 234 key slot. Bits 0-15 and 16-31 can only be 235 written when equal to 0xFFFF. */ 236 } UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */ 237 238 239 /** 240 * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified) 241 */ 242 typedef struct { 243 __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32] 244 of value assigned to KMU key slot. */ 245 } UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */ 246 247 248 /** 249 * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified) 250 */ 251 typedef struct { 252 __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */ 253 __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */ 254 } UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */ 255 256 257 /** 258 * @brief TAD_PSEL [PSEL] (Unspecified) 259 */ 260 typedef struct { 261 __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */ 262 __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */ 263 __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */ 264 __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */ 265 __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */ 266 } TAD_PSEL_Type; /*!< Size = 20 (0x14) */ 267 268 269 /** 270 * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified) 271 */ 272 typedef struct { 273 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated 274 from the external domain n List capabilities 275 of the external domain n */ 276 } SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */ 277 278 279 /** 280 * @brief SPU_DPPI [DPPI] (Unspecified) 281 */ 282 typedef struct { 283 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 284 non-secure attribute for the DPPI channels. */ 285 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 286 of the corresponding PERM register */ 287 } SPU_DPPI_Type; /*!< Size = 8 (0x8) */ 288 289 290 /** 291 * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified) 292 */ 293 typedef struct { 294 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 295 non-secure attribute for pins 0 to 31 of 296 port n. */ 297 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 298 of the corresponding PERM register */ 299 } SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ 300 301 302 /** 303 * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified) 304 */ 305 typedef struct { 306 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region 307 can contain the non-secure callable (NSC) 308 region n */ 309 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 310 callable (NSC) region n */ 311 } SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */ 312 313 314 /** 315 * @brief SPU_RAMNSC [RAMNSC] (Unspecified) 316 */ 317 typedef struct { 318 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region 319 can contain the non-secure callable (NSC) 320 region n */ 321 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 322 callable (NSC) region n */ 323 } SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */ 324 325 326 /** 327 * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified) 328 */ 329 typedef struct { 330 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash 331 region n */ 332 } SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */ 333 334 335 /** 336 * @brief SPU_RAMREGION [RAMREGION] (Unspecified) 337 */ 338 typedef struct { 339 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM 340 region n */ 341 } SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */ 342 343 344 /** 345 * @brief SPU_PERIPHID [PERIPHID] (Unspecified) 346 */ 347 typedef struct { 348 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access 349 permissions for the peripheral with ID n */ 350 } SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ 351 352 353 /** 354 * @brief POWER_LTEMODEM [LTEMODEM] (LTE Modem) 355 */ 356 typedef struct { 357 __IOM uint32_t STARTN; /*!< (@ 0x00000000) Start LTE modem */ 358 __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off LTE modem */ 359 } POWER_LTEMODEM_Type; /*!< Size = 8 (0x8) */ 360 361 362 /** 363 * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 364 */ 365 typedef struct { 366 __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ 367 __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if 368 data sent from the debugger to the CPU has 369 been read. */ 370 __IM uint32_t RESERVED[30]; 371 __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ 372 __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if 373 the data sent from the CPU to the debugger 374 has been read. */ 375 } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 376 377 378 /** 379 * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 380 */ 381 typedef struct { 382 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE 383 register from being written until next reset. */ 384 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register 385 and performs an ERASEALL operation. */ 386 } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 387 388 389 /** 390 * @brief SPIM_PSEL [PSEL] (Unspecified) 391 */ 392 typedef struct { 393 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 394 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 395 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 396 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 397 398 399 /** 400 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 401 */ 402 typedef struct { 403 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 404 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 405 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 406 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 407 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 408 409 410 /** 411 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 412 */ 413 typedef struct { 414 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 415 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 416 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 417 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 418 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 419 420 421 /** 422 * @brief SPIS_PSEL [PSEL] (Unspecified) 423 */ 424 typedef struct { 425 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 426 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 427 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 428 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 429 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 430 431 432 /** 433 * @brief SPIS_RXD [RXD] (Unspecified) 434 */ 435 typedef struct { 436 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 437 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 438 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 439 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 440 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 441 442 443 /** 444 * @brief SPIS_TXD [TXD] (Unspecified) 445 */ 446 typedef struct { 447 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 448 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 449 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 450 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 451 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 452 453 454 /** 455 * @brief TWIM_PSEL [PSEL] (Unspecified) 456 */ 457 typedef struct { 458 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 459 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 460 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 461 462 463 /** 464 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 465 */ 466 typedef struct { 467 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 468 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 469 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 470 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 471 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 472 473 474 /** 475 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 476 */ 477 typedef struct { 478 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 479 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 480 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 481 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 482 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 483 484 485 /** 486 * @brief TWIS_PSEL [PSEL] (Unspecified) 487 */ 488 typedef struct { 489 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 490 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 491 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 492 493 494 /** 495 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 496 */ 497 typedef struct { 498 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 499 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 500 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 501 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 502 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 503 504 505 /** 506 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 507 */ 508 typedef struct { 509 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 510 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 511 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 512 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 513 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 514 515 516 /** 517 * @brief UARTE_PSEL [PSEL] (Unspecified) 518 */ 519 typedef struct { 520 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 521 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 522 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 523 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 524 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 525 526 527 /** 528 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 529 */ 530 typedef struct { 531 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 532 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 533 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 534 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 535 536 537 /** 538 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 539 */ 540 typedef struct { 541 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 542 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 543 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 544 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 545 546 547 /** 548 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 549 */ 550 typedef struct { 551 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 552 above CH[n].LIMIT.HIGH */ 553 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 554 below CH[n].LIMIT.LOW */ 555 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 556 557 558 /** 559 * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events) 560 */ 561 typedef struct { 562 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for 563 event CH[n].LIMITH */ 564 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for 565 event CH[n].LIMITL */ 566 } SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */ 567 568 569 /** 570 * @brief SAADC_CH [CH] (Unspecified) 571 */ 572 typedef struct { 573 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 574 for CH[n] */ 575 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 576 for CH[n] */ 577 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 578 CH[n] */ 579 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 580 monitoring a channel */ 581 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 582 583 584 /** 585 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 586 */ 587 typedef struct { 588 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 589 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 590 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 591 START */ 592 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 593 594 595 /** 596 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 597 */ 598 typedef struct { 599 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 600 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 601 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 602 603 604 /** 605 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 606 */ 607 typedef struct { 608 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 609 for task CHG[n].EN */ 610 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 611 for task CHG[n].DIS */ 612 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 613 614 615 /** 616 * @brief PWM_SEQ [SEQ] (Unspecified) 617 */ 618 typedef struct { 619 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 620 of this sequence */ 621 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 622 in this sequence */ 623 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 624 periods between samples loaded into compare 625 register */ 626 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 627 __IM uint32_t RESERVED[4]; 628 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 629 630 631 /** 632 * @brief PWM_PSEL [PSEL] (Unspecified) 633 */ 634 typedef struct { 635 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 636 PWM channel n */ 637 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 638 639 640 /** 641 * @brief PDM_PSEL [PSEL] (Unspecified) 642 */ 643 typedef struct { 644 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 645 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 646 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 647 648 649 /** 650 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 651 */ 652 typedef struct { 653 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 654 EasyDMA */ 655 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 656 mode */ 657 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 658 659 660 /** 661 * @brief I2S_CONFIG [CONFIG] (Unspecified) 662 */ 663 typedef struct { 664 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 665 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 666 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 667 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 668 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 669 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 670 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 671 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 672 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 673 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 674 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 675 676 677 /** 678 * @brief I2S_RXD [RXD] (Unspecified) 679 */ 680 typedef struct { 681 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 682 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 683 684 685 /** 686 * @brief I2S_TXD [TXD] (Unspecified) 687 */ 688 typedef struct { 689 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 690 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 691 692 693 /** 694 * @brief I2S_RXTXD [RXTXD] (Unspecified) 695 */ 696 typedef struct { 697 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 698 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 699 700 701 /** 702 * @brief I2S_PSEL [PSEL] (Unspecified) 703 */ 704 typedef struct { 705 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 706 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 707 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 708 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 709 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 710 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 711 712 713 /** 714 * @brief VMC_RAM [RAM] (Unspecified) 715 */ 716 typedef struct { 717 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 718 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 719 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 720 register */ 721 __IM uint32_t RESERVED; 722 } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 723 724 725 /** @} */ /* End of group Device_Peripheral_clusters */ 726 727 728 /* =========================================================================================================================== */ 729 /* ================ Device Specific Peripheral Section ================ */ 730 /* =========================================================================================================================== */ 731 732 733 /** @addtogroup Device_Peripheral_peripherals 734 * @{ 735 */ 736 737 738 739 /* =========================================================================================================================== */ 740 /* ================ FICR_S ================ */ 741 /* =========================================================================================================================== */ 742 743 744 /** 745 * @brief Factory Information Configuration Registers (FICR_S) 746 */ 747 748 typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 749 __IM uint32_t RESERVED[80]; 750 __IOM FICR_SIPINFO_Type SIPINFO; /*!< (@ 0x00000140) SIP-specific device information is provided in 751 the following chapters. */ 752 __IM uint32_t RESERVED1[45]; 753 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 754 __IM uint32_t RESERVED2[53]; 755 __IOM FICR_TRIMCNF_Type TRIMCNF[256]; /*!< (@ 0x00000300) Unspecified */ 756 __IM uint32_t RESERVED3[64]; 757 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 758 } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 759 760 761 762 /* =========================================================================================================================== */ 763 /* ================ UICR_S ================ */ 764 /* =========================================================================================================================== */ 765 766 767 /** 768 * @brief User information configuration registers User information configuration registers (UICR_S) 769 */ 770 771 typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ 772 __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 773 __IM uint32_t RESERVED[4]; 774 __IOM uint32_t XOSC32M; /*!< (@ 0x00000014) Oscillator control */ 775 __IM uint32_t RESERVED1; 776 __IOM uint32_t HFXOSRC; /*!< (@ 0x0000001C) HFXO clock source selection */ 777 __IOM uint32_t HFXOCNT; /*!< (@ 0x00000020) HFXO startup counter */ 778 __IOM uint32_t APPNVMCPOFGUARD; /*!< (@ 0x00000024) Enable blocking NVM WRITE and aborting NVM ERASE 779 for Application NVM in POFWARN condition. */ 780 __IM uint32_t RESERVED2; 781 __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000002C) Secure access port protection */ 782 __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000030) Erase protection */ 783 __IM uint32_t RESERVED3[53]; 784 __IOM uint32_t OTP[190]; /*!< (@ 0x00000108) Description collection: One time programmable 785 memory */ 786 __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */ 787 } NRF_UICR_Type; /*!< Size = 4096 (0x1000) */ 788 789 790 791 /* =========================================================================================================================== */ 792 /* ================ ETM_NS ================ */ 793 /* =========================================================================================================================== */ 794 795 796 /** 797 * @brief Embedded Trace Macrocell (ETM_NS) 798 */ 799 800 typedef struct { /*!< (@ 0xE0041000) ETM_NS Structure */ 801 __IM uint32_t RESERVED; 802 __IOM uint32_t TRCPRGCTLR; /*!< (@ 0x00000004) Enables the trace unit. */ 803 __IOM uint32_t TRCPROCSELR; /*!< (@ 0x00000008) Controls which PE to trace. Might ignore writes 804 when the trace unit is enabled or not idle. 805 Before writing to this register, ensure 806 that TRCSTATR.IDLE == 1 so that the trace 807 unit can synchronize with the chosen PE. 808 Implemented if TRCIDR3.NUMPROC is greater 809 than zero. */ 810 __IOM uint32_t TRCSTATR; /*!< (@ 0x0000000C) Idle status bit */ 811 __IOM uint32_t TRCCONFIGR; /*!< (@ 0x00000010) Controls the tracing options This register must 812 always be programmed as part of trace unit 813 initialization. Might ignore writes when 814 the trace unit is enabled or not idle. */ 815 __IM uint32_t RESERVED1[3]; 816 __IOM uint32_t TRCEVENTCTL0R; /*!< (@ 0x00000020) Controls the tracing of arbitrary events. If 817 the selected event occurs a trace element 818 is generated in the trace stream according 819 to the settings in TRCEVENTCTL1R.DATAEN 820 and TRCEVENTCTL1R.INSTEN. */ 821 __IOM uint32_t TRCEVENTCTL1R; /*!< (@ 0x00000024) Controls the behavior of the events that TRCEVENTCTL0R 822 selects. This register must always be programmed 823 as part of trace unit initialization. Might 824 ignore writes when the trace unit is enabled 825 or not idle. */ 826 __IM uint32_t RESERVED2; 827 __IOM uint32_t TRCSTALLCTLR; /*!< (@ 0x0000002C) Enables trace unit functionality that prevents 828 trace unit buffer overflows. Might ignore 829 writes when the trace unit is enabled or 830 not idle. Must be programmed if TRCIDR3.STALLCTL 831 == 1. */ 832 __IOM uint32_t TRCTSCTLR; /*!< (@ 0x00000030) Controls the insertion of global timestamps in 833 the trace streams. When the selected event 834 is triggered, the trace unit inserts a global 835 timestamp into the trace streams. Might 836 ignore writes when the trace unit is enabled 837 or not idle. Must be programmed if TRCCONFIGR.TS 838 == 1. */ 839 __IOM uint32_t TRCSYNCPR; /*!< (@ 0x00000034) Controls how often trace synchronization requests 840 occur. Might ignore writes when the trace 841 unit is enabled or not idle. If writes are 842 permitted then the register must be programmed. */ 843 __IOM uint32_t TRCCCCTLR; /*!< (@ 0x00000038) Sets the threshold value for cycle counting. 844 Might ignore writes when the trace unit 845 is enabled or not idle. Must be programmed 846 if TRCCONFIGR.CCI==1. */ 847 __IOM uint32_t TRCBBCTLR; /*!< (@ 0x0000003C) Controls which regions in the memory map are 848 enabled to use branch broadcasting. Might 849 ignore writes when the trace unit is enabled 850 or not idle. Must be programmed if TRCCONFIGR.BB 851 == 1. */ 852 __IOM uint32_t TRCTRACEIDR; /*!< (@ 0x00000040) Sets the trace ID for instruction trace. If data 853 trace is enabled then it also sets the trace 854 ID for data trace, to (trace ID for instruction 855 trace) + 1. This register must always be 856 programmed as part of trace unit initialization. 857 Might ignore writes when the trace unit 858 is enabled or not idle. */ 859 __IOM uint32_t TRCQCTLR; /*!< (@ 0x00000044) Controls when Q elements are enabled. Might ignore 860 writes when the trace unit is enabled or 861 not idle. This register must be programmed 862 if it is implemented and TRCCONFIGR.QE is 863 set to any value other than 0b00. */ 864 __IM uint32_t RESERVED3[14]; 865 __IOM uint32_t TRCVICTLR; /*!< (@ 0x00000080) Controls instruction trace filtering. Might ignore 866 writes when the trace unit is enabled or 867 not idle. Only returns stable data when 868 TRCSTATR.PMSTABLE == 1. Must be programmed, 869 particularly to set the value of the SSSTATUS 870 bit, which sets the state of the start/stop 871 logic. */ 872 __IOM uint32_t TRCVIIECTLR; /*!< (@ 0x00000084) ViewInst exclude control. Might ignore writes 873 when the trace unit is enabled or not idle. 874 This register must be programmed when one 875 or more address comparators are implemented. */ 876 __IOM uint32_t TRCVISSCTLR; /*!< (@ 0x00000088) Use this to set, or read, the single address 877 comparators that control the ViewInst start/stoplogic. 878 The start/stop logic is active for an instruction 879 which causes a start and remains activeup 880 to and including an instruction which causes 881 a stop, and then the start/stop logic becomesinactive. 882 Might ignore writes when the trace unit 883 is enabled or not idle. If implemented then 884 this register must be programmed. */ 885 __IOM uint32_t TRCVIPCSSCTLR; /*!< (@ 0x0000008C) Use this to set, or read, which PE comparator 886 inputs can control the ViewInst start/stop 887 logic. Might ignore writes when the trace 888 unit is enabled or not idle. If implemented 889 then this register must be programmed. */ 890 __IM uint32_t RESERVED4[4]; 891 __IOM uint32_t TRCVDCTLR; /*!< (@ 0x000000A0) Controls data trace filtering. Might ignore writes 892 when the trace unit is enabled or not idle. 893 This register must be programmed when data 894 tracing is enabled, that is, when either 895 TRCCONFIGR.DA == 1 or TRCCONFIGR.DV == 1. */ 896 __IOM uint32_t TRCVDSACCTLR; /*!< (@ 0x000000A4) ViewData include / exclude control. Might ignore 897 writes when the trace unit is enabled or 898 not idle. This register must be programmed 899 when one or more address comparators are 900 implemented. */ 901 __IOM uint32_t TRCVDARCCTLR; /*!< (@ 0x000000A8) ViewData include / exclude control. Might ignore 902 writes when the trace unit is enabled or 903 not idle. This register must be programmed 904 when one or more address comparators are 905 implemented. */ 906 __IM uint32_t RESERVED5[21]; 907 __IOM uint32_t TRCSEQEVR[3]; /*!< (@ 0x00000100) Description collection: Moves the sequencer state 908 according to programmed events. Might ignore 909 writes when the trace unit is enabled or 910 not idle. When the sequencer is used, all 911 sequencer state transitions must be programmed 912 with a valid event. */ 913 __IM uint32_t RESERVED6[3]; 914 __IOM uint32_t TRCSEQRSTEVR; /*!< (@ 0x00000118) Moves the sequencer to state 0 when a programmed 915 event occurs. Might ignore writes when the 916 trace unit is enabled or not idle. When 917 the sequencer is used, all sequencer state 918 transitions must be programmed with a valid 919 event. */ 920 __IOM uint32_t TRCSEQSTR; /*!< (@ 0x0000011C) Use this to set, or read, the sequencer state. 921 Might ignore writes when the trace unit 922 is enabled or not idle. Only returns stable 923 data when TRCSTATR.PMSTABLE == 1. When the 924 sequencer is used, all sequencer state transitions 925 must be programmed with a valid event. */ 926 __IOM uint32_t TRCEXTINSELR; /*!< (@ 0x00000120) Use this to set, or read, which external inputs 927 are resources to the trace unit. Might ignore 928 writes when the trace unit is enabled or 929 not idle. Only returns stable data when 930 TRCSTATR.PMSTABLE == 1. When the sequencer 931 is used, all sequencer state transitions 932 must be programmed with a valid event. */ 933 __IM uint32_t RESERVED7[7]; 934 __IOM uint32_t TRCCNTRLDVR[4]; /*!< (@ 0x00000140) Description collection: This sets or returns 935 the reload count value for counter n. Might 936 ignore writes when the trace unit is enabled 937 or not idle. */ 938 __IOM uint32_t TRCCNTCTLR[4]; /*!< (@ 0x00000150) Description collection: Controls the operation 939 of counter n. Might ignore writes when the 940 trace unit is enabled or not idle. */ 941 __IOM uint32_t TRCCNTVR[4]; /*!< (@ 0x00000160) Description collection: This sets or returns 942 the value of counter n. The count value 943 is only stable when TRCSTATR.PMSTABLE == 944 1. If software uses counter n then it must 945 write to this register to set the initial 946 counter value. Might ignore writes when 947 the trace unit is enabled or not idle. */ 948 __IM uint32_t RESERVED8[36]; 949 __IOM uint32_t TRCRSCTLR[30]; /*!< (@ 0x00000200) Description collection: Controls the selection 950 of the resources in the trace unit. Might 951 ignore writes when the trace unit is enabled 952 or not idle. If software selects a non-implemented 953 resource then CONSTRAINED UNPREDICTABLEbehavior 954 of the resource selector occurs, so the 955 resource selector might fireunexpectedly 956 or might not fire. Reads of the TRCRSCTLRn 957 might return UNKNOWN. */ 958 __IM uint32_t RESERVED9[2]; 959 __IOM uint32_t TRCSSCCR0; /*!< (@ 0x00000280) Controls the single-shot comparator. */ 960 __IM uint32_t RESERVED10[7]; 961 __IOM uint32_t TRCSSCSR0; /*!< (@ 0x000002A0) Indicates the status of the single-shot comparators. 962 TRCSSCSR0 is sensitive toinstruction addresses. */ 963 __IM uint32_t RESERVED11[7]; 964 __IOM uint32_t TRCSSPCICR0; /*!< (@ 0x000002C0) Selects the processor comparator inputs for Single-shot 965 control. */ 966 __IM uint32_t RESERVED12[19]; 967 __IOM uint32_t TRCPDCR; /*!< (@ 0x00000310) Controls the single-shot comparator. */ 968 __IOM uint32_t TRCPDSR; /*!< (@ 0x00000314) Indicates the power down status of the ETM. */ 969 __IM uint32_t RESERVED13[755]; 970 __IOM uint32_t TRCITATBIDR; /*!< (@ 0x00000EE4) Sets the state of output pins. */ 971 __IM uint32_t RESERVED14[3]; 972 __IOM uint32_t TRCITIATBINR; /*!< (@ 0x00000EF4) Reads the state of the input pins. */ 973 __IM uint32_t RESERVED15; 974 __IOM uint32_t TRCITIATBOUTR; /*!< (@ 0x00000EFC) Sets the state of the output pins. */ 975 __IOM uint32_t TRCITCTRL; /*!< (@ 0x00000F00) Enables topology detection or integration testing, 976 by putting ETM-M33 into integration mode. */ 977 __IM uint32_t RESERVED16[39]; 978 __IOM uint32_t TRCCLAIMSET; /*!< (@ 0x00000FA0) Sets bits in the claim tag and determines the 979 number of claim tag bits implemented. */ 980 __IOM uint32_t TRCCLAIMCLR; /*!< (@ 0x00000FA4) Clears bits in the claim tag and determines the 981 current value of the claim tag. */ 982 __IM uint32_t RESERVED17[4]; 983 __IOM uint32_t TRCAUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted 984 by the system */ 985 __IM uint32_t TRCDEVARCH; /*!< (@ 0x00000FBC) The TRCDEVARCH identifies ETM-M33 as an ETMv4.2 986 component */ 987 __IM uint32_t RESERVED18[3]; 988 __IM uint32_t TRCDEVTYPE; /*!< (@ 0x00000FCC) Controls the single-shot comparator. */ 989 __IOM uint32_t TRCPIDR[8]; /*!< (@ 0x00000FD0) Description collection: Coresight peripheral 990 identification registers. */ 991 __IOM uint32_t TRCCIDR[4]; /*!< (@ 0x00000FF0) Description collection: Coresight component identification 992 registers. */ 993 } NRF_ETM_Type; /*!< Size = 4096 (0x1000) */ 994 995 996 997 /* =========================================================================================================================== */ 998 /* ================ ETB_NS ================ */ 999 /* =========================================================================================================================== */ 1000 1001 1002 /** 1003 * @brief Embedded Trace Buffer (ETB_NS) 1004 */ 1005 1006 typedef struct { /*!< (@ 0xE0051000) ETB_NS Structure */ 1007 __IM uint32_t RESERVED; 1008 __IM uint32_t RDP; /*!< (@ 0x00000004) ETB RAM Depth Register */ 1009 __IM uint32_t RESERVED1; 1010 __IM uint32_t STS; /*!< (@ 0x0000000C) ETB Status Register */ 1011 __IM uint32_t RRD; /*!< (@ 0x00000010) ETB RAM Read Data Register */ 1012 __IOM uint32_t RRP; /*!< (@ 0x00000014) ETB RAM Read Pointer Register */ 1013 __IOM uint32_t RWP; /*!< (@ 0x00000018) ETB RAM Write Pointer Register */ 1014 __IOM uint32_t TRG; /*!< (@ 0x0000001C) ETB Trigger Counter Register */ 1015 __IOM uint32_t CTL; /*!< (@ 0x00000020) ETB Control Register */ 1016 __IOM uint32_t RWD; /*!< (@ 0x00000024) ETB RAM Write Data Register */ 1017 __IM uint32_t RESERVED2[182]; 1018 __IM uint32_t FFSR; /*!< (@ 0x00000300) ETB Formatter and Flush Status Register */ 1019 __IOM uint32_t FFCR; /*!< (@ 0x00000304) ETB Formatter and Flush Control Register */ 1020 __IM uint32_t RESERVED3[758]; 1021 __OM uint32_t ITMISCOP0; /*!< (@ 0x00000EE0) Integration Test Miscellaneous Output Register 1022 0 */ 1023 __OM uint32_t ITTRFLINACK; /*!< (@ 0x00000EE4) Integration Test Trigger In and Flush In Acknowledge 1024 Register */ 1025 __IM uint32_t ITTRFLIN; /*!< (@ 0x00000EE8) Integration Test Trigger In and Flush In Register */ 1026 __IM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) Integration Test ATB Data Register 0 */ 1027 __OM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) Integration Test ATB Control Register 2 */ 1028 __IM uint32_t ITATBCTR1; /*!< (@ 0x00000EF4) Integration Test ATB Control Register 1 */ 1029 __IM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) Integration Test ATB Control Register 0 */ 1030 __IM uint32_t RESERVED4; 1031 __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) Integration Mode Control Register */ 1032 __IM uint32_t RESERVED5[39]; 1033 __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Claim Tag Set Register */ 1034 __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Claim Tag Clear Register */ 1035 __IM uint32_t RESERVED6[2]; 1036 __OM uint32_t LAR; /*!< (@ 0x00000FB0) Lock Access Register */ 1037 __IM uint32_t LSR; /*!< (@ 0x00000FB4) Lock Status Register */ 1038 __IM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Authentication Status Register */ 1039 __IM uint32_t RESERVED7[3]; 1040 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Device Configuration Register */ 1041 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Device Type Identifier Register */ 1042 __IM uint32_t PERIPHID4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ 1043 __IM uint32_t RESERVED8[3]; 1044 __IM uint32_t PERIPHID0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ 1045 __IM uint32_t PERIPHID1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ 1046 __IM uint32_t PERIPHID2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ 1047 __IM uint32_t PERIPHID3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ 1048 __IM uint32_t COMPID0; /*!< (@ 0x00000FF0) Component ID0 Register */ 1049 __IM uint32_t COMPID1; /*!< (@ 0x00000FF4) Component ID1 Register */ 1050 __IM uint32_t COMPID2; /*!< (@ 0x00000FF8) Component ID2 Register */ 1051 __IM uint32_t COMPID3; /*!< (@ 0x00000FFC) Component ID3 Register */ 1052 } NRF_ETB_Type; /*!< Size = 4096 (0x1000) */ 1053 1054 1055 1056 /* =========================================================================================================================== */ 1057 /* ================ TPIU_NS ================ */ 1058 /* =========================================================================================================================== */ 1059 1060 1061 /** 1062 * @brief Trace Port Interface Unit (TPIU_NS) 1063 */ 1064 1065 typedef struct { /*!< (@ 0xE0054000) TPIU_NS Structure */ 1066 __IOM uint32_t SUPPORTEDPORTSIZES; /*!< (@ 0x00000000) Each bit location is a single port size that 1067 is supported on the device. */ 1068 __IOM uint32_t CURRENTPORTSIZE; /*!< (@ 0x00000004) Each bit location is a single port size. One 1069 bit can be set, and indicates the current 1070 port size. */ 1071 __IM uint32_t RESERVED[62]; 1072 __IOM uint32_t SUPPORTEDTRIGGERMODES; /*!< (@ 0x00000100) The Supported_trigger_modes register indicates 1073 the implemented trigger counter multipliers 1074 and other supported features of the trigger 1075 system. */ 1076 __IOM uint32_t TRIGGERCOUNTERVALUE; /*!< (@ 0x00000104) The Trigger_counter_value register enables delaying 1077 the indication of triggers to any external 1078 connected trace capture or storage devices. */ 1079 __IOM uint32_t TRIGGERMULTIPLIER; /*!< (@ 0x00000108) The Trigger_multiplier register contains the 1080 selectors for the trigger counter multiplier. */ 1081 __IM uint32_t RESERVED1[61]; 1082 __IOM uint32_t SUPPPORTEDTESTPATTERNMODES; /*!< (@ 0x00000200) The Supported_test_pattern_modes register provides 1083 a set of known bit sequences or patterns 1084 that can be output over the trace port and 1085 can be detected by the TPA or other associated 1086 trace capture device. */ 1087 __IOM uint32_t CURRENTTESTPATTERNMODES; /*!< (@ 0x00000204) Current_test_pattern_mode indicates the current 1088 test pattern or mode selected. */ 1089 __IOM uint32_t TPRCR; /*!< (@ 0x00000208) The TPRCR register is an 8-bit counter start 1090 value that is decremented. A write sets 1091 the initial counter value and a read returns 1092 the programmed value. */ 1093 __IM uint32_t RESERVED2[61]; 1094 __IOM uint32_t FFSR; /*!< (@ 0x00000300) The FFSR register indicates the current status 1095 of the formatter and flush features available 1096 in the TPIU. */ 1097 __IOM uint32_t FFCR; /*!< (@ 0x00000304) The FFCR register controls the generation of 1098 stop, trigger, and flush events. */ 1099 __IOM uint32_t FSCR; /*!< (@ 0x00000308) The FSCR register enables the frequency of synchronization 1100 information to be optimized to suit the 1101 Trace Port Analyzer (TPA) capture buffer 1102 size. */ 1103 __IM uint32_t RESERVED3[61]; 1104 __IOM uint32_t EXTCTLINPORT; /*!< (@ 0x00000400) Two ports can be used as a control and feedback 1105 mechanism for any serializers, pin sharing 1106 multiplexers, or other solutions that might 1107 be added to the trace output pins either 1108 for pin control or a high-speed trace port 1109 solution. */ 1110 __IOM uint32_t EXTCTLOUTPORT; /*!< (@ 0x00000404) Two ports can be used as a control and feedback 1111 mechanism for any serializers, pin sharing 1112 multiplexers, or other solutions that might 1113 be added to the trace output pins either 1114 for pin control or a high speed trace port 1115 solution. These ports are raw register banks 1116 that sample or export the corresponding 1117 external pins. */ 1118 __IM uint32_t RESERVED4[695]; 1119 __IOM uint32_t ITTRFLINACK; /*!< (@ 0x00000EE4) The ITTRFLINACK register enables control of the 1120 triginack and flushinack outputs from the 1121 TPIU. */ 1122 __IOM uint32_t ITTRFLIN; /*!< (@ 0x00000EE8) The ITTRFLIN register contains the values of 1123 the flushin and trigin inputs to the TPIU. */ 1124 __IOM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) The ITATBDATA0 register contains the value of 1125 the atdatas inputs to the TPIU. The values 1126 are valid only when atvalids is HIGH. */ 1127 __IOM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) Enables control of the atreadys and afvalids 1128 outputs of the TPIU. */ 1129 __IOM uint32_t ITATBCTR1; /*!< (@ 0x00000EF4) The ITATBCTR1 register contains the value of 1130 the atids input to the TPIU. This is only 1131 valid when atvalids is HIGH. */ 1132 __IOM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) The ITATBCTR0 register captures the values of 1133 the atvalids, afreadys, and atbytess inputs 1134 to the TPIU. To ensure the integration 1135 registers work correctly in a system, the 1136 value of atbytess is only valid when atvalids, 1137 bit[0], is HIGH. */ 1138 __IM uint32_t RESERVED5; 1139 __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) Used to enable topology detection. This register 1140 enables the component to switch from a functional 1141 mode, the default behavior, to integration 1142 mode where the inputs and outputs of the 1143 component can be directly controlled for 1144 integration testing and topology solving. */ 1145 __IM uint32_t RESERVED6[39]; 1146 __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate 1147 application and debugger access to trace 1148 unit functionality. The claim tags have 1149 no effect on the operation of the component. 1150 The CLAIMSET register sets bits in the claim 1151 tag, and determines the number of claim 1152 bits implemented. */ 1153 __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate 1154 application and debugger access to trace 1155 unit functionality. The claim tags have 1156 no effect on the operation of the component. 1157 The CLAIMCLR register sets the bits in the 1158 claim tag to 0 and determines the current 1159 value of the claim tag. */ 1160 __IM uint32_t RESERVED7[2]; 1161 __IOM uint32_t LAR; /*!< (@ 0x00000FB0) This is used to enable write access to device 1162 registers. */ 1163 __IOM uint32_t LSR; /*!< (@ 0x00000FB4) This indicates the status of the lock control 1164 mechanism. This lock prevents accidental 1165 writes by code under debug. Accesses to 1166 the extended stimulus port registers are 1167 not affected by the lock mechanism. This 1168 register must always be present although 1169 there might not be any lock access control 1170 mechanism. The lock mechanism, where present 1171 and locked, must block write accesses to 1172 any control register, except the Lock Access 1173 Register. For most components this cover */ 1174 __IOM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted 1175 by the system */ 1176 __IM uint32_t RESERVED8[3]; 1177 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Indicates the capabilities of the component. */ 1178 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with 1179 information about the component when the 1180 Part Number field is not recognized. The 1181 debugger can then report this information. */ 1182 __IOM uint32_t PIDR4; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ 1183 __IM uint32_t RESERVED9[3]; 1184 __IOM uint32_t PIDR_0; /*!< (@ 0x00000FE0) Coresight peripheral identification registers. */ 1185 __IOM uint32_t PIDR_1; /*!< (@ 0x00000FE4) Coresight peripheral identification registers. */ 1186 __IOM uint32_t PIDR_2; /*!< (@ 0x00000FE8) Coresight peripheral identification registers. */ 1187 __IOM uint32_t PIDR_3; /*!< (@ 0x00000FEC) Coresight peripheral identification registers. */ 1188 __IOM uint32_t CIDR_0; /*!< (@ 0x00000FF0) Coresight component identification registers. */ 1189 __IOM uint32_t CIDR_1; /*!< (@ 0x00000FF4) Coresight component identification registers. */ 1190 __IOM uint32_t CIDR_2; /*!< (@ 0x00000FF8) Coresight component identification registers. */ 1191 __IOM uint32_t CIDR_3; /*!< (@ 0x00000FFC) Coresight component identification registers. */ 1192 } NRF_TPIU_Type; /*!< Size = 4096 (0x1000) */ 1193 1194 1195 1196 /* =========================================================================================================================== */ 1197 /* ================ ATBREPLICATOR_NS ================ */ 1198 /* =========================================================================================================================== */ 1199 1200 1201 /** 1202 * @brief ATB Replicator module (ATBREPLICATOR_NS) 1203 */ 1204 1205 typedef struct { /*!< (@ 0xE0058000) ATBREPLICATOR_NS Structure */ 1206 __IOM uint32_t IDFILTER0; /*!< (@ 0x00000000) The IDFILTER0 register enables the programming 1207 of ID filtering for master port 0. */ 1208 __IOM uint32_t IDFILTER1; /*!< (@ 0x00000004) The IDFILTER1 register enables the programming 1209 of ID filtering for master port 1. */ 1210 __IM uint32_t RESERVED[956]; 1211 __IOM uint32_t ITATBCTR1; /*!< (@ 0x00000EF8) The ITATBCTR1 register returns the value of the 1212 atreadym0, atreadym1, and atvalids inputs 1213 in integration mode. */ 1214 __IOM uint32_t ITATBCTR0; /*!< (@ 0x00000EFC) The ITATBCTR0 register controls the value of 1215 the atvalidm0, atvalidm1, and atreadys outputs 1216 in integration mode. */ 1217 __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) The ITCTRL register enables the component to 1218 switch from a functional mode, which is 1219 the default behavior, to integration mode 1220 where the inputs and outputs of the component 1221 can be directly controlled for the purposes 1222 of integration testing and topology detection. */ 1223 __IM uint32_t RESERVED1[39]; 1224 __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate 1225 application and debugger access to trace 1226 unit functionality. The claim tags have 1227 no effect on the operation of the component. 1228 The CLAIMSET register sets bits in the claim 1229 tag, and determines the number of claim 1230 bits implemented. */ 1231 __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate 1232 application and debugger access to trace 1233 unit functionality. The claim tags have 1234 no effect on the operation of the component. 1235 The CLAIMCLR register sets the bits in the 1236 claim tag to 0 and determines the current 1237 value of the claim tag. */ 1238 __IM uint32_t RESERVED2[2]; 1239 __IOM uint32_t LAR; /*!< (@ 0x00000FB0) This is used to enable write access to device 1240 registers. */ 1241 __IOM uint32_t LSR; /*!< (@ 0x00000FB4) This indicates the status of the lock control 1242 mechanism. This lock prevents accidental 1243 writes by code under debug. Accesses to 1244 the extended stimulus port registers are 1245 not affected by the lock mechanism. This 1246 register must always be present although 1247 there might not be any lock access control 1248 mechanism. The lock mechanism, where present 1249 and locked, must block write accesses to 1250 any control register, except the Lock Access 1251 Register. For most components this cover */ 1252 __IOM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted 1253 by the system */ 1254 __IM uint32_t RESERVED3[3]; 1255 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Indicates the capabilities of the component. */ 1256 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with 1257 information about the component when the 1258 Part Number field is not recognized. The 1259 debugger can then report this information. */ 1260 __IOM uint32_t PIDR4; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ 1261 __IM uint32_t RESERVED4[3]; 1262 __IOM uint32_t PIDR_0; /*!< (@ 0x00000FE0) Coresight peripheral identification registers. */ 1263 __IOM uint32_t PIDR_1; /*!< (@ 0x00000FE4) Coresight peripheral identification registers. */ 1264 __IOM uint32_t PIDR_2; /*!< (@ 0x00000FE8) Coresight peripheral identification registers. */ 1265 __IOM uint32_t PIDR_3; /*!< (@ 0x00000FEC) Coresight peripheral identification registers. */ 1266 __IOM uint32_t CIDR_0; /*!< (@ 0x00000FF0) Coresight component identification registers. */ 1267 __IOM uint32_t CIDR_1; /*!< (@ 0x00000FF4) Coresight component identification registers. */ 1268 __IOM uint32_t CIDR_2; /*!< (@ 0x00000FF8) Coresight component identification registers. */ 1269 __IOM uint32_t CIDR_3; /*!< (@ 0x00000FFC) Coresight component identification registers. */ 1270 } NRF_ATBREPLICATOR_Type; /*!< Size = 4096 (0x1000) */ 1271 1272 1273 1274 /* =========================================================================================================================== */ 1275 /* ================ ATBFUNNEL1_NS ================ */ 1276 /* =========================================================================================================================== */ 1277 1278 1279 /** 1280 * @brief ATB funnel module 0 (ATBFUNNEL1_NS) 1281 */ 1282 1283 typedef struct { /*!< (@ 0xE005A000) ATBFUNNEL1_NS Structure */ 1284 __IOM uint32_t CTRLREG; /*!< (@ 0x00000000) The IDFILTER0 register enables the programming 1285 of ID filtering for master port 0. */ 1286 __IOM uint32_t PRIORITYCTRLREG; /*!< (@ 0x00000004) The Priority_Ctrl_Reg register defines the order 1287 in which inputs are selected. Each 3-bit 1288 field is a priority for each particular 1289 slave interface. */ 1290 __IM uint32_t RESERVED[953]; 1291 __IOM uint32_t ITATBDATA0; /*!< (@ 0x00000EEC) The ITATBDATA0 register performs different functions 1292 depending on whether the access is a read 1293 or a write. */ 1294 __IOM uint32_t ITATBCTR2; /*!< (@ 0x00000EF0) The ITATBCTR2 register performs different functions 1295 depending on whether the access is a read 1296 or a write. */ 1297 __IOM uint32_t ITATBCTR1; /*!< (@ 0x00000EF4) The ITATBCTR1 register performs different functions 1298 depending on whether the access is a read 1299 or a write. */ 1300 __IOM uint32_t ITATBCTR0; /*!< (@ 0x00000EF8) The ITATBCTR0 register performs different functions 1301 depending on whether the access is a read 1302 or a write. */ 1303 __IM uint32_t RESERVED1; 1304 __IOM uint32_t ITCTRL; /*!< (@ 0x00000F00) The ITCTRL register enables the component to 1305 switch from a functional mode, which is 1306 the default behavior, to integration mode 1307 where the inputs and outputs of the component 1308 can be directly controlled for the purposes 1309 of integration testing and topology detection. */ 1310 __IM uint32_t RESERVED2[39]; 1311 __IOM uint32_t CLAIMSET; /*!< (@ 0x00000FA0) Software can use the claim tag to coordinate 1312 application and debugger access to trace 1313 unit functionality. The claim tags have 1314 no effect on the operation of the component. 1315 The CLAIMSET register sets bits in the claim 1316 tag, and determines the number of claim 1317 bits implemented. */ 1318 __IOM uint32_t CLAIMCLR; /*!< (@ 0x00000FA4) Software can use the claim tag to coordinate 1319 application and debugger access to trace 1320 unit functionality. The claim tags have 1321 no effect on the operation of the component. 1322 The CLAIMCLR register sets the bits in the 1323 claim tag to 0 and determines the current 1324 value of the claim tag. */ 1325 __IM uint32_t RESERVED3[2]; 1326 __IOM uint32_t LAR; /*!< (@ 0x00000FB0) This is used to enable write access to device 1327 registers. */ 1328 __IOM uint32_t LSR; /*!< (@ 0x00000FB4) This indicates the status of the lock control 1329 mechanism. This lock prevents accidental 1330 writes by code under debug. Accesses to 1331 the extended stimulus port registers are 1332 not affected by the lock mechanism. This 1333 register must always be present although 1334 there might not be any lock access control 1335 mechanism. The lock mechanism, where present 1336 and locked, must block write accesses to 1337 any control register, except the Lock Access 1338 Register. For most components this cover */ 1339 __IOM uint32_t AUTHSTATUS; /*!< (@ 0x00000FB8) Indicates the current level of tracing permitted 1340 by the system */ 1341 __IM uint32_t RESERVED4[3]; 1342 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Indicates the capabilities of the component. */ 1343 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) The DEVTYPE register provides a debugger with 1344 information about the component when the 1345 Part Number field is not recognized. The 1346 debugger can then report this information. */ 1347 __IOM uint32_t PIDR4; /*!< (@ 0x00000FD0) Coresight peripheral identification registers. */ 1348 __IM uint32_t RESERVED5[3]; 1349 __IOM uint32_t PIDR_0; /*!< (@ 0x00000FE0) Coresight peripheral identification registers. */ 1350 __IOM uint32_t PIDR_1; /*!< (@ 0x00000FE4) Coresight peripheral identification registers. */ 1351 __IOM uint32_t PIDR_2; /*!< (@ 0x00000FE8) Coresight peripheral identification registers. */ 1352 __IOM uint32_t PIDR_3; /*!< (@ 0x00000FEC) Coresight peripheral identification registers. */ 1353 __IOM uint32_t CIDR_0; /*!< (@ 0x00000FF0) Coresight component identification registers. */ 1354 __IOM uint32_t CIDR_1; /*!< (@ 0x00000FF4) Coresight component identification registers. */ 1355 __IOM uint32_t CIDR_2; /*!< (@ 0x00000FF8) Coresight component identification registers. */ 1356 __IOM uint32_t CIDR_3; /*!< (@ 0x00000FFC) Coresight component identification registers. */ 1357 } NRF_ATBFUNNEL_Type; /*!< Size = 4096 (0x1000) */ 1358 1359 1360 1361 /* =========================================================================================================================== */ 1362 /* ================ TAD_S ================ */ 1363 /* =========================================================================================================================== */ 1364 1365 1366 /** 1367 * @brief Trace and debug control (TAD_S) 1368 */ 1369 1370 typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ 1371 __OM uint32_t TASKS_CLOCKSTART; /*!< (@ 0x00000000) Start all trace and debug clocks. */ 1372 __OM uint32_t TASKS_CLOCKSTOP; /*!< (@ 0x00000004) Stop all trace and debug clocks. */ 1373 __IM uint32_t RESERVED[318]; 1374 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ 1375 __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ 1376 __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface 1377 Reset behavior is the same as debug components */ 1378 } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ 1379 1380 1381 1382 /* =========================================================================================================================== */ 1383 /* ================ SPU_S ================ */ 1384 /* =========================================================================================================================== */ 1385 1386 1387 /** 1388 * @brief System protection unit (SPU_S) 1389 */ 1390 1391 typedef struct { /*!< (@ 0x50003000) SPU_S Structure */ 1392 __IM uint32_t RESERVED[64]; 1393 __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the 1394 RAM memory space */ 1395 __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the 1396 flash memory space */ 1397 __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one 1398 or several peripherals */ 1399 __IM uint32_t RESERVED1[29]; 1400 __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */ 1401 __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */ 1402 __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */ 1403 __IM uint32_t RESERVED2[93]; 1404 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1405 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1406 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1407 __IM uint32_t RESERVED3[61]; 1408 __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */ 1409 __IM uint32_t RESERVED4[15]; 1410 __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */ 1411 __IM uint32_t RESERVED5[15]; 1412 __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */ 1413 __IM uint32_t RESERVED6[14]; 1414 __IOM SPU_GPIOPORT_Type GPIOPORT[1]; /*!< (@ 0x000004C0) Unspecified */ 1415 __IM uint32_t RESERVED7[14]; 1416 __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */ 1417 __IM uint32_t RESERVED8[12]; 1418 __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */ 1419 __IM uint32_t RESERVED9[44]; 1420 __IOM SPU_FLASHREGION_Type FLASHREGION[32]; /*!< (@ 0x00000600) Unspecified */ 1421 __IM uint32_t RESERVED10[32]; 1422 __IOM SPU_RAMREGION_Type RAMREGION[32]; /*!< (@ 0x00000700) Unspecified */ 1423 __IM uint32_t RESERVED11[32]; 1424 __IOM SPU_PERIPHID_Type PERIPHID[67]; /*!< (@ 0x00000800) Unspecified */ 1425 } NRF_SPU_Type; /*!< Size = 2316 (0x90c) */ 1426 1427 1428 1429 /* =========================================================================================================================== */ 1430 /* ================ REGULATORS_NS ================ */ 1431 /* =========================================================================================================================== */ 1432 1433 1434 /** 1435 * @brief Voltage regulators control 0 (REGULATORS_NS) 1436 */ 1437 1438 typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ 1439 __IM uint32_t RESERVED[320]; 1440 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 1441 __IM uint32_t RESERVED1[4]; 1442 __IOM uint32_t EXTPOFCON; /*!< (@ 0x00000514) External power failure warning configuration */ 1443 __IM uint32_t RESERVED2[24]; 1444 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable a step-down DC/DC voltage regulator. */ 1445 } NRF_REGULATORS_Type; /*!< Size = 1404 (0x57c) */ 1446 1447 1448 1449 /* =========================================================================================================================== */ 1450 /* ================ CLOCK_NS ================ */ 1451 /* =========================================================================================================================== */ 1452 1453 1454 /** 1455 * @brief Clock management 0 (CLOCK_NS) 1456 */ 1457 1458 typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 1459 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK source */ 1460 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK source */ 1461 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 1462 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 1463 __IM uint32_t RESERVED[28]; 1464 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 1465 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 1466 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 1467 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 1468 __IM uint32_t RESERVED1[28]; 1469 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 1470 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 1471 __IM uint32_t RESERVED2[30]; 1472 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 1473 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 1474 __IM uint32_t RESERVED3[94]; 1475 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1476 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1477 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1478 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1479 __IM uint32_t RESERVED4[62]; 1480 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 1481 triggered */ 1482 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) The register shows if HFXO has been requested 1483 by triggering HFCLKSTART task and if it 1484 has been started (STATE). */ 1485 __IM uint32_t RESERVED5; 1486 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 1487 triggered */ 1488 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) The register shows which LFCLK source has been 1489 requested (SRC) when triggering LFCLKSTART 1490 task and if the source has been started 1491 (STATE). */ 1492 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set after LFCLKSTART 1493 task has been triggered */ 1494 __IM uint32_t RESERVED6[62]; 1495 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK. LFCLKSTART task starts 1496 a clock source selected with this register. */ 1497 } NRF_CLOCK_Type; /*!< Size = 1308 (0x51c) */ 1498 1499 1500 1501 /* =========================================================================================================================== */ 1502 /* ================ POWER_NS ================ */ 1503 /* =========================================================================================================================== */ 1504 1505 1506 /** 1507 * @brief Power control 0 (POWER_NS) 1508 */ 1509 1510 typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 1511 __IM uint32_t RESERVED[30]; 1512 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ 1513 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 1514 __IM uint32_t RESERVED1[30]; 1515 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 1516 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 1517 __IM uint32_t RESERVED2[2]; 1518 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 1519 __IM uint32_t RESERVED3[2]; 1520 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1521 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1522 __IM uint32_t RESERVED4[27]; 1523 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 1524 __IM uint32_t RESERVED5[2]; 1525 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 1526 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 1527 __IM uint32_t RESERVED6[89]; 1528 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1529 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1530 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1531 __IM uint32_t RESERVED7[61]; 1532 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1533 __IM uint32_t RESERVED8[15]; 1534 __IM uint32_t POWERSTATUS; /*!< (@ 0x00000440) Modem domain power status */ 1535 __IM uint32_t RESERVED9[54]; 1536 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 1537 register */ 1538 __IM uint32_t RESERVED10[59]; 1539 __IOM POWER_LTEMODEM_Type LTEMODEM; /*!< (@ 0x00000610) LTE Modem */ 1540 } NRF_POWER_Type; /*!< Size = 1560 (0x618) */ 1541 1542 1543 1544 /* =========================================================================================================================== */ 1545 /* ================ CTRL_AP_PERI_S ================ */ 1546 /* =========================================================================================================================== */ 1547 1548 1549 /** 1550 * @brief Control access port (CTRL_AP_PERI_S) 1551 */ 1552 1553 typedef struct { /*!< (@ 0x50006000) CTRL_AP_PERI_S Structure */ 1554 __IM uint32_t RESERVED[256]; 1555 __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 1556 __IM uint32_t RESERVED1[30]; 1557 __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 1558 } NRF_CTRLAPPERI_Type; /*!< Size = 1288 (0x508) */ 1559 1560 1561 1562 /* =========================================================================================================================== */ 1563 /* ================ SPIM0_NS ================ */ 1564 /* =========================================================================================================================== */ 1565 1566 1567 /** 1568 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) 1569 */ 1570 1571 typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */ 1572 __IM uint32_t RESERVED[4]; 1573 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1574 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1575 __IM uint32_t RESERVED1; 1576 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1577 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1578 __IM uint32_t RESERVED2[27]; 1579 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 1580 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1581 __IM uint32_t RESERVED3; 1582 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1583 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1584 __IM uint32_t RESERVED4[24]; 1585 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1586 __IM uint32_t RESERVED5[2]; 1587 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1588 __IM uint32_t RESERVED6; 1589 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1590 __IM uint32_t RESERVED7; 1591 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1592 __IM uint32_t RESERVED8[10]; 1593 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1594 __IM uint32_t RESERVED9[13]; 1595 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1596 __IM uint32_t RESERVED10[2]; 1597 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1598 __IM uint32_t RESERVED11; 1599 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 1600 __IM uint32_t RESERVED12; 1601 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1602 __IM uint32_t RESERVED13[10]; 1603 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 1604 __IM uint32_t RESERVED14[12]; 1605 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1606 __IM uint32_t RESERVED15[64]; 1607 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1608 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1609 __IM uint32_t RESERVED16[125]; 1610 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1611 __IM uint32_t RESERVED17; 1612 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1613 __IM uint32_t RESERVED18[4]; 1614 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1615 source selected. */ 1616 __IM uint32_t RESERVED19[3]; 1617 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1618 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1619 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1620 __IM uint32_t RESERVED20[26]; 1621 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1622 case an over-read of the TXD buffer. */ 1623 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1624 1625 1626 1627 /* =========================================================================================================================== */ 1628 /* ================ SPIS0_NS ================ */ 1629 /* =========================================================================================================================== */ 1630 1631 1632 /** 1633 * @brief SPI Slave 0 (SPIS0_NS) 1634 */ 1635 1636 typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */ 1637 __IM uint32_t RESERVED[9]; 1638 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1639 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1640 to acquire it */ 1641 __IM uint32_t RESERVED1[30]; 1642 __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1643 __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1644 __IM uint32_t RESERVED2[22]; 1645 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1646 __IM uint32_t RESERVED3[2]; 1647 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1648 __IM uint32_t RESERVED4[5]; 1649 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1650 __IM uint32_t RESERVED5[22]; 1651 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1652 __IM uint32_t RESERVED6[2]; 1653 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1654 __IM uint32_t RESERVED7[5]; 1655 __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1656 __IM uint32_t RESERVED8[21]; 1657 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1658 __IM uint32_t RESERVED9[64]; 1659 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1660 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1661 __IM uint32_t RESERVED10[61]; 1662 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1663 __IM uint32_t RESERVED11[15]; 1664 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1665 __IM uint32_t RESERVED12[47]; 1666 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1667 __IM uint32_t RESERVED13; 1668 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1669 __IM uint32_t RESERVED14[7]; 1670 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1671 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1672 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1673 __IM uint32_t RESERVED15; 1674 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1675 of an ignored transaction. */ 1676 __IM uint32_t RESERVED16[24]; 1677 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1678 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1679 1680 1681 1682 /* =========================================================================================================================== */ 1683 /* ================ TWIM0_NS ================ */ 1684 /* =========================================================================================================================== */ 1685 1686 1687 /** 1688 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS) 1689 */ 1690 1691 typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */ 1692 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1693 __IM uint32_t RESERVED; 1694 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1695 __IM uint32_t RESERVED1[2]; 1696 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1697 TWI master is not suspended. */ 1698 __IM uint32_t RESERVED2; 1699 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1700 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1701 __IM uint32_t RESERVED3[23]; 1702 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1703 __IM uint32_t RESERVED4; 1704 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1705 __IM uint32_t RESERVED5[2]; 1706 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1707 __IM uint32_t RESERVED6; 1708 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1709 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1710 __IM uint32_t RESERVED7[24]; 1711 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1712 __IM uint32_t RESERVED8[7]; 1713 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1714 __IM uint32_t RESERVED9[8]; 1715 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1716 now suspended. */ 1717 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1718 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1719 __IM uint32_t RESERVED10[2]; 1720 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1721 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1722 byte */ 1723 __IM uint32_t RESERVED11[8]; 1724 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1725 __IM uint32_t RESERVED12[7]; 1726 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1727 __IM uint32_t RESERVED13[8]; 1728 __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1729 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1730 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1731 __IM uint32_t RESERVED14[2]; 1732 __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1733 __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1734 __IM uint32_t RESERVED15[7]; 1735 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1736 __IM uint32_t RESERVED16[63]; 1737 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1738 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1739 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1740 __IM uint32_t RESERVED17[110]; 1741 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1742 __IM uint32_t RESERVED18[14]; 1743 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1744 __IM uint32_t RESERVED19; 1745 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1746 __IM uint32_t RESERVED20[5]; 1747 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1748 source selected. */ 1749 __IM uint32_t RESERVED21[3]; 1750 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1751 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1752 __IM uint32_t RESERVED22[13]; 1753 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1754 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1755 1756 1757 1758 /* =========================================================================================================================== */ 1759 /* ================ TWIS0_NS ================ */ 1760 /* =========================================================================================================================== */ 1761 1762 1763 /** 1764 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS) 1765 */ 1766 1767 typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */ 1768 __IM uint32_t RESERVED[5]; 1769 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1770 __IM uint32_t RESERVED1; 1771 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1772 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1773 __IM uint32_t RESERVED2[3]; 1774 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1775 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1776 __IM uint32_t RESERVED3[23]; 1777 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1778 __IM uint32_t RESERVED4; 1779 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1780 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1781 __IM uint32_t RESERVED5[3]; 1782 __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1783 __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1784 __IM uint32_t RESERVED6[19]; 1785 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1786 __IM uint32_t RESERVED7[7]; 1787 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1788 __IM uint32_t RESERVED8[9]; 1789 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1790 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1791 __IM uint32_t RESERVED9[4]; 1792 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1793 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1794 __IM uint32_t RESERVED10[6]; 1795 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1796 __IM uint32_t RESERVED11[7]; 1797 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1798 __IM uint32_t RESERVED12[9]; 1799 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1800 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1801 __IM uint32_t RESERVED13[4]; 1802 __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1803 __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1804 __IM uint32_t RESERVED14[5]; 1805 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1806 __IM uint32_t RESERVED15[63]; 1807 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1808 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1809 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1810 __IM uint32_t RESERVED16[113]; 1811 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1812 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1813 a match */ 1814 __IM uint32_t RESERVED17[10]; 1815 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1816 __IM uint32_t RESERVED18; 1817 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1818 __IM uint32_t RESERVED19[9]; 1819 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1820 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1821 __IM uint32_t RESERVED20[13]; 1822 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1823 __IM uint32_t RESERVED21; 1824 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1825 mechanism */ 1826 __IM uint32_t RESERVED22[10]; 1827 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1828 of an over-read of the transmit buffer. */ 1829 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1830 1831 1832 1833 /* =========================================================================================================================== */ 1834 /* ================ UARTE0_NS ================ */ 1835 /* =========================================================================================================================== */ 1836 1837 1838 /** 1839 * @brief UART with EasyDMA 0 (UARTE0_NS) 1840 */ 1841 1842 typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ 1843 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1844 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1845 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1846 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1847 __IM uint32_t RESERVED[7]; 1848 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1849 __IM uint32_t RESERVED1[20]; 1850 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1851 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1852 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1853 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1854 __IM uint32_t RESERVED2[7]; 1855 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1856 __IM uint32_t RESERVED3[20]; 1857 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1858 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1859 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1860 transferred to Data RAM) */ 1861 __IM uint32_t RESERVED4; 1862 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1863 __IM uint32_t RESERVED5[2]; 1864 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1865 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1866 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1867 __IM uint32_t RESERVED6[7]; 1868 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1869 __IM uint32_t RESERVED7; 1870 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1871 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1872 __IM uint32_t RESERVED8; 1873 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1874 __IM uint32_t RESERVED9[9]; 1875 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1876 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1877 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1878 __IM uint32_t RESERVED10; 1879 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1880 __IM uint32_t RESERVED11[2]; 1881 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1882 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1883 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1884 __IM uint32_t RESERVED12[7]; 1885 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1886 __IM uint32_t RESERVED13; 1887 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1888 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1889 __IM uint32_t RESERVED14; 1890 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1891 __IM uint32_t RESERVED15[9]; 1892 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1893 __IM uint32_t RESERVED16[63]; 1894 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1895 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1896 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1897 __IM uint32_t RESERVED17[93]; 1898 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one 1899 to clear. */ 1900 __IM uint32_t RESERVED18[31]; 1901 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1902 __IM uint32_t RESERVED19; 1903 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1904 __IM uint32_t RESERVED20[3]; 1905 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1906 selected. */ 1907 __IM uint32_t RESERVED21[3]; 1908 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1909 __IM uint32_t RESERVED22; 1910 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1911 __IM uint32_t RESERVED23[7]; 1912 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1913 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1914 1915 1916 1917 /* =========================================================================================================================== */ 1918 /* ================ GPIOTE0_S ================ */ 1919 /* =========================================================================================================================== */ 1920 1921 1922 /** 1923 * @brief GPIO Tasks and Events 0 (GPIOTE0_S) 1924 */ 1925 1926 typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */ 1927 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1928 specified in CONFIG[n].PSEL. Action on pin 1929 is configured in CONFIG[n].POLARITY. */ 1930 __IM uint32_t RESERVED[4]; 1931 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1932 specified in CONFIG[n].PSEL. Action on pin 1933 is to set it high. */ 1934 __IM uint32_t RESERVED1[4]; 1935 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1936 specified in CONFIG[n].PSEL. Action on pin 1937 is to set it low. */ 1938 __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1939 for task OUT[n] */ 1940 __IM uint32_t RESERVED2[4]; 1941 __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 1942 for task SET[n] */ 1943 __IM uint32_t RESERVED3[4]; 1944 __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 1945 for task CLR[n] */ 1946 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1947 pin specified in CONFIG[n].PSEL */ 1948 __IM uint32_t RESERVED4[23]; 1949 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1950 with SENSE mechanism enabled */ 1951 __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 1952 for event IN[n] */ 1953 __IM uint32_t RESERVED5[23]; 1954 __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 1955 __IM uint32_t RESERVED6[65]; 1956 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1957 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1958 __IM uint32_t RESERVED7[129]; 1959 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1960 SET[n], and CLR[n] tasks and IN[n] event */ 1961 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1962 1963 1964 1965 /* =========================================================================================================================== */ 1966 /* ================ SAADC_NS ================ */ 1967 /* =========================================================================================================================== */ 1968 1969 1970 /** 1971 * @brief Analog to Digital Converter 0 (SAADC_NS) 1972 */ 1973 1974 typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */ 1975 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1976 RAM */ 1977 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1978 are sampled */ 1979 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1980 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1981 __IM uint32_t RESERVED[28]; 1982 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 1983 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ 1984 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 1985 __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ 1986 __IM uint32_t RESERVED1[28]; 1987 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1988 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1989 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1990 on the mode, multiple conversions might 1991 be needed for a result to be transferred 1992 to RAM. */ 1993 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1994 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1995 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1996 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1997 __IM uint32_t RESERVED2[10]; 1998 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 1999 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 2000 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ 2001 __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ 2002 __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ 2003 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ 2004 __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ 2005 __IM uint32_t RESERVED3[74]; 2006 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2007 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2008 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2009 __IM uint32_t RESERVED4[61]; 2010 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 2011 __IM uint32_t RESERVED5[63]; 2012 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 2013 __IM uint32_t RESERVED6[3]; 2014 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 2015 __IM uint32_t RESERVED7[24]; 2016 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 2017 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 2018 not be combined with SCAN. The RESOLUTION 2019 is applied before averaging, thus for high 2020 OVERSAMPLE a higher RESOLUTION should be 2021 used. */ 2022 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 2023 __IM uint32_t RESERVED8[12]; 2024 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 2025 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 2026 2027 2028 2029 /* =========================================================================================================================== */ 2030 /* ================ TIMER0_NS ================ */ 2031 /* =========================================================================================================================== */ 2032 2033 2034 /** 2035 * @brief Timer/Counter 0 (TIMER0_NS) 2036 */ 2037 2038 typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */ 2039 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 2040 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 2041 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 2042 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 2043 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 2044 __IM uint32_t RESERVED[11]; 2045 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 2046 CC[n] register */ 2047 __IM uint32_t RESERVED1[10]; 2048 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2049 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2050 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 2051 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 2052 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 2053 for task SHUTDOWN */ 2054 __IM uint32_t RESERVED2[11]; 2055 __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 2056 for task CAPTURE[n] */ 2057 __IM uint32_t RESERVED3[26]; 2058 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 2059 match */ 2060 __IM uint32_t RESERVED4[26]; 2061 __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration 2062 for event COMPARE[n] */ 2063 __IM uint32_t RESERVED5[10]; 2064 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2065 __IM uint32_t RESERVED6[64]; 2066 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2067 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2068 __IM uint32_t RESERVED7[126]; 2069 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 2070 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 2071 __IM uint32_t RESERVED8; 2072 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 2073 __IOM uint32_t ONESHOTEN[6]; /*!< (@ 0x00000514) Description collection: Enable one-shot operation 2074 for Capture/Compare channel n */ 2075 __IM uint32_t RESERVED9[5]; 2076 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 2077 n */ 2078 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 2079 2080 2081 2082 /* =========================================================================================================================== */ 2083 /* ================ RTC0_NS ================ */ 2084 /* =========================================================================================================================== */ 2085 2086 2087 /** 2088 * @brief Real-time counter 0 (RTC0_NS) 2089 */ 2090 2091 typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */ 2092 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 2093 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 2094 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 2095 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 2096 __IM uint32_t RESERVED[28]; 2097 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2098 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2099 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 2100 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 2101 __IM uint32_t RESERVED1[28]; 2102 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 2103 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 2104 __IM uint32_t RESERVED2[14]; 2105 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 2106 match */ 2107 __IM uint32_t RESERVED3[12]; 2108 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 2109 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 2110 __IM uint32_t RESERVED4[14]; 2111 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 2112 for event COMPARE[n] */ 2113 __IM uint32_t RESERVED5[77]; 2114 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2115 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2116 __IM uint32_t RESERVED6[13]; 2117 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 2118 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 2119 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 2120 __IM uint32_t RESERVED7[110]; 2121 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 2122 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). 2123 Must be written when RTC is stopped. */ 2124 __IM uint32_t RESERVED8[13]; 2125 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 2126 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 2127 2128 2129 2130 /* =========================================================================================================================== */ 2131 /* ================ DPPIC_NS ================ */ 2132 /* =========================================================================================================================== */ 2133 2134 2135 /** 2136 * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS) 2137 */ 2138 2139 typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ 2140 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2141 __IM uint32_t RESERVED[20]; 2142 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 2143 __IM uint32_t RESERVED1[276]; 2144 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2145 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2146 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2147 __IM uint32_t RESERVED2[189]; 2148 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 2149 Writes to this register are ignored if either 2150 SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS 2151 is enabled */ 2152 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 2153 2154 2155 2156 /* =========================================================================================================================== */ 2157 /* ================ WDT_NS ================ */ 2158 /* =========================================================================================================================== */ 2159 2160 2161 /** 2162 * @brief Watchdog Timer 0 (WDT_NS) 2163 */ 2164 2165 typedef struct { /*!< (@ 0x40018000) WDT_NS Structure */ 2166 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 2167 __IM uint32_t RESERVED[31]; 2168 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2169 __IM uint32_t RESERVED1[31]; 2170 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 2171 __IM uint32_t RESERVED2[31]; 2172 __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 2173 __IM uint32_t RESERVED3[96]; 2174 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2175 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2176 __IM uint32_t RESERVED4[61]; 2177 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 2178 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 2179 __IM uint32_t RESERVED5[63]; 2180 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 2181 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 2182 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 2183 __IM uint32_t RESERVED6[60]; 2184 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 2185 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 2186 2187 2188 2189 /* =========================================================================================================================== */ 2190 /* ================ EGU0_NS ================ */ 2191 /* =========================================================================================================================== */ 2192 2193 2194 /** 2195 * @brief Event generator unit 0 (EGU0_NS) 2196 */ 2197 2198 typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 2199 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 2200 the corresponding TRIGGERED[n] event */ 2201 __IM uint32_t RESERVED[16]; 2202 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 2203 for task TRIGGER[n] */ 2204 __IM uint32_t RESERVED1[16]; 2205 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 2206 by triggering the corresponding TRIGGER[n] 2207 task */ 2208 __IM uint32_t RESERVED2[16]; 2209 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 2210 for event TRIGGERED[n] */ 2211 __IM uint32_t RESERVED3[80]; 2212 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2213 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2214 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2215 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 2216 2217 2218 2219 /* =========================================================================================================================== */ 2220 /* ================ PWM0_NS ================ */ 2221 /* =========================================================================================================================== */ 2222 2223 2224 /** 2225 * @brief Pulse width modulation unit 0 (PWM0_NS) 2226 */ 2227 2228 typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */ 2229 __IM uint32_t RESERVED; 2230 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2231 the end of current PWM period, and stops 2232 sequence playback */ 2233 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 2234 on all enabled channels from sequence n, 2235 and starts playing that sequence at the 2236 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2237 Causes PWM generation to start if not running. */ 2238 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2239 all enabled channels if DECODER.MODE=NextStep. 2240 Does not cause PWM generation to start if 2241 not running. */ 2242 __IM uint32_t RESERVED1[28]; 2243 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2244 __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration 2245 for task SEQSTART[n] */ 2246 __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */ 2247 __IM uint32_t RESERVED2[28]; 2248 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2249 are no longer generated */ 2250 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 2251 on sequence n */ 2252 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 2253 sequence n, when last value from RAM has 2254 been applied to wave counter */ 2255 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2256 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2257 of times defined in LOOP.CNT */ 2258 __IM uint32_t RESERVED3[25]; 2259 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 2260 __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration 2261 for event SEQSTARTED[n] */ 2262 __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration 2263 for event SEQEND[n] */ 2264 __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ 2265 __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ 2266 __IM uint32_t RESERVED4[24]; 2267 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2268 __IM uint32_t RESERVED5[63]; 2269 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2270 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2271 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2272 __IM uint32_t RESERVED6[125]; 2273 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2274 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2275 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2276 counts */ 2277 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2278 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2279 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 2280 __IM uint32_t RESERVED7[2]; 2281 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2282 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2283 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2284 2285 2286 2287 /* =========================================================================================================================== */ 2288 /* ================ PDM_NS ================ */ 2289 /* =========================================================================================================================== */ 2290 2291 2292 /** 2293 * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM_NS) 2294 */ 2295 2296 typedef struct { /*!< (@ 0x40026000) PDM_NS Structure */ 2297 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2298 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2299 __IM uint32_t RESERVED[30]; 2300 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2301 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2302 __IM uint32_t RESERVED1[30]; 2303 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2304 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2305 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2306 by SAMPLE.MAXCNT (or the last sample after 2307 a STOP task has been received) to Data RAM */ 2308 __IM uint32_t RESERVED2[29]; 2309 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 2310 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 2311 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ 2312 __IM uint32_t RESERVED3[93]; 2313 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2314 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2315 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2316 __IM uint32_t RESERVED4[125]; 2317 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2318 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2319 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2320 signals */ 2321 __IM uint32_t RESERVED5[3]; 2322 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2323 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2324 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 2325 sample rate. Change PDMCLKCTRL accordingly. */ 2326 __IM uint32_t RESERVED6[7]; 2327 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2328 __IM uint32_t RESERVED7[6]; 2329 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2330 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2331 2332 2333 2334 /* =========================================================================================================================== */ 2335 /* ================ I2S_NS ================ */ 2336 /* =========================================================================================================================== */ 2337 2338 2339 /** 2340 * @brief Inter-IC Sound 0 (I2S_NS) 2341 */ 2342 2343 typedef struct { /*!< (@ 0x40028000) I2S_NS Structure */ 2344 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2345 generator when this is enabled. */ 2346 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2347 Triggering this task will cause the STOPPED 2348 event to be generated. */ 2349 __IM uint32_t RESERVED[30]; 2350 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2351 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2352 __IM uint32_t RESERVED1[31]; 2353 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2354 double-buffers. When the I2S module is started 2355 and RX is enabled, this event will be generated 2356 for every RXTXD.MAXCNT words that are received 2357 on the SDIN pin. */ 2358 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2359 __IM uint32_t RESERVED2[2]; 2360 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2361 double-buffers. When the I2S module is started 2362 and TX is enabled, this event will be generated 2363 for every RXTXD.MAXCNT words that are sent 2364 on the SDOUT pin. */ 2365 __IM uint32_t RESERVED3[27]; 2366 __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ 2367 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ 2368 __IM uint32_t RESERVED4[2]; 2369 __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ 2370 __IM uint32_t RESERVED5[90]; 2371 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2372 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2373 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2374 __IM uint32_t RESERVED6[125]; 2375 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2376 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2377 __IM uint32_t RESERVED7[3]; 2378 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2379 __IM uint32_t RESERVED8; 2380 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2381 __IM uint32_t RESERVED9[3]; 2382 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2383 __IM uint32_t RESERVED10[3]; 2384 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2385 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2386 2387 2388 2389 /* =========================================================================================================================== */ 2390 /* ================ IPC_NS ================ */ 2391 /* =========================================================================================================================== */ 2392 2393 2394 /** 2395 * @brief Interprocessor communication 0 (IPC_NS) 2396 */ 2397 2398 typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ 2399 __OM uint32_t TASKS_SEND[8]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC 2400 channel enabled in SEND_CNF[n] */ 2401 __IM uint32_t RESERVED[24]; 2402 __IOM uint32_t SUBSCRIBE_SEND[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 2403 for task SEND[n] */ 2404 __IM uint32_t RESERVED1[24]; 2405 __IOM uint32_t EVENTS_RECEIVE[8]; /*!< (@ 0x00000100) Description collection: Event received on one 2406 or more of the enabled IPC channels in RECEIVE_CNF[n] */ 2407 __IM uint32_t RESERVED2[24]; 2408 __IOM uint32_t PUBLISH_RECEIVE[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 2409 for event RECEIVE[n] */ 2410 __IM uint32_t RESERVED3[88]; 2411 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2412 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2413 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2414 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 2415 __IM uint32_t RESERVED4[128]; 2416 __IOM uint32_t SEND_CNF[8]; /*!< (@ 0x00000510) Description collection: Send event configuration 2417 for TASKS_SEND[n] */ 2418 __IM uint32_t RESERVED5[24]; 2419 __IOM uint32_t RECEIVE_CNF[8]; /*!< (@ 0x00000590) Description collection: Receive event configuration 2420 for EVENTS_RECEIVE[n] */ 2421 __IM uint32_t RESERVED6[24]; 2422 __IOM uint32_t GPMEM[4]; /*!< (@ 0x00000610) Description collection: General purpose memory */ 2423 } NRF_IPC_Type; /*!< Size = 1568 (0x620) */ 2424 2425 2426 2427 /* =========================================================================================================================== */ 2428 /* ================ FPU_NS ================ */ 2429 /* =========================================================================================================================== */ 2430 2431 2432 /** 2433 * @brief FPU (FPU_NS) 2434 */ 2435 2436 typedef struct { /*!< (@ 0x4002C000) FPU_NS Structure */ 2437 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2438 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2439 2440 2441 2442 /* =========================================================================================================================== */ 2443 /* ================ KMU_NS ================ */ 2444 /* =========================================================================================================================== */ 2445 2446 2447 /** 2448 * @brief Key management unit 0 (KMU_NS) 2449 */ 2450 2451 typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */ 2452 __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */ 2453 __IM uint32_t RESERVED[63]; 2454 __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key slot successfully pushed over secure APB */ 2455 __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked 2456 for selection */ 2457 __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address 2458 defined, or error during push operation */ 2459 __IM uint32_t RESERVED1[125]; 2460 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2461 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2462 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2463 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 2464 __IM uint32_t RESERVED2[63]; 2465 __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */ 2466 __IM uint32_t RESERVED3[60]; 2467 __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed 2468 over secure APB when TASKS_PUSH_KEYSLOT 2469 is started */ 2470 } NRF_KMU_Type; /*!< Size = 1284 (0x504) */ 2471 2472 2473 2474 /* =========================================================================================================================== */ 2475 /* ================ NVMC_NS ================ */ 2476 /* =========================================================================================================================== */ 2477 2478 2479 /** 2480 * @brief Non-volatile memory controller 0 (NVMC_NS) 2481 */ 2482 2483 typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 2484 __IM uint32_t RESERVED[256]; 2485 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2486 __IM uint32_t RESERVED1; 2487 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 2488 __IM uint32_t RESERVED2[62]; 2489 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2490 __IM uint32_t RESERVED3; 2491 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2492 __IM uint32_t RESERVED4[3]; 2493 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 2494 __IM uint32_t RESERVED5[8]; 2495 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 2496 __IM uint32_t RESERVED6; 2497 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 2498 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 2499 __IM uint32_t RESERVED7[13]; 2500 __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ 2501 __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 2502 } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ 2503 2504 2505 2506 /* =========================================================================================================================== */ 2507 /* ================ VMC_NS ================ */ 2508 /* =========================================================================================================================== */ 2509 2510 2511 /** 2512 * @brief Volatile Memory controller 0 (VMC_NS) 2513 */ 2514 2515 typedef struct { /*!< (@ 0x4003A000) VMC_NS Structure */ 2516 __IM uint32_t RESERVED[384]; 2517 __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */ 2518 } NRF_VMC_Type; /*!< Size = 1664 (0x680) */ 2519 2520 2521 2522 /* =========================================================================================================================== */ 2523 /* ================ CRYPTOCELL_S ================ */ 2524 /* =========================================================================================================================== */ 2525 2526 2527 /** 2528 * @brief CRYPTOCELL register interface (CRYPTOCELL_S) 2529 */ 2530 2531 typedef struct { /*!< (@ 0x50840000) CRYPTOCELL_S Structure */ 2532 __IM uint32_t RESERVED[320]; 2533 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem. */ 2534 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 2535 2536 2537 2538 /* =========================================================================================================================== */ 2539 /* ================ CC_AES_S ================ */ 2540 /* =========================================================================================================================== */ 2541 2542 2543 /** 2544 * @brief CRYPTOCELL AES engine (CC_AES_S) 2545 */ 2546 2547 typedef struct { /*!< (@ 0x50841000) CC_AES_S Structure */ 2548 __IM uint32_t RESERVED[256]; 2549 __OM uint32_t AES_KEY_0[8]; /*!< (@ 0x00000400) Description collection: AES key value to use. 2550 The initial AES_KEY_0[0] register holds 2551 the least significant bits [31:0] of the 2552 key value. */ 2553 __IM uint32_t RESERVED1[8]; 2554 __IOM uint32_t AES_IV_0[4]; /*!< (@ 0x00000440) Description collection: AES Initialization Vector 2555 (IV) to use. The initial AES_IV_0[0] register 2556 holds the least significant bits [31:0] 2557 of the IV. */ 2558 __IM uint32_t RESERVED2[4]; 2559 __IOM uint32_t AES_CTR[4]; /*!< (@ 0x00000460) Description collection: AES counter (CTR) to 2560 use. The initial AES_CTR[0] register holds 2561 the least significant bits [31:0] of the 2562 CTR. */ 2563 __IM uint32_t AES_BUSY; /*!< (@ 0x00000470) Status register for AES engine activity. */ 2564 __IM uint32_t RESERVED3; 2565 __OM uint32_t AES_SK; /*!< (@ 0x00000478) Writing to this address trigger sampling of the 2566 HW key to the AES_KEY_0 register */ 2567 __OM uint32_t AES_CMAC_INIT; /*!< (@ 0x0000047C) Writing to this address triggers the AES engine 2568 to generate K1 and K2 for AES-CMAC operations. */ 2569 __IM uint32_t RESERVED4[15]; 2570 __IOM uint32_t AES_REMAINING_BYTES; /*!< (@ 0x000004BC) This register should be set with the amount of 2571 remaining bytes until the end of the current 2572 AES operation. */ 2573 __IOM uint32_t AES_CONTROL; /*!< (@ 0x000004C0) Control the AES engine behavior. */ 2574 __IM uint32_t RESERVED5; 2575 __IM uint32_t AES_HW_FLAGS; /*!< (@ 0x000004C8) Hardware configuration of the AES engine. Reset 2576 value holds the supported features. */ 2577 __IM uint32_t RESERVED6[3]; 2578 __IOM uint32_t AES_CTR_NO_INCREMENT; /*!< (@ 0x000004D8) This register enables the AES CTR no increment 2579 mode in which the counter mode is not incremented 2580 between two blocks */ 2581 __IM uint32_t RESERVED7[6]; 2582 __OM uint32_t AES_SW_RESET; /*!< (@ 0x000004F4) Reset the AES engine. */ 2583 __IM uint32_t RESERVED8[11]; 2584 __OM uint32_t AES_CMAC_SIZE0_KICK; /*!< (@ 0x00000524) Writing to this address triggers the AES engine 2585 to perform a CMAC operation with size 0. 2586 The CMAC result can be read from the AES_IV_0 2587 register. */ 2588 } NRF_CC_AES_Type; /*!< Size = 1320 (0x528) */ 2589 2590 2591 2592 /* =========================================================================================================================== */ 2593 /* ================ CC_AHB_S ================ */ 2594 /* =========================================================================================================================== */ 2595 2596 2597 /** 2598 * @brief CRYPTOCELL AHB interface (CC_AHB_S) 2599 */ 2600 2601 typedef struct { /*!< (@ 0x50841000) CC_AHB_S Structure */ 2602 __IM uint32_t RESERVED[704]; 2603 __IOM uint32_t AHBM_SINGLES; /*!< (@ 0x00000B00) This register forces the AHB transactions from 2604 CRYPTOCELL master to be always singles. */ 2605 __IOM uint32_t AHBM_HPROT; /*!< (@ 0x00000B04) This register holds the AHB HPROT value */ 2606 __IOM uint32_t AHBM_HMASTLOCK; /*!< (@ 0x00000B08) This register holds AHB HMASTLOCK value */ 2607 __IOM uint32_t AHBM_HNONSEC; /*!< (@ 0x00000B0C) This register holds AHB HNONSEC value */ 2608 } NRF_CC_AHB_Type; /*!< Size = 2832 (0xb10) */ 2609 2610 2611 2612 /* =========================================================================================================================== */ 2613 /* ================ CC_CHACHA_S ================ */ 2614 /* =========================================================================================================================== */ 2615 2616 2617 /** 2618 * @brief CRYPTOCELL CHACHA engine (CC_CHACHA_S) 2619 */ 2620 2621 typedef struct { /*!< (@ 0x50841000) CC_CHACHA_S Structure */ 2622 __IM uint32_t RESERVED[224]; 2623 __IOM uint32_t CHACHA_CONTROL; /*!< (@ 0x00000380) Control the CHACHA engine behavior. */ 2624 __IM uint32_t CHACHA_VERSION; /*!< (@ 0x00000384) CHACHA engine HW version */ 2625 __OM uint32_t CHACHA_KEY[8]; /*!< (@ 0x00000388) Description collection: CHACHA key value to use. 2626 The initial CHACHA_KEY[0] register holds 2627 the least significant bits [31:0] of the 2628 key value. */ 2629 __IOM uint32_t CHACHA_IV[2]; /*!< (@ 0x000003A8) Description collection: CHACHA Initialization 2630 Vector (IV) to use. The IV is also known 2631 as the nonce. */ 2632 __IM uint32_t CHACHA_BUSY; /*!< (@ 0x000003B0) Status register for CHACHA engine activity. */ 2633 __IM uint32_t CHACHA_HW_FLAGS; /*!< (@ 0x000003B4) Hardware configuration of the CHACHA engine. 2634 Reset value holds the supported features. */ 2635 __IOM uint32_t CHACHA_BLOCK_CNT_LSB; /*!< (@ 0x000003B8) Store the LSB value of the block counter, in 2636 order to support suspend/resume of operation */ 2637 __IOM uint32_t CHACHA_BLOCK_CNT_MSB; /*!< (@ 0x000003BC) Store the MSB value of the block counter, in 2638 order to support suspend/resume of operation */ 2639 __OM uint32_t CHACHA_SW_RESET; /*!< (@ 0x000003C0) Reset the CHACHA engine. */ 2640 __IM uint32_t CHACHA_POLY1305_KEY[8]; /*!< (@ 0x000003C4) Description collection: The auto-generated key 2641 to use in Poly1305 MAC calculation. The 2642 initial CHACHA_POLY1305_KEY[0] register 2643 holds the least significant bits [31:0] 2644 of the key value. */ 2645 __IOM uint32_t CHACHA_ENDIANNESS; /*!< (@ 0x000003E4) CHACHA engine data order configuration. */ 2646 __IM uint32_t CHACHA_DEBUG; /*!< (@ 0x000003E8) Debug register for the CHACHA engine */ 2647 } NRF_CC_CHACHA_Type; /*!< Size = 1004 (0x3ec) */ 2648 2649 2650 2651 /* =========================================================================================================================== */ 2652 /* ================ CC_CTL_S ================ */ 2653 /* =========================================================================================================================== */ 2654 2655 2656 /** 2657 * @brief CRYPTOCELL CTL interface (CC_CTL_S) 2658 */ 2659 2660 typedef struct { /*!< (@ 0x50841000) CC_CTL_S Structure */ 2661 __IM uint32_t RESERVED[576]; 2662 __OM uint32_t CRYPTO_CTL; /*!< (@ 0x00000900) Defines the cryptographic flow. */ 2663 __IM uint32_t RESERVED1[3]; 2664 __IM uint32_t CRYPTO_BUSY; /*!< (@ 0x00000910) Status register for cryptographic cores engine 2665 activity. */ 2666 __IM uint32_t RESERVED2[2]; 2667 __IM uint32_t HASH_BUSY; /*!< (@ 0x0000091C) Status register for HASH engine activity. */ 2668 __IM uint32_t RESERVED3[4]; 2669 __IOM uint32_t CONTEXT_ID; /*!< (@ 0x00000930) A general-purpose read/write register. */ 2670 } NRF_CC_CTL_Type; /*!< Size = 2356 (0x934) */ 2671 2672 2673 2674 /* =========================================================================================================================== */ 2675 /* ================ CC_DIN_S ================ */ 2676 /* =========================================================================================================================== */ 2677 2678 2679 /** 2680 * @brief CRYPTOCELL Data IN interface (CC_DIN_S) 2681 */ 2682 2683 typedef struct { /*!< (@ 0x50841000) CC_DIN_S Structure */ 2684 __IM uint32_t RESERVED[768]; 2685 __OM uint32_t DIN_BUFFER; /*!< (@ 0x00000C00) Used by CPU to write data directly to the DIN 2686 buffer, which is then sent to the cryptographic 2687 engines for processing. */ 2688 __IM uint32_t RESERVED1[7]; 2689 __IM uint32_t DIN_DMA_MEM_BUSY; /*!< (@ 0x00000C20) Status register for DIN DMA engine activity when 2690 accessing memory. */ 2691 __IM uint32_t RESERVED2; 2692 __OM uint32_t SRC_MEM_ADDR; /*!< (@ 0x00000C28) Data source address in memory. */ 2693 __OM uint32_t SRC_MEM_SIZE; /*!< (@ 0x00000C2C) The number of bytes to be read from memory. Writing 2694 to this register triggers the DMA operation. */ 2695 __IOM uint32_t SRC_SRAM_ADDR; /*!< (@ 0x00000C30) Data source address in RNG SRAM. */ 2696 __OM uint32_t SRC_SRAM_SIZE; /*!< (@ 0x00000C34) The number of bytes to be read from RNG SRAM. 2697 Writing to this register triggers the DMA 2698 operation. */ 2699 __IM uint32_t DIN_DMA_SRAM_BUSY; /*!< (@ 0x00000C38) Status register for DIN DMA engine activity when 2700 accessing RNG SRAM. */ 2701 __IOM uint32_t DIN_DMA_SRAM_ENDIANNESS; /*!< (@ 0x00000C3C) Configure the endianness of DIN DMA transactions 2702 towards RNG SRAM. */ 2703 __IM uint32_t RESERVED3; 2704 __OM uint32_t DIN_SW_RESET; /*!< (@ 0x00000C44) Reset the DIN DMA engine. */ 2705 __OM uint32_t DIN_CPU_DATA; /*!< (@ 0x00000C48) Specifies the number of bytes the CPU will write 2706 to the DIN_BUFFER, ensuring the cryptographic 2707 engine processes the correct amount of data. */ 2708 __OM uint32_t DIN_WRITE_ALIGN; /*!< (@ 0x00000C4C) Indicates that the next CPU write to the DIN_BUFFER 2709 is the last in the sequence. This is needed 2710 only when the data size is NOT modulo 4 2711 (e.g. HASH padding). */ 2712 __IM uint32_t DIN_FIFO_EMPTY; /*!< (@ 0x00000C50) Register indicating if DIN FIFO is empty and 2713 if more data can be accepted. */ 2714 __IM uint32_t RESERVED4; 2715 __OM uint32_t DIN_FIFO_RESET; /*!< (@ 0x00000C58) Reset the DIN FIFO, effectively clearing the 2716 FIFO for new data. */ 2717 } NRF_CC_DIN_Type; /*!< Size = 3164 (0xc5c) */ 2718 2719 2720 2721 /* =========================================================================================================================== */ 2722 /* ================ CC_DOUT_S ================ */ 2723 /* =========================================================================================================================== */ 2724 2725 2726 /** 2727 * @brief CRYPTOCELL Data OUT interface (CC_DOUT_S) 2728 */ 2729 2730 typedef struct { /*!< (@ 0x50841000) CC_DOUT_S Structure */ 2731 __IM uint32_t RESERVED[768]; 2732 __IM uint32_t DOUT_BUFFER; /*!< (@ 0x00000C00) Cryptographic results directly accessible by 2733 the CPU. */ 2734 __IM uint32_t RESERVED1[71]; 2735 __IM uint32_t DOUT_DMA_MEM_BUSY; /*!< (@ 0x00000D20) Status register for DOUT DMA engine activity 2736 when accessing memory. */ 2737 __IM uint32_t RESERVED2; 2738 __OM uint32_t DST_MEM_ADDR; /*!< (@ 0x00000D28) Data destination address in memory. */ 2739 __OM uint32_t DST_MEM_SIZE; /*!< (@ 0x00000D2C) The number of bytes to be written to memory. */ 2740 __IOM uint32_t DST_SRAM_ADDR; /*!< (@ 0x00000D30) Data destination address in RNG SRAM. */ 2741 __OM uint32_t DST_SRAM_SIZE; /*!< (@ 0x00000D34) The number of bytes to be written to RNG SRAM. */ 2742 __IM uint32_t DOUT_DMA_SRAM_BUSY; /*!< (@ 0x00000D38) Status register for DOUT DMA engine activity 2743 when accessing RNG SRAM. */ 2744 __IOM uint32_t DOUT_DMA_SRAM_ENDIANNESS; /*!< (@ 0x00000D3C) Configure the endianness of DOUT DMA transactions 2745 towards RNG SRAM. */ 2746 __IM uint32_t RESERVED3; 2747 __OM uint32_t DOUT_READ_ALIGN; /*!< (@ 0x00000D44) Indication that the next CPU read from the DOUT_BUFFER 2748 is the last in the sequence. This is needed 2749 only when the data size is NOT modulo 4 2750 (e.g. HASH padding). */ 2751 __IM uint32_t RESERVED4[2]; 2752 __IM uint32_t DOUT_FIFO_EMPTY; /*!< (@ 0x00000D50) Register indicating if DOUT FIFO is empty or 2753 if more data will come. */ 2754 __IM uint32_t RESERVED5; 2755 __OM uint32_t DOUT_SW_RESET; /*!< (@ 0x00000D58) Reset the DOUT DMA engine. */ 2756 } NRF_CC_DOUT_Type; /*!< Size = 3420 (0xd5c) */ 2757 2758 2759 2760 /* =========================================================================================================================== */ 2761 /* ================ CC_HASH_S ================ */ 2762 /* =========================================================================================================================== */ 2763 2764 2765 /** 2766 * @brief CRYPTOCELL HASH engine (CC_HASH_S) 2767 */ 2768 2769 typedef struct { /*!< (@ 0x50841000) CC_HASH_S Structure */ 2770 __IM uint32_t RESERVED[400]; 2771 __IOM uint32_t HASH_H[8]; /*!< (@ 0x00000640) Description collection: HASH_H value registers. 2772 The initial HASH_H[0] register holds the 2773 least significant bits [31:0] of the value. */ 2774 __IM uint32_t RESERVED1[9]; 2775 __OM uint32_t HASH_PAD_AUTO; /*!< (@ 0x00000684) Configure the HASH engine to automatically pad 2776 data at the end of the DMA transfer to complete 2777 the digest operation. */ 2778 __IM uint32_t RESERVED2[3]; 2779 __OM uint32_t HASH_INIT_STATE; /*!< (@ 0x00000694) Configure HASH engine initial state registers. */ 2780 __IM uint32_t RESERVED3[70]; 2781 __IM uint32_t HASH_VERSION; /*!< (@ 0x000007B0) HASH engine HW version */ 2782 __IM uint32_t RESERVED4[3]; 2783 __IOM uint32_t HASH_CONTROL; /*!< (@ 0x000007C0) Control the HASH engine behavior. */ 2784 __IOM uint32_t HASH_PAD; /*!< (@ 0x000007C4) Enable the hardware padding feature of the HASH 2785 engine. */ 2786 __IOM uint32_t HASH_PAD_FORCE; /*!< (@ 0x000007C8) Force the hardware padding operation to trigger 2787 if the input data length is zero bytes. */ 2788 __IOM uint32_t HASH_CUR_LEN_0; /*!< (@ 0x000007CC) Bits [31:0] of the number of bytes that have 2789 been digested so far. */ 2790 __IOM uint32_t HASH_CUR_LEN_1; /*!< (@ 0x000007D0) Bits [63:32] of the number of bytes that have 2791 been digested so far. */ 2792 __IM uint32_t RESERVED5[2]; 2793 __IM uint32_t HASH_HW_FLAGS; /*!< (@ 0x000007DC) Hardware configuration of the HASH engine. Reset 2794 value holds the supported features. */ 2795 __IM uint32_t RESERVED6; 2796 __OM uint32_t HASH_SW_RESET; /*!< (@ 0x000007E4) Reset the HASH engine. */ 2797 __IOM uint32_t HASH_ENDIANNESS; /*!< (@ 0x000007E8) Configure the endianness of HASH data and padding 2798 generation. */ 2799 } NRF_CC_HASH_Type; /*!< Size = 2028 (0x7ec) */ 2800 2801 2802 2803 /* =========================================================================================================================== */ 2804 /* ================ CC_HOST_RGF_S ================ */ 2805 /* =========================================================================================================================== */ 2806 2807 2808 /** 2809 * @brief CRYPTOCELL HOST register interface (CC_HOST_RGF_S) 2810 */ 2811 2812 typedef struct { /*!< (@ 0x50841000) CC_HOST_RGF_S Structure */ 2813 __IM uint32_t RESERVED[640]; 2814 __IM uint32_t IRR; /*!< (@ 0x00000A00) Interrupt request register. Each bit of this 2815 register holds the interrupt status of a 2816 single interrupt source. If corresponding 2817 IMR bit is unmasked, an interrupt is generated. */ 2818 __IOM uint32_t IMR; /*!< (@ 0x00000A04) Interrupt mask register. Each bit of this register 2819 holds the mask of a single interrupt source. */ 2820 __OM uint32_t ICR; /*!< (@ 0x00000A08) Interrupt clear register. Writing a 1 bit into 2821 a field in this register will clear the 2822 corresponding bit in IRR. */ 2823 __IOM uint32_t ENDIANNESS; /*!< (@ 0x00000A0C) This register defines the endianness of the Host-accessible 2824 registers, and can only be written once. */ 2825 __IM uint32_t RESERVED1[5]; 2826 __IM uint32_t HOST_SIGNATURE; /*!< (@ 0x00000A24) This register holds the CRYPTOCELL subsystem 2827 signature. See reset value. */ 2828 __IM uint32_t HOST_BOOT; /*!< (@ 0x00000A28) Hardware configuration of the CRYPTOCELL subsystem. 2829 Reset value holds the supported features. */ 2830 __IM uint32_t RESERVED2[3]; 2831 __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00000A38) AES hardware key select. */ 2832 __IM uint32_t RESERVED3[4]; 2833 __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00000A4C) This write-once register is the K_PRTL lock register. 2834 When this register is set, K_PRTL cannot 2835 be used and a zeroed key will be used instead. 2836 The value of this register is saved in the 2837 CRYPTOCELL AO power domain. */ 2838 __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00000A50) This register holds bits 31:0 of K_DR. The value 2839 of this register is saved in the CRYPTOCELL 2840 AO power domain. Reading from this address 2841 returns the K_DR valid status indicating 2842 if K_DR is successfully retained. */ 2843 __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00000A54) This register holds bits 63:32 of K_DR. The value 2844 of this register is saved in the CRYPTOCELL 2845 AO power domain. */ 2846 __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00000A58) This register holds bits 95:64 of K_DR. The value 2847 of this register is saved in the CRYPTOCELL 2848 AO power domain. */ 2849 __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00000A5C) This register holds bits 127:96 of K_DR. The 2850 value of this register is saved in the CRYPTOCELL 2851 AO power domain. */ 2852 __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00000A60) Controls life-cycle state (LCS) for CRYPTOCELL 2853 subsystem */ 2854 } NRF_CC_HOST_RGF_Type; /*!< Size = 2660 (0xa64) */ 2855 2856 2857 2858 /* =========================================================================================================================== */ 2859 /* ================ CC_MISC_S ================ */ 2860 /* =========================================================================================================================== */ 2861 2862 2863 /** 2864 * @brief CRYPTOCELL MISC interface (CC_MISC_S) 2865 */ 2866 2867 typedef struct { /*!< (@ 0x50841000) CC_MISC_S Structure */ 2868 __IM uint32_t RESERVED[516]; 2869 __OM uint32_t AES_CLK; /*!< (@ 0x00000810) Clock control for the AES engine. */ 2870 __IM uint32_t RESERVED1; 2871 __OM uint32_t HASH_CLK; /*!< (@ 0x00000818) Clock control for the HASH engine. */ 2872 __OM uint32_t PKA_CLK; /*!< (@ 0x0000081C) Clock control for the PKA engine. */ 2873 __OM uint32_t DMA_CLK; /*!< (@ 0x00000820) Clock control for the DMA engines. */ 2874 __IM uint32_t CLK_STATUS; /*!< (@ 0x00000824) CRYPTOCELL clocks status register. */ 2875 __IM uint32_t RESERVED2[12]; 2876 __OM uint32_t CHACHA_CLK; /*!< (@ 0x00000858) Clock control for the CHACHA engine. */ 2877 } NRF_CC_MISC_Type; /*!< Size = 2140 (0x85c) */ 2878 2879 2880 2881 /* =========================================================================================================================== */ 2882 /* ================ CC_PKA_S ================ */ 2883 /* =========================================================================================================================== */ 2884 2885 2886 /** 2887 * @brief CRYPTOCELL PKA engine (CC_PKA_S) 2888 */ 2889 2890 typedef struct { /*!< (@ 0x50841000) CC_PKA_S Structure */ 2891 __IOM uint32_t MEMORY_MAP[32]; /*!< (@ 0x00000000) Description collection: Register for mapping 2892 the virtual register R[n] to a physical 2893 address in the PKA SRAM. */ 2894 __IOM uint32_t OPCODE; /*!< (@ 0x00000080) Operation code to be executed by the PKA engine. 2895 Writing to this register triggers the PKA 2896 operation. */ 2897 __IOM uint32_t N_NP_T0_T1_ADDR; /*!< (@ 0x00000084) This register defines the N, Np, T0, and T1 virtual 2898 register index. */ 2899 __IM uint32_t PKA_STATUS; /*!< (@ 0x00000088) This register holds the status for the PKA pipeline. */ 2900 __OM uint32_t PKA_SW_RESET; /*!< (@ 0x0000008C) Reset the PKA engine. */ 2901 __IOM uint32_t PKA_L[8]; /*!< (@ 0x00000090) Description collection: This register holds the 2902 operands bit size. */ 2903 __IM uint32_t PKA_PIPE; /*!< (@ 0x000000B0) Status register indicating if the PKA pipeline 2904 is ready to receive a new OPCODE. */ 2905 __IM uint32_t PKA_DONE; /*!< (@ 0x000000B4) Status register indicating if the PKA operation 2906 has been completed. */ 2907 __IM uint32_t RESERVED[3]; 2908 __IM uint32_t PKA_VERSION; /*!< (@ 0x000000C4) PKA engine HW version. Reset value holds the 2909 version. */ 2910 __IM uint32_t RESERVED1[3]; 2911 __OM uint32_t PKA_SRAM_WADDR; /*!< (@ 0x000000D4) Start address in PKA SRAM for subsequent write 2912 transactions. */ 2913 __OM uint32_t PKA_SRAM_WDATA; /*!< (@ 0x000000D8) Write data to PKA SRAM. Writing to this register 2914 triggers a DMA transaction writing data 2915 into PKA SRAM. The DMA address offset is 2916 automatically incremented during write. */ 2917 __IM uint32_t PKA_SRAM_RDATA; /*!< (@ 0x000000DC) Read data from PKA SRAM. Reading from this register 2918 triggers a DMA transaction read data from 2919 PKA SRAM. The DMA address offset is automatically 2920 incremented during read. */ 2921 __OM uint32_t PKA_SRAM_WCLEAR; /*!< (@ 0x000000E0) Register for clearing PKA SRAM write buffer. */ 2922 __OM uint32_t PKA_SRAM_RADDR; /*!< (@ 0x000000E4) Start address in PKA SRAM for subsequent read 2923 transactions. */ 2924 } NRF_CC_PKA_Type; /*!< Size = 232 (0xe8) */ 2925 2926 2927 2928 /* =========================================================================================================================== */ 2929 /* ================ CC_RNG_S ================ */ 2930 /* =========================================================================================================================== */ 2931 2932 2933 /** 2934 * @brief CRYPTOCELL RNG engine (CC_RNG_S) 2935 */ 2936 2937 typedef struct { /*!< (@ 0x50841000) CC_RNG_S Structure */ 2938 __IM uint32_t RESERVED[64]; 2939 __IOM uint32_t RNG_IMR; /*!< (@ 0x00000100) Interrupt mask register. Each bit of this register 2940 holds the mask of a single interrupt source. */ 2941 __IM uint32_t RNG_ISR; /*!< (@ 0x00000104) Interrupt status register. Each bit of this register 2942 holds the interrupt status of a single interrupt 2943 source. If corresponding RNG_IMR bit is 2944 unmasked, an interrupt is generated. */ 2945 __OM uint32_t RNG_ICR; /*!< (@ 0x00000108) Interrupt clear register. Writing a 1 bit into 2946 a field in this register will clear the 2947 corresponding bit in RNG_ISR. */ 2948 __IOM uint32_t TRNG_CONFIG; /*!< (@ 0x0000010C) TRNG ring oscillator length configuration */ 2949 __IM uint32_t TRNG_VALID; /*!< (@ 0x00000110) This register indicates if TRNG entropy collection 2950 is valid. */ 2951 __IM uint32_t EHR_DATA[6]; /*!< (@ 0x00000114) Description collection: The entropy holding registers 2952 (EHR) hold 192-bits random data collected 2953 by the TRNG. The initial EHR_DATA[0] register 2954 holds the least significant bits [31:0] 2955 of the random data value. */ 2956 __IOM uint32_t NOISE_SOURCE; /*!< (@ 0x0000012C) This register controls the ring oscillator circuit 2957 used as a noise source. */ 2958 __IOM uint32_t SAMPLE_CNT; /*!< (@ 0x00000130) Sample count defining the number of CPU clock 2959 cycles between two consecutive noise source 2960 samples. */ 2961 __IOM uint32_t AUTOCORR_STATISTIC; /*!< (@ 0x00000134) Statistics counter for autocorrelation test activations. 2962 Statistics collection is stopped if one 2963 of the counters reach its limit of all ones. */ 2964 __IOM uint32_t TRNG_DEBUG; /*!< (@ 0x00000138) Debug register for the TRNG. This register is 2965 used to bypass TRNG tests in hardware. */ 2966 __IM uint32_t RESERVED1; 2967 __OM uint32_t RNG_SW_RESET; /*!< (@ 0x00000140) Reset the RNG engine. */ 2968 __IM uint32_t RESERVED2[29]; 2969 __IM uint32_t RNG_BUSY; /*!< (@ 0x000001B8) Status register for RNG engine activity. */ 2970 __OM uint32_t TRNG_RESET; /*!< (@ 0x000001BC) Reset the TRNG, including internal counter of 2971 collected bits and registers EHR_DATA and 2972 TRNG_VALID. */ 2973 __IM uint32_t RNG_HW_FLAGS; /*!< (@ 0x000001C0) Hardware configuration of RNG engine. Reset value 2974 holds the supported features. */ 2975 __OM uint32_t RNG_CLK; /*!< (@ 0x000001C4) Control clock for the RNG engine. */ 2976 __IOM uint32_t RNG_DMA; /*!< (@ 0x000001C8) Writing to this register enables the RNG DMA 2977 engine. */ 2978 __IOM uint32_t RNG_DMA_ROSC_LEN; /*!< (@ 0x000001CC) This register defines which ring oscillator length 2979 configuration should be used when using 2980 the RNG DMA engine. */ 2981 __IOM uint32_t RNG_DMA_SRAM_ADDR; /*!< (@ 0x000001D0) This register defines the start address in TRNG 2982 SRAM for the TRNG data to be collected by 2983 the RNG DMA engine. */ 2984 __IOM uint32_t RNG_DMA_SAMPLES_NUM; /*!< (@ 0x000001D4) This register defines the number of 192-bits 2985 samples that the RNG DMA engine collects 2986 per run. */ 2987 __IOM uint32_t RNG_WATCHDOG_VAL; /*!< (@ 0x000001D8) This register defines the maximum number of CPU 2988 clock cycles per TRNG collection of 192-bits 2989 samples. If the number of cycles for a collection 2990 exceeds this threshold the WATCHDOG interrupt 2991 is triggered. */ 2992 __IM uint32_t RNG_DMA_BUSY; /*!< (@ 0x000001DC) Status register for RNG DMA engine activity. */ 2993 } NRF_CC_RNG_Type; /*!< Size = 480 (0x1e0) */ 2994 2995 2996 2997 /* =========================================================================================================================== */ 2998 /* ================ CC_RNG_SRAM_S ================ */ 2999 /* =========================================================================================================================== */ 3000 3001 3002 /** 3003 * @brief CRYPTOCELL RNG SRAM interface (CC_RNG_SRAM_S) 3004 */ 3005 3006 typedef struct { /*!< (@ 0x50841000) CC_RNG_SRAM_S Structure */ 3007 __IM uint32_t RESERVED[960]; 3008 __IOM uint32_t SRAM_DATA; /*!< (@ 0x00000F00) Read/Write data from RNG SRAM */ 3009 __OM uint32_t SRAM_ADDR; /*!< (@ 0x00000F04) First address given to RNG SRAM DMA for read/write 3010 transactions from/to RNG SRAM. */ 3011 __IM uint32_t SRAM_DATA_READY; /*!< (@ 0x00000F08) RNG SRAM DMA engine is ready to read/write from/to 3012 RNG SRAM. */ 3013 } NRF_CC_RNG_SRAM_Type; /*!< Size = 3852 (0xf0c) */ 3014 3015 3016 3017 /* =========================================================================================================================== */ 3018 /* ================ P0_NS ================ */ 3019 /* =========================================================================================================================== */ 3020 3021 3022 /** 3023 * @brief GPIO Port 0 (P0_NS) 3024 */ 3025 3026 typedef struct { /*!< (@ 0x40842500) P0_NS Structure */ 3027 __IM uint32_t RESERVED; 3028 __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 3029 __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 3030 __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 3031 __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 3032 __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 3033 __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 3034 __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 3035 __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 3036 have met the criteria set in the PIN_CNF[n].SENSE 3037 registers */ 3038 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior 3039 and LDETECT mode (For non-secure pin only) */ 3040 __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior 3041 and LDETECT mode (For secure pin only) */ 3042 __IM uint32_t RESERVED1[117]; 3043 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 3044 pins */ 3045 } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 3046 3047 3048 /** @} */ /* End of group Device_Peripheral_peripherals */ 3049 3050 3051 /* =========================================================================================================================== */ 3052 /* ================ Device Specific Peripheral Address Map ================ */ 3053 /* =========================================================================================================================== */ 3054 3055 3056 /** @addtogroup Device_Peripheral_peripheralAddr 3057 * @{ 3058 */ 3059 3060 #define NRF_FICR_S_BASE 0x00FF0000UL 3061 #define NRF_UICR_S_BASE 0x00FF8000UL 3062 #define NRF_ETM_NS_BASE 0xE0041000UL 3063 #define NRF_ETB_NS_BASE 0xE0051000UL 3064 #define NRF_TPIU_NS_BASE 0xE0054000UL 3065 #define NRF_ATBREPLICATOR_NS_BASE 0xE0058000UL 3066 #define NRF_ATBFUNNEL1_NS_BASE 0xE005A000UL 3067 #define NRF_ATBFUNNEL2_NS_BASE 0xE005B000UL 3068 #define NRF_TAD_S_BASE 0xE0080000UL 3069 #define NRF_SPU_S_BASE 0x50003000UL 3070 #define NRF_REGULATORS_NS_BASE 0x40004000UL 3071 #define NRF_REGULATORS_S_BASE 0x50004000UL 3072 #define NRF_CLOCK_NS_BASE 0x40005000UL 3073 #define NRF_POWER_NS_BASE 0x40005000UL 3074 #define NRF_CLOCK_S_BASE 0x50005000UL 3075 #define NRF_POWER_S_BASE 0x50005000UL 3076 #define NRF_CTRL_AP_PERI_S_BASE 0x50006000UL 3077 #define NRF_SPIM0_NS_BASE 0x40008000UL 3078 #define NRF_SPIS0_NS_BASE 0x40008000UL 3079 #define NRF_TWIM0_NS_BASE 0x40008000UL 3080 #define NRF_TWIS0_NS_BASE 0x40008000UL 3081 #define NRF_UARTE0_NS_BASE 0x40008000UL 3082 #define NRF_SPIM0_S_BASE 0x50008000UL 3083 #define NRF_SPIS0_S_BASE 0x50008000UL 3084 #define NRF_TWIM0_S_BASE 0x50008000UL 3085 #define NRF_TWIS0_S_BASE 0x50008000UL 3086 #define NRF_UARTE0_S_BASE 0x50008000UL 3087 #define NRF_SPIM1_NS_BASE 0x40009000UL 3088 #define NRF_SPIS1_NS_BASE 0x40009000UL 3089 #define NRF_TWIM1_NS_BASE 0x40009000UL 3090 #define NRF_TWIS1_NS_BASE 0x40009000UL 3091 #define NRF_UARTE1_NS_BASE 0x40009000UL 3092 #define NRF_SPIM1_S_BASE 0x50009000UL 3093 #define NRF_SPIS1_S_BASE 0x50009000UL 3094 #define NRF_TWIM1_S_BASE 0x50009000UL 3095 #define NRF_TWIS1_S_BASE 0x50009000UL 3096 #define NRF_UARTE1_S_BASE 0x50009000UL 3097 #define NRF_SPIM2_NS_BASE 0x4000A000UL 3098 #define NRF_SPIS2_NS_BASE 0x4000A000UL 3099 #define NRF_TWIM2_NS_BASE 0x4000A000UL 3100 #define NRF_TWIS2_NS_BASE 0x4000A000UL 3101 #define NRF_UARTE2_NS_BASE 0x4000A000UL 3102 #define NRF_SPIM2_S_BASE 0x5000A000UL 3103 #define NRF_SPIS2_S_BASE 0x5000A000UL 3104 #define NRF_TWIM2_S_BASE 0x5000A000UL 3105 #define NRF_TWIS2_S_BASE 0x5000A000UL 3106 #define NRF_UARTE2_S_BASE 0x5000A000UL 3107 #define NRF_SPIM3_NS_BASE 0x4000B000UL 3108 #define NRF_SPIS3_NS_BASE 0x4000B000UL 3109 #define NRF_TWIM3_NS_BASE 0x4000B000UL 3110 #define NRF_TWIS3_NS_BASE 0x4000B000UL 3111 #define NRF_UARTE3_NS_BASE 0x4000B000UL 3112 #define NRF_SPIM3_S_BASE 0x5000B000UL 3113 #define NRF_SPIS3_S_BASE 0x5000B000UL 3114 #define NRF_TWIM3_S_BASE 0x5000B000UL 3115 #define NRF_TWIS3_S_BASE 0x5000B000UL 3116 #define NRF_UARTE3_S_BASE 0x5000B000UL 3117 #define NRF_GPIOTE0_S_BASE 0x5000D000UL 3118 #define NRF_SAADC_NS_BASE 0x4000E000UL 3119 #define NRF_SAADC_S_BASE 0x5000E000UL 3120 #define NRF_TIMER0_NS_BASE 0x4000F000UL 3121 #define NRF_TIMER0_S_BASE 0x5000F000UL 3122 #define NRF_TIMER1_NS_BASE 0x40010000UL 3123 #define NRF_TIMER1_S_BASE 0x50010000UL 3124 #define NRF_TIMER2_NS_BASE 0x40011000UL 3125 #define NRF_TIMER2_S_BASE 0x50011000UL 3126 #define NRF_RTC0_NS_BASE 0x40014000UL 3127 #define NRF_RTC0_S_BASE 0x50014000UL 3128 #define NRF_RTC1_NS_BASE 0x40015000UL 3129 #define NRF_RTC1_S_BASE 0x50015000UL 3130 #define NRF_DPPIC_NS_BASE 0x40017000UL 3131 #define NRF_DPPIC_S_BASE 0x50017000UL 3132 #define NRF_WDT_NS_BASE 0x40018000UL 3133 #define NRF_WDT_S_BASE 0x50018000UL 3134 #define NRF_EGU0_NS_BASE 0x4001B000UL 3135 #define NRF_EGU0_S_BASE 0x5001B000UL 3136 #define NRF_EGU1_NS_BASE 0x4001C000UL 3137 #define NRF_EGU1_S_BASE 0x5001C000UL 3138 #define NRF_EGU2_NS_BASE 0x4001D000UL 3139 #define NRF_EGU2_S_BASE 0x5001D000UL 3140 #define NRF_EGU3_NS_BASE 0x4001E000UL 3141 #define NRF_EGU3_S_BASE 0x5001E000UL 3142 #define NRF_EGU4_NS_BASE 0x4001F000UL 3143 #define NRF_EGU4_S_BASE 0x5001F000UL 3144 #define NRF_EGU5_NS_BASE 0x40020000UL 3145 #define NRF_EGU5_S_BASE 0x50020000UL 3146 #define NRF_PWM0_NS_BASE 0x40021000UL 3147 #define NRF_PWM0_S_BASE 0x50021000UL 3148 #define NRF_PWM1_NS_BASE 0x40022000UL 3149 #define NRF_PWM1_S_BASE 0x50022000UL 3150 #define NRF_PWM2_NS_BASE 0x40023000UL 3151 #define NRF_PWM2_S_BASE 0x50023000UL 3152 #define NRF_PWM3_NS_BASE 0x40024000UL 3153 #define NRF_PWM3_S_BASE 0x50024000UL 3154 #define NRF_PDM_NS_BASE 0x40026000UL 3155 #define NRF_PDM_S_BASE 0x50026000UL 3156 #define NRF_I2S_NS_BASE 0x40028000UL 3157 #define NRF_I2S_S_BASE 0x50028000UL 3158 #define NRF_IPC_NS_BASE 0x4002A000UL 3159 #define NRF_IPC_S_BASE 0x5002A000UL 3160 #define NRF_FPU_NS_BASE 0x4002C000UL 3161 #define NRF_GPIOTE1_NS_BASE 0x40031000UL 3162 #define NRF_KMU_NS_BASE 0x40039000UL 3163 #define NRF_NVMC_NS_BASE 0x40039000UL 3164 #define NRF_KMU_S_BASE 0x50039000UL 3165 #define NRF_NVMC_S_BASE 0x50039000UL 3166 #define NRF_VMC_NS_BASE 0x4003A000UL 3167 #define NRF_VMC_S_BASE 0x5003A000UL 3168 #define NRF_CRYPTOCELL_S_BASE 0x50840000UL 3169 #define NRF_CC_AES_S_BASE 0x50841000UL 3170 #define NRF_CC_AHB_S_BASE 0x50841000UL 3171 #define NRF_CC_CHACHA_S_BASE 0x50841000UL 3172 #define NRF_CC_CTL_S_BASE 0x50841000UL 3173 #define NRF_CC_DIN_S_BASE 0x50841000UL 3174 #define NRF_CC_DOUT_S_BASE 0x50841000UL 3175 #define NRF_CC_HASH_S_BASE 0x50841000UL 3176 #define NRF_CC_HOST_RGF_S_BASE 0x50841000UL 3177 #define NRF_CC_MISC_S_BASE 0x50841000UL 3178 #define NRF_CC_PKA_S_BASE 0x50841000UL 3179 #define NRF_CC_RNG_S_BASE 0x50841000UL 3180 #define NRF_CC_RNG_SRAM_S_BASE 0x50841000UL 3181 #define NRF_P0_NS_BASE 0x40842500UL 3182 #define NRF_P0_S_BASE 0x50842500UL 3183 3184 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 3185 3186 3187 /* =========================================================================================================================== */ 3188 /* ================ Peripheral declaration ================ */ 3189 /* =========================================================================================================================== */ 3190 3191 3192 /** @addtogroup Device_Peripheral_declaration 3193 * @{ 3194 */ 3195 3196 #define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE) 3197 #define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) 3198 #define NRF_ETM_NS ((NRF_ETM_Type*) NRF_ETM_NS_BASE) 3199 #define NRF_ETB_NS ((NRF_ETB_Type*) NRF_ETB_NS_BASE) 3200 #define NRF_TPIU_NS ((NRF_TPIU_Type*) NRF_TPIU_NS_BASE) 3201 #define NRF_ATBREPLICATOR_NS ((NRF_ATBREPLICATOR_Type*) NRF_ATBREPLICATOR_NS_BASE) 3202 #define NRF_ATBFUNNEL1_NS ((NRF_ATBFUNNEL_Type*) NRF_ATBFUNNEL1_NS_BASE) 3203 #define NRF_ATBFUNNEL2_NS ((NRF_ATBFUNNEL_Type*) NRF_ATBFUNNEL2_NS_BASE) 3204 #define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) 3205 #define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE) 3206 #define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) 3207 #define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) 3208 #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 3209 #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 3210 #define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) 3211 #define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) 3212 #define NRF_CTRL_AP_PERI_S ((NRF_CTRLAPPERI_Type*) NRF_CTRL_AP_PERI_S_BASE) 3213 #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 3214 #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 3215 #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 3216 #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 3217 #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 3218 #define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE) 3219 #define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE) 3220 #define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE) 3221 #define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE) 3222 #define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE) 3223 #define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE) 3224 #define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE) 3225 #define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE) 3226 #define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE) 3227 #define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE) 3228 #define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE) 3229 #define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE) 3230 #define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE) 3231 #define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE) 3232 #define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE) 3233 #define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE) 3234 #define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE) 3235 #define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE) 3236 #define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE) 3237 #define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE) 3238 #define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE) 3239 #define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE) 3240 #define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE) 3241 #define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE) 3242 #define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE) 3243 #define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE) 3244 #define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE) 3245 #define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE) 3246 #define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE) 3247 #define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE) 3248 #define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE) 3249 #define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE) 3250 #define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE) 3251 #define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE) 3252 #define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE) 3253 #define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE) 3254 #define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) 3255 #define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) 3256 #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 3257 #define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE) 3258 #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 3259 #define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE) 3260 #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 3261 #define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE) 3262 #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 3263 #define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE) 3264 #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 3265 #define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE) 3266 #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 3267 #define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE) 3268 #define NRF_WDT_NS ((NRF_WDT_Type*) NRF_WDT_NS_BASE) 3269 #define NRF_WDT_S ((NRF_WDT_Type*) NRF_WDT_S_BASE) 3270 #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 3271 #define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE) 3272 #define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE) 3273 #define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE) 3274 #define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE) 3275 #define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE) 3276 #define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE) 3277 #define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE) 3278 #define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE) 3279 #define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE) 3280 #define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE) 3281 #define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE) 3282 #define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE) 3283 #define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE) 3284 #define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE) 3285 #define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE) 3286 #define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE) 3287 #define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE) 3288 #define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE) 3289 #define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE) 3290 #define NRF_PDM_NS ((NRF_PDM_Type*) NRF_PDM_NS_BASE) 3291 #define NRF_PDM_S ((NRF_PDM_Type*) NRF_PDM_S_BASE) 3292 #define NRF_I2S_NS ((NRF_I2S_Type*) NRF_I2S_NS_BASE) 3293 #define NRF_I2S_S ((NRF_I2S_Type*) NRF_I2S_S_BASE) 3294 #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 3295 #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) 3296 #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) 3297 #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) 3298 #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) 3299 #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 3300 #define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) 3301 #define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE) 3302 #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 3303 #define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE) 3304 #define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE) 3305 #define NRF_CC_AES_S ((NRF_CC_AES_Type*) NRF_CC_AES_S_BASE) 3306 #define NRF_CC_AHB_S ((NRF_CC_AHB_Type*) NRF_CC_AHB_S_BASE) 3307 #define NRF_CC_CHACHA_S ((NRF_CC_CHACHA_Type*) NRF_CC_CHACHA_S_BASE) 3308 #define NRF_CC_CTL_S ((NRF_CC_CTL_Type*) NRF_CC_CTL_S_BASE) 3309 #define NRF_CC_DIN_S ((NRF_CC_DIN_Type*) NRF_CC_DIN_S_BASE) 3310 #define NRF_CC_DOUT_S ((NRF_CC_DOUT_Type*) NRF_CC_DOUT_S_BASE) 3311 #define NRF_CC_HASH_S ((NRF_CC_HASH_Type*) NRF_CC_HASH_S_BASE) 3312 #define NRF_CC_HOST_RGF_S ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_S_BASE) 3313 #define NRF_CC_MISC_S ((NRF_CC_MISC_Type*) NRF_CC_MISC_S_BASE) 3314 #define NRF_CC_PKA_S ((NRF_CC_PKA_Type*) NRF_CC_PKA_S_BASE) 3315 #define NRF_CC_RNG_S ((NRF_CC_RNG_Type*) NRF_CC_RNG_S_BASE) 3316 #define NRF_CC_RNG_SRAM_S ((NRF_CC_RNG_SRAM_Type*) NRF_CC_RNG_SRAM_S_BASE) 3317 #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 3318 #define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) 3319 3320 /** @} */ /* End of group Device_Peripheral_declaration */ 3321 3322 3323 #ifdef __cplusplus 3324 } 3325 #endif 3326 3327 #endif /* NRF9160_H */ 3328 3329 3330 /** @} */ /* End of group nrf9160 */ 3331 3332 /** @} */ /* End of group Nordic Semiconductor */ 3333
