1 /* 2 3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF7120_ENGA_WIFICORE_PERIPHERALS_H 36 #define NRF7120_ENGA_WIFICORE_PERIPHERALS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdbool.h> 43 /*VPR peripheral registers*/ 44 #define VPR_PRESENT 1 45 #define VPR_COUNT 3 46 47 #define LMAC_VPR_INIT_PC_RESET_VALUE 0x28080000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x28080000 */ 48 #define LMAC_VPR_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 49 #define LMAC_VPR_RAM_BASE_ADDR 0x28000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x28000000 */ 50 #define LMAC_VPR_RAM_SZ 18 /*!< VPR RAM size (RAM_SZ): 18 (Value in bytes is computed as 2^(RAM 51 size))*/ 52 #define LMAC_VPR_VPRSAVEDCTX_REGNAME NRF_MEMCONFWIFI->POWER[0].RET /*!< (unspecified) */ 53 #define LMAC_VPR_VPRSAVEDCTX_REGBIT 0 /*!< (unspecified) */ 54 #define LMAC_VPR_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ 55 #define LMAC_VPR_VPRSAVEDCTX 1 /*!< (unspecified) */ 56 #define LMAC_VPR_VPRSAVEADDR 0x28000000 /*!< VPR context save address: 0x28000000 */ 57 #define LMAC_VPR_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ 58 #define LMAC_VPR_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..23 */ 59 #define LMAC_VPR_VEVIF_NTASKS_MAX 23 /*!< VEVIF tasks: 16..23 */ 60 #define LMAC_VPR_VEVIF_NTASKS_SIZE 24 /*!< VEVIF tasks: 16..23 */ 61 #define LMAC_VPR_VEVIF_TASKS_MASK 0x00FF0000 /*!< Mask of supported VEVIF tasks: 0x00FF0000 */ 62 #define LMAC_VPR_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..0 */ 63 #define LMAC_VPR_VEVIF_NDPPI_MAX 0 /*!< VEVIF DPPI channels: 0..0 */ 64 #define LMAC_VPR_VEVIF_NDPPI_SIZE 1 /*!< VEVIF DPPI channels: 0..0 */ 65 #define LMAC_VPR_VEVIF_DPPI_MASK 0x00000000 /*!< Mask of supported VEVIF DPPI channels: 0x00000000 */ 66 #define LMAC_VPR_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..0 */ 67 #define LMAC_VPR_VEVIF_NEVENTS_MAX 0 /*!< VEVIF events: 0..0 */ 68 #define LMAC_VPR_VEVIF_NEVENTS_SIZE 1 /*!< VEVIF events: 0..0 */ 69 #define LMAC_VPR_VEVIF_EVENTS_MASK 0x01000000 /*!< Mask of supported VEVIF events: 0x01000000 */ 70 #define LMAC_VPR_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x48000400 */ 71 #define LMAC_VPR_RTP_VPR_1_5 1 /*!< (unspecified) */ 72 73 #define UMAC_VPR_INIT_PC_RESET_VALUE 0x28180000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x28180000 */ 74 #define UMAC_VPR_VPR_START_RESET_VALUE 0 /*!< Self-booting (VPR_START_RESET_VALUE): 0 */ 75 #define UMAC_VPR_RAM_BASE_ADDR 0x28100000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x28100000 */ 76 #define UMAC_VPR_RAM_SZ 19 /*!< VPR RAM size (RAM_SZ): 19 (Value in bytes is computed as 2^(RAM 77 size))*/ 78 #define UMAC_VPR_VPRSAVEDCTX_REGNAME NRF_MEMCONFWIFI->POWER[0].RET /*!< (unspecified) */ 79 #define UMAC_VPR_VPRSAVEDCTX_REGBIT 1 /*!< (unspecified) */ 80 #define UMAC_VPR_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ 81 #define UMAC_VPR_VPRSAVEDCTX 1 /*!< (unspecified) */ 82 #define UMAC_VPR_VPRSAVEADDR 0x280000180 /*!< VPR context save address: 0x280000180 */ 83 #define UMAC_VPR_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ 84 #define UMAC_VPR_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..23 */ 85 #define UMAC_VPR_VEVIF_NTASKS_MAX 23 /*!< VEVIF tasks: 16..23 */ 86 #define UMAC_VPR_VEVIF_NTASKS_SIZE 24 /*!< VEVIF tasks: 16..23 */ 87 #define UMAC_VPR_VEVIF_TASKS_MASK 0x00FF0000 /*!< Mask of supported VEVIF tasks: 0x00FF0000 */ 88 #define UMAC_VPR_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..0 */ 89 #define UMAC_VPR_VEVIF_NDPPI_MAX 0 /*!< VEVIF DPPI channels: 0..0 */ 90 #define UMAC_VPR_VEVIF_NDPPI_SIZE 1 /*!< VEVIF DPPI channels: 0..0 */ 91 #define UMAC_VPR_VEVIF_DPPI_MASK 0x00000000 /*!< Mask of supported VEVIF DPPI channels: 0x00000000 */ 92 #define UMAC_VPR_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..0 */ 93 #define UMAC_VPR_VEVIF_NEVENTS_MAX 0 /*!< VEVIF events: 0..0 */ 94 #define UMAC_VPR_VEVIF_NEVENTS_SIZE 1 /*!< VEVIF events: 0..0 */ 95 #define UMAC_VPR_VEVIF_EVENTS_MASK 0x01000000 /*!< Mask of supported VEVIF events: 0x01000000 */ 96 #define UMAC_VPR_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x48004400 */ 97 #define UMAC_VPR_RTP_VPR_1_5 1 /*!< (unspecified) */ 98 99 #define VPR00_INIT_PC_RESET_VALUE 0x01000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x01000000 */ 100 #define VPR00_VPR_START_RESET_VALUE 1 /*!< Self-booting (VPR_START_RESET_VALUE): 1 */ 101 #define VPR00_RAM_BASE_ADDR 0x20000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x20000000 */ 102 #define VPR00_RAM_SZ 20 /*!< VPR RAM size (RAM_SZ): 20 (Value in bytes is computed as 2^(RAM 103 size))*/ 104 #define VPR00_VPRSAVEDCTX_REGNAME NRF_MEMCONF->POWER[1].RET /*!< (unspecified) */ 105 #define VPR00_VPRSAVEDCTX_REGBIT 0 /*!< (unspecified) */ 106 #define VPR00_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ 107 #define VPR00_VPRSAVEDCTX 1 /*!< (unspecified) */ 108 #define VPR00_VPRSAVEADDR 0x200FFE00 /*!< VPR context save address: 0x200FFE00 */ 109 #define VPR00_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ 110 #define VPR00_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..22 */ 111 #define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ 112 #define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ 113 #define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ 114 #define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ 115 #define VPR00_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ 116 #define VPR00_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ 117 #define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ 118 #define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ 119 #define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ 120 #define VPR00_VEVIF_NEVENTS_SIZE 23 /*!< VEVIF events: 16..22 */ 121 #define VPR00_VEVIF_EVENTS_MASK 0x00100000 /*!< Mask of supported VEVIF events: 0x00100000 */ 122 #define VPR00_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5004C400 */ 123 #define VPR00_RTP_VPR_1_5 1 /*!< (unspecified) */ 124 125 /*MVDMA performs direct-memory-accesses between memories. Data is transferred according to job descriptor lists. Each transfer has corresponding source and sink descriptor lists with matching data amounts. The lists are in memory and they contain data buffer information, address pointers, buffer sizes and data type attributes.*/ 126 127 #define MVDMA_PRESENT 1 128 #define MVDMA_COUNT 1 129 130 #define MVDMA_COMPLETED_EVENT 1 /*!< (unspecified) */ 131 #define MVDMA_DPPI_DISCONNECTED 0 /*!< (unspecified) */ 132 #define MVDMA_INSTANCE_IN_WRAPPER 0 /*!< (unspecified) */ 133 134 /*LRCCONF*/ 135 #define LRCCONF_PRESENT 1 136 #define LRCCONF_COUNT 1 137 138 #define LRCCONF_LRC0_POWERON 1 /*!< (unspecified) */ 139 #define LRCCONF_LRC0_RETAIN 1 /*!< (unspecified) */ 140 #define LRCCONF_LRC0_SYSTEMOFF 1 /*!< (unspecified) */ 141 #define LRCCONF_LRC0_LRCREQHFXO 0 /*!< (unspecified) */ 142 #define LRCCONF_LRC0_NCLK_MIN 0 /*!< (unspecified) */ 143 #define LRCCONF_LRC0_NCLK_MAX 7 /*!< (unspecified) */ 144 #define LRCCONF_LRC0_NCLK_SIZE 8 /*!< (unspecified) */ 145 #define LRCCONF_LRC0_CLKCTRL 0 /*!< (unspecified) */ 146 #define LRCCONF_LRC0_NACTPD_MIN 0 /*!< (unspecified) */ 147 #define LRCCONF_LRC0_NACTPD_MAX 0 /*!< (unspecified) */ 148 #define LRCCONF_LRC0_NACTPD_SIZE 1 /*!< (unspecified) */ 149 #define LRCCONF_LRC0_PDACT 1 /*!< (unspecified) */ 150 #define LRCCONF_LRC0_NPD_MIN 0 /*!< (unspecified) */ 151 #define LRCCONF_LRC0_NPD_MAX 7 /*!< (unspecified) */ 152 #define LRCCONF_LRC0_NPD_SIZE 8 /*!< (unspecified) */ 153 #define LRCCONF_LRC0_OTHERON 0 /*!< (unspecified) */ 154 #define LRCCONF_LRC0_NDOMAINS_MIN 0 /*!< (unspecified) */ 155 #define LRCCONF_LRC0_NDOMAINS_MAX 15 /*!< (unspecified) */ 156 #define LRCCONF_LRC0_NDOMAINS_SIZE 16 /*!< (unspecified) */ 157 #define LRCCONF_LRC0_AX2XWAITSTATES 0 /*!< (unspecified) */ 158 #define LRCCONF_LRC0_POWERON_MAIN_RESET 0 /*!< Reset value of register POWERON.MAIN: 0 */ 159 #define LRCCONF_LRC0_POWERON_ACT_RESET 0 /*!< Reset value of register POWERON.ACT: 0 */ 160 #define LRCCONF_LRC0_RETAIN_MAIN_RESET 1 /*!< Reset value of register RETAIN.MAIN: 1 */ 161 #define LRCCONF_LRC0_RETAIN_ACT_RESET 1 /*!< Reset value of register RETAIN.ACT: 1 */ 162 163 /*Antenna switch controller*/ 164 #define ANTSWC_PRESENT 1 165 #define ANTSWC_COUNT 1 166 167 #define ANTSWC_NRADIOS 2 /*!< Number of radio ports : 2 */ 168 #define ANTSWC_NANTSWBITS 1 /*!< Number of antenna switch control bits: 1 */ 169 #define ANTSWC_DPPI_ENABLE_REGISTERS 0 /*!< (unspecified) */ 170 171 /*BELLBOARD APB registers*/ 172 #define BELLBOARD_PRESENT 1 173 #define BELLBOARD_COUNT 1 174 175 #define BELLBOARD_IRQ_COUNT 4 176 177 /*Factory Information Configuration Registers*/ 178 #define FICR_PRESENT 1 179 #define FICR_COUNT 1 180 181 /*User Information Configuration Registers*/ 182 #define UICR_PRESENT 1 183 #define UICR_COUNT 1 184 185 #define UICR_MRAM 1 /*!< (unspecified) */ 186 187 /*Factory Information Configuration Registers*/ 188 #define SICR_PRESENT 1 189 #define SICR_COUNT 1 190 191 /*CRACENCORE*/ 192 #define CRACENCORE_PRESENT 1 193 #define CRACENCORE_COUNT 1 194 195 #define CRACENCORE_CRYPTMSTRDMAREGS 1 /*!< (unspecified) */ 196 #define CRACENCORE_CRYPTMSTRHWREGS 1 /*!< (unspecified) */ 197 #define CRACENCORE_RNGCONTROLREGS 1 /*!< (unspecified) */ 198 #define CRACENCORE_PKREGS 1 /*!< (unspecified) */ 199 #define CRACENCORE_IKGREGS 1 /*!< (unspecified) */ 200 #define CRACENCORE_RNGDATAREGS 1 /*!< (unspecified) */ 201 #define CRACENCORE_EXTPRIVKEYSREGS 0 /*!< (unspecified) */ 202 #define CRACENCORE_LITESMALLRESETVALUES 0 /*!< (unspecified) */ 203 #define CRACENCORE_LITEMEDIUMRESETVALUES 1 /*!< (unspecified) */ 204 #define CRACENCORE_FULLRESETVALUES 0 /*!< (unspecified) */ 205 #define CRACENCORE_CRACENRESETVALUES 1 /*!< (unspecified) */ 206 #define CRACENCORE_SHA3RESETVALUES 0 /*!< (unspecified) */ 207 #define CRACENCORE_PKE_DATA_MEMORY 0x50018000 /*!< (unspecified) */ 208 #define CRACENCORE_PKE_DATA_MEMORY_SIZE 16384 /*!< (unspecified) */ 209 #define CRACENCORE_PKE_CODE_MEMORY 0x5001C000 /*!< (unspecified) */ 210 #define CRACENCORE_PKE_CODE_MEMORY_SIZE 8192 /*!< (unspecified) */ 211 212 /*USBHSCORE*/ 213 #define USBHSCORE_PRESENT 1 214 #define USBHSCORE_COUNT 1 215 216 /*System protection unit*/ 217 #define SPU_PRESENT 1 218 #define SPU_COUNT 4 219 220 #define SPU00_BELLS 0 /*!< (unspecified) */ 221 #define SPU00_IPCT 0 /*!< (unspecified) */ 222 #define SPU00_DPPI 1 /*!< (unspecified) */ 223 #define SPU00_GPIOTE 0 /*!< (unspecified) */ 224 #define SPU00_GRTC 0 /*!< (unspecified) */ 225 #define SPU00_GPIO 1 /*!< (unspecified) */ 226 #define SPU00_CRACEN 0 /*!< (unspecified) */ 227 #define SPU00_MRAMC 0 /*!< (unspecified) */ 228 #define SPU00_COEXC 0 /*!< (unspecified) */ 229 #define SPU00_ANTSWC 0 /*!< (unspecified) */ 230 #define SPU00_TDD 0 /*!< (unspecified) */ 231 #define SPU00_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 232 peripheral slave index)*/ 233 234 #define SPU10_BELLS 0 /*!< (unspecified) */ 235 #define SPU10_IPCT 0 /*!< (unspecified) */ 236 #define SPU10_DPPI 1 /*!< (unspecified) */ 237 #define SPU10_GPIOTE 0 /*!< (unspecified) */ 238 #define SPU10_GRTC 0 /*!< (unspecified) */ 239 #define SPU10_GPIO 0 /*!< (unspecified) */ 240 #define SPU10_CRACEN 0 /*!< (unspecified) */ 241 #define SPU10_MRAMC 0 /*!< (unspecified) */ 242 #define SPU10_COEXC 0 /*!< (unspecified) */ 243 #define SPU10_ANTSWC 0 /*!< (unspecified) */ 244 #define SPU10_TDD 0 /*!< (unspecified) */ 245 #define SPU10_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 246 peripheral slave index)*/ 247 248 #define SPU20_BELLS 0 /*!< (unspecified) */ 249 #define SPU20_IPCT 0 /*!< (unspecified) */ 250 #define SPU20_DPPI 1 /*!< (unspecified) */ 251 #define SPU20_GPIOTE 1 /*!< (unspecified) */ 252 #define SPU20_GRTC 1 /*!< (unspecified) */ 253 #define SPU20_GPIO 1 /*!< (unspecified) */ 254 #define SPU20_CRACEN 0 /*!< (unspecified) */ 255 #define SPU20_MRAMC 0 /*!< (unspecified) */ 256 #define SPU20_COEXC 1 /*!< (unspecified) */ 257 #define SPU20_ANTSWC 0 /*!< (unspecified) */ 258 #define SPU20_TDD 0 /*!< (unspecified) */ 259 #define SPU20_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 260 peripheral slave index)*/ 261 262 #define SPU30_BELLS 0 /*!< (unspecified) */ 263 #define SPU30_IPCT 0 /*!< (unspecified) */ 264 #define SPU30_DPPI 1 /*!< (unspecified) */ 265 #define SPU30_GPIOTE 1 /*!< (unspecified) */ 266 #define SPU30_GRTC 0 /*!< (unspecified) */ 267 #define SPU30_GPIO 1 /*!< (unspecified) */ 268 #define SPU30_CRACEN 0 /*!< (unspecified) */ 269 #define SPU30_MRAMC 0 /*!< (unspecified) */ 270 #define SPU30_COEXC 0 /*!< (unspecified) */ 271 #define SPU30_ANTSWC 0 /*!< (unspecified) */ 272 #define SPU30_TDD 0 /*!< (unspecified) */ 273 #define SPU30_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 274 peripheral slave index)*/ 275 276 /*Memory Privilege Controller*/ 277 #define MPC_PRESENT 1 278 #define MPC_COUNT 1 279 280 #define MPC00_EXTEND_CLOCK_REQ 0 /*!< (unspecified) */ 281 #define MPC00_RTCHOKE 0 /*!< (unspecified) */ 282 #define MPC00_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ 283 284 /*Distributed programmable peripheral interconnect controller*/ 285 #define DPPIC_PRESENT 1 286 #define DPPIC_COUNT 4 287 288 #define DPPIC00_HASCHANNELGROUPS 1 /*!< (unspecified) */ 289 #define DPPIC00_CH_NUM_MIN 0 /*!< (unspecified) */ 290 #define DPPIC00_CH_NUM_MAX 15 /*!< (unspecified) */ 291 #define DPPIC00_CH_NUM_SIZE 16 /*!< (unspecified) */ 292 #define DPPIC00_GROUP_NUM_MIN 0 /*!< (unspecified) */ 293 #define DPPIC00_GROUP_NUM_MAX 1 /*!< (unspecified) */ 294 #define DPPIC00_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 295 296 #define DPPIC10_HASCHANNELGROUPS 1 /*!< (unspecified) */ 297 #define DPPIC10_CH_NUM_MIN 0 /*!< (unspecified) */ 298 #define DPPIC10_CH_NUM_MAX 23 /*!< (unspecified) */ 299 #define DPPIC10_CH_NUM_SIZE 24 /*!< (unspecified) */ 300 #define DPPIC10_GROUP_NUM_MIN 0 /*!< (unspecified) */ 301 #define DPPIC10_GROUP_NUM_MAX 5 /*!< (unspecified) */ 302 #define DPPIC10_GROUP_NUM_SIZE 6 /*!< (unspecified) */ 303 304 #define DPPIC20_HASCHANNELGROUPS 1 /*!< (unspecified) */ 305 #define DPPIC20_CH_NUM_MIN 0 /*!< (unspecified) */ 306 #define DPPIC20_CH_NUM_MAX 15 /*!< (unspecified) */ 307 #define DPPIC20_CH_NUM_SIZE 16 /*!< (unspecified) */ 308 #define DPPIC20_GROUP_NUM_MIN 0 /*!< (unspecified) */ 309 #define DPPIC20_GROUP_NUM_MAX 5 /*!< (unspecified) */ 310 #define DPPIC20_GROUP_NUM_SIZE 6 /*!< (unspecified) */ 311 312 #define DPPIC30_HASCHANNELGROUPS 1 /*!< (unspecified) */ 313 #define DPPIC30_CH_NUM_MIN 0 /*!< (unspecified) */ 314 #define DPPIC30_CH_NUM_MAX 3 /*!< (unspecified) */ 315 #define DPPIC30_CH_NUM_SIZE 4 /*!< (unspecified) */ 316 #define DPPIC30_GROUP_NUM_MIN 0 /*!< (unspecified) */ 317 #define DPPIC30_GROUP_NUM_MAX 1 /*!< (unspecified) */ 318 #define DPPIC30_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 319 320 /*PPIB APB registers*/ 321 #define PPIB_PRESENT 1 322 #define PPIB_COUNT 8 323 324 #define PPIB00_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 325 #define PPIB00_NTASKSEVENTS_MAX 11 /*!< (unspecified) */ 326 #define PPIB00_NTASKSEVENTS_SIZE 12 /*!< (unspecified) */ 327 328 #define PPIB01_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 329 #define PPIB01_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 330 #define PPIB01_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 331 332 #define PPIB10_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 333 #define PPIB10_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 334 #define PPIB10_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 335 336 #define PPIB11_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 337 #define PPIB11_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 338 #define PPIB11_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 339 340 #define PPIB20_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 341 #define PPIB20_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 342 #define PPIB20_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 343 344 #define PPIB21_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 345 #define PPIB21_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 346 #define PPIB21_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 347 348 #define PPIB22_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 349 #define PPIB22_NTASKSEVENTS_MAX 3 /*!< (unspecified) */ 350 #define PPIB22_NTASKSEVENTS_SIZE 4 /*!< (unspecified) */ 351 352 #define PPIB30_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 353 #define PPIB30_NTASKSEVENTS_MAX 3 /*!< (unspecified) */ 354 #define PPIB30_NTASKSEVENTS_SIZE 4 /*!< (unspecified) */ 355 356 /*Key management unit*/ 357 #define KMU_PRESENT 1 358 #define KMU_COUNT 1 359 360 #define KMU_KEYSLOTNUM 250 /*!< Number of keyslots is 250 */ 361 #define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot is 128 */ 362 #define KMU_PUSHBLOCK 1 /*!< (unspecified) */ 363 #define KMU_BLOCK 1 /*!< (unspecified) */ 364 365 /*Accelerated Address Resolver*/ 366 #define AAR_PRESENT 1 367 #define AAR_COUNT 1 368 369 #define AAR00_DMAERROR 1 /*!< (unspecified) */ 370 #define AAR00_ERRORSTATUS 1 /*!< (unspecified) */ 371 #define AAR00_ERROREVENT 1 /*!< (unspecified) */ 372 373 /*AES CCM Mode Encryption*/ 374 #define CCM_PRESENT 1 375 #define CCM_COUNT 1 376 377 #define CCM00_AMOUNTREG 0 /*!< (unspecified) */ 378 #define CCM00_ONTHEFLYDECRYPTION 0 /*!< (unspecified) */ 379 #define CCM00_DMAERROR 1 /*!< (unspecified) */ 380 381 /*AES ECB Mode Encryption*/ 382 #define ECB_PRESENT 1 383 #define ECB_COUNT 1 384 385 #define ECB00_AMOUNTREG 0 /*!< (unspecified) */ 386 #define ECB00_DMAERROR 1 /*!< (unspecified) */ 387 #define ECB00_ERRORSTATUS 1 /*!< (unspecified) */ 388 389 /*Serial Peripheral Interface Master with EasyDMA*/ 390 #define SPIM_PRESENT 1 391 #define SPIM_COUNT 8 392 393 #define SPIM00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 394 #define SPIM00_MAX_DATARATE 32 /*!< (unspecified) */ 395 #define SPIM00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 396 #define SPIM00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 397 #define SPIM00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 398 #define SPIM00_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 399 #define SPIM00_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 400 #define SPIM00_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 401 #define SPIM00_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 402 #define SPIM00_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 403 #define SPIM00_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 404 #define SPIM00_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 405 #define SPIM00_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 406 #define SPIM00_CORE_FREQUENCY 256 /*!< Peripheral core frequency is 256 MHz. */ 407 #define SPIM00_PRESCALER_PRESENT 1 /*!< (unspecified) */ 408 #define SPIM00_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 409 #define SPIM00_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 410 #define SPIM00_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 411 #define SPIM00_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 412 #define SPIM00_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 413 #define SPIM00_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 414 #define SPIM00_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 415 #define SPIM00_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 416 #define SPIM00_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 417 #define SPIM00_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 418 419 #define SPIM01_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 420 #define SPIM01_MAX_DATARATE 32 /*!< (unspecified) */ 421 #define SPIM01_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 422 #define SPIM01_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 423 #define SPIM01_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 424 #define SPIM01_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 425 #define SPIM01_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 426 #define SPIM01_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 427 #define SPIM01_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 428 #define SPIM01_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 429 #define SPIM01_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 430 #define SPIM01_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 431 #define SPIM01_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 432 #define SPIM01_CORE_FREQUENCY 256 /*!< Peripheral core frequency is 256 MHz. */ 433 #define SPIM01_PRESCALER_PRESENT 1 /*!< (unspecified) */ 434 #define SPIM01_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 435 #define SPIM01_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 436 #define SPIM01_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 437 #define SPIM01_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 438 #define SPIM01_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 439 #define SPIM01_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 440 #define SPIM01_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 441 #define SPIM01_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 442 #define SPIM01_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 443 #define SPIM01_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 444 445 #define SPIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 446 #define SPIM20_MAX_DATARATE 8 /*!< (unspecified) */ 447 #define SPIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 448 #define SPIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 449 #define SPIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 450 #define SPIM20_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 451 #define SPIM20_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 452 #define SPIM20_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 453 #define SPIM20_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 454 #define SPIM20_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 455 #define SPIM20_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 456 #define SPIM20_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 457 #define SPIM20_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 458 #define SPIM20_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 459 #define SPIM20_PRESCALER_PRESENT 1 /*!< (unspecified) */ 460 #define SPIM20_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 461 #define SPIM20_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 462 #define SPIM20_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 463 #define SPIM20_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 464 #define SPIM20_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 465 #define SPIM20_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 466 #define SPIM20_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 467 #define SPIM20_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 468 #define SPIM20_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 469 #define SPIM20_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 470 471 #define SPIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 472 #define SPIM21_MAX_DATARATE 8 /*!< (unspecified) */ 473 #define SPIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 474 #define SPIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 475 #define SPIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 476 #define SPIM21_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 477 #define SPIM21_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 478 #define SPIM21_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 479 #define SPIM21_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 480 #define SPIM21_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 481 #define SPIM21_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 482 #define SPIM21_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 483 #define SPIM21_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 484 #define SPIM21_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 485 #define SPIM21_PRESCALER_PRESENT 1 /*!< (unspecified) */ 486 #define SPIM21_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 487 #define SPIM21_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 488 #define SPIM21_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 489 #define SPIM21_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 490 #define SPIM21_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 491 #define SPIM21_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 492 #define SPIM21_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 493 #define SPIM21_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 494 #define SPIM21_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 495 #define SPIM21_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 496 497 #define SPIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 498 #define SPIM22_MAX_DATARATE 8 /*!< (unspecified) */ 499 #define SPIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 500 #define SPIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 501 #define SPIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 502 #define SPIM22_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 503 #define SPIM22_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 504 #define SPIM22_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 505 #define SPIM22_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 506 #define SPIM22_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 507 #define SPIM22_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 508 #define SPIM22_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 509 #define SPIM22_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 510 #define SPIM22_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 511 #define SPIM22_PRESCALER_PRESENT 1 /*!< (unspecified) */ 512 #define SPIM22_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 513 #define SPIM22_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 514 #define SPIM22_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 515 #define SPIM22_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 516 #define SPIM22_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 517 #define SPIM22_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 518 #define SPIM22_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 519 #define SPIM22_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 520 #define SPIM22_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 521 #define SPIM22_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 522 523 #define SPIM23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 524 #define SPIM23_MAX_DATARATE 8 /*!< (unspecified) */ 525 #define SPIM23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 526 #define SPIM23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 527 #define SPIM23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 528 #define SPIM23_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 529 #define SPIM23_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 530 #define SPIM23_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 531 #define SPIM23_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 532 #define SPIM23_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 533 #define SPIM23_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 534 #define SPIM23_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 535 #define SPIM23_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 536 #define SPIM23_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 537 #define SPIM23_PRESCALER_PRESENT 1 /*!< (unspecified) */ 538 #define SPIM23_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 539 #define SPIM23_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 540 #define SPIM23_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 541 #define SPIM23_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 542 #define SPIM23_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 543 #define SPIM23_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 544 #define SPIM23_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 545 #define SPIM23_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 546 #define SPIM23_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 547 #define SPIM23_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 548 549 #define SPIM24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 550 #define SPIM24_MAX_DATARATE 8 /*!< (unspecified) */ 551 #define SPIM24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 552 #define SPIM24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 553 #define SPIM24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 554 #define SPIM24_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 555 #define SPIM24_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 556 #define SPIM24_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 557 #define SPIM24_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 558 #define SPIM24_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 559 #define SPIM24_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 560 #define SPIM24_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 561 #define SPIM24_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 562 #define SPIM24_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 563 #define SPIM24_PRESCALER_PRESENT 1 /*!< (unspecified) */ 564 #define SPIM24_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 565 #define SPIM24_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 566 #define SPIM24_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 567 #define SPIM24_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 568 #define SPIM24_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 569 #define SPIM24_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 570 #define SPIM24_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 571 #define SPIM24_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 572 #define SPIM24_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 573 #define SPIM24_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 574 575 #define SPIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 576 #define SPIM30_MAX_DATARATE 8 /*!< (unspecified) */ 577 #define SPIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 578 #define SPIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 579 #define SPIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 580 #define SPIM30_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 581 #define SPIM30_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 582 #define SPIM30_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 583 #define SPIM30_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 584 #define SPIM30_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 585 #define SPIM30_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 586 #define SPIM30_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 587 #define SPIM30_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 588 #define SPIM30_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 589 #define SPIM30_PRESCALER_PRESENT 1 /*!< (unspecified) */ 590 #define SPIM30_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 591 #define SPIM30_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 592 #define SPIM30_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 593 #define SPIM30_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 594 #define SPIM30_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 595 #define SPIM30_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 596 #define SPIM30_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 597 #define SPIM30_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 598 #define SPIM30_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 599 #define SPIM30_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 600 601 /*UART with EasyDMA*/ 602 #define UARTE_PRESENT 1 603 #define UARTE_COUNT 7 604 605 #define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 606 #define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 607 #define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 608 #define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 609 #define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 610 #define UARTE00_CORE_FREQUENCY 256 /*!< Peripheral clock frequency is 256 MHz. */ 611 #define UARTE00_CORE_CLOCK_256 1 /*!< (unspecified) */ 612 #define UARTE00_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 613 #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 614 615 #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 616 #define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 617 #define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 618 #define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 619 #define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 620 #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 621 #define UARTE20_CORE_CLOCK_16 1 /*!< (unspecified) */ 622 #define UARTE20_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 623 #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 624 625 #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 626 #define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 627 #define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 628 #define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 629 #define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 630 #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 631 #define UARTE21_CORE_CLOCK_16 1 /*!< (unspecified) */ 632 #define UARTE21_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 633 #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 634 635 #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 636 #define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 637 #define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 638 #define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 639 #define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 640 #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 641 #define UARTE22_CORE_CLOCK_16 1 /*!< (unspecified) */ 642 #define UARTE22_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 643 #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 644 645 #define UARTE23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 646 #define UARTE23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 647 #define UARTE23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 648 #define UARTE23_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 649 #define UARTE23_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 650 #define UARTE23_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 651 #define UARTE23_CORE_CLOCK_16 1 /*!< (unspecified) */ 652 #define UARTE23_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 653 #define UARTE23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 654 655 #define UARTE24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 656 #define UARTE24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 657 #define UARTE24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 658 #define UARTE24_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 659 #define UARTE24_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 660 #define UARTE24_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 661 #define UARTE24_CORE_CLOCK_16 1 /*!< (unspecified) */ 662 #define UARTE24_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 663 #define UARTE24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 664 665 #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 666 #define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 667 #define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 668 #define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 669 #define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 670 #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 671 #define UARTE30_CORE_CLOCK_16 1 /*!< (unspecified) */ 672 #define UARTE30_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 673 #define UARTE30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 674 675 /*MRAM controller*/ 676 #define MRAMC_PRESENT 1 677 #define MRAMC_COUNT 1 678 679 #define MRAMC_NMRAMWORDSIZE 128 /*!< (unspecified) */ 680 #define MRAMC_NMRAMPAGESIZE 4 /*!< (unspecified) */ 681 #define MRAMC_NNVRPAGESIZE 4 /*!< (unspecified) */ 682 #define MRAMC_NMAINMEMORYSIZE 4 /*!< MRAM main memory size: 4 MB */ 683 #define MRAMC_NNVRPAGES_MIN 0 /*!< Number of MRAM NVR pages: 0..1 */ 684 #define MRAMC_NNVRPAGES_MAX 1 /*!< Number of MRAM NVR pages: 0..1 */ 685 #define MRAMC_NNVRPAGES_SIZE 2 /*!< Number of MRAM NVR pages: 0..1 */ 686 #define MRAMC_NSIZEMRAMWORDS_MIN 1 /*!< Register ERASE.SIZE.SIZE range: 1..262144 */ 687 #define MRAMC_NSIZEMRAMWORDS_MAX 262144 /*!< Register ERASE.SIZE.SIZE range: 1..262144 */ 688 #define MRAMC_NSIZEMRAMWORDS_SIZE 262145 /*!< Register ERASE.SIZE.SIZE range: 1..262144 */ 689 #define MRAMC_MARMDATAWIDTHWORDS_MIN 0 /*!< (unspecified) */ 690 #define MRAMC_MARMDATAWIDTHWORDS_MAX 3 /*!< (unspecified) */ 691 #define MRAMC_MARMDATAWIDTHWORDS_SIZE 4 /*!< (unspecified) */ 692 #define MRAMC_NVRPAGEUPPER 1 /*!< (unspecified) */ 693 #define MRAMC_NVRPAGELOWER 1 /*!< (unspecified) */ 694 #define MRAMC_NVRPAGEENABLENORMALWRITE 1 /*!< (unspecified) */ 695 #define MRAMC_NVRPAGELRSIZEBITS_MIN 24 /*!< (unspecified) */ 696 #define MRAMC_NVRPAGELRSIZEBITS_MAX 27 /*!< (unspecified) */ 697 #define MRAMC_NVRPAGELRSIZEBITS_SIZE 28 /*!< (unspecified) */ 698 #define MRAMC_NVRPAGELRSIZERESET 15 /*!< (unspecified) */ 699 #define MRAMC_NVRPAGELRSIZEVALUE_MIN 0 /*!< (unspecified) */ 700 #define MRAMC_NVRPAGELRSIZEVALUE_MAX 15 /*!< (unspecified) */ 701 #define MRAMC_NVRPAGELRSIZEVALUE_SIZE 16 /*!< (unspecified) */ 702 #define MRAMC_NVRPAGELWSIZEBITS_MIN 28 /*!< (unspecified) */ 703 #define MRAMC_NVRPAGELWSIZEBITS_MAX 31 /*!< (unspecified) */ 704 #define MRAMC_NVRPAGELWSIZEBITS_SIZE 32 /*!< (unspecified) */ 705 #define MRAMC_NVRPAGELWSIZERESET 15 /*!< (unspecified) */ 706 #define MRAMC_NVRPAGELWSIZEVALUE_MIN 0 /*!< (unspecified) */ 707 #define MRAMC_NVRPAGELWSIZEVALUE_MAX 15 /*!< (unspecified) */ 708 #define MRAMC_NVRPAGELWSIZEVALUE_SIZE 16 /*!< (unspecified) */ 709 710 /*GPIO Port*/ 711 #define GPIO_PRESENT 1 712 #define GPIO_COUNT 5 713 714 #define P2_CTRLSEL_MAP1 0 /*!< (unspecified) */ 715 #define P2_CTRLSEL_MAP2 1 /*!< (unspecified) */ 716 #define P2_CTRLSEL_MAP3 0 /*!< (unspecified) */ 717 #define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ 718 #define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ 719 #define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ 720 #define P2_FEATURE_PINS_PRESENT 4095 /*!< (unspecified) */ 721 #define P2_PIN_SENSE_MECHANISM 0 /*!< (unspecified) */ 722 #define P2_DRIVECTRL 0 /*!< (unspecified) */ 723 #define P2_RETAIN 0 /*!< (unspecified) */ 724 #define P2_PWRCTRL 0 /*!< (unspecified) */ 725 #define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ 726 #define P2_BIASCTRL 0 /*!< (unspecified) */ 727 728 #define P1_CTRLSEL_MAP1 0 /*!< (unspecified) */ 729 #define P1_CTRLSEL_MAP2 1 /*!< (unspecified) */ 730 #define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ 731 #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ 732 #define P1_PIN_NUM_MAX 19 /*!< (unspecified) */ 733 #define P1_PIN_NUM_SIZE 20 /*!< (unspecified) */ 734 #define P1_FEATURE_PINS_PRESENT 1048575 /*!< (unspecified) */ 735 #define P1_PIN_SENSE_MECHANISM 1 /*!< (unspecified) */ 736 #define P1_DRIVECTRL 0 /*!< (unspecified) */ 737 #define P1_RETAIN 0 /*!< (unspecified) */ 738 #define P1_PWRCTRL 0 /*!< (unspecified) */ 739 #define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ 740 #define P1_BIASCTRL 0 /*!< (unspecified) */ 741 742 #define P3_CTRLSEL_MAP1 0 /*!< (unspecified) */ 743 #define P3_CTRLSEL_MAP2 1 /*!< (unspecified) */ 744 #define P3_CTRLSEL_MAP3 0 /*!< (unspecified) */ 745 #define P3_PIN_NUM_MIN 0 /*!< (unspecified) */ 746 #define P3_PIN_NUM_MAX 12 /*!< (unspecified) */ 747 #define P3_PIN_NUM_SIZE 13 /*!< (unspecified) */ 748 #define P3_FEATURE_PINS_PRESENT 8191 /*!< (unspecified) */ 749 #define P3_PIN_SENSE_MECHANISM 1 /*!< (unspecified) */ 750 #define P3_DRIVECTRL 0 /*!< (unspecified) */ 751 #define P3_RETAIN 0 /*!< (unspecified) */ 752 #define P3_PWRCTRL 0 /*!< (unspecified) */ 753 #define P3_PIN_OWNER_SEC 0 /*!< (unspecified) */ 754 #define P3_BIASCTRL 0 /*!< (unspecified) */ 755 756 #define P4_CTRLSEL_MAP1 0 /*!< (unspecified) */ 757 #define P4_CTRLSEL_MAP2 1 /*!< (unspecified) */ 758 #define P4_CTRLSEL_MAP3 0 /*!< (unspecified) */ 759 #define P4_PIN_NUM_MIN 0 /*!< (unspecified) */ 760 #define P4_PIN_NUM_MAX 11 /*!< (unspecified) */ 761 #define P4_PIN_NUM_SIZE 12 /*!< (unspecified) */ 762 #define P4_FEATURE_PINS_PRESENT 4095 /*!< (unspecified) */ 763 #define P4_PIN_SENSE_MECHANISM 1 /*!< (unspecified) */ 764 #define P4_DRIVECTRL 0 /*!< (unspecified) */ 765 #define P4_RETAIN 0 /*!< (unspecified) */ 766 #define P4_PWRCTRL 0 /*!< (unspecified) */ 767 #define P4_PIN_OWNER_SEC 0 /*!< (unspecified) */ 768 #define P4_BIASCTRL 0 /*!< (unspecified) */ 769 770 #define P0_CTRLSEL_MAP1 0 /*!< (unspecified) */ 771 #define P0_CTRLSEL_MAP2 1 /*!< (unspecified) */ 772 #define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ 773 #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ 774 #define P0_PIN_NUM_MAX 9 /*!< (unspecified) */ 775 #define P0_PIN_NUM_SIZE 10 /*!< (unspecified) */ 776 #define P0_FEATURE_PINS_PRESENT 1023 /*!< (unspecified) */ 777 #define P0_PIN_SENSE_MECHANISM 1 /*!< (unspecified) */ 778 #define P0_DRIVECTRL 0 /*!< (unspecified) */ 779 #define P0_RETAIN 0 /*!< (unspecified) */ 780 #define P0_PWRCTRL 0 /*!< (unspecified) */ 781 #define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ 782 #define P0_BIASCTRL 0 /*!< (unspecified) */ 783 784 /*Control access port*/ 785 #define CTRLAPPERI_PRESENT 1 786 #define CTRLAPPERI_COUNT 1 787 788 /*Trace and debug control*/ 789 #define TAD_PRESENT 1 790 #define TAD_COUNT 1 791 792 #define TAD_TADFORCEON 0 /*!< (unspecified) */ 793 #define TAD_TAD_HAS_TASKS 0 /*!< (unspecified) */ 794 #define TAD_PDREQCLR 1 /*!< (unspecified) */ 795 796 /*Timer/Counter*/ 797 #define TIMER_PRESENT 1 798 #define TIMER_COUNT 7 799 800 #define TIMER00_CC_NUM_MIN 0 /*!< (unspecified) */ 801 #define TIMER00_CC_NUM_MAX 5 /*!< (unspecified) */ 802 #define TIMER00_CC_NUM_SIZE 6 /*!< (unspecified) */ 803 #define TIMER00_MAX_SIZE_MIN 0 /*!< (unspecified) */ 804 #define TIMER00_MAX_SIZE_MAX 31 /*!< (unspecified) */ 805 #define TIMER00_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 806 #define TIMER00_PCLK_MHZ 256 /*!< Peripheral clock frequency (PCLK) is 256 MHz */ 807 #define TIMER00_PCLK_VARIABLE 1 /*!< (unspecified) */ 808 #define TIMER00_SHUTDOWN_TASK 0 /*!< (unspecified) */ 809 810 #define TIMER10_CC_NUM_MIN 0 /*!< (unspecified) */ 811 #define TIMER10_CC_NUM_MAX 7 /*!< (unspecified) */ 812 #define TIMER10_CC_NUM_SIZE 8 /*!< (unspecified) */ 813 #define TIMER10_MAX_SIZE_MIN 0 /*!< (unspecified) */ 814 #define TIMER10_MAX_SIZE_MAX 31 /*!< (unspecified) */ 815 #define TIMER10_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 816 #define TIMER10_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ 817 #define TIMER10_PCLK_VARIABLE 0 /*!< (unspecified) */ 818 #define TIMER10_SHUTDOWN_TASK 0 /*!< (unspecified) */ 819 820 #define TIMER20_CC_NUM_MIN 0 /*!< (unspecified) */ 821 #define TIMER20_CC_NUM_MAX 5 /*!< (unspecified) */ 822 #define TIMER20_CC_NUM_SIZE 6 /*!< (unspecified) */ 823 #define TIMER20_MAX_SIZE_MIN 0 /*!< (unspecified) */ 824 #define TIMER20_MAX_SIZE_MAX 31 /*!< (unspecified) */ 825 #define TIMER20_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 826 #define TIMER20_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 827 #define TIMER20_PCLK_VARIABLE 0 /*!< (unspecified) */ 828 #define TIMER20_SHUTDOWN_TASK 0 /*!< (unspecified) */ 829 830 #define TIMER21_CC_NUM_MIN 0 /*!< (unspecified) */ 831 #define TIMER21_CC_NUM_MAX 5 /*!< (unspecified) */ 832 #define TIMER21_CC_NUM_SIZE 6 /*!< (unspecified) */ 833 #define TIMER21_MAX_SIZE_MIN 0 /*!< (unspecified) */ 834 #define TIMER21_MAX_SIZE_MAX 31 /*!< (unspecified) */ 835 #define TIMER21_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 836 #define TIMER21_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 837 #define TIMER21_PCLK_VARIABLE 0 /*!< (unspecified) */ 838 #define TIMER21_SHUTDOWN_TASK 0 /*!< (unspecified) */ 839 840 #define TIMER22_CC_NUM_MIN 0 /*!< (unspecified) */ 841 #define TIMER22_CC_NUM_MAX 5 /*!< (unspecified) */ 842 #define TIMER22_CC_NUM_SIZE 6 /*!< (unspecified) */ 843 #define TIMER22_MAX_SIZE_MIN 0 /*!< (unspecified) */ 844 #define TIMER22_MAX_SIZE_MAX 31 /*!< (unspecified) */ 845 #define TIMER22_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 846 #define TIMER22_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 847 #define TIMER22_PCLK_VARIABLE 0 /*!< (unspecified) */ 848 #define TIMER22_SHUTDOWN_TASK 0 /*!< (unspecified) */ 849 850 #define TIMER23_CC_NUM_MIN 0 /*!< (unspecified) */ 851 #define TIMER23_CC_NUM_MAX 5 /*!< (unspecified) */ 852 #define TIMER23_CC_NUM_SIZE 6 /*!< (unspecified) */ 853 #define TIMER23_MAX_SIZE_MIN 0 /*!< (unspecified) */ 854 #define TIMER23_MAX_SIZE_MAX 31 /*!< (unspecified) */ 855 #define TIMER23_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 856 #define TIMER23_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 857 #define TIMER23_PCLK_VARIABLE 0 /*!< (unspecified) */ 858 #define TIMER23_SHUTDOWN_TASK 0 /*!< (unspecified) */ 859 860 #define TIMER24_CC_NUM_MIN 0 /*!< (unspecified) */ 861 #define TIMER24_CC_NUM_MAX 5 /*!< (unspecified) */ 862 #define TIMER24_CC_NUM_SIZE 6 /*!< (unspecified) */ 863 #define TIMER24_MAX_SIZE_MIN 0 /*!< (unspecified) */ 864 #define TIMER24_MAX_SIZE_MAX 31 /*!< (unspecified) */ 865 #define TIMER24_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 866 #define TIMER24_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 867 #define TIMER24_PCLK_VARIABLE 0 /*!< (unspecified) */ 868 #define TIMER24_SHUTDOWN_TASK 0 /*!< (unspecified) */ 869 870 /*Event generator unit*/ 871 #define EGU_PRESENT 1 872 #define EGU_COUNT 3 873 874 #define EGU00_PEND 0 /*!< (unspecified) */ 875 #define EGU00_CH_NUM_MIN 0 /*!< (unspecified) */ 876 #define EGU00_CH_NUM_MAX 5 /*!< (unspecified) */ 877 #define EGU00_CH_NUM_SIZE 6 /*!< (unspecified) */ 878 879 #define EGU10_PEND 0 /*!< (unspecified) */ 880 #define EGU10_CH_NUM_MIN 0 /*!< (unspecified) */ 881 #define EGU10_CH_NUM_MAX 15 /*!< (unspecified) */ 882 #define EGU10_CH_NUM_SIZE 16 /*!< (unspecified) */ 883 884 #define EGU20_PEND 0 /*!< (unspecified) */ 885 #define EGU20_CH_NUM_MIN 0 /*!< (unspecified) */ 886 #define EGU20_CH_NUM_MAX 5 /*!< (unspecified) */ 887 #define EGU20_CH_NUM_SIZE 6 /*!< (unspecified) */ 888 889 /*CRACEN*/ 890 #define CRACEN_PRESENT 1 891 #define CRACEN_COUNT 1 892 893 #define CRACEN_CRYPTOACCELERATOR 1 /*!< (unspecified) */ 894 #define CRACEN_SEEDRAMLOCK 0 /*!< (unspecified) */ 895 #define CRACEN_SPLITKEYRAMLOCK 1 /*!< (unspecified) */ 896 #define CRACEN_SEEDALIGNED 1 /*!< (unspecified) */ 897 #define CRACEN_PROTECTED_RAM_SEED 0x51810000 /*!< (unspecified) */ 898 #define CRACEN_PROTECTED_RAM_SEED_SIZE 64 /*!< (unspecified) */ 899 #define CRACEN_PROTECTED_RAM_AES_KEY0 0x51810040 /*!< (unspecified) */ 900 #define CRACEN_PROTECTED_RAM_AES_KEY0_SIZE 32 /*!< (unspecified) */ 901 #define CRACEN_PROTECTED_RAM_AES_KEY1 0x51810060 /*!< (unspecified) */ 902 #define CRACEN_PROTECTED_RAM_AES_KEY1_SIZE 32 /*!< (unspecified) */ 903 #define CRACEN_PROTECTED_RAM_SM4_KEY0 0x51810080 /*!< (unspecified) */ 904 #define CRACEN_PROTECTED_RAM_SM4_KEY0_SIZE 16 /*!< (unspecified) */ 905 #define CRACEN_PROTECTED_RAM_SM4_KEY1 0x51810090 /*!< (unspecified) */ 906 #define CRACEN_PROTECTED_RAM_SM4_KEY1_SIZE 16 /*!< (unspecified) */ 907 #define CRACEN_PROTECTED_RAM_SM4_KEY2 0x518100A0 /*!< (unspecified) */ 908 #define CRACEN_PROTECTED_RAM_SM4_KEY2_SIZE 16 /*!< (unspecified) */ 909 #define CRACEN_PROTECTED_RAM_SM4_KEY3 0x518100B0 /*!< (unspecified) */ 910 #define CRACEN_PROTECTED_RAM_SM4_KEY3_SIZE 16 /*!< (unspecified) */ 911 #define CRACEN_PROTECTED_RAM_RESERVED 0x518100C0 /*!< (unspecified) */ 912 #define CRACEN_PROTECTED_RAM_RESERVED_SIZE 64 /*!< (unspecified) */ 913 #define CRACEN_PKEDATA 0x50018000 /*!< PKE data (address 0x50018000) must be read and written using aligned 914 access, i.e. using an operation where a word-aligned address is used 915 for a word, or a halfword-aligned address is used for a halfword 916 access.*/ 917 #define CRACEN_PKECODE 0x5001C000 /*!< PKE code (address 0x5001C000) must be read and written using aligned 918 access, i.e. using an operation where a word-aligned address is used 919 for a word, or a halfword-aligned address is used for a halfword 920 access.*/ 921 922 /*USBHS*/ 923 #define USBHS_PRESENT 1 924 #define USBHS_COUNT 1 925 926 #define USBHS_HAS_SOF_EVENT 1 /*!< (unspecified) */ 927 #define USBHS_RTUNE_AVAILABLE 1 /*!< (unspecified) */ 928 929 /*Quad serial peripheral interface*/ 930 #define QSPI_PRESENT 1 931 #define QSPI_COUNT 2 932 933 #define QSPI00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 934 #define QSPI00_FIFO_DEPTH 16 /*!< Depth of the transmit and receive FIFOs is 16 */ 935 936 #define QSPI01_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 937 #define QSPI01_FIFO_DEPTH 16 /*!< Depth of the transmit and receive FIFOs is 16 */ 938 939 /*2.4 GHz radio*/ 940 #define RADIO_PRESENT 1 941 #define RADIO_COUNT 1 942 943 #define RADIO_IRQ_COUNT 2 944 #define RADIO_WHITENINGPOLY 1 /*!< (unspecified) */ 945 #define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< (unspecified) */ 946 947 /*IPCT APB registers*/ 948 #define IPCT_PRESENT 1 949 #define IPCT_COUNT 1 950 951 #define IPCT10_IRQ_COUNT 4 952 953 /*SPI Slave*/ 954 #define SPIS_PRESENT 1 955 #define SPIS_COUNT 6 956 957 #define SPIS20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 958 #define SPIS20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 959 #define SPIS20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 960 #define SPIS20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 961 962 #define SPIS21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 963 #define SPIS21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 964 #define SPIS21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 965 #define SPIS21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 966 967 #define SPIS22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 968 #define SPIS22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 969 #define SPIS22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 970 #define SPIS22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 971 972 #define SPIS23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 973 #define SPIS23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 974 #define SPIS23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 975 #define SPIS23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 976 977 #define SPIS24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 978 #define SPIS24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 979 #define SPIS24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 980 #define SPIS24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 981 982 #define SPIS30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 983 #define SPIS30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 984 #define SPIS30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 985 #define SPIS30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 986 987 /*I2C compatible Two-Wire Master Interface with EasyDMA*/ 988 #define TWIM_PRESENT 1 989 #define TWIM_COUNT 6 990 991 #define TWIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 992 #define TWIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 993 #define TWIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 994 #define TWIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 995 996 #define TWIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 997 #define TWIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 998 #define TWIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 999 #define TWIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1000 1001 #define TWIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1002 #define TWIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1003 #define TWIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1004 #define TWIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1005 1006 #define TWIM23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1007 #define TWIM23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1008 #define TWIM23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1009 #define TWIM23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1010 1011 #define TWIM24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1012 #define TWIM24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1013 #define TWIM24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1014 #define TWIM24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1015 1016 #define TWIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1017 #define TWIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1018 #define TWIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1019 #define TWIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1020 1021 /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ 1022 #define TWIS_PRESENT 1 1023 #define TWIS_COUNT 6 1024 1025 #define TWIS20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1026 #define TWIS20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1027 #define TWIS20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1028 #define TWIS20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1029 1030 #define TWIS21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1031 #define TWIS21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1032 #define TWIS21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1033 #define TWIS21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1034 1035 #define TWIS22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1036 #define TWIS22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1037 #define TWIS22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1038 #define TWIS22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1039 1040 #define TWIS23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1041 #define TWIS23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1042 #define TWIS23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1043 #define TWIS23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1044 1045 #define TWIS24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1046 #define TWIS24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1047 #define TWIS24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1048 #define TWIS24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1049 1050 #define TWIS30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 1051 #define TWIS30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 1052 #define TWIS30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 1053 #define TWIS30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1054 1055 /*Memory configuration*/ 1056 #define MEMCONF_PRESENT 1 1057 #define MEMCONF_COUNT 1 1058 1059 #define MEMCONF_RETTRIM 1 /*!< (unspecified) */ 1060 #define MEMCONF_REPAIR 0 /*!< (unspecified) */ 1061 #define MEMCONF_POWER 1 /*!< (unspecified) */ 1062 1063 /*Pulse Density Modulation (Digital Microphone) Interface*/ 1064 #define PDM_PRESENT 1 1065 #define PDM_COUNT 2 1066 1067 #define PDM20_SAMPLE16 0 /*!< (unspecified) */ 1068 #define PDM20_SAMPLE48 1 /*!< (unspecified) */ 1069 #define PDM20_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1070 #define PDM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1071 1072 #define PDM21_SAMPLE16 0 /*!< (unspecified) */ 1073 #define PDM21_SAMPLE48 1 /*!< (unspecified) */ 1074 #define PDM21_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1075 #define PDM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1076 1077 /*Pulse width modulation unit*/ 1078 #define PWM_PRESENT 1 1079 #define PWM_COUNT 3 1080 1081 #define PWM20_IDLE_OUT 1 /*!< (unspecified) */ 1082 #define PWM20_COMPARE_MATCH 1 /*!< (unspecified) */ 1083 #define PWM20_FEATURES_V2 0 /*!< (unspecified) */ 1084 #define PWM20_NO_FEATURES_V2 1 /*!< (unspecified) */ 1085 #define PWM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1086 1087 #define PWM21_IDLE_OUT 1 /*!< (unspecified) */ 1088 #define PWM21_COMPARE_MATCH 1 /*!< (unspecified) */ 1089 #define PWM21_FEATURES_V2 0 /*!< (unspecified) */ 1090 #define PWM21_NO_FEATURES_V2 1 /*!< (unspecified) */ 1091 #define PWM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1092 1093 #define PWM22_IDLE_OUT 1 /*!< (unspecified) */ 1094 #define PWM22_COMPARE_MATCH 1 /*!< (unspecified) */ 1095 #define PWM22_FEATURES_V2 0 /*!< (unspecified) */ 1096 #define PWM22_NO_FEATURES_V2 1 /*!< (unspecified) */ 1097 #define PWM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1098 1099 /*Analog to Digital Converter*/ 1100 #define SAADC_PRESENT 1 1101 #define SAADC_COUNT 1 1102 1103 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ 1104 #define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ 1105 #define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ 1106 #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ 1107 #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ 1108 #define SAADC_TACQ_VALUE_RANGE_MIN 1 /*!< (unspecified) */ 1109 #define SAADC_TACQ_VALUE_RANGE_MAX 319 /*!< (unspecified) */ 1110 #define SAADC_TACQ_VALUE_RANGE_SIZE 320 /*!< (unspecified) */ 1111 #define SAADC_TCONV_VALUE_RANGE_MIN 1 /*!< (unspecified) */ 1112 #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 1113 #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 1114 #define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1115 1116 /*NFC-A compatible radio NFC-A compatible radio*/ 1117 #define NFCT_PRESENT 1 1118 #define NFCT_COUNT 1 1119 1120 #define NFCT_NFCTFIELDDETCFG_RESET 1 /*!< Reset value of register NFCTFIELDDETCFG: 1 */ 1121 1122 /*Temperature Sensor*/ 1123 #define TEMP_PRESENT 1 1124 #define TEMP_COUNT 1 1125 1126 /*GPIO Tasks and Events*/ 1127 #define GPIOTE_PRESENT 1 1128 #define GPIOTE_COUNT 2 1129 1130 #define GPIOTE20_IRQ_COUNT 2 1131 #define GPIOTE20_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 1132 #define GPIOTE20_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 1133 #define GPIOTE20_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 1134 #define GPIOTE20_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..0 */ 1135 #define GPIOTE20_GPIOTE_NPORTEVENTS_MAX 0 /*!< Number of GPIOTE port events: 0..0 */ 1136 #define GPIOTE20_GPIOTE_NPORTEVENTS_SIZE 1 /*!< Number of GPIOTE port events: 0..0 */ 1137 #define GPIOTE20_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 1138 #define GPIOTE20_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 1139 #define GPIOTE20_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 1140 #define GPIOTE20_HAS_PORT_EVENT 1 /*!< (unspecified) */ 1141 1142 #define GPIOTE30_IRQ_COUNT 2 1143 #define GPIOTE30_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..3 */ 1144 #define GPIOTE30_GPIOTE_NCHANNELS_MAX 3 /*!< Number of GPIOTE channels: 0..3 */ 1145 #define GPIOTE30_GPIOTE_NCHANNELS_SIZE 4 /*!< Number of GPIOTE channels: 0..3 */ 1146 #define GPIOTE30_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..0 */ 1147 #define GPIOTE30_GPIOTE_NPORTEVENTS_MAX 0 /*!< Number of GPIOTE port events: 0..0 */ 1148 #define GPIOTE30_GPIOTE_NPORTEVENTS_SIZE 1 /*!< Number of GPIOTE port events: 0..0 */ 1149 #define GPIOTE30_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 1150 #define GPIOTE30_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 1151 #define GPIOTE30_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 1152 #define GPIOTE30_HAS_PORT_EVENT 1 /*!< (unspecified) */ 1153 1154 /*Quadrature Decoder*/ 1155 #define QDEC_PRESENT 1 1156 #define QDEC_COUNT 2 1157 1158 /*Global Real-time counter*/ 1159 #define GRTC_PRESENT 1 1160 #define GRTC_COUNT 1 1161 1162 #define GRTC_IRQ_COUNT 6 1163 #define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 1164 0..14*/ 1165 #define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 1166 0..14*/ 1167 #define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 1168 0..14*/ 1169 #define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ 1170 #define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ 1171 #define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ 1172 #define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ 1173 #define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ 1174 #define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ 1175 #define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..5 */ 1176 #define GRTC_GRTC_NINTERRUPTS_MAX 5 /*!< Number of GRTC interrupts : 0..5 */ 1177 #define GRTC_GRTC_NINTERRUPTS_SIZE 6 /*!< Number of GRTC interrupts : 0..5 */ 1178 #define GRTC_PWMREGS 1 /*!< (unspecified) */ 1179 #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ 1180 #define GRTC_CLKSELREG 1 /*!< (unspecified) */ 1181 #define GRTC_CLKSELLFLPRC 1 /*!< (unspecified) */ 1182 #define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ 1183 #define GRTC_READY_STATUS_AND_EVENTS 0 /*!< (unspecified) */ 1184 #define GRTC_SYSCOUNTER_LOADED_STATUS 1 /*!< (unspecified) */ 1185 #define GRTC_CC_PAST_STATUS 1 /*!< (unspecified) */ 1186 #define GRTC_SYSCOUNTER_WRITEABLE 1 /*!< (unspecified) */ 1187 1188 /*Time division multiplexed audio interface*/ 1189 #define TDM_PRESENT 1 1190 #define TDM_COUNT 1 1191 1192 #define TDM_NUM_CHANNELS_MIN 0 /*!< (unspecified) */ 1193 #define TDM_NUM_CHANNELS_MAX 7 /*!< (unspecified) */ 1194 #define TDM_NUM_CHANNELS_SIZE 8 /*!< (unspecified) */ 1195 #define TDM_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1196 1197 /*AUXPLL*/ 1198 #define AUXPLL_PRESENT 1 1199 #define AUXPLL_COUNT 1 1200 1201 /*AUXPM*/ 1202 #define AUXPM_PRESENT 1 1203 #define AUXPM_COUNT 1 1204 1205 /*Tamper controller*/ 1206 #define TAMPC_PRESENT 1 1207 #define TAMPC_COUNT 1 1208 1209 #define TAMPC_APSPIDEN 0 /*!< (unspecified) */ 1210 #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 1 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 1 */ 1211 #define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ 1212 1213 /*Coexistence controller*/ 1214 #define COEXC_PRESENT 1 1215 #define COEXC_COUNT 1 1216 1217 #define COEXC_NCLIENTS_MIN 0 /*!< Number of clients supported : 0..7 */ 1218 #define COEXC_NCLIENTS_MAX 7 /*!< Number of clients supported : 0..7 */ 1219 #define COEXC_NCLIENTS_SIZE 8 /*!< Number of clients supported : 0..7 */ 1220 #define COEXC_NMODES_MIN 0 /*!< Number of modes per client: 0..1 */ 1221 #define COEXC_NMODES_MAX 1 /*!< Number of modes per client: 0..1 */ 1222 #define COEXC_NMODES_SIZE 2 /*!< Number of modes per client: 0..1 */ 1223 #define COEXC_NCCMALLOWMODES_MIN 0 /*!< (unspecified) */ 1224 #define COEXC_NCCMALLOWMODES_MAX 1 /*!< (unspecified) */ 1225 #define COEXC_NCCMALLOWMODES_SIZE 2 /*!< (unspecified) */ 1226 #define COEXC_NPRIORITYBITS_MIN 16 /*!< CCCONF priority bits : 16..23 */ 1227 #define COEXC_NPRIORITYBITS_MAX 23 /*!< CCCONF priority bits : 16..23 */ 1228 #define COEXC_NPRIORITYBITS_SIZE 24 /*!< CCCONF priority bits : 16..23 */ 1229 1230 /*Comparator*/ 1231 #define COMP_PRESENT 1 1232 #define COMP_COUNT 1 1233 1234 /*Low-power comparator*/ 1235 #define LPCOMP_PRESENT 1 1236 #define LPCOMP_COUNT 1 1237 1238 /*Watchdog Timer*/ 1239 #define WDT_PRESENT 1 1240 #define WDT_COUNT 2 1241 1242 #define WDT30_ALLOW_STOP 1 /*!< (unspecified) */ 1243 #define WDT30_HAS_INTEN 0 /*!< (unspecified) */ 1244 1245 #define WDT31_ALLOW_STOP 1 /*!< (unspecified) */ 1246 #define WDT31_HAS_INTEN 0 /*!< (unspecified) */ 1247 1248 /*Clock management*/ 1249 #define CLOCK_PRESENT 1 1250 #define CLOCK_COUNT 1 1251 1252 #define CLOCK_XOTUNE 0 /*!< (unspecified) */ 1253 #define CLOCK_PLL24M 1 /*!< (unspecified) */ 1254 1255 /*Power control*/ 1256 #define POWER_PRESENT 1 1257 #define POWER_COUNT 1 1258 1259 #define POWER_CONSTLATSTAT 1 /*!< (unspecified) */ 1260 1261 /*Reset control*/ 1262 #define RESET_PRESENT 1 1263 #define RESET_COUNT 1 1264 1265 /*Voltage glitch detectors*/ 1266 #define GLITCHDET_PRESENT 1 1267 #define GLITCHDET_COUNT 1 1268 1269 /*Oscillator control*/ 1270 #define OSCILLATORS_PRESENT 1 1271 #define OSCILLATORS_COUNT 1 1272 1273 /*Voltage regulators*/ 1274 #define REGULATORS_PRESENT 1 1275 #define REGULATORS_COUNT 1 1276 1277 /*VREGUSB peripheral*/ 1278 #define VREGUSB_PRESENT 1 1279 #define VREGUSB_COUNT 1 1280 1281 #define VREGUSB_PROLONGED_WAKEUP 0 /*!< (unspecified) */ 1282 1283 /*LFXO peripheral*/ 1284 #define LFXO_PRESENT 1 1285 #define LFXO_COUNT 1 1286 1287 /*LFRC peripheral*/ 1288 #define LFRC_PRESENT 1 1289 #define LFRC_COUNT 1 1290 1291 /*HFXO64M peripheral*/ 1292 #define HFXO64M_PRESENT 1 1293 #define HFXO64M_COUNT 1 1294 1295 /*VREGMRAM peripheral*/ 1296 #define VREGMRAM_PRESENT 1 1297 #define VREGMRAM_COUNT 1 1298 1299 /*OSCRFR peripheral*/ 1300 #define OSCRFR_PRESENT 1 1301 #define OSCRFR_COUNT 1 1302 1303 /*VDETAO1V8 peripheral*/ 1304 #define VDETAO1V8_PRESENT 1 1305 #define VDETAO1V8_COUNT 1 1306 1307 /*VDETAO0V8 peripheral*/ 1308 #define VDETAO0V8_PRESENT 1 1309 #define VDETAO0V8_COUNT 1 1310 1311 /*VDETIO peripheral*/ 1312 #define VDETIO_PRESENT 1 1313 #define VDETIO_COUNT 1 1314 1315 #define VDETIO_CONFIG_PWRGOOD_RESET 30 /*!< Reset value of register CONFIG.PWRGOOD: 30 */ 1316 #define VDETIO_NPORTS_MIN 0 /*!< Number of ports supported : 0..4 */ 1317 #define VDETIO_NPORTS_MAX 4 /*!< Number of ports supported : 0..4 */ 1318 #define VDETIO_NPORTS_SIZE 5 /*!< Number of ports supported : 0..4 */ 1319 1320 /* ==================================================== Baudrate settings ==================================================== */ 1321 /** 1322 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1323 */ 1324 typedef enum { 1325 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core64M = 77824, /*!< 1200 baud (actual rate: 1161, -3.2 percent error), 64 MHz core 1326 frequency*/ 1327 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core64M = 159744, /*!< 2400 baud (actual rate: 2384, -0.7 percent error), 64 MHz core 1328 frequency*/ 1329 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core64M = 319488, /*!< 4800 baud (actual rate: 4768, -0.7 percent error), 64 MHz core 1330 frequency*/ 1331 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core64M = 643072, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 64 MHz core 1332 frequency*/ 1333 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core64M = 962560, /*!< 14400 baud (actual rate: 14366, -0.2 percent error), 64 MHz core 1334 frequency*/ 1335 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core64M = 1286144, /*!< 19200 baud (actual rate: 19196, -0.0 percent error), 64 MHz 1336 core frequency*/ 1337 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core64M = 1929216, /*!< 28800 baud (actual rate: 28794, -0.0 percent error), 64 MHz 1338 core frequency*/ 1339 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core64M = 2097152, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 64 MHz core 1340 frequency*/ 1341 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core64M = 2576384, /*!< 38400 baud (actual rate: 38453, 0.1 percent error), 64 MHz core 1342 frequency*/ 1343 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core64M = 3756032, /*!< 56000 baud (actual rate: 56060, 0.1 percent error), 64 MHz core 1344 frequency*/ 1345 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core64M = 3862528, /*!< 57600 baud (actual rate: 57649, 0.1 percent error), 64 MHz core 1346 frequency*/ 1347 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core64M = 5152768, /*!< 76800 baud (actual rate: 76906, 0.1 percent error), 64 MHz core 1348 frequency*/ 1349 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core64M = 7720960, /*!< 115200 baud (actual rate: 115238, 0.0 percent error), 64 MHz 1350 core frequency*/ 1351 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core64M = 15446016, /*!< 230400 baud (actual rate: 230537, 0.1 percent error), 64 MHz 1352 core frequency*/ 1353 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core64M = 16777216, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 64 MHz 1354 core frequency*/ 1355 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core64M = 30896128, /*!< 460800 baud (actual rate: 461136, 0.1 percent error), 64 MHz 1356 core frequency*/ 1357 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core64M = 62242816, /*!< 921600 baud (actual rate: 928997, 0.8 percent error), 64 MHz 1358 core frequency*/ 1359 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core64M = 67108864, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 64 1360 MHz core frequency*/ 1361 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core128M = 36864, /*!< 1200 baud (actual rate: 1117, -6.9 percent error), 128 MHz core 1362 frequency*/ 1363 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core128M = 77824, /*!< 2400 baud (actual rate: 2358, -1.7 percent error), 128 MHz core 1364 frequency*/ 1365 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core128M = 159744, /*!< 4800 baud (actual rate: 4840, 0.8 percent error), 128 MHz core 1366 frequency*/ 1367 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core128M = 319488, /*!< 9600 baud (actual rate: 9681, 0.8 percent error), 128 MHz core 1368 frequency*/ 1369 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core128M = 479232, /*!< 14400 baud (actual rate: 14522, 0.8 percent error), 128 MHz 1370 core frequency*/ 1371 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core128M = 643072, /*!< 19200 baud (actual rate: 19487, 1.5 percent error), 128 MHz 1372 core frequency*/ 1373 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core128M = 962560, /*!< 28800 baud (actual rate: 29168, 1.3 percent error), 128 MHz 1374 core frequency*/ 1375 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core128M = 1048576, /*!< 31250 baud (actual rate: 31775, 1.7 percent error), 128 MHz 1376 core frequency*/ 1377 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core128M = 1286144, /*!< 38400 baud (actual rate: 38974, 1.5 percent error), 128 MHz 1378 core frequency*/ 1379 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core128M = 1875968, /*!< 56000 baud (actual rate: 56847, 1.5 percent error), 128 MHz 1380 core frequency*/ 1381 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core128M = 1929216, /*!< 57600 baud (actual rate: 58461, 1.5 percent error), 128 MHz 1382 core frequency*/ 1383 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core128M = 2576384, /*!< 76800 baud (actual rate: 78072, 1.7 percent error), 128 MHz 1384 core frequency*/ 1385 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core128M = 3862528, /*!< 115200 baud (actual rate: 117046, 1.6 percent error), 128 MHz 1386 core frequency*/ 1387 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core128M = 7720960, /*!< 230400 baud (actual rate: 233968, 1.5 percent error), 128 MHz 1388 core frequency*/ 1389 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core128M = 8388608, /*!< 250000 baud (actual rate: 254200, 1.7 percent error), 128 MHz 1390 core frequency*/ 1391 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core128M = 15446016, /*!< 460800 baud (actual rate: 468061, 1.6 percent error), 128 1392 MHz core frequency*/ 1393 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core128M = 30896128, /*!< 921600 baud (actual rate: 936246, 1.6 percent error), 128 1394 MHz core frequency*/ 1395 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core128M = 33554432, /*!< 1000000 baud (actual rate: 1016800, 1.7 percent error), 128 1396 MHz core frequency*/ 1397 } NRF_UARTE00_BAUDRATE_BAUDRATE_ENUM_t; 1398 1399 /* ==================================================== Baudrate settings ==================================================== */ 1400 /** 1401 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1402 */ 1403 typedef enum { 1404 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1405 frequency*/ 1406 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1407 frequency*/ 1408 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1409 frequency*/ 1410 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1411 frequency*/ 1412 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1413 frequency*/ 1414 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1415 frequency*/ 1416 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1417 frequency*/ 1418 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1419 frequency*/ 1420 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1421 core frequency*/ 1422 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1423 core frequency*/ 1424 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1425 core frequency*/ 1426 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1427 core frequency*/ 1428 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1429 core frequency*/ 1430 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1431 core frequency*/ 1432 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1433 core frequency*/ 1434 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1435 MHz core frequency*/ 1436 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1437 core frequency*/ 1438 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1439 MHz core frequency*/ 1440 } NRF_UARTE20_BAUDRATE_BAUDRATE_ENUM_t; 1441 1442 /* ==================================================== Baudrate settings ==================================================== */ 1443 /** 1444 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1445 */ 1446 typedef enum { 1447 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1448 frequency*/ 1449 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1450 frequency*/ 1451 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1452 frequency*/ 1453 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1454 frequency*/ 1455 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1456 frequency*/ 1457 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1458 frequency*/ 1459 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1460 frequency*/ 1461 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1462 frequency*/ 1463 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1464 core frequency*/ 1465 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1466 core frequency*/ 1467 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1468 core frequency*/ 1469 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1470 core frequency*/ 1471 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1472 core frequency*/ 1473 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1474 core frequency*/ 1475 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1476 core frequency*/ 1477 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1478 MHz core frequency*/ 1479 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1480 core frequency*/ 1481 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1482 MHz core frequency*/ 1483 } NRF_UARTE21_BAUDRATE_BAUDRATE_ENUM_t; 1484 1485 /* ==================================================== Baudrate settings ==================================================== */ 1486 /** 1487 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1488 */ 1489 typedef enum { 1490 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1491 frequency*/ 1492 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1493 frequency*/ 1494 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1495 frequency*/ 1496 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1497 frequency*/ 1498 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1499 frequency*/ 1500 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1501 frequency*/ 1502 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1503 frequency*/ 1504 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1505 frequency*/ 1506 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1507 core frequency*/ 1508 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1509 core frequency*/ 1510 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1511 core frequency*/ 1512 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1513 core frequency*/ 1514 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1515 core frequency*/ 1516 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1517 core frequency*/ 1518 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1519 core frequency*/ 1520 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1521 MHz core frequency*/ 1522 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1523 core frequency*/ 1524 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1525 MHz core frequency*/ 1526 } NRF_UARTE22_BAUDRATE_BAUDRATE_ENUM_t; 1527 1528 /* ==================================================== Baudrate settings ==================================================== */ 1529 /** 1530 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1531 */ 1532 typedef enum { 1533 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1534 frequency*/ 1535 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1536 frequency*/ 1537 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1538 frequency*/ 1539 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1540 frequency*/ 1541 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1542 frequency*/ 1543 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1544 frequency*/ 1545 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1546 frequency*/ 1547 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1548 frequency*/ 1549 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1550 core frequency*/ 1551 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1552 core frequency*/ 1553 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1554 core frequency*/ 1555 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1556 core frequency*/ 1557 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1558 core frequency*/ 1559 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1560 core frequency*/ 1561 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1562 core frequency*/ 1563 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1564 MHz core frequency*/ 1565 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1566 core frequency*/ 1567 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1568 MHz core frequency*/ 1569 } NRF_UARTE23_BAUDRATE_BAUDRATE_ENUM_t; 1570 1571 /* ==================================================== Baudrate settings ==================================================== */ 1572 /** 1573 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1574 */ 1575 typedef enum { 1576 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1577 frequency*/ 1578 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1579 frequency*/ 1580 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1581 frequency*/ 1582 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1583 frequency*/ 1584 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1585 frequency*/ 1586 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1587 frequency*/ 1588 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1589 frequency*/ 1590 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1591 frequency*/ 1592 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1593 core frequency*/ 1594 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1595 core frequency*/ 1596 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1597 core frequency*/ 1598 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1599 core frequency*/ 1600 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1601 core frequency*/ 1602 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1603 core frequency*/ 1604 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1605 core frequency*/ 1606 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1607 MHz core frequency*/ 1608 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1609 core frequency*/ 1610 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1611 MHz core frequency*/ 1612 } NRF_UARTE24_BAUDRATE_BAUDRATE_ENUM_t; 1613 1614 /* ==================================================== Baudrate settings ==================================================== */ 1615 /** 1616 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1617 */ 1618 typedef enum { 1619 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1620 frequency*/ 1621 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1622 frequency*/ 1623 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1624 frequency*/ 1625 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1626 frequency*/ 1627 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1628 frequency*/ 1629 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1630 frequency*/ 1631 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1632 frequency*/ 1633 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1634 frequency*/ 1635 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1636 core frequency*/ 1637 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1638 core frequency*/ 1639 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1640 core frequency*/ 1641 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1642 core frequency*/ 1643 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1644 core frequency*/ 1645 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1646 core frequency*/ 1647 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1648 core frequency*/ 1649 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1650 MHz core frequency*/ 1651 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1652 core frequency*/ 1653 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1654 MHz core frequency*/ 1655 } NRF_UARTE30_BAUDRATE_BAUDRATE_ENUM_t; 1656 1657 1658 #ifdef __cplusplus 1659 } 1660 #endif 1661 #endif /* NRF7120_ENGA_WIFICORE_PERIPHERALS_H */ 1662 1663
