1 /* 2 3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF7120_ENGA_UMAC_PERIPHERALS_H 36 #define NRF7120_ENGA_UMAC_PERIPHERALS_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include <stdbool.h> 43 /*VPR CSR registers*/ 44 #define VPRCSR_PRESENT 1 45 #define VPRCSR_COUNT 1 46 47 #define VPRCSR_HARTNUM 5 /*!< HARTNUM: 5 */ 48 #define VPRCSR_MCLICBASERESET 0xF0000000 /*!< MCLICBASE: 0xF0000000 */ 49 #define VPRCSR_MULDIV 2 /*!< MULDIV: 2 */ 50 #define VPRCSR_HIBERNATE 1 /*!< HIBERNATE: 1 */ 51 #define VPRCSR_DBG 1 /*!< DBG: 1 */ 52 #define VPRCSR_REMAP 0 /*!< Code patching (REMAP): 0 */ 53 #define VPRCSR_BUSWIDTH 64 /*!< BUSWIDTH: 64 */ 54 #define VPRCSR_BKPT 1 /*!< BKPT: 1 */ 55 #define VPRCSR_RETAINED 0 /*!< (unspecified) */ 56 #define VPRCSR_VIOPINS 0x00000000 /*!< CSR VIOPINS value: 0x00000000 */ 57 #define VPRCSR_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..23 */ 58 #define VPRCSR_VEVIF_NTASKS_MAX 23 /*!< VEVIF tasks: 16..23 */ 59 #define VPRCSR_VEVIF_NTASKS_SIZE 24 /*!< VEVIF tasks: 16..23 */ 60 #define VPRCSR_VEVIF_TASKS_MASK 0x00FF0000 /*!< Mask of supported VEVIF tasks: 0x00FF0000 */ 61 #define VPRCSR_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..0 */ 62 #define VPRCSR_VEVIF_NDPPI_MAX 0 /*!< VEVIF DPPI channels: 0..0 */ 63 #define VPRCSR_VEVIF_NDPPI_SIZE 1 /*!< VEVIF DPPI channels: 0..0 */ 64 #define VPRCSR_VEVIF_NEVENTS_MIN 0 /*!< VEVIF events: 0..31 */ 65 #define VPRCSR_VEVIF_NEVENTS_MAX 31 /*!< VEVIF events: 0..31 */ 66 #define VPRCSR_VEVIF_NEVENTS_SIZE 32 /*!< VEVIF events: 0..31 */ 67 #define VPRCSR_BEXT 1 /*!< Bit-Manipulation extension: 1 */ 68 #define VPRCSR_CACHE_EN 1 /*!< (unspecified) */ 69 #define VPRCSR_CACHEEXTRATAGBUF 1 /*!< CACHEEXTRATAGBUF: 1 */ 70 #define VPRCSR_OUTMODE_VPR1_2 1 /*!< (unspecified) */ 71 #define VPRCSR_VPR_BUS_PRIO 1 /*!< (unspecified) */ 72 #define VPRCSR_NMIMPID_VPR1_3_3 0 /*!< (unspecified) */ 73 #define VPRCSR_PERIPHERALBLOCKINGACCESS 0 /*!< (unspecified) */ 74 #define VPRCSR_BRANCHPREDECODING 0 /*!< (unspecified) */ 75 #define VPRCSR_RTP_VPR_1_5 1 /*!< (unspecified) */ 76 77 /*VPR CLIC registers*/ 78 #define CLIC_PRESENT 1 79 #define CLIC_COUNT 1 80 81 #define VPRCLIC_IRQ_COUNT 8 82 #define VPRCLIC_IRQNUM_MIN 0 /*!< Supported interrupts (IRQNUM): 0..480 */ 83 #define VPRCLIC_IRQNUM_MAX 480 /*!< Supported interrupts (IRQNUM): 0..480 */ 84 #define VPRCLIC_IRQNUM_SIZE 481 /*!< Supported interrupts (IRQNUM): 0..480 */ 85 #define VPRCLIC_CLIC_NTASKS_MIN 16 /*!< VEVIF tasks: 16..23 */ 86 #define VPRCLIC_CLIC_NTASKS_MAX 23 /*!< VEVIF tasks: 16..23 */ 87 #define VPRCLIC_CLIC_NTASKS_SIZE 24 /*!< VEVIF tasks: 16..23 */ 88 #define VPRCLIC_CLIC_TASKS_MASK 0x00FF0000 /*!< Mask of supported VEVIF tasks: 0x00FF0000 */ 89 #define VPRCLIC_COUNTER_IRQ_NUM 7 /*!< VPR counter (CNT0) interrupt handler number (COUNTER_IRQ_NUM): 7 */ 90 #define VPRCLIC_CLIC_VPR_1_2 1 /*!< (unspecified) */ 91 92 /*Factory Information Configuration Registers*/ 93 #define FICR_PRESENT 1 94 #define FICR_COUNT 1 95 96 /*User Information Configuration Registers*/ 97 #define UICR_PRESENT 1 98 #define UICR_COUNT 1 99 100 #define UICR_MRAM 1 /*!< (unspecified) */ 101 102 /*Factory Information Configuration Registers*/ 103 #define SICR_PRESENT 1 104 #define SICR_COUNT 1 105 106 /*CRACENCORE*/ 107 #define CRACENCORE_PRESENT 1 108 #define CRACENCORE_COUNT 1 109 110 #define CRACENCORE_CRYPTMSTRDMAREGS 1 /*!< (unspecified) */ 111 #define CRACENCORE_CRYPTMSTRHWREGS 1 /*!< (unspecified) */ 112 #define CRACENCORE_RNGCONTROLREGS 1 /*!< (unspecified) */ 113 #define CRACENCORE_PKREGS 1 /*!< (unspecified) */ 114 #define CRACENCORE_IKGREGS 1 /*!< (unspecified) */ 115 #define CRACENCORE_RNGDATAREGS 1 /*!< (unspecified) */ 116 #define CRACENCORE_EXTPRIVKEYSREGS 0 /*!< (unspecified) */ 117 #define CRACENCORE_LITESMALLRESETVALUES 0 /*!< (unspecified) */ 118 #define CRACENCORE_LITEMEDIUMRESETVALUES 1 /*!< (unspecified) */ 119 #define CRACENCORE_FULLRESETVALUES 0 /*!< (unspecified) */ 120 #define CRACENCORE_CRACENRESETVALUES 1 /*!< (unspecified) */ 121 #define CRACENCORE_SHA3RESETVALUES 0 /*!< (unspecified) */ 122 #define CRACENCORE_PKE_DATA_MEMORY 0x50018000 /*!< (unspecified) */ 123 #define CRACENCORE_PKE_DATA_MEMORY_SIZE 16384 /*!< (unspecified) */ 124 #define CRACENCORE_PKE_CODE_MEMORY 0x5001C000 /*!< (unspecified) */ 125 #define CRACENCORE_PKE_CODE_MEMORY_SIZE 8192 /*!< (unspecified) */ 126 127 /*USBHSCORE*/ 128 #define USBHSCORE_PRESENT 1 129 #define USBHSCORE_COUNT 1 130 131 /*System protection unit*/ 132 #define SPU_PRESENT 1 133 #define SPU_COUNT 4 134 135 #define SPU00_BELLS 0 /*!< (unspecified) */ 136 #define SPU00_IPCT 0 /*!< (unspecified) */ 137 #define SPU00_DPPI 1 /*!< (unspecified) */ 138 #define SPU00_GPIOTE 0 /*!< (unspecified) */ 139 #define SPU00_GRTC 0 /*!< (unspecified) */ 140 #define SPU00_GPIO 1 /*!< (unspecified) */ 141 #define SPU00_CRACEN 0 /*!< (unspecified) */ 142 #define SPU00_MRAMC 0 /*!< (unspecified) */ 143 #define SPU00_COEXC 0 /*!< (unspecified) */ 144 #define SPU00_ANTSWC 0 /*!< (unspecified) */ 145 #define SPU00_TDD 0 /*!< (unspecified) */ 146 #define SPU00_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 147 peripheral slave index)*/ 148 149 #define SPU10_BELLS 0 /*!< (unspecified) */ 150 #define SPU10_IPCT 0 /*!< (unspecified) */ 151 #define SPU10_DPPI 1 /*!< (unspecified) */ 152 #define SPU10_GPIOTE 0 /*!< (unspecified) */ 153 #define SPU10_GRTC 0 /*!< (unspecified) */ 154 #define SPU10_GPIO 0 /*!< (unspecified) */ 155 #define SPU10_CRACEN 0 /*!< (unspecified) */ 156 #define SPU10_MRAMC 0 /*!< (unspecified) */ 157 #define SPU10_COEXC 0 /*!< (unspecified) */ 158 #define SPU10_ANTSWC 0 /*!< (unspecified) */ 159 #define SPU10_TDD 0 /*!< (unspecified) */ 160 #define SPU10_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 161 peripheral slave index)*/ 162 163 #define SPU20_BELLS 0 /*!< (unspecified) */ 164 #define SPU20_IPCT 0 /*!< (unspecified) */ 165 #define SPU20_DPPI 1 /*!< (unspecified) */ 166 #define SPU20_GPIOTE 1 /*!< (unspecified) */ 167 #define SPU20_GRTC 1 /*!< (unspecified) */ 168 #define SPU20_GPIO 1 /*!< (unspecified) */ 169 #define SPU20_CRACEN 0 /*!< (unspecified) */ 170 #define SPU20_MRAMC 0 /*!< (unspecified) */ 171 #define SPU20_COEXC 1 /*!< (unspecified) */ 172 #define SPU20_ANTSWC 0 /*!< (unspecified) */ 173 #define SPU20_TDD 0 /*!< (unspecified) */ 174 #define SPU20_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 175 peripheral slave index)*/ 176 177 #define SPU30_BELLS 0 /*!< (unspecified) */ 178 #define SPU30_IPCT 0 /*!< (unspecified) */ 179 #define SPU30_DPPI 1 /*!< (unspecified) */ 180 #define SPU30_GPIOTE 1 /*!< (unspecified) */ 181 #define SPU30_GRTC 0 /*!< (unspecified) */ 182 #define SPU30_GPIO 1 /*!< (unspecified) */ 183 #define SPU30_CRACEN 0 /*!< (unspecified) */ 184 #define SPU30_MRAMC 0 /*!< (unspecified) */ 185 #define SPU30_COEXC 0 /*!< (unspecified) */ 186 #define SPU30_ANTSWC 0 /*!< (unspecified) */ 187 #define SPU30_TDD 0 /*!< (unspecified) */ 188 #define SPU30_SLAVE_BITS 4 /*!< SLAVE_BITS=4 (number of address bits required to represent the 189 peripheral slave index)*/ 190 191 /*Memory Privilege Controller*/ 192 #define MPC_PRESENT 1 193 #define MPC_COUNT 1 194 195 #define MPC00_EXTEND_CLOCK_REQ 0 /*!< (unspecified) */ 196 #define MPC00_RTCHOKE 0 /*!< (unspecified) */ 197 #define MPC00_OVERRIDE_GRAN 4096 /*!< The override region granularity is 4096 bytes */ 198 199 /*Distributed programmable peripheral interconnect controller*/ 200 #define DPPIC_PRESENT 1 201 #define DPPIC_COUNT 4 202 203 #define DPPIC00_HASCHANNELGROUPS 1 /*!< (unspecified) */ 204 #define DPPIC00_CH_NUM_MIN 0 /*!< (unspecified) */ 205 #define DPPIC00_CH_NUM_MAX 15 /*!< (unspecified) */ 206 #define DPPIC00_CH_NUM_SIZE 16 /*!< (unspecified) */ 207 #define DPPIC00_GROUP_NUM_MIN 0 /*!< (unspecified) */ 208 #define DPPIC00_GROUP_NUM_MAX 1 /*!< (unspecified) */ 209 #define DPPIC00_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 210 211 #define DPPIC10_HASCHANNELGROUPS 1 /*!< (unspecified) */ 212 #define DPPIC10_CH_NUM_MIN 0 /*!< (unspecified) */ 213 #define DPPIC10_CH_NUM_MAX 23 /*!< (unspecified) */ 214 #define DPPIC10_CH_NUM_SIZE 24 /*!< (unspecified) */ 215 #define DPPIC10_GROUP_NUM_MIN 0 /*!< (unspecified) */ 216 #define DPPIC10_GROUP_NUM_MAX 5 /*!< (unspecified) */ 217 #define DPPIC10_GROUP_NUM_SIZE 6 /*!< (unspecified) */ 218 219 #define DPPIC20_HASCHANNELGROUPS 1 /*!< (unspecified) */ 220 #define DPPIC20_CH_NUM_MIN 0 /*!< (unspecified) */ 221 #define DPPIC20_CH_NUM_MAX 15 /*!< (unspecified) */ 222 #define DPPIC20_CH_NUM_SIZE 16 /*!< (unspecified) */ 223 #define DPPIC20_GROUP_NUM_MIN 0 /*!< (unspecified) */ 224 #define DPPIC20_GROUP_NUM_MAX 5 /*!< (unspecified) */ 225 #define DPPIC20_GROUP_NUM_SIZE 6 /*!< (unspecified) */ 226 227 #define DPPIC30_HASCHANNELGROUPS 1 /*!< (unspecified) */ 228 #define DPPIC30_CH_NUM_MIN 0 /*!< (unspecified) */ 229 #define DPPIC30_CH_NUM_MAX 3 /*!< (unspecified) */ 230 #define DPPIC30_CH_NUM_SIZE 4 /*!< (unspecified) */ 231 #define DPPIC30_GROUP_NUM_MIN 0 /*!< (unspecified) */ 232 #define DPPIC30_GROUP_NUM_MAX 1 /*!< (unspecified) */ 233 #define DPPIC30_GROUP_NUM_SIZE 2 /*!< (unspecified) */ 234 235 /*PPIB APB registers*/ 236 #define PPIB_PRESENT 1 237 #define PPIB_COUNT 8 238 239 #define PPIB00_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 240 #define PPIB00_NTASKSEVENTS_MAX 11 /*!< (unspecified) */ 241 #define PPIB00_NTASKSEVENTS_SIZE 12 /*!< (unspecified) */ 242 243 #define PPIB01_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 244 #define PPIB01_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 245 #define PPIB01_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 246 247 #define PPIB10_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 248 #define PPIB10_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 249 #define PPIB10_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 250 251 #define PPIB11_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 252 #define PPIB11_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 253 #define PPIB11_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 254 255 #define PPIB20_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 256 #define PPIB20_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 257 #define PPIB20_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 258 259 #define PPIB21_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 260 #define PPIB21_NTASKSEVENTS_MAX 7 /*!< (unspecified) */ 261 #define PPIB21_NTASKSEVENTS_SIZE 8 /*!< (unspecified) */ 262 263 #define PPIB22_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 264 #define PPIB22_NTASKSEVENTS_MAX 3 /*!< (unspecified) */ 265 #define PPIB22_NTASKSEVENTS_SIZE 4 /*!< (unspecified) */ 266 267 #define PPIB30_NTASKSEVENTS_MIN 0 /*!< (unspecified) */ 268 #define PPIB30_NTASKSEVENTS_MAX 3 /*!< (unspecified) */ 269 #define PPIB30_NTASKSEVENTS_SIZE 4 /*!< (unspecified) */ 270 271 /*Key management unit*/ 272 #define KMU_PRESENT 1 273 #define KMU_COUNT 1 274 275 #define KMU_KEYSLOTNUM 250 /*!< Number of keyslots is 250 */ 276 #define KMU_KEYSLOTBITS 128 /*!< Number of bits per keyslot is 128 */ 277 #define KMU_PUSHBLOCK 1 /*!< (unspecified) */ 278 #define KMU_BLOCK 1 /*!< (unspecified) */ 279 280 /*Accelerated Address Resolver*/ 281 #define AAR_PRESENT 1 282 #define AAR_COUNT 1 283 284 #define AAR00_DMAERROR 1 /*!< (unspecified) */ 285 #define AAR00_ERRORSTATUS 1 /*!< (unspecified) */ 286 #define AAR00_ERROREVENT 1 /*!< (unspecified) */ 287 288 /*AES CCM Mode Encryption*/ 289 #define CCM_PRESENT 1 290 #define CCM_COUNT 1 291 292 #define CCM00_AMOUNTREG 0 /*!< (unspecified) */ 293 #define CCM00_ONTHEFLYDECRYPTION 0 /*!< (unspecified) */ 294 #define CCM00_DMAERROR 1 /*!< (unspecified) */ 295 296 /*AES ECB Mode Encryption*/ 297 #define ECB_PRESENT 1 298 #define ECB_COUNT 1 299 300 #define ECB00_AMOUNTREG 0 /*!< (unspecified) */ 301 #define ECB00_DMAERROR 1 /*!< (unspecified) */ 302 #define ECB00_ERRORSTATUS 1 /*!< (unspecified) */ 303 304 /*VPR peripheral registers*/ 305 #define VPR_PRESENT 1 306 #define VPR_COUNT 1 307 308 #define VPR00_INIT_PC_RESET_VALUE 0x01000000 /*!< Boot vector (INIT_PC_RESET_VALUE): 0x01000000 */ 309 #define VPR00_VPR_START_RESET_VALUE 1 /*!< Self-booting (VPR_START_RESET_VALUE): 1 */ 310 #define VPR00_RAM_BASE_ADDR 0x20000000 /*!< VPR RAM base address (RAM_BASE_ADDR): 0x20000000 */ 311 #define VPR00_RAM_SZ 20 /*!< VPR RAM size (RAM_SZ): 20 (Value in bytes is computed as 2^(RAM 312 size))*/ 313 #define VPR00_VPRSAVEDCTX_REGNAME NRF_MEMCONF->POWER[1].RET /*!< (unspecified) */ 314 #define VPR00_VPRSAVEDCTX_REGBIT 0 /*!< (unspecified) */ 315 #define VPR00_RETAINED 0 /*!< Retain registers in Deep Sleep mode: 0 */ 316 #define VPR00_VPRSAVEDCTX 1 /*!< (unspecified) */ 317 #define VPR00_VPRSAVEADDR 0x200FFE00 /*!< VPR context save address: 0x200FFE00 */ 318 #define VPR00_VPRREMAPADDRVTOB 0x00000000 /*!< VPR remap address: 0x00000000 */ 319 #define VPR00_VEVIF_NTASKS_MIN 16 /*!< VEVIF tasks: 16..22 */ 320 #define VPR00_VEVIF_NTASKS_MAX 22 /*!< VEVIF tasks: 16..22 */ 321 #define VPR00_VEVIF_NTASKS_SIZE 23 /*!< VEVIF tasks: 16..22 */ 322 #define VPR00_VEVIF_TASKS_MASK 0x007F0000 /*!< Mask of supported VEVIF tasks: 0x007F0000 */ 323 #define VPR00_VEVIF_NDPPI_MIN 0 /*!< VEVIF DPPI channels: 0..3 */ 324 #define VPR00_VEVIF_NDPPI_MAX 3 /*!< VEVIF DPPI channels: 0..3 */ 325 #define VPR00_VEVIF_NDPPI_SIZE 4 /*!< VEVIF DPPI channels: 0..3 */ 326 #define VPR00_VEVIF_DPPI_MASK 0x000F0000 /*!< Mask of supported VEVIF DPPI channels: 0x000F0000 */ 327 #define VPR00_VEVIF_NEVENTS_MIN 16 /*!< VEVIF events: 16..22 */ 328 #define VPR00_VEVIF_NEVENTS_MAX 22 /*!< VEVIF events: 16..22 */ 329 #define VPR00_VEVIF_NEVENTS_SIZE 23 /*!< VEVIF events: 16..22 */ 330 #define VPR00_VEVIF_EVENTS_MASK 0x00100000 /*!< Mask of supported VEVIF events: 0x00100000 */ 331 #define VPR00_DEBUGGER_OFFSET 1024 /*!< Debugger interface register offset: 0x5004C400 */ 332 #define VPR00_RTP_VPR_1_5 1 /*!< (unspecified) */ 333 334 /*Serial Peripheral Interface Master with EasyDMA*/ 335 #define SPIM_PRESENT 1 336 #define SPIM_COUNT 8 337 338 #define SPIM00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 339 #define SPIM00_MAX_DATARATE 32 /*!< (unspecified) */ 340 #define SPIM00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 341 #define SPIM00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 342 #define SPIM00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 343 #define SPIM00_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 344 #define SPIM00_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 345 #define SPIM00_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 346 #define SPIM00_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 347 #define SPIM00_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 348 #define SPIM00_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 349 #define SPIM00_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 350 #define SPIM00_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 351 #define SPIM00_CORE_FREQUENCY 256 /*!< Peripheral core frequency is 256 MHz. */ 352 #define SPIM00_PRESCALER_PRESENT 1 /*!< (unspecified) */ 353 #define SPIM00_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 354 #define SPIM00_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 355 #define SPIM00_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 356 #define SPIM00_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 357 #define SPIM00_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 358 #define SPIM00_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 359 #define SPIM00_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 360 #define SPIM00_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 361 #define SPIM00_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 362 #define SPIM00_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 363 364 #define SPIM01_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 365 #define SPIM01_MAX_DATARATE 32 /*!< (unspecified) */ 366 #define SPIM01_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 367 #define SPIM01_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 368 #define SPIM01_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 369 #define SPIM01_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 370 #define SPIM01_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 371 #define SPIM01_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 372 #define SPIM01_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 373 #define SPIM01_STALL_STATUS_TX_PRESENT 1 /*!< (unspecified) */ 374 #define SPIM01_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 375 #define SPIM01_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 376 #define SPIM01_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 377 #define SPIM01_CORE_FREQUENCY 256 /*!< Peripheral core frequency is 256 MHz. */ 378 #define SPIM01_PRESCALER_PRESENT 1 /*!< (unspecified) */ 379 #define SPIM01_PRESCALER_DIVISOR_RANGE_MIN 4 /*!< (unspecified) */ 380 #define SPIM01_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 381 #define SPIM01_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 382 #define SPIM01_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 383 #define SPIM01_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 384 #define SPIM01_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 385 #define SPIM01_RXDELAY_RESET_VALUE 2 /*!< (unspecified) */ 386 #define SPIM01_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 387 #define SPIM01_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 388 #define SPIM01_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 389 390 #define SPIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 391 #define SPIM20_MAX_DATARATE 8 /*!< (unspecified) */ 392 #define SPIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 393 #define SPIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 394 #define SPIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 395 #define SPIM20_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 396 #define SPIM20_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 397 #define SPIM20_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 398 #define SPIM20_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 399 #define SPIM20_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 400 #define SPIM20_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 401 #define SPIM20_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 402 #define SPIM20_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 403 #define SPIM20_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 404 #define SPIM20_PRESCALER_PRESENT 1 /*!< (unspecified) */ 405 #define SPIM20_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 406 #define SPIM20_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 407 #define SPIM20_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 408 #define SPIM20_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 409 #define SPIM20_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 410 #define SPIM20_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 411 #define SPIM20_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 412 #define SPIM20_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 413 #define SPIM20_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 414 #define SPIM20_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 415 416 #define SPIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 417 #define SPIM21_MAX_DATARATE 8 /*!< (unspecified) */ 418 #define SPIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 419 #define SPIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 420 #define SPIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 421 #define SPIM21_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 422 #define SPIM21_FEATURE_HARDWARE_DCX_PRESENT 1 /*!< (unspecified) */ 423 #define SPIM21_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 424 #define SPIM21_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 425 #define SPIM21_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 426 #define SPIM21_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 427 #define SPIM21_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 428 #define SPIM21_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 429 #define SPIM21_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 430 #define SPIM21_PRESCALER_PRESENT 1 /*!< (unspecified) */ 431 #define SPIM21_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 432 #define SPIM21_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 433 #define SPIM21_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 434 #define SPIM21_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 435 #define SPIM21_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 436 #define SPIM21_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 437 #define SPIM21_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 438 #define SPIM21_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 439 #define SPIM21_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 440 #define SPIM21_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 441 442 #define SPIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 443 #define SPIM22_MAX_DATARATE 8 /*!< (unspecified) */ 444 #define SPIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 445 #define SPIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 446 #define SPIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 447 #define SPIM22_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 448 #define SPIM22_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 449 #define SPIM22_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 450 #define SPIM22_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 451 #define SPIM22_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 452 #define SPIM22_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 453 #define SPIM22_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 454 #define SPIM22_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 455 #define SPIM22_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 456 #define SPIM22_PRESCALER_PRESENT 1 /*!< (unspecified) */ 457 #define SPIM22_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 458 #define SPIM22_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 459 #define SPIM22_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 460 #define SPIM22_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 461 #define SPIM22_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 462 #define SPIM22_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 463 #define SPIM22_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 464 #define SPIM22_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 465 #define SPIM22_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 466 #define SPIM22_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 467 468 #define SPIM23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 469 #define SPIM23_MAX_DATARATE 8 /*!< (unspecified) */ 470 #define SPIM23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 471 #define SPIM23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 472 #define SPIM23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 473 #define SPIM23_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 474 #define SPIM23_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 475 #define SPIM23_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 476 #define SPIM23_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 477 #define SPIM23_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 478 #define SPIM23_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 479 #define SPIM23_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 480 #define SPIM23_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 481 #define SPIM23_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 482 #define SPIM23_PRESCALER_PRESENT 1 /*!< (unspecified) */ 483 #define SPIM23_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 484 #define SPIM23_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 485 #define SPIM23_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 486 #define SPIM23_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 487 #define SPIM23_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 488 #define SPIM23_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 489 #define SPIM23_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 490 #define SPIM23_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 491 #define SPIM23_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 492 #define SPIM23_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 493 494 #define SPIM24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 495 #define SPIM24_MAX_DATARATE 8 /*!< (unspecified) */ 496 #define SPIM24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 497 #define SPIM24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 498 #define SPIM24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 499 #define SPIM24_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 500 #define SPIM24_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 501 #define SPIM24_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 502 #define SPIM24_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 503 #define SPIM24_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 504 #define SPIM24_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 505 #define SPIM24_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 506 #define SPIM24_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 507 #define SPIM24_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 508 #define SPIM24_PRESCALER_PRESENT 1 /*!< (unspecified) */ 509 #define SPIM24_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 510 #define SPIM24_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 511 #define SPIM24_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 512 #define SPIM24_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 513 #define SPIM24_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 514 #define SPIM24_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 515 #define SPIM24_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 516 #define SPIM24_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 517 #define SPIM24_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 518 #define SPIM24_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 519 520 #define SPIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 521 #define SPIM30_MAX_DATARATE 8 /*!< (unspecified) */ 522 #define SPIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 523 #define SPIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 524 #define SPIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 525 #define SPIM30_FEATURE_HARDWARE_CSN_PRESENT 1 /*!< (unspecified) */ 526 #define SPIM30_FEATURE_HARDWARE_DCX_PRESENT 0 /*!< (unspecified) */ 527 #define SPIM30_FEATURE_RXDELAY_PRESENT 1 /*!< (unspecified) */ 528 #define SPIM30_STALL_STATUS_PRESENT 0 /*!< (unspecified) */ 529 #define SPIM30_STALL_STATUS_TX_PRESENT 0 /*!< (unspecified) */ 530 #define SPIM30_NUM_CHIPSELECT_MIN 0 /*!< (unspecified) */ 531 #define SPIM30_NUM_CHIPSELECT_MAX 0 /*!< (unspecified) */ 532 #define SPIM30_NUM_CHIPSELECT_SIZE 1 /*!< (unspecified) */ 533 #define SPIM30_CORE_FREQUENCY 16 /*!< Peripheral core frequency is 16 MHz. */ 534 #define SPIM30_PRESCALER_PRESENT 1 /*!< (unspecified) */ 535 #define SPIM30_PRESCALER_DIVISOR_RANGE_MIN 2 /*!< (unspecified) */ 536 #define SPIM30_PRESCALER_DIVISOR_RANGE_MAX 126 /*!< (unspecified) */ 537 #define SPIM30_PRESCALER_DIVISOR_RANGE_SIZE 127 /*!< (unspecified) */ 538 #define SPIM30_RXDELAY_VALUE_RANGE_MIN 0 /*!< (unspecified) */ 539 #define SPIM30_RXDELAY_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 540 #define SPIM30_RXDELAY_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 541 #define SPIM30_RXDELAY_RESET_VALUE 1 /*!< (unspecified) */ 542 #define SPIM30_RXDELAY_FIELD_WIDTH_MIN 0 /*!< (unspecified) */ 543 #define SPIM30_RXDELAY_FIELD_WIDTH_MAX 2 /*!< (unspecified) */ 544 #define SPIM30_RXDELAY_FIELD_WIDTH_SIZE 3 /*!< (unspecified) */ 545 546 /*UART with EasyDMA*/ 547 #define UARTE_PRESENT 1 548 #define UARTE_COUNT 7 549 550 #define UARTE00_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 551 #define UARTE00_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 552 #define UARTE00_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 553 #define UARTE00_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 554 #define UARTE00_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 555 #define UARTE00_CORE_FREQUENCY 256 /*!< Peripheral clock frequency is 256 MHz. */ 556 #define UARTE00_CORE_CLOCK_256 1 /*!< (unspecified) */ 557 #define UARTE00_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 558 #define UARTE00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 559 560 #define UARTE20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 561 #define UARTE20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 562 #define UARTE20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 563 #define UARTE20_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 564 #define UARTE20_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 565 #define UARTE20_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 566 #define UARTE20_CORE_CLOCK_16 1 /*!< (unspecified) */ 567 #define UARTE20_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 568 #define UARTE20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 569 570 #define UARTE21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 571 #define UARTE21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 572 #define UARTE21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 573 #define UARTE21_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 574 #define UARTE21_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 575 #define UARTE21_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 576 #define UARTE21_CORE_CLOCK_16 1 /*!< (unspecified) */ 577 #define UARTE21_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 578 #define UARTE21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 579 580 #define UARTE22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 581 #define UARTE22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 582 #define UARTE22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 583 #define UARTE22_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 584 #define UARTE22_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 585 #define UARTE22_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 586 #define UARTE22_CORE_CLOCK_16 1 /*!< (unspecified) */ 587 #define UARTE22_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 588 #define UARTE22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 589 590 #define UARTE23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 591 #define UARTE23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 592 #define UARTE23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 593 #define UARTE23_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 594 #define UARTE23_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 595 #define UARTE23_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 596 #define UARTE23_CORE_CLOCK_16 1 /*!< (unspecified) */ 597 #define UARTE23_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 598 #define UARTE23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 599 600 #define UARTE24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 601 #define UARTE24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 602 #define UARTE24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 603 #define UARTE24_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 604 #define UARTE24_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 605 #define UARTE24_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 606 #define UARTE24_CORE_CLOCK_16 1 /*!< (unspecified) */ 607 #define UARTE24_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 608 #define UARTE24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 609 610 #define UARTE30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 611 #define UARTE30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 612 #define UARTE30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 613 #define UARTE30_TIMEOUT_INTERRUPT 1 /*!< (unspecified) */ 614 #define UARTE30_CONFIGURABLE_DATA_FRAME_SIZE 1 /*!< (unspecified) */ 615 #define UARTE30_CORE_FREQUENCY 16 /*!< Peripheral clock frequency is 16 MHz. */ 616 #define UARTE30_CORE_CLOCK_16 1 /*!< (unspecified) */ 617 #define UARTE30_SHORTS_ENDTX_STOPTX 1 /*!< (unspecified) */ 618 #define UARTE30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 619 620 /*MRAM controller*/ 621 #define MRAMC_PRESENT 1 622 #define MRAMC_COUNT 1 623 624 #define MRAMC_NMRAMWORDSIZE 128 /*!< (unspecified) */ 625 #define MRAMC_NMRAMPAGESIZE 4 /*!< (unspecified) */ 626 #define MRAMC_NNVRPAGESIZE 4 /*!< (unspecified) */ 627 #define MRAMC_NMAINMEMORYSIZE 4 /*!< MRAM main memory size: 4 MB */ 628 #define MRAMC_NNVRPAGES_MIN 0 /*!< Number of MRAM NVR pages: 0..1 */ 629 #define MRAMC_NNVRPAGES_MAX 1 /*!< Number of MRAM NVR pages: 0..1 */ 630 #define MRAMC_NNVRPAGES_SIZE 2 /*!< Number of MRAM NVR pages: 0..1 */ 631 #define MRAMC_NSIZEMRAMWORDS_MIN 1 /*!< Register ERASE.SIZE.SIZE range: 1..262144 */ 632 #define MRAMC_NSIZEMRAMWORDS_MAX 262144 /*!< Register ERASE.SIZE.SIZE range: 1..262144 */ 633 #define MRAMC_NSIZEMRAMWORDS_SIZE 262145 /*!< Register ERASE.SIZE.SIZE range: 1..262144 */ 634 #define MRAMC_MARMDATAWIDTHWORDS_MIN 0 /*!< (unspecified) */ 635 #define MRAMC_MARMDATAWIDTHWORDS_MAX 3 /*!< (unspecified) */ 636 #define MRAMC_MARMDATAWIDTHWORDS_SIZE 4 /*!< (unspecified) */ 637 #define MRAMC_NVRPAGEUPPER 1 /*!< (unspecified) */ 638 #define MRAMC_NVRPAGELOWER 1 /*!< (unspecified) */ 639 #define MRAMC_NVRPAGEENABLENORMALWRITE 1 /*!< (unspecified) */ 640 #define MRAMC_NVRPAGELRSIZEBITS_MIN 24 /*!< (unspecified) */ 641 #define MRAMC_NVRPAGELRSIZEBITS_MAX 27 /*!< (unspecified) */ 642 #define MRAMC_NVRPAGELRSIZEBITS_SIZE 28 /*!< (unspecified) */ 643 #define MRAMC_NVRPAGELRSIZERESET 15 /*!< (unspecified) */ 644 #define MRAMC_NVRPAGELRSIZEVALUE_MIN 0 /*!< (unspecified) */ 645 #define MRAMC_NVRPAGELRSIZEVALUE_MAX 15 /*!< (unspecified) */ 646 #define MRAMC_NVRPAGELRSIZEVALUE_SIZE 16 /*!< (unspecified) */ 647 #define MRAMC_NVRPAGELWSIZEBITS_MIN 28 /*!< (unspecified) */ 648 #define MRAMC_NVRPAGELWSIZEBITS_MAX 31 /*!< (unspecified) */ 649 #define MRAMC_NVRPAGELWSIZEBITS_SIZE 32 /*!< (unspecified) */ 650 #define MRAMC_NVRPAGELWSIZERESET 15 /*!< (unspecified) */ 651 #define MRAMC_NVRPAGELWSIZEVALUE_MIN 0 /*!< (unspecified) */ 652 #define MRAMC_NVRPAGELWSIZEVALUE_MAX 15 /*!< (unspecified) */ 653 #define MRAMC_NVRPAGELWSIZEVALUE_SIZE 16 /*!< (unspecified) */ 654 655 /*GPIO Port*/ 656 #define GPIO_PRESENT 1 657 #define GPIO_COUNT 5 658 659 #define P2_CTRLSEL_MAP1 0 /*!< (unspecified) */ 660 #define P2_CTRLSEL_MAP2 1 /*!< (unspecified) */ 661 #define P2_CTRLSEL_MAP3 0 /*!< (unspecified) */ 662 #define P2_PIN_NUM_MIN 0 /*!< (unspecified) */ 663 #define P2_PIN_NUM_MAX 11 /*!< (unspecified) */ 664 #define P2_PIN_NUM_SIZE 12 /*!< (unspecified) */ 665 #define P2_FEATURE_PINS_PRESENT 4095 /*!< (unspecified) */ 666 #define P2_PIN_SENSE_MECHANISM 0 /*!< (unspecified) */ 667 #define P2_DRIVECTRL 0 /*!< (unspecified) */ 668 #define P2_RETAIN 0 /*!< (unspecified) */ 669 #define P2_PWRCTRL 0 /*!< (unspecified) */ 670 #define P2_PIN_OWNER_SEC 0 /*!< (unspecified) */ 671 #define P2_BIASCTRL 0 /*!< (unspecified) */ 672 673 #define P1_CTRLSEL_MAP1 0 /*!< (unspecified) */ 674 #define P1_CTRLSEL_MAP2 1 /*!< (unspecified) */ 675 #define P1_CTRLSEL_MAP3 0 /*!< (unspecified) */ 676 #define P1_PIN_NUM_MIN 0 /*!< (unspecified) */ 677 #define P1_PIN_NUM_MAX 19 /*!< (unspecified) */ 678 #define P1_PIN_NUM_SIZE 20 /*!< (unspecified) */ 679 #define P1_FEATURE_PINS_PRESENT 1048575 /*!< (unspecified) */ 680 #define P1_PIN_SENSE_MECHANISM 1 /*!< (unspecified) */ 681 #define P1_DRIVECTRL 0 /*!< (unspecified) */ 682 #define P1_RETAIN 0 /*!< (unspecified) */ 683 #define P1_PWRCTRL 0 /*!< (unspecified) */ 684 #define P1_PIN_OWNER_SEC 0 /*!< (unspecified) */ 685 #define P1_BIASCTRL 0 /*!< (unspecified) */ 686 687 #define P3_CTRLSEL_MAP1 0 /*!< (unspecified) */ 688 #define P3_CTRLSEL_MAP2 1 /*!< (unspecified) */ 689 #define P3_CTRLSEL_MAP3 0 /*!< (unspecified) */ 690 #define P3_PIN_NUM_MIN 0 /*!< (unspecified) */ 691 #define P3_PIN_NUM_MAX 12 /*!< (unspecified) */ 692 #define P3_PIN_NUM_SIZE 13 /*!< (unspecified) */ 693 #define P3_FEATURE_PINS_PRESENT 8191 /*!< (unspecified) */ 694 #define P3_PIN_SENSE_MECHANISM 1 /*!< (unspecified) */ 695 #define P3_DRIVECTRL 0 /*!< (unspecified) */ 696 #define P3_RETAIN 0 /*!< (unspecified) */ 697 #define P3_PWRCTRL 0 /*!< (unspecified) */ 698 #define P3_PIN_OWNER_SEC 0 /*!< (unspecified) */ 699 #define P3_BIASCTRL 0 /*!< (unspecified) */ 700 701 #define P4_CTRLSEL_MAP1 0 /*!< (unspecified) */ 702 #define P4_CTRLSEL_MAP2 1 /*!< (unspecified) */ 703 #define P4_CTRLSEL_MAP3 0 /*!< (unspecified) */ 704 #define P4_PIN_NUM_MIN 0 /*!< (unspecified) */ 705 #define P4_PIN_NUM_MAX 11 /*!< (unspecified) */ 706 #define P4_PIN_NUM_SIZE 12 /*!< (unspecified) */ 707 #define P4_FEATURE_PINS_PRESENT 4095 /*!< (unspecified) */ 708 #define P4_PIN_SENSE_MECHANISM 1 /*!< (unspecified) */ 709 #define P4_DRIVECTRL 0 /*!< (unspecified) */ 710 #define P4_RETAIN 0 /*!< (unspecified) */ 711 #define P4_PWRCTRL 0 /*!< (unspecified) */ 712 #define P4_PIN_OWNER_SEC 0 /*!< (unspecified) */ 713 #define P4_BIASCTRL 0 /*!< (unspecified) */ 714 715 #define P0_CTRLSEL_MAP1 0 /*!< (unspecified) */ 716 #define P0_CTRLSEL_MAP2 1 /*!< (unspecified) */ 717 #define P0_CTRLSEL_MAP3 0 /*!< (unspecified) */ 718 #define P0_PIN_NUM_MIN 0 /*!< (unspecified) */ 719 #define P0_PIN_NUM_MAX 9 /*!< (unspecified) */ 720 #define P0_PIN_NUM_SIZE 10 /*!< (unspecified) */ 721 #define P0_FEATURE_PINS_PRESENT 1023 /*!< (unspecified) */ 722 #define P0_PIN_SENSE_MECHANISM 1 /*!< (unspecified) */ 723 #define P0_DRIVECTRL 0 /*!< (unspecified) */ 724 #define P0_RETAIN 0 /*!< (unspecified) */ 725 #define P0_PWRCTRL 0 /*!< (unspecified) */ 726 #define P0_PIN_OWNER_SEC 0 /*!< (unspecified) */ 727 #define P0_BIASCTRL 0 /*!< (unspecified) */ 728 729 /*Control access port*/ 730 #define CTRLAPPERI_PRESENT 1 731 #define CTRLAPPERI_COUNT 1 732 733 /*Trace and debug control*/ 734 #define TAD_PRESENT 1 735 #define TAD_COUNT 1 736 737 #define TAD_TADFORCEON 0 /*!< (unspecified) */ 738 #define TAD_TAD_HAS_TASKS 0 /*!< (unspecified) */ 739 #define TAD_PDREQCLR 1 /*!< (unspecified) */ 740 741 /*Timer/Counter*/ 742 #define TIMER_PRESENT 1 743 #define TIMER_COUNT 7 744 745 #define TIMER00_CC_NUM_MIN 0 /*!< (unspecified) */ 746 #define TIMER00_CC_NUM_MAX 5 /*!< (unspecified) */ 747 #define TIMER00_CC_NUM_SIZE 6 /*!< (unspecified) */ 748 #define TIMER00_MAX_SIZE_MIN 0 /*!< (unspecified) */ 749 #define TIMER00_MAX_SIZE_MAX 31 /*!< (unspecified) */ 750 #define TIMER00_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 751 #define TIMER00_PCLK_MHZ 256 /*!< Peripheral clock frequency (PCLK) is 256 MHz */ 752 #define TIMER00_PCLK_VARIABLE 1 /*!< (unspecified) */ 753 #define TIMER00_SHUTDOWN_TASK 0 /*!< (unspecified) */ 754 755 #define TIMER10_CC_NUM_MIN 0 /*!< (unspecified) */ 756 #define TIMER10_CC_NUM_MAX 7 /*!< (unspecified) */ 757 #define TIMER10_CC_NUM_SIZE 8 /*!< (unspecified) */ 758 #define TIMER10_MAX_SIZE_MIN 0 /*!< (unspecified) */ 759 #define TIMER10_MAX_SIZE_MAX 31 /*!< (unspecified) */ 760 #define TIMER10_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 761 #define TIMER10_PCLK_MHZ 32 /*!< Peripheral clock frequency (PCLK) is 32 MHz */ 762 #define TIMER10_PCLK_VARIABLE 0 /*!< (unspecified) */ 763 #define TIMER10_SHUTDOWN_TASK 0 /*!< (unspecified) */ 764 765 #define TIMER20_CC_NUM_MIN 0 /*!< (unspecified) */ 766 #define TIMER20_CC_NUM_MAX 5 /*!< (unspecified) */ 767 #define TIMER20_CC_NUM_SIZE 6 /*!< (unspecified) */ 768 #define TIMER20_MAX_SIZE_MIN 0 /*!< (unspecified) */ 769 #define TIMER20_MAX_SIZE_MAX 31 /*!< (unspecified) */ 770 #define TIMER20_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 771 #define TIMER20_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 772 #define TIMER20_PCLK_VARIABLE 0 /*!< (unspecified) */ 773 #define TIMER20_SHUTDOWN_TASK 0 /*!< (unspecified) */ 774 775 #define TIMER21_CC_NUM_MIN 0 /*!< (unspecified) */ 776 #define TIMER21_CC_NUM_MAX 5 /*!< (unspecified) */ 777 #define TIMER21_CC_NUM_SIZE 6 /*!< (unspecified) */ 778 #define TIMER21_MAX_SIZE_MIN 0 /*!< (unspecified) */ 779 #define TIMER21_MAX_SIZE_MAX 31 /*!< (unspecified) */ 780 #define TIMER21_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 781 #define TIMER21_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 782 #define TIMER21_PCLK_VARIABLE 0 /*!< (unspecified) */ 783 #define TIMER21_SHUTDOWN_TASK 0 /*!< (unspecified) */ 784 785 #define TIMER22_CC_NUM_MIN 0 /*!< (unspecified) */ 786 #define TIMER22_CC_NUM_MAX 5 /*!< (unspecified) */ 787 #define TIMER22_CC_NUM_SIZE 6 /*!< (unspecified) */ 788 #define TIMER22_MAX_SIZE_MIN 0 /*!< (unspecified) */ 789 #define TIMER22_MAX_SIZE_MAX 31 /*!< (unspecified) */ 790 #define TIMER22_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 791 #define TIMER22_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 792 #define TIMER22_PCLK_VARIABLE 0 /*!< (unspecified) */ 793 #define TIMER22_SHUTDOWN_TASK 0 /*!< (unspecified) */ 794 795 #define TIMER23_CC_NUM_MIN 0 /*!< (unspecified) */ 796 #define TIMER23_CC_NUM_MAX 5 /*!< (unspecified) */ 797 #define TIMER23_CC_NUM_SIZE 6 /*!< (unspecified) */ 798 #define TIMER23_MAX_SIZE_MIN 0 /*!< (unspecified) */ 799 #define TIMER23_MAX_SIZE_MAX 31 /*!< (unspecified) */ 800 #define TIMER23_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 801 #define TIMER23_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 802 #define TIMER23_PCLK_VARIABLE 0 /*!< (unspecified) */ 803 #define TIMER23_SHUTDOWN_TASK 0 /*!< (unspecified) */ 804 805 #define TIMER24_CC_NUM_MIN 0 /*!< (unspecified) */ 806 #define TIMER24_CC_NUM_MAX 5 /*!< (unspecified) */ 807 #define TIMER24_CC_NUM_SIZE 6 /*!< (unspecified) */ 808 #define TIMER24_MAX_SIZE_MIN 0 /*!< (unspecified) */ 809 #define TIMER24_MAX_SIZE_MAX 31 /*!< (unspecified) */ 810 #define TIMER24_MAX_SIZE_SIZE 32 /*!< (unspecified) */ 811 #define TIMER24_PCLK_MHZ 16 /*!< Peripheral clock frequency (PCLK) is 16 MHz */ 812 #define TIMER24_PCLK_VARIABLE 0 /*!< (unspecified) */ 813 #define TIMER24_SHUTDOWN_TASK 0 /*!< (unspecified) */ 814 815 /*Event generator unit*/ 816 #define EGU_PRESENT 1 817 #define EGU_COUNT 3 818 819 #define EGU00_PEND 0 /*!< (unspecified) */ 820 #define EGU00_CH_NUM_MIN 0 /*!< (unspecified) */ 821 #define EGU00_CH_NUM_MAX 5 /*!< (unspecified) */ 822 #define EGU00_CH_NUM_SIZE 6 /*!< (unspecified) */ 823 824 #define EGU10_PEND 0 /*!< (unspecified) */ 825 #define EGU10_CH_NUM_MIN 0 /*!< (unspecified) */ 826 #define EGU10_CH_NUM_MAX 15 /*!< (unspecified) */ 827 #define EGU10_CH_NUM_SIZE 16 /*!< (unspecified) */ 828 829 #define EGU20_PEND 0 /*!< (unspecified) */ 830 #define EGU20_CH_NUM_MIN 0 /*!< (unspecified) */ 831 #define EGU20_CH_NUM_MAX 5 /*!< (unspecified) */ 832 #define EGU20_CH_NUM_SIZE 6 /*!< (unspecified) */ 833 834 /*CRACEN*/ 835 #define CRACEN_PRESENT 1 836 #define CRACEN_COUNT 1 837 838 #define CRACEN_CRYPTOACCELERATOR 1 /*!< (unspecified) */ 839 #define CRACEN_SEEDRAMLOCK 0 /*!< (unspecified) */ 840 #define CRACEN_SPLITKEYRAMLOCK 1 /*!< (unspecified) */ 841 #define CRACEN_SEEDALIGNED 1 /*!< (unspecified) */ 842 #define CRACEN_PROTECTED_RAM_SEED 0x51810000 /*!< (unspecified) */ 843 #define CRACEN_PROTECTED_RAM_SEED_SIZE 64 /*!< (unspecified) */ 844 #define CRACEN_PROTECTED_RAM_AES_KEY0 0x51810040 /*!< (unspecified) */ 845 #define CRACEN_PROTECTED_RAM_AES_KEY0_SIZE 32 /*!< (unspecified) */ 846 #define CRACEN_PROTECTED_RAM_AES_KEY1 0x51810060 /*!< (unspecified) */ 847 #define CRACEN_PROTECTED_RAM_AES_KEY1_SIZE 32 /*!< (unspecified) */ 848 #define CRACEN_PROTECTED_RAM_SM4_KEY0 0x51810080 /*!< (unspecified) */ 849 #define CRACEN_PROTECTED_RAM_SM4_KEY0_SIZE 16 /*!< (unspecified) */ 850 #define CRACEN_PROTECTED_RAM_SM4_KEY1 0x51810090 /*!< (unspecified) */ 851 #define CRACEN_PROTECTED_RAM_SM4_KEY1_SIZE 16 /*!< (unspecified) */ 852 #define CRACEN_PROTECTED_RAM_SM4_KEY2 0x518100A0 /*!< (unspecified) */ 853 #define CRACEN_PROTECTED_RAM_SM4_KEY2_SIZE 16 /*!< (unspecified) */ 854 #define CRACEN_PROTECTED_RAM_SM4_KEY3 0x518100B0 /*!< (unspecified) */ 855 #define CRACEN_PROTECTED_RAM_SM4_KEY3_SIZE 16 /*!< (unspecified) */ 856 #define CRACEN_PROTECTED_RAM_RESERVED 0x518100C0 /*!< (unspecified) */ 857 #define CRACEN_PROTECTED_RAM_RESERVED_SIZE 64 /*!< (unspecified) */ 858 #define CRACEN_PKEDATA 0x50018000 /*!< PKE data (address 0x50018000) must be read and written using aligned 859 access, i.e. using an operation where a word-aligned address is used 860 for a word, or a halfword-aligned address is used for a halfword 861 access.*/ 862 #define CRACEN_PKECODE 0x5001C000 /*!< PKE code (address 0x5001C000) must be read and written using aligned 863 access, i.e. using an operation where a word-aligned address is used 864 for a word, or a halfword-aligned address is used for a halfword 865 access.*/ 866 867 /*USBHS*/ 868 #define USBHS_PRESENT 1 869 #define USBHS_COUNT 1 870 871 #define USBHS_HAS_SOF_EVENT 1 /*!< (unspecified) */ 872 #define USBHS_RTUNE_AVAILABLE 1 /*!< (unspecified) */ 873 874 /*Quad serial peripheral interface*/ 875 #define QSPI_PRESENT 1 876 #define QSPI_COUNT 2 877 878 #define QSPI00_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 879 #define QSPI00_FIFO_DEPTH 16 /*!< Depth of the transmit and receive FIFOs is 16 */ 880 881 #define QSPI01_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 882 #define QSPI01_FIFO_DEPTH 16 /*!< Depth of the transmit and receive FIFOs is 16 */ 883 884 /*2.4 GHz radio*/ 885 #define RADIO_PRESENT 1 886 #define RADIO_COUNT 1 887 888 #define RADIO_IRQ_COUNT 2 889 #define RADIO_WHITENINGPOLY 1 /*!< (unspecified) */ 890 #define RADIO_ADPLLCOMPANION_INCLUDE_DMA 0 /*!< (unspecified) */ 891 892 /*IPCT APB registers*/ 893 #define IPCT_PRESENT 1 894 #define IPCT_COUNT 1 895 896 #define IPCT10_IRQ_COUNT 4 897 898 /*SPI Slave*/ 899 #define SPIS_PRESENT 1 900 #define SPIS_COUNT 6 901 902 #define SPIS20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 903 #define SPIS20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 904 #define SPIS20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 905 #define SPIS20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 906 907 #define SPIS21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 908 #define SPIS21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 909 #define SPIS21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 910 #define SPIS21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 911 912 #define SPIS22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 913 #define SPIS22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 914 #define SPIS22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 915 #define SPIS22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 916 917 #define SPIS23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 918 #define SPIS23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 919 #define SPIS23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 920 #define SPIS23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 921 922 #define SPIS24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 923 #define SPIS24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 924 #define SPIS24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 925 #define SPIS24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 926 927 #define SPIS30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 928 #define SPIS30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 929 #define SPIS30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 930 #define SPIS30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 931 932 /*I2C compatible Two-Wire Master Interface with EasyDMA*/ 933 #define TWIM_PRESENT 1 934 #define TWIM_COUNT 6 935 936 #define TWIM20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 937 #define TWIM20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 938 #define TWIM20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 939 #define TWIM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 940 941 #define TWIM21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 942 #define TWIM21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 943 #define TWIM21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 944 #define TWIM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 945 946 #define TWIM22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 947 #define TWIM22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 948 #define TWIM22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 949 #define TWIM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 950 951 #define TWIM23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 952 #define TWIM23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 953 #define TWIM23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 954 #define TWIM23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 955 956 #define TWIM24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 957 #define TWIM24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 958 #define TWIM24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 959 #define TWIM24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 960 961 #define TWIM30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 962 #define TWIM30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 963 #define TWIM30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 964 #define TWIM30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 965 966 /*I2C compatible Two-Wire Slave Interface with EasyDMA*/ 967 #define TWIS_PRESENT 1 968 #define TWIS_COUNT 6 969 970 #define TWIS20_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 971 #define TWIS20_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 972 #define TWIS20_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 973 #define TWIS20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 974 975 #define TWIS21_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 976 #define TWIS21_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 977 #define TWIS21_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 978 #define TWIS21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 979 980 #define TWIS22_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 981 #define TWIS22_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 982 #define TWIS22_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 983 #define TWIS22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 984 985 #define TWIS23_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 986 #define TWIS23_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 987 #define TWIS23_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 988 #define TWIS23_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 989 990 #define TWIS24_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 991 #define TWIS24_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 992 #define TWIS24_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 993 #define TWIS24_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 994 995 #define TWIS30_EASYDMA_MAXCNT_MIN 0 /*!< (unspecified) */ 996 #define TWIS30_EASYDMA_MAXCNT_MAX 15 /*!< (unspecified) */ 997 #define TWIS30_EASYDMA_MAXCNT_SIZE 16 /*!< (unspecified) */ 998 #define TWIS30_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 999 1000 /*Memory configuration*/ 1001 #define MEMCONF_PRESENT 1 1002 #define MEMCONF_COUNT 1 1003 1004 #define MEMCONF_RETTRIM 1 /*!< (unspecified) */ 1005 #define MEMCONF_REPAIR 0 /*!< (unspecified) */ 1006 #define MEMCONF_POWER 1 /*!< (unspecified) */ 1007 1008 /*Pulse Density Modulation (Digital Microphone) Interface*/ 1009 #define PDM_PRESENT 1 1010 #define PDM_COUNT 2 1011 1012 #define PDM20_SAMPLE16 0 /*!< (unspecified) */ 1013 #define PDM20_SAMPLE48 1 /*!< (unspecified) */ 1014 #define PDM20_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1015 #define PDM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1016 1017 #define PDM21_SAMPLE16 0 /*!< (unspecified) */ 1018 #define PDM21_SAMPLE48 1 /*!< (unspecified) */ 1019 #define PDM21_PRESCALER_PRESENT 1 /*!< (unspecified) */ 1020 #define PDM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1021 1022 /*Pulse width modulation unit*/ 1023 #define PWM_PRESENT 1 1024 #define PWM_COUNT 3 1025 1026 #define PWM20_IDLE_OUT 1 /*!< (unspecified) */ 1027 #define PWM20_COMPARE_MATCH 1 /*!< (unspecified) */ 1028 #define PWM20_FEATURES_V2 0 /*!< (unspecified) */ 1029 #define PWM20_NO_FEATURES_V2 1 /*!< (unspecified) */ 1030 #define PWM20_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1031 1032 #define PWM21_IDLE_OUT 1 /*!< (unspecified) */ 1033 #define PWM21_COMPARE_MATCH 1 /*!< (unspecified) */ 1034 #define PWM21_FEATURES_V2 0 /*!< (unspecified) */ 1035 #define PWM21_NO_FEATURES_V2 1 /*!< (unspecified) */ 1036 #define PWM21_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1037 1038 #define PWM22_IDLE_OUT 1 /*!< (unspecified) */ 1039 #define PWM22_COMPARE_MATCH 1 /*!< (unspecified) */ 1040 #define PWM22_FEATURES_V2 0 /*!< (unspecified) */ 1041 #define PWM22_NO_FEATURES_V2 1 /*!< (unspecified) */ 1042 #define PWM22_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1043 1044 /*Analog to Digital Converter*/ 1045 #define SAADC_PRESENT 1 1046 #define SAADC_COUNT 1 1047 1048 #define SAADC_PSEL_V2 1 /*!< (unspecified) */ 1049 #define SAADC_TASKS_CALIBRATEGAIN 1 /*!< (unspecified) */ 1050 #define SAADC_SAMPLERATE_CC_VALUERANGE_MIN 8 /*!< (unspecified) */ 1051 #define SAADC_SAMPLERATE_CC_VALUERANGE_MAX 2047 /*!< (unspecified) */ 1052 #define SAADC_SAMPLERATE_CC_VALUERANGE_SIZE 2048 /*!< (unspecified) */ 1053 #define SAADC_TACQ_VALUE_RANGE_MIN 1 /*!< (unspecified) */ 1054 #define SAADC_TACQ_VALUE_RANGE_MAX 319 /*!< (unspecified) */ 1055 #define SAADC_TACQ_VALUE_RANGE_SIZE 320 /*!< (unspecified) */ 1056 #define SAADC_TCONV_VALUE_RANGE_MIN 1 /*!< (unspecified) */ 1057 #define SAADC_TCONV_VALUE_RANGE_MAX 7 /*!< (unspecified) */ 1058 #define SAADC_TCONV_VALUE_RANGE_SIZE 8 /*!< (unspecified) */ 1059 #define SAADC_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 0 /*!< (unspecified) */ 1060 1061 /*NFC-A compatible radio NFC-A compatible radio*/ 1062 #define NFCT_PRESENT 1 1063 #define NFCT_COUNT 1 1064 1065 #define NFCT_NFCTFIELDDETCFG_RESET 1 /*!< Reset value of register NFCTFIELDDETCFG: 1 */ 1066 1067 /*Temperature Sensor*/ 1068 #define TEMP_PRESENT 1 1069 #define TEMP_COUNT 1 1070 1071 /*GPIO Tasks and Events*/ 1072 #define GPIOTE_PRESENT 1 1073 #define GPIOTE_COUNT 2 1074 1075 #define GPIOTE20_IRQ_COUNT 2 1076 #define GPIOTE20_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..7 */ 1077 #define GPIOTE20_GPIOTE_NCHANNELS_MAX 7 /*!< Number of GPIOTE channels: 0..7 */ 1078 #define GPIOTE20_GPIOTE_NCHANNELS_SIZE 8 /*!< Number of GPIOTE channels: 0..7 */ 1079 #define GPIOTE20_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..0 */ 1080 #define GPIOTE20_GPIOTE_NPORTEVENTS_MAX 0 /*!< Number of GPIOTE port events: 0..0 */ 1081 #define GPIOTE20_GPIOTE_NPORTEVENTS_SIZE 1 /*!< Number of GPIOTE port events: 0..0 */ 1082 #define GPIOTE20_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 1083 #define GPIOTE20_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 1084 #define GPIOTE20_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 1085 #define GPIOTE20_HAS_PORT_EVENT 1 /*!< (unspecified) */ 1086 1087 #define GPIOTE30_IRQ_COUNT 2 1088 #define GPIOTE30_GPIOTE_NCHANNELS_MIN 0 /*!< Number of GPIOTE channels: 0..3 */ 1089 #define GPIOTE30_GPIOTE_NCHANNELS_MAX 3 /*!< Number of GPIOTE channels: 0..3 */ 1090 #define GPIOTE30_GPIOTE_NCHANNELS_SIZE 4 /*!< Number of GPIOTE channels: 0..3 */ 1091 #define GPIOTE30_GPIOTE_NPORTEVENTS_MIN 0 /*!< Number of GPIOTE port events: 0..0 */ 1092 #define GPIOTE30_GPIOTE_NPORTEVENTS_MAX 0 /*!< Number of GPIOTE port events: 0..0 */ 1093 #define GPIOTE30_GPIOTE_NPORTEVENTS_SIZE 1 /*!< Number of GPIOTE port events: 0..0 */ 1094 #define GPIOTE30_GPIOTE_NINTERRUPTS_MIN 0 /*!< Number of GPIOTE interrupts: 0..1 */ 1095 #define GPIOTE30_GPIOTE_NINTERRUPTS_MAX 1 /*!< Number of GPIOTE interrupts: 0..1 */ 1096 #define GPIOTE30_GPIOTE_NINTERRUPTS_SIZE 2 /*!< Number of GPIOTE interrupts: 0..1 */ 1097 #define GPIOTE30_HAS_PORT_EVENT 1 /*!< (unspecified) */ 1098 1099 /*Quadrature Decoder*/ 1100 #define QDEC_PRESENT 1 1101 #define QDEC_COUNT 2 1102 1103 /*Global Real-time counter*/ 1104 #define GRTC_PRESENT 1 1105 #define GRTC_COUNT 1 1106 1107 #define GRTC_IRQ_COUNT 6 1108 #define GRTC_MSBWIDTH_MIN 0 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 1109 0..14*/ 1110 #define GRTC_MSBWIDTH_MAX 14 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 1111 0..14*/ 1112 #define GRTC_MSBWIDTH_SIZE 15 /*!< Width of the RTCOUNTERH, RTCOMPAREH and RTCOMPARESYNCH registers : 1113 0..14*/ 1114 #define GRTC_NCC_MIN 0 /*!< Number of compare/capture registers : 0..15 */ 1115 #define GRTC_NCC_MAX 15 /*!< Number of compare/capture registers : 0..15 */ 1116 #define GRTC_NCC_SIZE 16 /*!< Number of compare/capture registers : 0..15 */ 1117 #define GRTC_NTIMEOUT_MIN 0 /*!< Width of the TIMEOUT register : 0..15 */ 1118 #define GRTC_NTIMEOUT_MAX 15 /*!< Width of the TIMEOUT register : 0..15 */ 1119 #define GRTC_NTIMEOUT_SIZE 16 /*!< Width of the TIMEOUT register : 0..15 */ 1120 #define GRTC_GRTC_NINTERRUPTS_MIN 0 /*!< Number of GRTC interrupts : 0..5 */ 1121 #define GRTC_GRTC_NINTERRUPTS_MAX 5 /*!< Number of GRTC interrupts : 0..5 */ 1122 #define GRTC_GRTC_NINTERRUPTS_SIZE 6 /*!< Number of GRTC interrupts : 0..5 */ 1123 #define GRTC_PWMREGS 1 /*!< (unspecified) */ 1124 #define GRTC_CLKOUTREG 1 /*!< (unspecified) */ 1125 #define GRTC_CLKSELREG 1 /*!< (unspecified) */ 1126 #define GRTC_CLKSELLFLPRC 1 /*!< (unspecified) */ 1127 #define GRTC_CCADD_WRITE_ONLY 0 /*!< (unspecified) */ 1128 #define GRTC_READY_STATUS_AND_EVENTS 0 /*!< (unspecified) */ 1129 #define GRTC_SYSCOUNTER_LOADED_STATUS 1 /*!< (unspecified) */ 1130 #define GRTC_CC_PAST_STATUS 1 /*!< (unspecified) */ 1131 #define GRTC_SYSCOUNTER_WRITEABLE 1 /*!< (unspecified) */ 1132 1133 /*Time division multiplexed audio interface*/ 1134 #define TDM_PRESENT 1 1135 #define TDM_COUNT 1 1136 1137 #define TDM_NUM_CHANNELS_MIN 0 /*!< (unspecified) */ 1138 #define TDM_NUM_CHANNELS_MAX 7 /*!< (unspecified) */ 1139 #define TDM_NUM_CHANNELS_SIZE 8 /*!< (unspecified) */ 1140 #define TDM_EASYDMA_CURRENT_AMOUNT_REGISTER_INCLUDED 1 /*!< (unspecified) */ 1141 1142 /*AUXPLL*/ 1143 #define AUXPLL_PRESENT 1 1144 #define AUXPLL_COUNT 1 1145 1146 /*AUXPM*/ 1147 #define AUXPM_PRESENT 1 1148 #define AUXPM_COUNT 1 1149 1150 /*Tamper controller*/ 1151 #define TAMPC_PRESENT 1 1152 #define TAMPC_COUNT 1 1153 1154 #define TAMPC_APSPIDEN 0 /*!< (unspecified) */ 1155 #define TAMPC_PROTECT_INTRESETEN_CTRL_VALUE_RESET 1 /*!< Reset value of field VALUE in register PROTECT.INTRESETEN.CTRL: 1 */ 1156 #define TAMPC_TAMPERSWITCH 0 /*!< (unspecified) */ 1157 1158 /*Coexistence controller*/ 1159 #define COEXC_PRESENT 1 1160 #define COEXC_COUNT 1 1161 1162 #define COEXC_NCLIENTS_MIN 0 /*!< Number of clients supported : 0..7 */ 1163 #define COEXC_NCLIENTS_MAX 7 /*!< Number of clients supported : 0..7 */ 1164 #define COEXC_NCLIENTS_SIZE 8 /*!< Number of clients supported : 0..7 */ 1165 #define COEXC_NMODES_MIN 0 /*!< Number of modes per client: 0..1 */ 1166 #define COEXC_NMODES_MAX 1 /*!< Number of modes per client: 0..1 */ 1167 #define COEXC_NMODES_SIZE 2 /*!< Number of modes per client: 0..1 */ 1168 #define COEXC_NCCMALLOWMODES_MIN 0 /*!< (unspecified) */ 1169 #define COEXC_NCCMALLOWMODES_MAX 1 /*!< (unspecified) */ 1170 #define COEXC_NCCMALLOWMODES_SIZE 2 /*!< (unspecified) */ 1171 #define COEXC_NPRIORITYBITS_MIN 16 /*!< CCCONF priority bits : 16..23 */ 1172 #define COEXC_NPRIORITYBITS_MAX 23 /*!< CCCONF priority bits : 16..23 */ 1173 #define COEXC_NPRIORITYBITS_SIZE 24 /*!< CCCONF priority bits : 16..23 */ 1174 1175 /*Comparator*/ 1176 #define COMP_PRESENT 1 1177 #define COMP_COUNT 1 1178 1179 /*Low-power comparator*/ 1180 #define LPCOMP_PRESENT 1 1181 #define LPCOMP_COUNT 1 1182 1183 /*Watchdog Timer*/ 1184 #define WDT_PRESENT 1 1185 #define WDT_COUNT 2 1186 1187 #define WDT30_ALLOW_STOP 1 /*!< (unspecified) */ 1188 #define WDT30_HAS_INTEN 0 /*!< (unspecified) */ 1189 1190 #define WDT31_ALLOW_STOP 1 /*!< (unspecified) */ 1191 #define WDT31_HAS_INTEN 0 /*!< (unspecified) */ 1192 1193 /*Clock management*/ 1194 #define CLOCK_PRESENT 1 1195 #define CLOCK_COUNT 1 1196 1197 #define CLOCK_XOTUNE 0 /*!< (unspecified) */ 1198 #define CLOCK_PLL24M 1 /*!< (unspecified) */ 1199 1200 /*Power control*/ 1201 #define POWER_PRESENT 1 1202 #define POWER_COUNT 1 1203 1204 #define POWER_CONSTLATSTAT 1 /*!< (unspecified) */ 1205 1206 /*Reset control*/ 1207 #define RESET_PRESENT 1 1208 #define RESET_COUNT 1 1209 1210 /*Voltage glitch detectors*/ 1211 #define GLITCHDET_PRESENT 1 1212 #define GLITCHDET_COUNT 1 1213 1214 /*Oscillator control*/ 1215 #define OSCILLATORS_PRESENT 1 1216 #define OSCILLATORS_COUNT 1 1217 1218 /*Voltage regulators*/ 1219 #define REGULATORS_PRESENT 1 1220 #define REGULATORS_COUNT 1 1221 1222 /*VREGUSB peripheral*/ 1223 #define VREGUSB_PRESENT 1 1224 #define VREGUSB_COUNT 1 1225 1226 #define VREGUSB_PROLONGED_WAKEUP 0 /*!< (unspecified) */ 1227 1228 /*LFXO peripheral*/ 1229 #define LFXO_PRESENT 1 1230 #define LFXO_COUNT 1 1231 1232 /*LFRC peripheral*/ 1233 #define LFRC_PRESENT 1 1234 #define LFRC_COUNT 1 1235 1236 /*HFXO64M peripheral*/ 1237 #define HFXO64M_PRESENT 1 1238 #define HFXO64M_COUNT 1 1239 1240 /*VREGMRAM peripheral*/ 1241 #define VREGMRAM_PRESENT 1 1242 #define VREGMRAM_COUNT 1 1243 1244 /*OSCRFR peripheral*/ 1245 #define OSCRFR_PRESENT 1 1246 #define OSCRFR_COUNT 1 1247 1248 /*VDETAO1V8 peripheral*/ 1249 #define VDETAO1V8_PRESENT 1 1250 #define VDETAO1V8_COUNT 1 1251 1252 /*VDETAO0V8 peripheral*/ 1253 #define VDETAO0V8_PRESENT 1 1254 #define VDETAO0V8_COUNT 1 1255 1256 /*VDETIO peripheral*/ 1257 #define VDETIO_PRESENT 1 1258 #define VDETIO_COUNT 1 1259 1260 #define VDETIO_CONFIG_PWRGOOD_RESET 30 /*!< Reset value of register CONFIG.PWRGOOD: 30 */ 1261 #define VDETIO_NPORTS_MIN 0 /*!< Number of ports supported : 0..4 */ 1262 #define VDETIO_NPORTS_MAX 4 /*!< Number of ports supported : 0..4 */ 1263 #define VDETIO_NPORTS_SIZE 5 /*!< Number of ports supported : 0..4 */ 1264 1265 /* ==================================================== Baudrate settings ==================================================== */ 1266 /** 1267 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1268 */ 1269 typedef enum { 1270 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core64M = 77824, /*!< 1200 baud (actual rate: 1161, -3.2 percent error), 64 MHz core 1271 frequency*/ 1272 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core64M = 159744, /*!< 2400 baud (actual rate: 2384, -0.7 percent error), 64 MHz core 1273 frequency*/ 1274 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core64M = 319488, /*!< 4800 baud (actual rate: 4768, -0.7 percent error), 64 MHz core 1275 frequency*/ 1276 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core64M = 643072, /*!< 9600 baud (actual rate: 9598, -0.0 percent error), 64 MHz core 1277 frequency*/ 1278 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core64M = 962560, /*!< 14400 baud (actual rate: 14366, -0.2 percent error), 64 MHz core 1279 frequency*/ 1280 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core64M = 1286144, /*!< 19200 baud (actual rate: 19196, -0.0 percent error), 64 MHz 1281 core frequency*/ 1282 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core64M = 1929216, /*!< 28800 baud (actual rate: 28794, -0.0 percent error), 64 MHz 1283 core frequency*/ 1284 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core64M = 2097152, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 64 MHz core 1285 frequency*/ 1286 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core64M = 2576384, /*!< 38400 baud (actual rate: 38453, 0.1 percent error), 64 MHz core 1287 frequency*/ 1288 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core64M = 3756032, /*!< 56000 baud (actual rate: 56060, 0.1 percent error), 64 MHz core 1289 frequency*/ 1290 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core64M = 3862528, /*!< 57600 baud (actual rate: 57649, 0.1 percent error), 64 MHz core 1291 frequency*/ 1292 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core64M = 5152768, /*!< 76800 baud (actual rate: 76906, 0.1 percent error), 64 MHz core 1293 frequency*/ 1294 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core64M = 7720960, /*!< 115200 baud (actual rate: 115238, 0.0 percent error), 64 MHz 1295 core frequency*/ 1296 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core64M = 15446016, /*!< 230400 baud (actual rate: 230537, 0.1 percent error), 64 MHz 1297 core frequency*/ 1298 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core64M = 16777216, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 64 MHz 1299 core frequency*/ 1300 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core64M = 30896128, /*!< 460800 baud (actual rate: 461136, 0.1 percent error), 64 MHz 1301 core frequency*/ 1302 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core64M = 62242816, /*!< 921600 baud (actual rate: 928997, 0.8 percent error), 64 MHz 1303 core frequency*/ 1304 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core64M = 67108864, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 64 1305 MHz core frequency*/ 1306 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1200Core128M = 36864, /*!< 1200 baud (actual rate: 1117, -6.9 percent error), 128 MHz core 1307 frequency*/ 1308 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud2400Core128M = 77824, /*!< 2400 baud (actual rate: 2358, -1.7 percent error), 128 MHz core 1309 frequency*/ 1310 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud4800Core128M = 159744, /*!< 4800 baud (actual rate: 4840, 0.8 percent error), 128 MHz core 1311 frequency*/ 1312 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud9600Core128M = 319488, /*!< 9600 baud (actual rate: 9681, 0.8 percent error), 128 MHz core 1313 frequency*/ 1314 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud14400Core128M = 479232, /*!< 14400 baud (actual rate: 14522, 0.8 percent error), 128 MHz 1315 core frequency*/ 1316 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud19200Core128M = 643072, /*!< 19200 baud (actual rate: 19487, 1.5 percent error), 128 MHz 1317 core frequency*/ 1318 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud28800Core128M = 962560, /*!< 28800 baud (actual rate: 29168, 1.3 percent error), 128 MHz 1319 core frequency*/ 1320 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud31250Core128M = 1048576, /*!< 31250 baud (actual rate: 31775, 1.7 percent error), 128 MHz 1321 core frequency*/ 1322 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud38400Core128M = 1286144, /*!< 38400 baud (actual rate: 38974, 1.5 percent error), 128 MHz 1323 core frequency*/ 1324 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud56000Core128M = 1875968, /*!< 56000 baud (actual rate: 56847, 1.5 percent error), 128 MHz 1325 core frequency*/ 1326 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud57600Core128M = 1929216, /*!< 57600 baud (actual rate: 58461, 1.5 percent error), 128 MHz 1327 core frequency*/ 1328 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud76800Core128M = 2576384, /*!< 76800 baud (actual rate: 78072, 1.7 percent error), 128 MHz 1329 core frequency*/ 1330 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud115200Core128M = 3862528, /*!< 115200 baud (actual rate: 117046, 1.6 percent error), 128 MHz 1331 core frequency*/ 1332 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud230400Core128M = 7720960, /*!< 230400 baud (actual rate: 233968, 1.5 percent error), 128 MHz 1333 core frequency*/ 1334 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud250000Core128M = 8388608, /*!< 250000 baud (actual rate: 254200, 1.7 percent error), 128 MHz 1335 core frequency*/ 1336 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud460800Core128M = 15446016, /*!< 460800 baud (actual rate: 468061, 1.6 percent error), 128 1337 MHz core frequency*/ 1338 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud921600Core128M = 30896128, /*!< 921600 baud (actual rate: 936246, 1.6 percent error), 128 1339 MHz core frequency*/ 1340 NRF_UARTE00_BAUDRATE_BAUDRATE_Baud1000000Core128M = 33554432, /*!< 1000000 baud (actual rate: 1016800, 1.7 percent error), 128 1341 MHz core frequency*/ 1342 } NRF_UARTE00_BAUDRATE_BAUDRATE_ENUM_t; 1343 1344 /* ==================================================== Baudrate settings ==================================================== */ 1345 /** 1346 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1347 */ 1348 typedef enum { 1349 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1350 frequency*/ 1351 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1352 frequency*/ 1353 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1354 frequency*/ 1355 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1356 frequency*/ 1357 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1358 frequency*/ 1359 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1360 frequency*/ 1361 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1362 frequency*/ 1363 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1364 frequency*/ 1365 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1366 core frequency*/ 1367 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1368 core frequency*/ 1369 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1370 core frequency*/ 1371 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1372 core frequency*/ 1373 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1374 core frequency*/ 1375 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1376 core frequency*/ 1377 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1378 core frequency*/ 1379 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1380 MHz core frequency*/ 1381 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1382 core frequency*/ 1383 NRF_UARTE20_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1384 MHz core frequency*/ 1385 } NRF_UARTE20_BAUDRATE_BAUDRATE_ENUM_t; 1386 1387 /* ==================================================== Baudrate settings ==================================================== */ 1388 /** 1389 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1390 */ 1391 typedef enum { 1392 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1393 frequency*/ 1394 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1395 frequency*/ 1396 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1397 frequency*/ 1398 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1399 frequency*/ 1400 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1401 frequency*/ 1402 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1403 frequency*/ 1404 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1405 frequency*/ 1406 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1407 frequency*/ 1408 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1409 core frequency*/ 1410 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1411 core frequency*/ 1412 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1413 core frequency*/ 1414 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1415 core frequency*/ 1416 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1417 core frequency*/ 1418 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1419 core frequency*/ 1420 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1421 core frequency*/ 1422 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1423 MHz core frequency*/ 1424 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1425 core frequency*/ 1426 NRF_UARTE21_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1427 MHz core frequency*/ 1428 } NRF_UARTE21_BAUDRATE_BAUDRATE_ENUM_t; 1429 1430 /* ==================================================== Baudrate settings ==================================================== */ 1431 /** 1432 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1433 */ 1434 typedef enum { 1435 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1436 frequency*/ 1437 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1438 frequency*/ 1439 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1440 frequency*/ 1441 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1442 frequency*/ 1443 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1444 frequency*/ 1445 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1446 frequency*/ 1447 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1448 frequency*/ 1449 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1450 frequency*/ 1451 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1452 core frequency*/ 1453 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1454 core frequency*/ 1455 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1456 core frequency*/ 1457 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1458 core frequency*/ 1459 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1460 core frequency*/ 1461 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1462 core frequency*/ 1463 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1464 core frequency*/ 1465 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1466 MHz core frequency*/ 1467 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1468 core frequency*/ 1469 NRF_UARTE22_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1470 MHz core frequency*/ 1471 } NRF_UARTE22_BAUDRATE_BAUDRATE_ENUM_t; 1472 1473 /* ==================================================== Baudrate settings ==================================================== */ 1474 /** 1475 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1476 */ 1477 typedef enum { 1478 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1479 frequency*/ 1480 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1481 frequency*/ 1482 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1483 frequency*/ 1484 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1485 frequency*/ 1486 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1487 frequency*/ 1488 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1489 frequency*/ 1490 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1491 frequency*/ 1492 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1493 frequency*/ 1494 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1495 core frequency*/ 1496 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1497 core frequency*/ 1498 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1499 core frequency*/ 1500 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1501 core frequency*/ 1502 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1503 core frequency*/ 1504 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1505 core frequency*/ 1506 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1507 core frequency*/ 1508 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1509 MHz core frequency*/ 1510 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1511 core frequency*/ 1512 NRF_UARTE23_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1513 MHz core frequency*/ 1514 } NRF_UARTE23_BAUDRATE_BAUDRATE_ENUM_t; 1515 1516 /* ==================================================== Baudrate settings ==================================================== */ 1517 /** 1518 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1519 */ 1520 typedef enum { 1521 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1522 frequency*/ 1523 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1524 frequency*/ 1525 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1526 frequency*/ 1527 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1528 frequency*/ 1529 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1530 frequency*/ 1531 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1532 frequency*/ 1533 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1534 frequency*/ 1535 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1536 frequency*/ 1537 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1538 core frequency*/ 1539 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1540 core frequency*/ 1541 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1542 core frequency*/ 1543 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1544 core frequency*/ 1545 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1546 core frequency*/ 1547 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1548 core frequency*/ 1549 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1550 core frequency*/ 1551 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1552 MHz core frequency*/ 1553 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1554 core frequency*/ 1555 NRF_UARTE24_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1556 MHz core frequency*/ 1557 } NRF_UARTE24_BAUDRATE_BAUDRATE_ENUM_t; 1558 1559 /* ==================================================== Baudrate settings ==================================================== */ 1560 /** 1561 * @brief UARTE.BAUDRATE register values for combinations of baudrate and core frequency 1562 */ 1563 typedef enum { 1564 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1200Core16M = 319488, /*!< 1200 baud (actual rate: 1192, -0.7 percent error), 16 MHz core 1565 frequency*/ 1566 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud2400Core16M = 643072, /*!< 2400 baud (actual rate: 2399, -0.0 percent error), 16 MHz core 1567 frequency*/ 1568 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud4800Core16M = 1286144, /*!< 4800 baud (actual rate: 4799, -0.0 percent error), 16 MHz core 1569 frequency*/ 1570 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud9600Core16M = 2576384, /*!< 9600 baud (actual rate: 9613, 0.1 percent error), 16 MHz core 1571 frequency*/ 1572 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud14400Core16M = 3862528, /*!< 14400 baud (actual rate: 14412, 0.1 percent error), 16 MHz core 1573 frequency*/ 1574 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud19200Core16M = 5152768, /*!< 19200 baud (actual rate: 19226, 0.1 percent error), 16 MHz core 1575 frequency*/ 1576 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud28800Core16M = 7720960, /*!< 28800 baud (actual rate: 28809, 0.0 percent error), 16 MHz core 1577 frequency*/ 1578 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud31250Core16M = 8388608, /*!< 31250 baud (actual rate: 31300, 0.2 percent error), 16 MHz core 1579 frequency*/ 1580 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud38400Core16M = 10297344, /*!< 38400 baud (actual rate: 38422, 0.1 percent error), 16 MHz 1581 core frequency*/ 1582 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud56000Core16M = 15015936, /*!< 56000 baud (actual rate: 56029, 0.1 percent error), 16 MHz 1583 core frequency*/ 1584 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud57600Core16M = 15446016, /*!< 57600 baud (actual rate: 57634, 0.1 percent error), 16 MHz 1585 core frequency*/ 1586 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud76800Core16M = 20647936, /*!< 76800 baud (actual rate: 77044, 0.3 percent error), 16 MHz 1587 core frequency*/ 1588 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud115200Core16M = 30896128, /*!< 115200 baud (actual rate: 115284, 0.1 percent error), 16 MHz 1589 core frequency*/ 1590 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud230400Core16M = 62242816, /*!< 230400 baud (actual rate: 232249, 0.8 percent error), 16 MHz 1591 core frequency*/ 1592 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud250000Core16M = 67108864, /*!< 250000 baud (actual rate: 250406, 0.2 percent error), 16 MHz 1593 core frequency*/ 1594 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud460800Core16M = 122712064, /*!< 460800 baud (actual rate: 457880, -0.6 percent error), 16 1595 MHz core frequency*/ 1596 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud921600Core16M = 252641280, /*!< 921600 baud (actual rate: 942691, 2.3 percent error), 16 MHz 1597 core frequency*/ 1598 NRF_UARTE30_BAUDRATE_BAUDRATE_Baud1000000Core16M = 268435456, /*!< 1000000 baud (actual rate: 1001624, 0.2 percent error), 16 1599 MHz core frequency*/ 1600 } NRF_UARTE30_BAUDRATE_BAUDRATE_ENUM_t; 1601 1602 1603 #ifdef __cplusplus 1604 } 1605 #endif 1606 #endif /* NRF7120_ENGA_UMAC_PERIPHERALS_H */ 1607 1608
