1 /* 2 3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF7120_ENGA_FLPR_H 36 #define NRF7120_ENGA_FLPR_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_FLPR /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 /* ============================================== Processor Specific Interrupts ============================================== */ 53 VPRCLIC_16_IRQn = 16, /*!< 16 VPRCLIC_16 */ 54 VPRCLIC_17_IRQn = 17, /*!< 17 VPRCLIC_17 */ 55 VPRCLIC_18_IRQn = 18, /*!< 18 VPRCLIC_18 */ 56 VPRCLIC_19_IRQn = 19, /*!< 19 VPRCLIC_19 */ 57 VPRCLIC_20_IRQn = 20, /*!< 20 VPRCLIC_20 */ 58 VPRCLIC_21_IRQn = 21, /*!< 21 VPRCLIC_21 */ 59 VPRCLIC_22_IRQn = 22, /*!< 22 VPRCLIC_22 */ 60 SPU00_IRQn = 64, /*!< 64 SPU00 */ 61 MPC00_IRQn = 65, /*!< 65 MPC00 */ 62 AAR00_CCM00_IRQn = 74, /*!< 74 AAR00_CCM00 */ 63 ECB00_IRQn = 75, /*!< 75 ECB00 */ 64 VPR00_IRQn = 76, /*!< 76 VPR00 */ 65 SERIAL00_IRQn = 77, /*!< 77 SERIAL00 */ 66 MRAMC_IRQn = 78, /*!< 78 MRAMC */ 67 CTRLAP_IRQn = 82, /*!< 82 CTRLAP */ 68 CM33SS_IRQn = 84, /*!< 84 CM33SS */ 69 TIMER00_IRQn = 85, /*!< 85 TIMER00 */ 70 EGU00_IRQn = 88, /*!< 88 EGU00 */ 71 CRACEN_IRQn = 89, /*!< 89 CRACEN */ 72 USBHS_IRQn = 90, /*!< 90 USBHS */ 73 QSPI00_IRQn = 91, /*!< 91 QSPI00 */ 74 QSPI01_IRQn = 92, /*!< 92 QSPI01 */ 75 SERIAL01_IRQn = 93, /*!< 93 SERIAL01 */ 76 SPU10_IRQn = 128, /*!< 128 SPU10 */ 77 TIMER10_IRQn = 133, /*!< 133 TIMER10 */ 78 EGU10_IRQn = 135, /*!< 135 EGU10 */ 79 RADIO_0_IRQn = 138, /*!< 138 RADIO_0 */ 80 RADIO_1_IRQn = 139, /*!< 139 RADIO_1 */ 81 IPCT10_0_IRQn = 141, /*!< 141 IPCT10_0 */ 82 IPCT10_1_IRQn = 142, /*!< 142 IPCT10_1 */ 83 IPCT10_2_IRQn = 143, /*!< 143 IPCT10_2 */ 84 IPCT10_3_IRQn = 144, /*!< 144 IPCT10_3 */ 85 SPU20_IRQn = 192, /*!< 192 SPU20 */ 86 SERIAL20_IRQn = 198, /*!< 198 SERIAL20 */ 87 SERIAL21_IRQn = 199, /*!< 199 SERIAL21 */ 88 SERIAL22_IRQn = 200, /*!< 200 SERIAL22 */ 89 EGU20_IRQn = 201, /*!< 201 EGU20 */ 90 TIMER20_IRQn = 202, /*!< 202 TIMER20 */ 91 TIMER21_IRQn = 203, /*!< 203 TIMER21 */ 92 TIMER22_IRQn = 204, /*!< 204 TIMER22 */ 93 TIMER23_IRQn = 205, /*!< 205 TIMER23 */ 94 TIMER24_IRQn = 206, /*!< 206 TIMER24 */ 95 PDM20_IRQn = 208, /*!< 208 PDM20 */ 96 PDM21_IRQn = 209, /*!< 209 PDM21 */ 97 PWM20_IRQn = 210, /*!< 210 PWM20 */ 98 PWM21_IRQn = 211, /*!< 211 PWM21 */ 99 PWM22_IRQn = 212, /*!< 212 PWM22 */ 100 SAADC_IRQn = 213, /*!< 213 SAADC */ 101 NFCT_IRQn = 214, /*!< 214 NFCT */ 102 TEMP_IRQn = 215, /*!< 215 TEMP */ 103 GPIOTE20_0_IRQn = 218, /*!< 218 GPIOTE20_0 */ 104 GPIOTE20_1_IRQn = 219, /*!< 219 GPIOTE20_1 */ 105 QDEC20_IRQn = 224, /*!< 224 QDEC20 */ 106 QDEC21_IRQn = 225, /*!< 225 QDEC21 */ 107 GRTC_0_IRQn = 226, /*!< 226 GRTC_0 */ 108 GRTC_1_IRQn = 227, /*!< 227 GRTC_1 */ 109 GRTC_2_IRQn = 228, /*!< 228 GRTC_2 */ 110 GRTC_3_IRQn = 229, /*!< 229 GRTC_3 */ 111 GRTC_4_IRQn = 230, /*!< 230 GRTC_4 */ 112 GRTC_5_IRQn = 231, /*!< 231 GRTC_5 */ 113 TDM_IRQn = 232, /*!< 232 TDM */ 114 AUXPLL_AUXPM_IRQn = 235, /*!< 235 AUXPLL_AUXPM */ 115 SERIAL23_IRQn = 237, /*!< 237 SERIAL23 */ 116 SERIAL24_IRQn = 238, /*!< 238 SERIAL24 */ 117 TAMPC_IRQn = 239, /*!< 239 TAMPC */ 118 SPU30_IRQn = 256, /*!< 256 SPU30 */ 119 SERIAL30_IRQn = 260, /*!< 260 SERIAL30 */ 120 COMP_LPCOMP_IRQn = 262, /*!< 262 COMP_LPCOMP */ 121 WDT30_IRQn = 264, /*!< 264 WDT30 */ 122 WDT31_IRQn = 265, /*!< 265 WDT31 */ 123 GPIOTE30_0_IRQn = 268, /*!< 268 GPIOTE30_0 */ 124 GPIOTE30_1_IRQn = 269, /*!< 269 GPIOTE30_1 */ 125 CLOCK_POWER_IRQn = 270, /*!< 270 CLOCK_POWER */ 126 LFXO_IRQn = 290, /*!< 290 LFXO */ 127 LFRC_IRQn = 291, /*!< 291 LFRC */ 128 HFXO64M_IRQn = 292, /*!< 292 HFXO64M */ 129 } IRQn_Type; 130 131 /* ==================================================== Interrupt Aliases ==================================================== */ 132 #define AAR00_IRQn AAR00_CCM00_IRQn 133 #define AAR00_IRQHandler AAR00_CCM00_IRQHandler 134 #define CCM00_IRQn AAR00_CCM00_IRQn 135 #define CCM00_IRQHandler AAR00_CCM00_IRQHandler 136 #define SPIM00_IRQn SERIAL00_IRQn 137 #define SPIM00_IRQHandler SERIAL00_IRQHandler 138 #define UARTE00_IRQn SERIAL00_IRQn 139 #define UARTE00_IRQHandler SERIAL00_IRQHandler 140 #define CPUC_IRQn CM33SS_IRQn 141 #define CPUC_IRQHandler CM33SS_IRQHandler 142 #define SPIM01_IRQn SERIAL01_IRQn 143 #define SPIM01_IRQHandler SERIAL01_IRQHandler 144 #define SPIM20_IRQn SERIAL20_IRQn 145 #define SPIM20_IRQHandler SERIAL20_IRQHandler 146 #define SPIS20_IRQn SERIAL20_IRQn 147 #define SPIS20_IRQHandler SERIAL20_IRQHandler 148 #define TWIM20_IRQn SERIAL20_IRQn 149 #define TWIM20_IRQHandler SERIAL20_IRQHandler 150 #define TWIS20_IRQn SERIAL20_IRQn 151 #define TWIS20_IRQHandler SERIAL20_IRQHandler 152 #define UARTE20_IRQn SERIAL20_IRQn 153 #define UARTE20_IRQHandler SERIAL20_IRQHandler 154 #define SPIM21_IRQn SERIAL21_IRQn 155 #define SPIM21_IRQHandler SERIAL21_IRQHandler 156 #define SPIS21_IRQn SERIAL21_IRQn 157 #define SPIS21_IRQHandler SERIAL21_IRQHandler 158 #define TWIM21_IRQn SERIAL21_IRQn 159 #define TWIM21_IRQHandler SERIAL21_IRQHandler 160 #define TWIS21_IRQn SERIAL21_IRQn 161 #define TWIS21_IRQHandler SERIAL21_IRQHandler 162 #define UARTE21_IRQn SERIAL21_IRQn 163 #define UARTE21_IRQHandler SERIAL21_IRQHandler 164 #define SPIM22_IRQn SERIAL22_IRQn 165 #define SPIM22_IRQHandler SERIAL22_IRQHandler 166 #define SPIS22_IRQn SERIAL22_IRQn 167 #define SPIS22_IRQHandler SERIAL22_IRQHandler 168 #define TWIM22_IRQn SERIAL22_IRQn 169 #define TWIM22_IRQHandler SERIAL22_IRQHandler 170 #define TWIS22_IRQn SERIAL22_IRQn 171 #define TWIS22_IRQHandler SERIAL22_IRQHandler 172 #define UARTE22_IRQn SERIAL22_IRQn 173 #define UARTE22_IRQHandler SERIAL22_IRQHandler 174 #define AUXPLL_IRQn AUXPLL_AUXPM_IRQn 175 #define AUXPLL_IRQHandler AUXPLL_AUXPM_IRQHandler 176 #define AUXPM_IRQn AUXPLL_AUXPM_IRQn 177 #define AUXPM_IRQHandler AUXPLL_AUXPM_IRQHandler 178 #define SPIM23_IRQn SERIAL23_IRQn 179 #define SPIM23_IRQHandler SERIAL23_IRQHandler 180 #define SPIS23_IRQn SERIAL23_IRQn 181 #define SPIS23_IRQHandler SERIAL23_IRQHandler 182 #define TWIM23_IRQn SERIAL23_IRQn 183 #define TWIM23_IRQHandler SERIAL23_IRQHandler 184 #define TWIS23_IRQn SERIAL23_IRQn 185 #define TWIS23_IRQHandler SERIAL23_IRQHandler 186 #define UARTE23_IRQn SERIAL23_IRQn 187 #define UARTE23_IRQHandler SERIAL23_IRQHandler 188 #define SPIM24_IRQn SERIAL24_IRQn 189 #define SPIM24_IRQHandler SERIAL24_IRQHandler 190 #define SPIS24_IRQn SERIAL24_IRQn 191 #define SPIS24_IRQHandler SERIAL24_IRQHandler 192 #define TWIM24_IRQn SERIAL24_IRQn 193 #define TWIM24_IRQHandler SERIAL24_IRQHandler 194 #define TWIS24_IRQn SERIAL24_IRQn 195 #define TWIS24_IRQHandler SERIAL24_IRQHandler 196 #define UARTE24_IRQn SERIAL24_IRQn 197 #define UARTE24_IRQHandler SERIAL24_IRQHandler 198 #define SPIM30_IRQn SERIAL30_IRQn 199 #define SPIM30_IRQHandler SERIAL30_IRQHandler 200 #define SPIS30_IRQn SERIAL30_IRQn 201 #define SPIS30_IRQHandler SERIAL30_IRQHandler 202 #define TWIM30_IRQn SERIAL30_IRQn 203 #define TWIM30_IRQHandler SERIAL30_IRQHandler 204 #define TWIS30_IRQn SERIAL30_IRQn 205 #define TWIS30_IRQHandler SERIAL30_IRQHandler 206 #define UARTE30_IRQn SERIAL30_IRQn 207 #define UARTE30_IRQHandler SERIAL30_IRQHandler 208 #define COMP_IRQn COMP_LPCOMP_IRQn 209 #define COMP_IRQHandler COMP_LPCOMP_IRQHandler 210 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 211 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 212 #define CLOCK_IRQn CLOCK_POWER_IRQn 213 #define CLOCK_IRQHandler CLOCK_POWER_IRQHandler 214 #define POWER_IRQn CLOCK_POWER_IRQn 215 #define POWER_IRQHandler CLOCK_POWER_IRQHandler 216 217 /* =========================================================================================================================== */ 218 /* ================ Processor and Core Peripheral Section ================ */ 219 /* =========================================================================================================================== */ 220 221 /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ 222 #define __VPR_REV 1.4.1 /*!< VPR Core Revision */ 223 #define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ 224 #define __VPR_REV_MINOR 4 /*!< VPR Core Minor Revision */ 225 #define __VPR_REV_PATCH 1 /*!< VPR Core Patch Revision */ 226 #define __DSP_PRESENT 0 /*!< DSP present or not */ 227 #define __CLIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 228 #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 229 #define __MPU_PRESENT 1 /*!< MPU present */ 230 #define __FPU_PRESENT 0 /*!< FPU present */ 231 #define __FPU_DP 0 /*!< Double Precision FPU */ 232 #define __INTERRUPTS_MAX 270 /*!< Size of interrupt vector table */ 233 234 #define NRF_VPR NRF_VPR00 /*!< VPR instance name */ 235 #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ 236 #include "system_nrf.h" /*!< nrf7120_enga_flpr System Library */ 237 238 #endif /*!< NRF_FLPR */ 239 240 241 #ifdef NRF_FLPR 242 243 #define NRF_DOMAIN NRF_DOMAIN_SYSTEM 244 #define NRF_PROCESSOR NRF_PROCESSOR_VPR 245 246 #endif /*!< NRF_FLPR */ 247 248 249 /* ========================================= Start of section using anonymous unions ========================================= */ 250 251 #include "compiler_abstraction.h" 252 253 #if defined (__CC_ARM) 254 #pragma push 255 #pragma anon_unions 256 #elif defined (__ICCARM__) 257 #pragma language=extended 258 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 259 #pragma clang diagnostic push 260 #pragma clang diagnostic ignored "-Wc11-extensions" 261 #pragma clang diagnostic ignored "-Wreserved-id-macro" 262 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 263 #pragma clang diagnostic ignored "-Wnested-anon-types" 264 #elif defined (__GNUC__) 265 /* anonymous unions are enabled by default */ 266 #elif defined (__TMS470__) 267 /* anonymous unions are enabled by default */ 268 #elif defined (__TASKING__) 269 #pragma warning 586 270 #elif defined (__CSMC__) 271 /* anonymous unions are enabled by default */ 272 #else 273 #warning Unsupported compiler type 274 #endif 275 276 /* =========================================================================================================================== */ 277 /* ================ Peripheral Address Map ================ */ 278 /* =========================================================================================================================== */ 279 280 #define NRF_FLPR_VPRCLIC_NS_BASE 0xF0000000UL 281 282 /* =========================================================================================================================== */ 283 /* ================ Peripheral Declaration ================ */ 284 /* =========================================================================================================================== */ 285 286 #define NRF_FLPR_VPRCLIC_NS ((NRF_CLIC_Type*) NRF_FLPR_VPRCLIC_NS_BASE) 287 288 /* =========================================================================================================================== */ 289 /* ================ TrustZone Remapping ================ */ 290 /* =========================================================================================================================== */ 291 292 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ 293 #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS 294 #else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ 295 #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS 296 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 297 298 /* =========================================================================================================================== */ 299 /* ================ Local Domain Remapping ================ */ 300 /* =========================================================================================================================== */ 301 302 #ifdef NRF_FLPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ 303 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ 304 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 305 #else /*!< Remap all instances. */ 306 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 307 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 308 #endif /*!< NRF_FLPR */ 309 310 /* ========================================== End of section using anonymous unions ========================================== */ 311 312 #if defined (__CC_ARM) 313 #pragma pop 314 #elif defined (__ICCARM__) 315 /* leave anonymous unions enabled */ 316 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 317 #pragma clang diagnostic pop 318 #elif defined (__GNUC__) 319 /* anonymous unions are enabled by default */ 320 #elif defined (__TMS470__) 321 /* anonymous unions are enabled by default */ 322 #elif defined (__TASKING__) 323 #pragma warning restore 324 #elif defined (__CSMC__) 325 /* anonymous unions are enabled by default */ 326 #endif 327 328 329 #ifdef __cplusplus 330 } 331 #endif 332 #endif /* NRF7120_ENGA_FLPR_H */ 333 334
