1 /* 2 3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54L20_ENGA_FLPR_H 36 #define NRF54L20_ENGA_FLPR_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_FLPR /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 /* ============================================== Processor Specific Interrupts ============================================== */ 53 VPRCLIC_0_IRQn = 0, /*!< 0 VPRCLIC_0 */ 54 VPRCLIC_1_IRQn = 1, /*!< 1 VPRCLIC_1 */ 55 VPRCLIC_2_IRQn = 2, /*!< 2 VPRCLIC_2 */ 56 VPRCLIC_3_IRQn = 3, /*!< 3 VPRCLIC_3 */ 57 VPRCLIC_4_IRQn = 4, /*!< 4 VPRCLIC_4 */ 58 VPRCLIC_5_IRQn = 5, /*!< 5 VPRCLIC_5 */ 59 VPRCLIC_6_IRQn = 6, /*!< 6 VPRCLIC_6 */ 60 VPRCLIC_7_IRQn = 7, /*!< 7 VPRCLIC_7 */ 61 VPRCLIC_8_IRQn = 8, /*!< 8 VPRCLIC_8 */ 62 VPRCLIC_9_IRQn = 9, /*!< 9 VPRCLIC_9 */ 63 VPRCLIC_10_IRQn = 10, /*!< 10 VPRCLIC_10 */ 64 VPRCLIC_11_IRQn = 11, /*!< 11 VPRCLIC_11 */ 65 VPRCLIC_12_IRQn = 12, /*!< 12 VPRCLIC_12 */ 66 VPRCLIC_13_IRQn = 13, /*!< 13 VPRCLIC_13 */ 67 VPRCLIC_14_IRQn = 14, /*!< 14 VPRCLIC_14 */ 68 VPRCLIC_15_IRQn = 15, /*!< 15 VPRCLIC_15 */ 69 VPRCLIC_16_IRQn = 16, /*!< 16 VPRCLIC_16 */ 70 VPRCLIC_17_IRQn = 17, /*!< 17 VPRCLIC_17 */ 71 VPRCLIC_18_IRQn = 18, /*!< 18 VPRCLIC_18 */ 72 VPRCLIC_19_IRQn = 19, /*!< 19 VPRCLIC_19 */ 73 VPRCLIC_20_IRQn = 20, /*!< 20 VPRCLIC_20 */ 74 VPRCLIC_21_IRQn = 21, /*!< 21 VPRCLIC_21 */ 75 VPRCLIC_22_IRQn = 22, /*!< 22 VPRCLIC_22 */ 76 VPRCLIC_23_IRQn = 23, /*!< 23 VPRCLIC_23 */ 77 VPRCLIC_24_IRQn = 24, /*!< 24 VPRCLIC_24 */ 78 VPRCLIC_25_IRQn = 25, /*!< 25 VPRCLIC_25 */ 79 VPRCLIC_26_IRQn = 26, /*!< 26 VPRCLIC_26 */ 80 VPRCLIC_27_IRQn = 27, /*!< 27 VPRCLIC_27 */ 81 VPRCLIC_28_IRQn = 28, /*!< 28 VPRCLIC_28 */ 82 VPRCLIC_29_IRQn = 29, /*!< 29 VPRCLIC_29 */ 83 VPRCLIC_30_IRQn = 30, /*!< 30 VPRCLIC_30 */ 84 VPRCLIC_31_IRQn = 31, /*!< 31 VPRCLIC_31 */ 85 SPU00_IRQn = 64, /*!< 64 SPU00 */ 86 MPC00_IRQn = 65, /*!< 65 MPC00 */ 87 AAR00_CCM00_IRQn = 74, /*!< 74 AAR00_CCM00 */ 88 ECB00_IRQn = 75, /*!< 75 ECB00 */ 89 VPR00_IRQn = 76, /*!< 76 VPR00 */ 90 SERIAL00_IRQn = 77, /*!< 77 SERIAL00 */ 91 RRAMC_IRQn = 78, /*!< 78 RRAMC */ 92 CTRLAP_IRQn = 82, /*!< 82 CTRLAP */ 93 CM33SS_IRQn = 84, /*!< 84 CM33SS */ 94 TIMER00_IRQn = 85, /*!< 85 TIMER00 */ 95 EGU00_IRQn = 88, /*!< 88 EGU00 */ 96 CRACEN_IRQn = 89, /*!< 89 CRACEN */ 97 USBHS_IRQn = 90, /*!< 90 USBHS */ 98 SPU10_IRQn = 128, /*!< 128 SPU10 */ 99 TIMER10_IRQn = 133, /*!< 133 TIMER10 */ 100 EGU10_IRQn = 135, /*!< 135 EGU10 */ 101 RADIO_0_IRQn = 138, /*!< 138 RADIO_0 */ 102 RADIO_1_IRQn = 139, /*!< 139 RADIO_1 */ 103 SPU20_IRQn = 192, /*!< 192 SPU20 */ 104 SERIAL20_IRQn = 198, /*!< 198 SERIAL20 */ 105 SERIAL21_IRQn = 199, /*!< 199 SERIAL21 */ 106 SERIAL22_IRQn = 200, /*!< 200 SERIAL22 */ 107 EGU20_IRQn = 201, /*!< 201 EGU20 */ 108 TIMER20_IRQn = 202, /*!< 202 TIMER20 */ 109 TIMER21_IRQn = 203, /*!< 203 TIMER21 */ 110 TIMER22_IRQn = 204, /*!< 204 TIMER22 */ 111 TIMER23_IRQn = 205, /*!< 205 TIMER23 */ 112 TIMER24_IRQn = 206, /*!< 206 TIMER24 */ 113 PDM20_IRQn = 208, /*!< 208 PDM20 */ 114 PDM21_IRQn = 209, /*!< 209 PDM21 */ 115 PWM20_IRQn = 210, /*!< 210 PWM20 */ 116 PWM21_IRQn = 211, /*!< 211 PWM21 */ 117 PWM22_IRQn = 212, /*!< 212 PWM22 */ 118 SAADC_IRQn = 213, /*!< 213 SAADC */ 119 NFCT_IRQn = 214, /*!< 214 NFCT */ 120 TEMP_IRQn = 215, /*!< 215 TEMP */ 121 GPIOTE20_0_IRQn = 218, /*!< 218 GPIOTE20_0 */ 122 GPIOTE20_1_IRQn = 219, /*!< 219 GPIOTE20_1 */ 123 QDEC20_IRQn = 224, /*!< 224 QDEC20 */ 124 QDEC21_IRQn = 225, /*!< 225 QDEC21 */ 125 GRTC_0_IRQn = 226, /*!< 226 GRTC_0 */ 126 GRTC_1_IRQn = 227, /*!< 227 GRTC_1 */ 127 GRTC_2_IRQn = 228, /*!< 228 GRTC_2 */ 128 GRTC_3_IRQn = 229, /*!< 229 GRTC_3 */ 129 TDM_IRQn = 232, /*!< 232 TDM */ 130 SERIAL23_IRQn = 237, /*!< 237 SERIAL23 */ 131 SERIAL24_IRQn = 238, /*!< 238 SERIAL24 */ 132 TAMPC_IRQn = 239, /*!< 239 TAMPC */ 133 SPU30_IRQn = 256, /*!< 256 SPU30 */ 134 SERIAL30_IRQn = 260, /*!< 260 SERIAL30 */ 135 COMP_LPCOMP_IRQn = 262, /*!< 262 COMP_LPCOMP */ 136 WDT30_IRQn = 264, /*!< 264 WDT30 */ 137 WDT31_IRQn = 265, /*!< 265 WDT31 */ 138 GPIOTE30_0_IRQn = 268, /*!< 268 GPIOTE30_0 */ 139 GPIOTE30_1_IRQn = 269, /*!< 269 GPIOTE30_1 */ 140 CLOCK_POWER_IRQn = 270, /*!< 270 CLOCK_POWER */ 141 VREGUSB_IRQn = 289, /*!< 289 VREGUSB */ 142 } IRQn_Type; 143 144 /* ==================================================== Interrupt Aliases ==================================================== */ 145 #define AAR00_IRQn AAR00_CCM00_IRQn 146 #define AAR00_IRQHandler AAR00_CCM00_IRQHandler 147 #define CCM00_IRQn AAR00_CCM00_IRQn 148 #define CCM00_IRQHandler AAR00_CCM00_IRQHandler 149 #define SPIM00_IRQn SERIAL00_IRQn 150 #define SPIM00_IRQHandler SERIAL00_IRQHandler 151 #define SPIS00_IRQn SERIAL00_IRQn 152 #define SPIS00_IRQHandler SERIAL00_IRQHandler 153 #define UARTE00_IRQn SERIAL00_IRQn 154 #define UARTE00_IRQHandler SERIAL00_IRQHandler 155 #define CPUC_IRQn CM33SS_IRQn 156 #define CPUC_IRQHandler CM33SS_IRQHandler 157 #define SPIM20_IRQn SERIAL20_IRQn 158 #define SPIM20_IRQHandler SERIAL20_IRQHandler 159 #define SPIS20_IRQn SERIAL20_IRQn 160 #define SPIS20_IRQHandler SERIAL20_IRQHandler 161 #define TWIM20_IRQn SERIAL20_IRQn 162 #define TWIM20_IRQHandler SERIAL20_IRQHandler 163 #define TWIS20_IRQn SERIAL20_IRQn 164 #define TWIS20_IRQHandler SERIAL20_IRQHandler 165 #define UARTE20_IRQn SERIAL20_IRQn 166 #define UARTE20_IRQHandler SERIAL20_IRQHandler 167 #define SPIM21_IRQn SERIAL21_IRQn 168 #define SPIM21_IRQHandler SERIAL21_IRQHandler 169 #define SPIS21_IRQn SERIAL21_IRQn 170 #define SPIS21_IRQHandler SERIAL21_IRQHandler 171 #define TWIM21_IRQn SERIAL21_IRQn 172 #define TWIM21_IRQHandler SERIAL21_IRQHandler 173 #define TWIS21_IRQn SERIAL21_IRQn 174 #define TWIS21_IRQHandler SERIAL21_IRQHandler 175 #define UARTE21_IRQn SERIAL21_IRQn 176 #define UARTE21_IRQHandler SERIAL21_IRQHandler 177 #define SPIM22_IRQn SERIAL22_IRQn 178 #define SPIM22_IRQHandler SERIAL22_IRQHandler 179 #define SPIS22_IRQn SERIAL22_IRQn 180 #define SPIS22_IRQHandler SERIAL22_IRQHandler 181 #define TWIM22_IRQn SERIAL22_IRQn 182 #define TWIM22_IRQHandler SERIAL22_IRQHandler 183 #define TWIS22_IRQn SERIAL22_IRQn 184 #define TWIS22_IRQHandler SERIAL22_IRQHandler 185 #define UARTE22_IRQn SERIAL22_IRQn 186 #define UARTE22_IRQHandler SERIAL22_IRQHandler 187 #define SPIM23_IRQn SERIAL23_IRQn 188 #define SPIM23_IRQHandler SERIAL23_IRQHandler 189 #define SPIS23_IRQn SERIAL23_IRQn 190 #define SPIS23_IRQHandler SERIAL23_IRQHandler 191 #define TWIM23_IRQn SERIAL23_IRQn 192 #define TWIM23_IRQHandler SERIAL23_IRQHandler 193 #define TWIS23_IRQn SERIAL23_IRQn 194 #define TWIS23_IRQHandler SERIAL23_IRQHandler 195 #define UARTE23_IRQn SERIAL23_IRQn 196 #define UARTE23_IRQHandler SERIAL23_IRQHandler 197 #define SPIM24_IRQn SERIAL24_IRQn 198 #define SPIM24_IRQHandler SERIAL24_IRQHandler 199 #define SPIS24_IRQn SERIAL24_IRQn 200 #define SPIS24_IRQHandler SERIAL24_IRQHandler 201 #define TWIM24_IRQn SERIAL24_IRQn 202 #define TWIM24_IRQHandler SERIAL24_IRQHandler 203 #define TWIS24_IRQn SERIAL24_IRQn 204 #define TWIS24_IRQHandler SERIAL24_IRQHandler 205 #define UARTE24_IRQn SERIAL24_IRQn 206 #define UARTE24_IRQHandler SERIAL24_IRQHandler 207 #define SPIM30_IRQn SERIAL30_IRQn 208 #define SPIM30_IRQHandler SERIAL30_IRQHandler 209 #define SPIS30_IRQn SERIAL30_IRQn 210 #define SPIS30_IRQHandler SERIAL30_IRQHandler 211 #define TWIM30_IRQn SERIAL30_IRQn 212 #define TWIM30_IRQHandler SERIAL30_IRQHandler 213 #define TWIS30_IRQn SERIAL30_IRQn 214 #define TWIS30_IRQHandler SERIAL30_IRQHandler 215 #define UARTE30_IRQn SERIAL30_IRQn 216 #define UARTE30_IRQHandler SERIAL30_IRQHandler 217 #define COMP_IRQn COMP_LPCOMP_IRQn 218 #define COMP_IRQHandler COMP_LPCOMP_IRQHandler 219 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 220 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 221 #define CLOCK_IRQn CLOCK_POWER_IRQn 222 #define CLOCK_IRQHandler CLOCK_POWER_IRQHandler 223 #define POWER_IRQn CLOCK_POWER_IRQn 224 #define POWER_IRQHandler CLOCK_POWER_IRQHandler 225 226 /* =========================================================================================================================== */ 227 /* ================ Processor and Core Peripheral Section ================ */ 228 /* =========================================================================================================================== */ 229 230 /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ 231 #define __VPR_REV 1.4.1 /*!< VPR Core Revision */ 232 #define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ 233 #define __VPR_REV_MINOR 4 /*!< VPR Core Minor Revision */ 234 #define __VPR_REV_PATCH 1 /*!< VPR Core Patch Revision */ 235 #define __DSP_PRESENT 0 /*!< DSP present or not */ 236 #define __CLIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 237 #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 238 #define __MPU_PRESENT 1 /*!< MPU present */ 239 #define __FPU_PRESENT 0 /*!< FPU present */ 240 #define __FPU_DP 0 /*!< Double Precision FPU */ 241 #define __INTERRUPTS_MAX 270 /*!< Size of interrupt vector table */ 242 243 #define NRF_VPR NRF_VPR00 /*!< VPR instance name */ 244 #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ 245 #include "system_nrf.h" /*!< nrf54l20_enga_flpr System Library */ 246 247 #endif /*!< NRF_FLPR */ 248 249 250 #ifdef NRF_FLPR 251 252 #define NRF_DOMAIN NRF_DOMAIN_NONE 253 #define NRF_PROCESSOR NRF_PROCESSOR_VPR 254 255 #endif /*!< NRF_FLPR */ 256 257 258 /* ========================================= Start of section using anonymous unions ========================================= */ 259 260 #include "compiler_abstraction.h" 261 262 #if defined (__CC_ARM) 263 #pragma push 264 #pragma anon_unions 265 #elif defined (__ICCARM__) 266 #pragma language=extended 267 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 268 #pragma clang diagnostic push 269 #pragma clang diagnostic ignored "-Wc11-extensions" 270 #pragma clang diagnostic ignored "-Wreserved-id-macro" 271 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 272 #pragma clang diagnostic ignored "-Wnested-anon-types" 273 #elif defined (__GNUC__) 274 /* anonymous unions are enabled by default */ 275 #elif defined (__TMS470__) 276 /* anonymous unions are enabled by default */ 277 #elif defined (__TASKING__) 278 #pragma warning 586 279 #elif defined (__CSMC__) 280 /* anonymous unions are enabled by default */ 281 #else 282 #warning Unsupported compiler type 283 #endif 284 285 /* =========================================================================================================================== */ 286 /* ================ Peripheral Address Map ================ */ 287 /* =========================================================================================================================== */ 288 289 #define NRF_FLPR_VPRCLIC_NS_BASE 0xF0000000UL 290 291 /* =========================================================================================================================== */ 292 /* ================ Peripheral Declaration ================ */ 293 /* =========================================================================================================================== */ 294 295 #define NRF_FLPR_VPRCLIC_NS ((NRF_CLIC_Type*) NRF_FLPR_VPRCLIC_NS_BASE) 296 297 /* =========================================================================================================================== */ 298 /* ================ TrustZone Remapping ================ */ 299 /* =========================================================================================================================== */ 300 301 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ 302 #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS 303 #else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ 304 #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS 305 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 306 307 /* =========================================================================================================================== */ 308 /* ================ Local Domain Remapping ================ */ 309 /* =========================================================================================================================== */ 310 311 #ifdef NRF_FLPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ 312 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ 313 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 314 #else /*!< Remap all instances. */ 315 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 316 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 317 #endif /*!< NRF_FLPR */ 318 319 /* ========================================== End of section using anonymous unions ========================================== */ 320 321 #if defined (__CC_ARM) 322 #pragma pop 323 #elif defined (__ICCARM__) 324 /* leave anonymous unions enabled */ 325 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 326 #pragma clang diagnostic pop 327 #elif defined (__GNUC__) 328 /* anonymous unions are enabled by default */ 329 #elif defined (__TMS470__) 330 /* anonymous unions are enabled by default */ 331 #elif defined (__TASKING__) 332 #pragma warning restore 333 #elif defined (__CSMC__) 334 /* anonymous unions are enabled by default */ 335 #endif 336 337 338 #ifdef __cplusplus 339 } 340 #endif 341 #endif /* NRF54L20_ENGA_FLPR_H */ 342 343
