1 /*
2 
3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef NRF54L10_INTERIM_H__
36 #define NRF54L10_INTERIM_H__
37 
38 #if defined(NRF54L10_XXAA)
39 
40 
41     #define NRF_DOMAIN_COUNT NRF_DOMAIN_NONE + 1
42 
43     #define ADDRESS_BUS_Pos (18UL)
44     #define ADDRESS_BUS_Msk (0x3FUL << ADDRESS_BUS_Pos)
45 
46 
47     #define PPIB00_CH_NUM 8
48     #define PPIB10_CH_NUM 8
49     #define PPIB11_CH_NUM 16
50     #define PPIB21_CH_NUM 16
51     #define PPIB22_CH_NUM 4
52     #define PPIB30_CH_NUM 4
53     #define PPIB20_CH_NUM 8
54     #define PPIB01_CH_NUM 8
55 
56     typedef enum
57     {
58         NRF_APB_INDEX_MCU   = 1,
59         NRF_APB_INDEX_RADIO = 2,
60         NRF_APB_INDEX_PERI  = 3,
61         NRF_APB_INDEX_LP    = 4
62     } nrf_apb_index_t;
63 
64     #if defined(NRF_FLPR)
65         #define GRTC_IRQ_GROUP   0
66         #define GPIOTE_IRQ_GROUP 0
67     #elif defined(NRF_APPLICATION)
68         #if defined(NRF_TRUSTZONE_NONSECURE)
69             #define GPIOTE_IRQ_GROUP       0
70             #define GRTC_IRQ_GROUP         1
71         #else
72             #define GPIOTE_IRQ_GROUP       1
73             #define GRTC_IRQ_GROUP         2
74         #endif
75     #endif
76 
77     #define EASYVDMA_PRESENT
78     #define VDMADESCRIPTOR_CONFIG_CNT_Pos (0UL)        /*!< Position of CNT field.                                               */
79     #define VDMADESCRIPTOR_CONFIG_CNT_Msk (0xFFFFFFUL << VDMADESCRIPTOR_CONFIG_CNT_Pos) /*!< Bit mask of CNT field.              */
80     #define VDMADESCRIPTOR_CONFIG_ATTRIBUTE_Pos (24UL) /*!< Position of ATTRIBUTE field.                                         */
81 
82     #define SAADC_CH_NUM SAADC_CH_MaxCount
83     #define SAADC_EASYDMA_MAXCNT_SIZE 15
84 
85     #define LPCOMP_REFSEL_RESOLUTION 16
86 
87     #define MPC_MASTER_PORTS_MaxCount (15UL) /*!< Max number of master ports. */
88 
89     #define GPIOTE20_CH_NUM GPIOTE20_GPIOTE_NCHANNELS_SIZE
90     #define GPIOTE30_CH_NUM GPIOTE30_GPIOTE_NCHANNELS_SIZE
91 
92     #define GPIOTE_CH_NUM   8
93     #define GPIOTE20_AVAILABLE_GPIO_PORTS 0x2UL
94     #define GPIOTE30_AVAILABLE_GPIO_PORTS 0x1UL
95     #define GPIOTE_FEATURE_SET_PRESENT
96     #define GPIOTE_FEATURE_CLR_PRESENT
97     #define GPIOTE_PORT_NUM GPIOTE_EVENTS_PORT_MaxCount
98 
99     #define DPPI_PRESENT DPPIC_PRESENT
100 
101     #define DPPIC00_CH_NUM DPPIC00_CH_NUM_SIZE
102     #define DPPIC10_CH_NUM DPPIC10_CH_NUM_SIZE
103     #define DPPIC20_CH_NUM DPPIC20_CH_NUM_SIZE
104     #define DPPIC30_CH_NUM DPPIC30_CH_NUM_SIZE
105 
106     #define DPPIC00_GROUP_NUM DPPIC00_GROUP_NUM_SIZE
107     #define DPPIC10_GROUP_NUM DPPIC10_GROUP_NUM_SIZE
108     #define DPPIC20_GROUP_NUM DPPIC20_GROUP_NUM_SIZE
109     #define DPPIC30_GROUP_NUM DPPIC30_GROUP_NUM_SIZE
110 
111     #define PPIB_CHANNEL_MAX_COUNT 24UL
112 
113     #define P0_PIN_NUM P0_PIN_NUM_SIZE
114     #define P1_PIN_NUM P1_PIN_NUM_SIZE
115     #define P2_PIN_NUM P2_PIN_NUM_SIZE
116 
117 
118     #define TIMER00_CC_NUM TIMER00_CC_NUM_SIZE
119     #define TIMER10_CC_NUM TIMER10_CC_NUM_SIZE
120     #define TIMER20_CC_NUM TIMER20_CC_NUM_SIZE
121     #define TIMER21_CC_NUM TIMER21_CC_NUM_SIZE
122     #define TIMER22_CC_NUM TIMER22_CC_NUM_SIZE
123     #define TIMER23_CC_NUM TIMER23_CC_NUM_SIZE
124     #define TIMER24_CC_NUM TIMER24_CC_NUM_SIZE
125 
126     #define TIMER00_MAX_SIZE TIMER00_MAX_SIZE_SIZE
127     #define TIMER10_MAX_SIZE TIMER10_MAX_SIZE_SIZE
128     #define TIMER20_MAX_SIZE TIMER20_MAX_SIZE_SIZE
129     #define TIMER21_MAX_SIZE TIMER21_MAX_SIZE_SIZE
130     #define TIMER22_MAX_SIZE TIMER22_MAX_SIZE_SIZE
131     #define TIMER23_MAX_SIZE TIMER23_MAX_SIZE_SIZE
132     #define TIMER24_MAX_SIZE TIMER24_MAX_SIZE_SIZE
133 
134     #define EGU10_CH_NUM EGU10_CH_NUM_SIZE
135     #define EGU20_CH_NUM EGU20_CH_NUM_SIZE
136 
137 
138     #define RTC10_CC_NUM RTC10_CC_NUM_SIZE
139     #define RTC30_CC_NUM RTC30_CC_NUM_SIZE
140 
141     #define I2S20_EASYDMA_MAXCNT_SIZE I2S20_EASYDMA_MAXCNT_SIZE_SIZE
142 
143     #define VPR_VEVIF_EVENT_MaxCount  32
144     #define VPR_CLIC_PRIO_COUNT       4
145     #define ADDRESS_SLAVE_Pos         (12UL)
146     #define ADDRESS_SLAVE_Msk         (0x3FUL << ADDRESS_SLAVE_Pos)
147 
148 
149 #endif
150 
151 #endif