1 /* 2 3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54L09_ENGA_FLPR_H 36 #define NRF54L09_ENGA_FLPR_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_FLPR /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 /* ============================================== Processor Specific Interrupts ============================================== */ 53 VPRCLIC_0_IRQn = 0, /*!< 0 VPRCLIC_0 */ 54 VPRCLIC_1_IRQn = 1, /*!< 1 VPRCLIC_1 */ 55 VPRCLIC_2_IRQn = 2, /*!< 2 VPRCLIC_2 */ 56 VPRCLIC_3_IRQn = 3, /*!< 3 VPRCLIC_3 */ 57 VPRCLIC_4_IRQn = 4, /*!< 4 VPRCLIC_4 */ 58 VPRCLIC_5_IRQn = 5, /*!< 5 VPRCLIC_5 */ 59 VPRCLIC_6_IRQn = 6, /*!< 6 VPRCLIC_6 */ 60 VPRCLIC_7_IRQn = 7, /*!< 7 VPRCLIC_7 */ 61 VPRCLIC_8_IRQn = 8, /*!< 8 VPRCLIC_8 */ 62 VPRCLIC_9_IRQn = 9, /*!< 9 VPRCLIC_9 */ 63 VPRCLIC_10_IRQn = 10, /*!< 10 VPRCLIC_10 */ 64 VPRCLIC_11_IRQn = 11, /*!< 11 VPRCLIC_11 */ 65 VPRCLIC_12_IRQn = 12, /*!< 12 VPRCLIC_12 */ 66 VPRCLIC_13_IRQn = 13, /*!< 13 VPRCLIC_13 */ 67 VPRCLIC_14_IRQn = 14, /*!< 14 VPRCLIC_14 */ 68 VPRCLIC_15_IRQn = 15, /*!< 15 VPRCLIC_15 */ 69 VPRCLIC_16_IRQn = 16, /*!< 16 VPRCLIC_16 */ 70 VPRCLIC_17_IRQn = 17, /*!< 17 VPRCLIC_17 */ 71 VPRCLIC_18_IRQn = 18, /*!< 18 VPRCLIC_18 */ 72 VPRCLIC_19_IRQn = 19, /*!< 19 VPRCLIC_19 */ 73 VPRCLIC_20_IRQn = 20, /*!< 20 VPRCLIC_20 */ 74 VPRCLIC_21_IRQn = 21, /*!< 21 VPRCLIC_21 */ 75 VPRCLIC_22_IRQn = 22, /*!< 22 VPRCLIC_22 */ 76 VPRCLIC_23_IRQn = 23, /*!< 23 VPRCLIC_23 */ 77 VPRCLIC_24_IRQn = 24, /*!< 24 VPRCLIC_24 */ 78 VPRCLIC_25_IRQn = 25, /*!< 25 VPRCLIC_25 */ 79 VPRCLIC_26_IRQn = 26, /*!< 26 VPRCLIC_26 */ 80 VPRCLIC_27_IRQn = 27, /*!< 27 VPRCLIC_27 */ 81 VPRCLIC_28_IRQn = 28, /*!< 28 VPRCLIC_28 */ 82 VPRCLIC_29_IRQn = 29, /*!< 29 VPRCLIC_29 */ 83 VPRCLIC_30_IRQn = 30, /*!< 30 VPRCLIC_30 */ 84 VPRCLIC_31_IRQn = 31, /*!< 31 VPRCLIC_31 */ 85 SPU00_IRQn = 64, /*!< 64 SPU00 */ 86 MPC00_IRQn = 65, /*!< 65 MPC00 */ 87 AAR00_CCM00_IRQn = 74, /*!< 74 AAR00_CCM00 */ 88 ECB00_IRQn = 75, /*!< 75 ECB00 */ 89 VPR00_IRQn = 76, /*!< 76 VPR00 */ 90 RRAMC_IRQn = 78, /*!< 78 RRAMC */ 91 CTRLAP_IRQn = 82, /*!< 82 CTRLAP */ 92 CM33SS_IRQn = 84, /*!< 84 CM33SS */ 93 TIMER00_IRQn = 85, /*!< 85 TIMER00 */ 94 EGU00_IRQn = 88, /*!< 88 EGU00 */ 95 CRACEN_IRQn = 89, /*!< 89 CRACEN */ 96 SPU10_IRQn = 128, /*!< 128 SPU10 */ 97 TIMER10_IRQn = 133, /*!< 133 TIMER10 */ 98 EGU10_IRQn = 135, /*!< 135 EGU10 */ 99 RADIO_0_IRQn = 138, /*!< 138 RADIO_0 */ 100 RADIO_1_IRQn = 139, /*!< 139 RADIO_1 */ 101 SPU20_IRQn = 192, /*!< 192 SPU20 */ 102 SERIAL20_IRQn = 198, /*!< 198 SERIAL20 */ 103 SERIAL21_IRQn = 199, /*!< 199 SERIAL21 */ 104 EGU20_IRQn = 201, /*!< 201 EGU20 */ 105 TIMER20_IRQn = 202, /*!< 202 TIMER20 */ 106 TIMER21_IRQn = 203, /*!< 203 TIMER21 */ 107 TIMER22_IRQn = 204, /*!< 204 TIMER22 */ 108 TIMER23_IRQn = 205, /*!< 205 TIMER23 */ 109 TIMER24_IRQn = 206, /*!< 206 TIMER24 */ 110 SAADC_IRQn = 213, /*!< 213 SAADC */ 111 TEMP_IRQn = 215, /*!< 215 TEMP */ 112 GPIOTE20_0_IRQn = 218, /*!< 218 GPIOTE20_0 */ 113 GPIOTE20_1_IRQn = 219, /*!< 219 GPIOTE20_1 */ 114 GRTC_0_IRQn = 226, /*!< 226 GRTC_0 */ 115 GRTC_1_IRQn = 227, /*!< 227 GRTC_1 */ 116 GRTC_2_IRQn = 228, /*!< 228 GRTC_2 */ 117 GRTC_3_IRQn = 229, /*!< 229 GRTC_3 */ 118 TAMPC_IRQn = 239, /*!< 239 TAMPC */ 119 SPU30_IRQn = 256, /*!< 256 SPU30 */ 120 SERIAL30_IRQn = 260, /*!< 260 SERIAL30 */ 121 COMP_LPCOMP_IRQn = 262, /*!< 262 COMP_LPCOMP */ 122 WDT30_IRQn = 264, /*!< 264 WDT30 */ 123 WDT31_IRQn = 265, /*!< 265 WDT31 */ 124 GPIOTE30_0_IRQn = 268, /*!< 268 GPIOTE30_0 */ 125 GPIOTE30_1_IRQn = 269, /*!< 269 GPIOTE30_1 */ 126 CLOCK_POWER_IRQn = 270, /*!< 270 CLOCK_POWER */ 127 } IRQn_Type; 128 129 /* ==================================================== Interrupt Aliases ==================================================== */ 130 #define AAR00_IRQn AAR00_CCM00_IRQn 131 #define AAR00_IRQHandler AAR00_CCM00_IRQHandler 132 #define CCM00_IRQn AAR00_CCM00_IRQn 133 #define CCM00_IRQHandler AAR00_CCM00_IRQHandler 134 #define CPUC_IRQn CM33SS_IRQn 135 #define CPUC_IRQHandler CM33SS_IRQHandler 136 #define SPIM20_IRQn SERIAL20_IRQn 137 #define SPIM20_IRQHandler SERIAL20_IRQHandler 138 #define SPIS20_IRQn SERIAL20_IRQn 139 #define SPIS20_IRQHandler SERIAL20_IRQHandler 140 #define TWIM20_IRQn SERIAL20_IRQn 141 #define TWIM20_IRQHandler SERIAL20_IRQHandler 142 #define TWIS20_IRQn SERIAL20_IRQn 143 #define TWIS20_IRQHandler SERIAL20_IRQHandler 144 #define UARTE20_IRQn SERIAL20_IRQn 145 #define UARTE20_IRQHandler SERIAL20_IRQHandler 146 #define SPIM21_IRQn SERIAL21_IRQn 147 #define SPIM21_IRQHandler SERIAL21_IRQHandler 148 #define SPIS21_IRQn SERIAL21_IRQn 149 #define SPIS21_IRQHandler SERIAL21_IRQHandler 150 #define TWIM21_IRQn SERIAL21_IRQn 151 #define TWIM21_IRQHandler SERIAL21_IRQHandler 152 #define TWIS21_IRQn SERIAL21_IRQn 153 #define TWIS21_IRQHandler SERIAL21_IRQHandler 154 #define UARTE21_IRQn SERIAL21_IRQn 155 #define UARTE21_IRQHandler SERIAL21_IRQHandler 156 #define SPIM30_IRQn SERIAL30_IRQn 157 #define SPIM30_IRQHandler SERIAL30_IRQHandler 158 #define SPIS30_IRQn SERIAL30_IRQn 159 #define SPIS30_IRQHandler SERIAL30_IRQHandler 160 #define TWIM30_IRQn SERIAL30_IRQn 161 #define TWIM30_IRQHandler SERIAL30_IRQHandler 162 #define TWIS30_IRQn SERIAL30_IRQn 163 #define TWIS30_IRQHandler SERIAL30_IRQHandler 164 #define UARTE30_IRQn SERIAL30_IRQn 165 #define UARTE30_IRQHandler SERIAL30_IRQHandler 166 #define COMP_IRQn COMP_LPCOMP_IRQn 167 #define COMP_IRQHandler COMP_LPCOMP_IRQHandler 168 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 169 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 170 #define CLOCK_IRQn CLOCK_POWER_IRQn 171 #define CLOCK_IRQHandler CLOCK_POWER_IRQHandler 172 #define POWER_IRQn CLOCK_POWER_IRQn 173 #define POWER_IRQHandler CLOCK_POWER_IRQHandler 174 175 /* =========================================================================================================================== */ 176 /* ================ Processor and Core Peripheral Section ================ */ 177 /* =========================================================================================================================== */ 178 179 /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ 180 #define __VPR_REV 1.4.1 /*!< VPR Core Revision */ 181 #define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ 182 #define __VPR_REV_MINOR 4 /*!< VPR Core Minor Revision */ 183 #define __VPR_REV_PATCH 1 /*!< VPR Core Patch Revision */ 184 #define __DSP_PRESENT 0 /*!< DSP present or not */ 185 #define __CLIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 186 #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 187 #define __MPU_PRESENT 1 /*!< MPU present */ 188 #define __FPU_PRESENT 0 /*!< FPU present */ 189 #define __FPU_DP 0 /*!< Double Precision FPU */ 190 #define __INTERRUPTS_MAX 270 /*!< Size of interrupt vector table */ 191 192 #define NRF_VPR NRF_VPR00 /*!< VPR instance name */ 193 #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ 194 #include "system_nrf.h" /*!< nrf54l09_enga_flpr System Library */ 195 196 #endif /*!< NRF_FLPR */ 197 198 199 #ifdef NRF_FLPR 200 201 #define NRF_DOMAIN NRF_DOMAIN_NONE 202 #define NRF_PROCESSOR NRF_PROCESSOR_VPR 203 204 #endif /*!< NRF_FLPR */ 205 206 207 /* ========================================= Start of section using anonymous unions ========================================= */ 208 209 #include "compiler_abstraction.h" 210 211 #if defined (__CC_ARM) 212 #pragma push 213 #pragma anon_unions 214 #elif defined (__ICCARM__) 215 #pragma language=extended 216 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 217 #pragma clang diagnostic push 218 #pragma clang diagnostic ignored "-Wc11-extensions" 219 #pragma clang diagnostic ignored "-Wreserved-id-macro" 220 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 221 #pragma clang diagnostic ignored "-Wnested-anon-types" 222 #elif defined (__GNUC__) 223 /* anonymous unions are enabled by default */ 224 #elif defined (__TMS470__) 225 /* anonymous unions are enabled by default */ 226 #elif defined (__TASKING__) 227 #pragma warning 586 228 #elif defined (__CSMC__) 229 /* anonymous unions are enabled by default */ 230 #else 231 #warning Unsupported compiler type 232 #endif 233 234 /* =========================================================================================================================== */ 235 /* ================ Peripheral Address Map ================ */ 236 /* =========================================================================================================================== */ 237 238 #define NRF_FLPR_VPRCLIC_NS_BASE 0xF0000000UL 239 240 /* =========================================================================================================================== */ 241 /* ================ Peripheral Declaration ================ */ 242 /* =========================================================================================================================== */ 243 244 #define NRF_FLPR_VPRCLIC_NS ((NRF_CLIC_Type*) NRF_FLPR_VPRCLIC_NS_BASE) 245 246 /* =========================================================================================================================== */ 247 /* ================ TrustZone Remapping ================ */ 248 /* =========================================================================================================================== */ 249 250 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap NRF_X_NS instances to NRF_X symbol for ease of use. */ 251 #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS 252 #else /*!< Remap NRF_X_S instances to NRF_X symbol for ease of use. */ 253 #define NRF_FLPR_VPRCLIC NRF_FLPR_VPRCLIC_NS 254 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 255 256 /* =========================================================================================================================== */ 257 /* ================ Local Domain Remapping ================ */ 258 /* =========================================================================================================================== */ 259 260 #ifdef NRF_FLPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ 261 #ifdef NRF_TRUSTZONE_NONSECURE /*!< Remap only nonsecure instances. */ 262 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 263 #else /*!< Remap all instances. */ 264 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 265 #endif /*!< NRF_TRUSTZONE_NONSECURE */ 266 #endif /*!< NRF_FLPR */ 267 268 /* ========================================== End of section using anonymous unions ========================================== */ 269 270 #if defined (__CC_ARM) 271 #pragma pop 272 #elif defined (__ICCARM__) 273 /* leave anonymous unions enabled */ 274 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 275 #pragma clang diagnostic pop 276 #elif defined (__GNUC__) 277 /* anonymous unions are enabled by default */ 278 #elif defined (__TMS470__) 279 /* anonymous unions are enabled by default */ 280 #elif defined (__TASKING__) 281 #pragma warning restore 282 #elif defined (__CSMC__) 283 /* anonymous unions are enabled by default */ 284 #endif 285 286 287 #ifdef __cplusplus 288 } 289 #endif 290 #endif /* NRF54L09_ENGA_FLPR_H */ 291 292
