1 /* 2 3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF54H20_FLPR_H 36 #define NRF54H20_FLPR_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 43 #ifdef NRF_FLPR /*!< Processor information is domain local. */ 44 45 46 /* =========================================================================================================================== */ 47 /* ================ Interrupt Number Definition ================ */ 48 /* =========================================================================================================================== */ 49 50 typedef enum { 51 /* ===================================================== Core Interrupts ===================================================== */ 52 /* ============================================== Processor Specific Interrupts ============================================== */ 53 VPRCLIC_0_IRQn = 0, /*!< 0 VPRCLIC_0 */ 54 VPRCLIC_1_IRQn = 1, /*!< 1 VPRCLIC_1 */ 55 VPRCLIC_2_IRQn = 2, /*!< 2 VPRCLIC_2 */ 56 VPRCLIC_3_IRQn = 3, /*!< 3 VPRCLIC_3 */ 57 VPRCLIC_4_IRQn = 4, /*!< 4 VPRCLIC_4 */ 58 VPRCLIC_5_IRQn = 5, /*!< 5 VPRCLIC_5 */ 59 VPRCLIC_6_IRQn = 6, /*!< 6 VPRCLIC_6 */ 60 VPRCLIC_7_IRQn = 7, /*!< 7 VPRCLIC_7 */ 61 VPRCLIC_8_IRQn = 8, /*!< 8 VPRCLIC_8 */ 62 VPRCLIC_9_IRQn = 9, /*!< 9 VPRCLIC_9 */ 63 VPRCLIC_10_IRQn = 10, /*!< 10 VPRCLIC_10 */ 64 VPRCLIC_11_IRQn = 11, /*!< 11 VPRCLIC_11 */ 65 VPRCLIC_12_IRQn = 12, /*!< 12 VPRCLIC_12 */ 66 VPRCLIC_13_IRQn = 13, /*!< 13 VPRCLIC_13 */ 67 VPRCLIC_14_IRQn = 14, /*!< 14 VPRCLIC_14 */ 68 VPRCLIC_15_IRQn = 15, /*!< 15 VPRCLIC_15 */ 69 VPRCLIC_16_IRQn = 16, /*!< 16 VPRCLIC_16 */ 70 VPRCLIC_17_IRQn = 17, /*!< 17 VPRCLIC_17 */ 71 VPRCLIC_18_IRQn = 18, /*!< 18 VPRCLIC_18 */ 72 VPRCLIC_19_IRQn = 19, /*!< 19 VPRCLIC_19 */ 73 VPRCLIC_20_IRQn = 20, /*!< 20 VPRCLIC_20 */ 74 VPRCLIC_21_IRQn = 21, /*!< 21 VPRCLIC_21 */ 75 VPRCLIC_22_IRQn = 22, /*!< 22 VPRCLIC_22 */ 76 VPRCLIC_23_IRQn = 23, /*!< 23 VPRCLIC_23 */ 77 VPRCLIC_24_IRQn = 24, /*!< 24 VPRCLIC_24 */ 78 VPRCLIC_25_IRQn = 25, /*!< 25 VPRCLIC_25 */ 79 VPRCLIC_26_IRQn = 26, /*!< 26 VPRCLIC_26 */ 80 VPRCLIC_27_IRQn = 27, /*!< 27 VPRCLIC_27 */ 81 VPRCLIC_28_IRQn = 28, /*!< 28 VPRCLIC_28 */ 82 VPRCLIC_29_IRQn = 29, /*!< 29 VPRCLIC_29 */ 83 VPRCLIC_30_IRQn = 30, /*!< 30 VPRCLIC_30 */ 84 VPRCLIC_31_IRQn = 31, /*!< 31 VPRCLIC_31 */ 85 VPRTIM_IRQn = 32, /*!< 32 VPRTIM */ 86 GPIOTE130_0_IRQn = 104, /*!< 104 GPIOTE130_0 */ 87 GPIOTE130_1_IRQn = 105, /*!< 105 GPIOTE130_1 */ 88 GRTC_0_IRQn = 108, /*!< 108 GRTC_0 */ 89 GRTC_1_IRQn = 109, /*!< 109 GRTC_1 */ 90 GRTC_2_IRQn = 110, /*!< 110 GRTC_2 */ 91 TBM_IRQn = 127, /*!< 127 TBM */ 92 USBHS_IRQn = 134, /*!< 134 USBHS */ 93 EXMIF_IRQn = 149, /*!< 149 EXMIF */ 94 IPCT120_0_IRQn = 209, /*!< 209 IPCT120_0 */ 95 I3C120_IRQn = 211, /*!< 211 I3C120 */ 96 VPR121_IRQn = 212, /*!< 212 VPR121 */ 97 CAN120_IRQn = 216, /*!< 216 CAN120 */ 98 MVDMA120_IRQn = 217, /*!< 217 MVDMA120 */ 99 I3C121_IRQn = 222, /*!< 222 I3C121 */ 100 TIMER120_IRQn = 226, /*!< 226 TIMER120 */ 101 TIMER121_IRQn = 227, /*!< 227 TIMER121 */ 102 PWM120_IRQn = 228, /*!< 228 PWM120 */ 103 SPIS120_IRQn = 229, /*!< 229 SPIS120 */ 104 SPIM120_UARTE120_IRQn = 230, /*!< 230 SPIM120_UARTE120 */ 105 SPIM121_IRQn = 231, /*!< 231 SPIM121 */ 106 VPR130_IRQn = 264, /*!< 264 VPR130 */ 107 IPCT130_0_IRQn = 289, /*!< 289 IPCT130_0 */ 108 RTC130_IRQn = 296, /*!< 296 RTC130 */ 109 RTC131_IRQn = 297, /*!< 297 RTC131 */ 110 WDT131_IRQn = 299, /*!< 299 WDT131 */ 111 WDT132_IRQn = 300, /*!< 300 WDT132 */ 112 EGU130_IRQn = 301, /*!< 301 EGU130 */ 113 SAADC_IRQn = 386, /*!< 386 SAADC */ 114 COMP_LPCOMP_IRQn = 387, /*!< 387 COMP_LPCOMP */ 115 TEMP_IRQn = 388, /*!< 388 TEMP */ 116 NFCT_IRQn = 389, /*!< 389 NFCT */ 117 TDM130_IRQn = 402, /*!< 402 TDM130 */ 118 PDM_IRQn = 403, /*!< 403 PDM */ 119 QDEC130_IRQn = 404, /*!< 404 QDEC130 */ 120 QDEC131_IRQn = 405, /*!< 405 QDEC131 */ 121 TDM131_IRQn = 407, /*!< 407 TDM131 */ 122 TIMER130_IRQn = 418, /*!< 418 TIMER130 */ 123 TIMER131_IRQn = 419, /*!< 419 TIMER131 */ 124 PWM130_IRQn = 420, /*!< 420 PWM130 */ 125 SERIAL0_IRQn = 421, /*!< 421 SERIAL0 */ 126 SERIAL1_IRQn = 422, /*!< 422 SERIAL1 */ 127 TIMER132_IRQn = 434, /*!< 434 TIMER132 */ 128 TIMER133_IRQn = 435, /*!< 435 TIMER133 */ 129 PWM131_IRQn = 436, /*!< 436 PWM131 */ 130 SERIAL2_IRQn = 437, /*!< 437 SERIAL2 */ 131 SERIAL3_IRQn = 438, /*!< 438 SERIAL3 */ 132 TIMER134_IRQn = 450, /*!< 450 TIMER134 */ 133 TIMER135_IRQn = 451, /*!< 451 TIMER135 */ 134 PWM132_IRQn = 452, /*!< 452 PWM132 */ 135 SERIAL4_IRQn = 453, /*!< 453 SERIAL4 */ 136 SERIAL5_IRQn = 454, /*!< 454 SERIAL5 */ 137 TIMER136_IRQn = 466, /*!< 466 TIMER136 */ 138 TIMER137_IRQn = 467, /*!< 467 TIMER137 */ 139 PWM133_IRQn = 468, /*!< 468 PWM133 */ 140 SERIAL6_IRQn = 469, /*!< 469 SERIAL6 */ 141 SERIAL7_IRQn = 470, /*!< 470 SERIAL7 */ 142 } IRQn_Type; 143 144 /* ==================================================== Interrupt Aliases ==================================================== */ 145 #define SPIM120_IRQn SPIM120_UARTE120_IRQn 146 #define SPIM120_IRQHandler SPIM120_UARTE120_IRQHandler 147 #define UARTE120_IRQn SPIM120_UARTE120_IRQn 148 #define UARTE120_IRQHandler SPIM120_UARTE120_IRQHandler 149 #define COMP_IRQn COMP_LPCOMP_IRQn 150 #define COMP_IRQHandler COMP_LPCOMP_IRQHandler 151 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 152 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 153 #define SPIM130_IRQn SERIAL0_IRQn 154 #define SPIM130_IRQHandler SERIAL0_IRQHandler 155 #define SPIS130_IRQn SERIAL0_IRQn 156 #define SPIS130_IRQHandler SERIAL0_IRQHandler 157 #define TWIM130_IRQn SERIAL0_IRQn 158 #define TWIM130_IRQHandler SERIAL0_IRQHandler 159 #define TWIS130_IRQn SERIAL0_IRQn 160 #define TWIS130_IRQHandler SERIAL0_IRQHandler 161 #define UARTE130_IRQn SERIAL0_IRQn 162 #define UARTE130_IRQHandler SERIAL0_IRQHandler 163 #define SPIM131_IRQn SERIAL1_IRQn 164 #define SPIM131_IRQHandler SERIAL1_IRQHandler 165 #define SPIS131_IRQn SERIAL1_IRQn 166 #define SPIS131_IRQHandler SERIAL1_IRQHandler 167 #define TWIM131_IRQn SERIAL1_IRQn 168 #define TWIM131_IRQHandler SERIAL1_IRQHandler 169 #define TWIS131_IRQn SERIAL1_IRQn 170 #define TWIS131_IRQHandler SERIAL1_IRQHandler 171 #define UARTE131_IRQn SERIAL1_IRQn 172 #define UARTE131_IRQHandler SERIAL1_IRQHandler 173 #define SPIM132_IRQn SERIAL2_IRQn 174 #define SPIM132_IRQHandler SERIAL2_IRQHandler 175 #define SPIS132_IRQn SERIAL2_IRQn 176 #define SPIS132_IRQHandler SERIAL2_IRQHandler 177 #define TWIM132_IRQn SERIAL2_IRQn 178 #define TWIM132_IRQHandler SERIAL2_IRQHandler 179 #define TWIS132_IRQn SERIAL2_IRQn 180 #define TWIS132_IRQHandler SERIAL2_IRQHandler 181 #define UARTE132_IRQn SERIAL2_IRQn 182 #define UARTE132_IRQHandler SERIAL2_IRQHandler 183 #define SPIM133_IRQn SERIAL3_IRQn 184 #define SPIM133_IRQHandler SERIAL3_IRQHandler 185 #define SPIS133_IRQn SERIAL3_IRQn 186 #define SPIS133_IRQHandler SERIAL3_IRQHandler 187 #define TWIM133_IRQn SERIAL3_IRQn 188 #define TWIM133_IRQHandler SERIAL3_IRQHandler 189 #define TWIS133_IRQn SERIAL3_IRQn 190 #define TWIS133_IRQHandler SERIAL3_IRQHandler 191 #define UARTE133_IRQn SERIAL3_IRQn 192 #define UARTE133_IRQHandler SERIAL3_IRQHandler 193 #define SPIM134_IRQn SERIAL4_IRQn 194 #define SPIM134_IRQHandler SERIAL4_IRQHandler 195 #define SPIS134_IRQn SERIAL4_IRQn 196 #define SPIS134_IRQHandler SERIAL4_IRQHandler 197 #define TWIM134_IRQn SERIAL4_IRQn 198 #define TWIM134_IRQHandler SERIAL4_IRQHandler 199 #define TWIS134_IRQn SERIAL4_IRQn 200 #define TWIS134_IRQHandler SERIAL4_IRQHandler 201 #define UARTE134_IRQn SERIAL4_IRQn 202 #define UARTE134_IRQHandler SERIAL4_IRQHandler 203 #define SPIM135_IRQn SERIAL5_IRQn 204 #define SPIM135_IRQHandler SERIAL5_IRQHandler 205 #define SPIS135_IRQn SERIAL5_IRQn 206 #define SPIS135_IRQHandler SERIAL5_IRQHandler 207 #define TWIM135_IRQn SERIAL5_IRQn 208 #define TWIM135_IRQHandler SERIAL5_IRQHandler 209 #define TWIS135_IRQn SERIAL5_IRQn 210 #define TWIS135_IRQHandler SERIAL5_IRQHandler 211 #define UARTE135_IRQn SERIAL5_IRQn 212 #define UARTE135_IRQHandler SERIAL5_IRQHandler 213 #define SPIM136_IRQn SERIAL6_IRQn 214 #define SPIM136_IRQHandler SERIAL6_IRQHandler 215 #define SPIS136_IRQn SERIAL6_IRQn 216 #define SPIS136_IRQHandler SERIAL6_IRQHandler 217 #define TWIM136_IRQn SERIAL6_IRQn 218 #define TWIM136_IRQHandler SERIAL6_IRQHandler 219 #define TWIS136_IRQn SERIAL6_IRQn 220 #define TWIS136_IRQHandler SERIAL6_IRQHandler 221 #define UARTE136_IRQn SERIAL6_IRQn 222 #define UARTE136_IRQHandler SERIAL6_IRQHandler 223 #define SPIM137_IRQn SERIAL7_IRQn 224 #define SPIM137_IRQHandler SERIAL7_IRQHandler 225 #define SPIS137_IRQn SERIAL7_IRQn 226 #define SPIS137_IRQHandler SERIAL7_IRQHandler 227 #define TWIM137_IRQn SERIAL7_IRQn 228 #define TWIM137_IRQHandler SERIAL7_IRQHandler 229 #define TWIS137_IRQn SERIAL7_IRQn 230 #define TWIS137_IRQHandler SERIAL7_IRQHandler 231 #define UARTE137_IRQn SERIAL7_IRQn 232 #define UARTE137_IRQHandler SERIAL7_IRQHandler 233 234 /* =========================================================================================================================== */ 235 /* ================ Processor and Core Peripheral Section ================ */ 236 /* =========================================================================================================================== */ 237 238 /* ====================== Configuration of the Nordic Semiconductor VPR Processor and Core Peripherals ======================= */ 239 #define __VPR_REV 1.1 /*!< VPR Core Revision */ 240 #define __VPR_REV_MAJOR 1 /*!< VPR Core Major Revision */ 241 #define __VPR_REV_MINOR 1 /*!< VPR Core Minor Revision */ 242 #define __VPR_REV_PATCH 0 /*!< VPR Core Patch Revision */ 243 #define __DSP_PRESENT 0 /*!< DSP present or not */ 244 #define __CLIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 245 #define __MTVT_PRESENT 1 /*!< CPU supports alternate Vector Table address */ 246 #define __MPU_PRESENT 1 /*!< MPU present */ 247 #define __FPU_PRESENT 0 /*!< FPU present */ 248 #define __FPU_DP 0 /*!< Double Precision FPU */ 249 #define __INTERRUPTS_MAX 480 /*!< Size of interrupt vector table */ 250 251 #define NRF_VPR NRF_VPR121 /*!< VPR instance name */ 252 #include "core_vpr.h" /*!< Nordic Semiconductor VPR processor and core peripherals */ 253 #include "system_nrf.h" /*!< nrf54h20_flpr System Library */ 254 255 #endif /*!< NRF_FLPR */ 256 257 258 #ifdef NRF_FLPR 259 260 #define NRF_DOMAIN NRF_DOMAIN_GLOBALFAST 261 #define NRF_PROCESSOR NRF_PROCESSOR_FLPR 262 #ifndef NRF_OWNER 263 #define NRF_OWNER NRF_OWNER_APPLICATION 264 #endif 265 266 #endif /*!< NRF_FLPR */ 267 268 269 /* ========================================= Start of section using anonymous unions ========================================= */ 270 271 #include "compiler_abstraction.h" 272 273 #if defined (__CC_ARM) 274 #pragma push 275 #pragma anon_unions 276 #elif defined (__ICCARM__) 277 #pragma language=extended 278 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 279 #pragma clang diagnostic push 280 #pragma clang diagnostic ignored "-Wc11-extensions" 281 #pragma clang diagnostic ignored "-Wreserved-id-macro" 282 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 283 #pragma clang diagnostic ignored "-Wnested-anon-types" 284 #elif defined (__GNUC__) 285 /* anonymous unions are enabled by default */ 286 #elif defined (__TMS470__) 287 /* anonymous unions are enabled by default */ 288 #elif defined (__TASKING__) 289 #pragma warning 586 290 #elif defined (__CSMC__) 291 /* anonymous unions are enabled by default */ 292 #else 293 #warning Unsupported compiler type 294 #endif 295 296 /* =========================================================================================================================== */ 297 /* ================ Peripheral Address Map ================ */ 298 /* =========================================================================================================================== */ 299 300 #define NRF_FLPR_VPRCLIC_BASE 0xF0000000UL 301 302 /* =========================================================================================================================== */ 303 /* ================ Peripheral Declaration ================ */ 304 /* =========================================================================================================================== */ 305 306 #define NRF_FLPR_VPRCLIC ((NRF_CLIC_Type*) NRF_FLPR_VPRCLIC_BASE) 307 308 /* =========================================================================================================================== */ 309 /* ================ Local Domain Remapping ================ */ 310 /* =========================================================================================================================== */ 311 312 #ifdef NRF_FLPR /*!< Remap NRF_DOMAIN_X instances to NRF_X symbol for ease of use. */ 313 #define NRF_VPRCLIC NRF_FLPR_VPRCLIC 314 #endif /*!< NRF_FLPR */ 315 316 /* ========================================== End of section using anonymous unions ========================================== */ 317 318 #if defined (__CC_ARM) 319 #pragma pop 320 #elif defined (__ICCARM__) 321 /* leave anonymous unions enabled */ 322 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 323 #pragma clang diagnostic pop 324 #elif defined (__GNUC__) 325 /* anonymous unions are enabled by default */ 326 #elif defined (__TMS470__) 327 /* anonymous unions are enabled by default */ 328 #elif defined (__TASKING__) 329 #pragma warning restore 330 #elif defined (__CSMC__) 331 /* anonymous unions are enabled by default */ 332 #endif 333 334 335 #ifdef __cplusplus 336 } 337 #endif 338 #endif /* NRF54H20_FLPR_H */ 339 340
