1/*
2 * Copyright (c) 2019-2020 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/*
8 * Default Flash planning for nrf5340dk_nrf5340 CPUAPP (Application MCU).
9 *
10 * Zephyr build for nRF5340 with ARM TrustZone-M support,
11 * implies building Secure and Non-Secure Zephyr images.
12 *
13 * Secure image will be placed, by default, in flash0
14 * (or in slot0, if MCUboot is present).
15 * Secure image will use sram0 for system memory.
16 *
17 * Non-Secure image will be placed in slot0_ns, and use
18 * sram0_ns for system memory.
19 *
20 * Note that the Secure image only requires knowledge of
21 * the beginning of the Non-Secure image (not its size).
22 */
23
24&slot0_partition {
25	reg = <0x00010000 0x40000>;
26};
27
28&slot0_ns_partition {
29	reg = <0x00050000 0x30000>;
30};
31
32&slot1_partition {
33	reg = <0x00080000 0x40000>;
34};
35
36&slot1_ns_partition {
37	reg = <0x000c0000 0x30000>;
38};
39
40/* Default SRAM planning when building for nRF5340 with
41 * ARM TrustZone-M support
42 * - Lowest 256 kB SRAM allocated to Secure image (sram0_s)
43 * - Middle 192 kB allocated to Non-Secure image (sram0_ns)
44 * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
45 *   (see nrf5340_shared_sram_planning_conf.dtsi)
46 */
47&sram0_image {
48	reg = <0x20000000 DT_SIZE_K(448)>;
49};
50
51&sram0_s {
52	reg = <0x20000000 0x40000>;
53};
54
55&sram0_ns {
56	reg = <0x20040000 0x30000>;
57};
58
59/* Include shared RAM configuration file */
60#include "nrf5340_shared_sram_planning_conf.dtsi"
61