1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 6)>,
10				<NRF_PSEL(UART_RX, 0, 8)>,
11				<NRF_PSEL(UART_RTS, 0, 5)>,
12				<NRF_PSEL(UART_CTS, 0, 7)>;
13		};
14	};
15
16	uart0_sleep: uart0_sleep {
17		group1 {
18			psels = <NRF_PSEL(UART_TX, 0, 6)>,
19				<NRF_PSEL(UART_RX, 0, 8)>,
20				<NRF_PSEL(UART_RTS, 0, 5)>,
21				<NRF_PSEL(UART_CTS, 0, 7)>;
22			low-power-enable;
23		};
24	};
25
26	i2c0_default: i2c0_default {
27		group1 {
28			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
29				<NRF_PSEL(TWIM_SCL, 0, 27)>;
30		};
31	};
32
33	i2c0_sleep: i2c0_sleep {
34		group1 {
35			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
36				<NRF_PSEL(TWIM_SCL, 0, 27)>;
37			low-power-enable;
38		};
39	};
40
41	spi0_default: spi0_default {
42		group1 {
43			psels = <NRF_PSEL(SPIM_SCK, 0, 29)>,
44				<NRF_PSEL(SPIM_MOSI, 0, 31)>,
45				<NRF_PSEL(SPIM_MISO, 0, 30)>;
46		};
47	};
48
49	spi0_sleep: spi0_sleep {
50		group1 {
51			psels = <NRF_PSEL(SPIM_SCK, 0, 29)>,
52				<NRF_PSEL(SPIM_MOSI, 0, 31)>,
53				<NRF_PSEL(SPIM_MISO, 0, 30)>;
54			low-power-enable;
55		};
56	};
57
58};
59