1 /* 2 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n 3 \n 4 SPDX-License-Identifier: BSD-3-Clause\n 5 \n 6 Redistribution and use in source and binary forms, with or without\n 7 modification, are permitted provided that the following conditions are met:\n 8 \n 9 1. Redistributions of source code must retain the above copyright notice, this\n 10 list of conditions and the following disclaimer.\n 11 \n 12 2. Redistributions in binary form must reproduce the above copyright\n 13 notice, this list of conditions and the following disclaimer in the\n 14 documentation and/or other materials provided with the distribution.\n 15 \n 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n 17 contributors may be used to endorse or promote products derived from this\n 18 software without specific prior written permission.\n 19 \n 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n 30 POSSIBILITY OF SUCH DAMAGE.\n 31 * 32 * @file nrf52833.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 19. December 2023 36 * @note Generated by SVDConv V3.3.35 on Tuesday, 19.12.2023 10:19:52 37 * from File 'nrf52833.svd', 38 * last modified on Tuesday, 19.12.2023 09:18:47 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf52833 49 * @{ 50 */ 51 52 53 #ifndef NRF52833_H 54 #define NRF52833_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 82 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 83 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 84 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 85 /* ========================================== nrf52833 Specific Interrupt Numbers ========================================== */ 86 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 87 RADIO_IRQn = 1, /*!< 1 RADIO */ 88 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 89 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ 90 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ 91 NFCT_IRQn = 5, /*!< 5 NFCT */ 92 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 93 SAADC_IRQn = 7, /*!< 7 SAADC */ 94 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 95 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 96 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 97 RTC0_IRQn = 11, /*!< 11 RTC0 */ 98 TEMP_IRQn = 12, /*!< 12 TEMP */ 99 RNG_IRQn = 13, /*!< 13 RNG */ 100 ECB_IRQn = 14, /*!< 14 ECB */ 101 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 102 WDT_IRQn = 16, /*!< 16 WDT */ 103 RTC1_IRQn = 17, /*!< 17 RTC1 */ 104 QDEC_IRQn = 18, /*!< 18 QDEC */ 105 COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ 106 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 107 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 108 SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ 109 SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ 110 SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ 111 SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ 112 TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 113 TIMER4_IRQn = 27, /*!< 27 TIMER4 */ 114 PWM0_IRQn = 28, /*!< 28 PWM0 */ 115 PDM_IRQn = 29, /*!< 29 PDM */ 116 MWU_IRQn = 32, /*!< 32 MWU */ 117 PWM1_IRQn = 33, /*!< 33 PWM1 */ 118 PWM2_IRQn = 34, /*!< 34 PWM2 */ 119 SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ 120 RTC2_IRQn = 36, /*!< 36 RTC2 */ 121 I2S_IRQn = 37, /*!< 37 I2S */ 122 FPU_IRQn = 38, /*!< 38 FPU */ 123 USBD_IRQn = 39, /*!< 39 USBD */ 124 UARTE1_IRQn = 40, /*!< 40 UARTE1 */ 125 PWM3_IRQn = 45, /*!< 45 PWM3 */ 126 SPIM3_IRQn = 47 /*!< 47 SPIM3 */ 127 } IRQn_Type; 128 129 130 131 /* =========================================================================================================================== */ 132 /* ================ Processor and Core Peripheral Section ================ */ 133 /* =========================================================================================================================== */ 134 135 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 136 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 137 #define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ 138 #define __DSP_PRESENT 1 /*!< DSP present or not */ 139 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 140 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 141 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 142 #define __MPU_PRESENT 1 /*!< MPU present */ 143 #define __FPU_PRESENT 1 /*!< FPU present */ 144 145 146 /** @} */ /* End of group Configuration_of_CMSIS */ 147 148 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 149 #include "system_nrf52833.h" /*!< nrf52833 System */ 150 151 #ifndef __IM /*!< Fallback for older CMSIS versions */ 152 #define __IM __I 153 #endif 154 #ifndef __OM /*!< Fallback for older CMSIS versions */ 155 #define __OM __O 156 #endif 157 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 158 #define __IOM __IO 159 #endif 160 161 162 /* ======================================== Start of section using anonymous unions ======================================== */ 163 #if defined (__CC_ARM) 164 #pragma push 165 #pragma anon_unions 166 #elif defined (__ICCARM__) 167 #pragma language=extended 168 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 169 #pragma clang diagnostic push 170 #pragma clang diagnostic ignored "-Wc11-extensions" 171 #pragma clang diagnostic ignored "-Wreserved-id-macro" 172 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 173 #pragma clang diagnostic ignored "-Wnested-anon-types" 174 #elif defined (__GNUC__) 175 /* anonymous unions are enabled by default */ 176 #elif defined (__TMS470__) 177 /* anonymous unions are enabled by default */ 178 #elif defined (__TASKING__) 179 #pragma warning 586 180 #elif defined (__CSMC__) 181 /* anonymous unions are enabled by default */ 182 #else 183 #warning Not supported compiler type 184 #endif 185 186 187 /* =========================================================================================================================== */ 188 /* ================ Device Specific Cluster Section ================ */ 189 /* =========================================================================================================================== */ 190 191 192 /** @addtogroup Device_Peripheral_clusters 193 * @{ 194 */ 195 196 197 /** 198 * @brief FICR_INFO [INFO] (Device info) 199 */ 200 typedef struct { 201 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 202 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ 203 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 204 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 205 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 206 } FICR_INFO_Type; /*!< Size = 20 (0x14) */ 207 208 209 /** 210 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 211 */ 212 typedef struct { 213 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 214 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 215 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 216 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 217 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 218 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 219 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 220 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 221 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 222 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 223 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 224 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 225 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 226 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 227 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 228 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 229 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 230 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 231 232 233 /** 234 * @brief FICR_NFC [NFC] (Unspecified) 235 */ 236 typedef struct { 237 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read 238 these values to populate NFCID1_3RD_LAST, 239 NFCID1_2ND_LAST, and NFCID1_LAST. */ 240 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read 241 these values to populate NFCID1_3RD_LAST, 242 NFCID1_2ND_LAST, and NFCID1_LAST. */ 243 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read 244 these values to populate NFCID1_3RD_LAST, 245 NFCID1_2ND_LAST, and NFCID1_LAST. */ 246 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read 247 these values to populate NFCID1_3RD_LAST, 248 NFCID1_2ND_LAST, and NFCID1_LAST. */ 249 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 250 251 252 /** 253 * @brief POWER_RAM [RAM] (Unspecified) 254 */ 255 typedef struct { 256 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 257 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 258 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 259 register */ 260 __IM uint32_t RESERVED; 261 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 262 263 264 /** 265 * @brief RADIO_PSEL [PSEL] (Unspecified) 266 */ 267 typedef struct { 268 __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin 269 n */ 270 } RADIO_PSEL_Type; /*!< Size = 32 (0x20) */ 271 272 273 /** 274 * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel) 275 */ 276 typedef struct { 277 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 278 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 279 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */ 280 } RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */ 281 282 283 /** 284 * @brief UART_PSEL [PSEL] (Unspecified) 285 */ 286 typedef struct { 287 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 288 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 289 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 290 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 291 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 292 293 294 /** 295 * @brief UARTE_PSEL [PSEL] (Unspecified) 296 */ 297 typedef struct { 298 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 299 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 300 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 301 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 302 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 303 304 305 /** 306 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 307 */ 308 typedef struct { 309 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 310 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 311 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 312 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 313 314 315 /** 316 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 317 */ 318 typedef struct { 319 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 320 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 321 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 322 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 323 324 325 /** 326 * @brief SPI_PSEL [PSEL] (Unspecified) 327 */ 328 typedef struct { 329 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 330 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 331 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 332 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 333 334 335 /** 336 * @brief SPIM_PSEL [PSEL] (Unspecified) 337 */ 338 typedef struct { 339 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 340 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 341 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 342 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ 343 } SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ 344 345 346 /** 347 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 348 */ 349 typedef struct { 350 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 351 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 352 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 353 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 354 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 355 356 357 /** 358 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 359 */ 360 typedef struct { 361 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 362 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 363 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 364 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 365 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 366 367 368 /** 369 * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) 370 */ 371 typedef struct { 372 __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ 373 __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge 374 of SCK and minimum duration CSN must stay 375 high between transactions */ 376 } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ 377 378 379 /** 380 * @brief SPIS_PSEL [PSEL] (Unspecified) 381 */ 382 typedef struct { 383 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 384 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 385 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 386 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 387 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 388 389 390 /** 391 * @brief SPIS_RXD [RXD] (Unspecified) 392 */ 393 typedef struct { 394 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 395 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 396 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 397 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 398 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 399 400 401 /** 402 * @brief SPIS_TXD [TXD] (Unspecified) 403 */ 404 typedef struct { 405 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 406 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 407 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 408 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 409 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 410 411 412 /** 413 * @brief TWI_PSEL [PSEL] (Unspecified) 414 */ 415 typedef struct { 416 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 417 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 418 } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 419 420 421 /** 422 * @brief TWIM_PSEL [PSEL] (Unspecified) 423 */ 424 typedef struct { 425 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 426 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 427 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 428 429 430 /** 431 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 432 */ 433 typedef struct { 434 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 435 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 436 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 437 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 438 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 439 440 441 /** 442 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 443 */ 444 typedef struct { 445 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 446 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 447 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 448 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 449 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 450 451 452 /** 453 * @brief TWIS_PSEL [PSEL] (Unspecified) 454 */ 455 typedef struct { 456 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 457 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 458 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 459 460 461 /** 462 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 463 */ 464 typedef struct { 465 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 466 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 467 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 468 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 469 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 470 471 472 /** 473 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 474 */ 475 typedef struct { 476 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 477 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 478 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 479 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 480 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 481 482 483 /** 484 * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 485 */ 486 typedef struct { 487 __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ 488 } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 489 490 491 /** 492 * @brief NFCT_TXD [TXD] (Unspecified) 493 */ 494 typedef struct { 495 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 496 __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 497 } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 498 499 500 /** 501 * @brief NFCT_RXD [RXD] (Unspecified) 502 */ 503 typedef struct { 504 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 505 __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 506 } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 507 508 509 /** 510 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 511 */ 512 typedef struct { 513 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or 514 above CH[n].LIMIT.HIGH */ 515 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or 516 below CH[n].LIMIT.LOW */ 517 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 518 519 520 /** 521 * @brief SAADC_CH [CH] (Unspecified) 522 */ 523 typedef struct { 524 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 525 for CH[n] */ 526 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 527 for CH[n] */ 528 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 529 CH[n] */ 530 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 531 monitoring of a channel */ 532 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 533 534 535 /** 536 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 537 */ 538 typedef struct { 539 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 540 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written 541 to output RAM buffer */ 542 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM 543 buffer since the previous START task */ 544 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 545 546 547 /** 548 * @brief QDEC_PSEL [PSEL] (Unspecified) 549 */ 550 typedef struct { 551 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 552 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 553 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 554 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 555 556 557 /** 558 * @brief PWM_SEQ [SEQ] (Unspecified) 559 */ 560 typedef struct { 561 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 562 of this sequence */ 563 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 564 in this sequence */ 565 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 566 periods between samples loaded into compare 567 register */ 568 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 569 __IM uint32_t RESERVED[4]; 570 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 571 572 573 /** 574 * @brief PWM_PSEL [PSEL] (Unspecified) 575 */ 576 typedef struct { 577 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 578 PWM channel n */ 579 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 580 581 582 /** 583 * @brief PDM_PSEL [PSEL] (Unspecified) 584 */ 585 typedef struct { 586 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 587 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 588 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 589 590 591 /** 592 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 593 */ 594 typedef struct { 595 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 596 EasyDMA */ 597 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 598 mode */ 599 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 600 601 602 /** 603 * @brief ACL_ACL [ACL] (Unspecified) 604 */ 605 typedef struct { 606 __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region 607 to protect. The start address must be word-aligned. */ 608 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect 609 counting from address ACL[n].ADDR. Writing 610 a '0' has no effect. */ 611 __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region 612 n as defined by start address ACL[n].ADDR 613 and size ACL[n].SIZE */ 614 __IM uint32_t RESERVED; 615 } ACL_ACL_Type; /*!< Size = 16 (0x10) */ 616 617 618 /** 619 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 620 */ 621 typedef struct { 622 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 623 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 624 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 625 626 627 /** 628 * @brief PPI_CH [CH] (PPI Channel) 629 */ 630 typedef struct { 631 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ 632 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ 633 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 634 635 636 /** 637 * @brief PPI_FORK [FORK] (Fork) 638 */ 639 typedef struct { 640 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ 641 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 642 643 644 /** 645 * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.) 646 */ 647 typedef struct { 648 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n 649 detected */ 650 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n 651 detected */ 652 } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ 653 654 655 /** 656 * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.) 657 */ 658 typedef struct { 659 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral 660 region n detected */ 661 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral 662 region n detected */ 663 } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ 664 665 666 /** 667 * @brief MWU_PERREGION [PERREGION] (Unspecified) 668 */ 669 typedef struct { 670 __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt 671 in region n, write access detected while 672 corresponding subregion was enabled for 673 watching */ 674 __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt 675 in region n, read access detected while 676 corresponding subregion was enabled for 677 watching */ 678 } MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ 679 680 681 /** 682 * @brief MWU_REGION [REGION] (Unspecified) 683 */ 684 typedef struct { 685 __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region 686 n */ 687 __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */ 688 __IM uint32_t RESERVED[2]; 689 } MWU_REGION_Type; /*!< Size = 16 (0x10) */ 690 691 692 /** 693 * @brief MWU_PREGION [PREGION] (Unspecified) 694 */ 695 typedef struct { 696 __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */ 697 __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */ 698 __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */ 699 __IM uint32_t RESERVED; 700 } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ 701 702 703 /** 704 * @brief I2S_CONFIG [CONFIG] (Unspecified) 705 */ 706 typedef struct { 707 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 708 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 709 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 710 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 711 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 712 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 713 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 714 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 715 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 716 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 717 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 718 719 720 /** 721 * @brief I2S_RXD [RXD] (Unspecified) 722 */ 723 typedef struct { 724 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 725 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 726 727 728 /** 729 * @brief I2S_TXD [TXD] (Unspecified) 730 */ 731 typedef struct { 732 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 733 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 734 735 736 /** 737 * @brief I2S_RXTXD [RXTXD] (Unspecified) 738 */ 739 typedef struct { 740 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 741 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 742 743 744 /** 745 * @brief I2S_PSEL [PSEL] (Unspecified) 746 */ 747 typedef struct { 748 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 749 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 750 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 751 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 752 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 753 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 754 755 756 /** 757 * @brief USBD_HALTED [HALTED] (Unspecified) 758 */ 759 typedef struct { 760 __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. 761 Can be used as is as response to a GetStatus() 762 request to endpoint. */ 763 __IM uint32_t RESERVED; 764 __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. 765 Can be used as is as response to a GetStatus() 766 request to endpoint. */ 767 } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ 768 769 770 /** 771 * @brief USBD_SIZE [SIZE] (Unspecified) 772 */ 773 typedef struct { 774 __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received 775 last in the data stage of this OUT endpoint */ 776 __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT 777 data endpoint */ 778 } USBD_SIZE_Type; /*!< Size = 36 (0x24) */ 779 780 781 /** 782 * @brief USBD_EPIN [EPIN] (Unspecified) 783 */ 784 typedef struct { 785 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 786 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 787 to transfer */ 788 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 789 in the last transaction */ 790 __IM uint32_t RESERVED[2]; 791 } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ 792 793 794 /** 795 * @brief USBD_ISOIN [ISOIN] (Unspecified) 796 */ 797 typedef struct { 798 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 799 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 800 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 801 } USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ 802 803 804 /** 805 * @brief USBD_EPOUT [EPOUT] (Unspecified) 806 */ 807 typedef struct { 808 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 809 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 810 to transfer */ 811 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 812 in the last transaction */ 813 __IM uint32_t RESERVED[2]; 814 } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ 815 816 817 /** 818 * @brief USBD_ISOOUT [ISOOUT] (Unspecified) 819 */ 820 typedef struct { 821 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 822 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 823 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 824 } USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ 825 826 827 /** @} */ /* End of group Device_Peripheral_clusters */ 828 829 830 /* =========================================================================================================================== */ 831 /* ================ Device Specific Peripheral Section ================ */ 832 /* =========================================================================================================================== */ 833 834 835 /** @addtogroup Device_Peripheral_peripherals 836 * @{ 837 */ 838 839 840 841 /* =========================================================================================================================== */ 842 /* ================ FICR ================ */ 843 /* =========================================================================================================================== */ 844 845 846 /** 847 * @brief Factory information configuration registers (FICR) 848 */ 849 850 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 851 __IM uint32_t RESERVED[4]; 852 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 853 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 854 __IM uint32_t RESERVED1[18]; 855 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ 856 __IM uint32_t RESERVED2[6]; 857 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word 858 n */ 859 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ 860 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 861 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ 862 __IM uint32_t RESERVED3[21]; 863 __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 864 __IM uint32_t RESERVED4[143]; 865 __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature 866 n */ 867 __IM uint32_t RESERVED5[42]; 868 __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 869 coefficients */ 870 __IM uint32_t RESERVED6[2]; 871 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 872 } NRF_FICR_Type; /*!< Size = 1120 (0x460) */ 873 874 875 876 /* =========================================================================================================================== */ 877 /* ================ UICR ================ */ 878 /* =========================================================================================================================== */ 879 880 881 /** 882 * @brief User information configuration registers (UICR) 883 */ 884 885 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 886 __IM uint32_t RESERVED[5]; 887 __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware 888 design */ 889 __IM uint32_t RESERVED1[2]; 890 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware 891 design */ 892 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ 893 __IM uint32_t RESERVED2[64]; 894 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET 895 function (see POWER chapter for details) */ 896 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 897 __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: 898 NFC antenna or GPIO */ 899 __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ 900 __IM uint32_t RESERVED3[60]; 901 __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The 902 maximum output voltage from this stage is 903 given as VDDH - V_VDDH-VDD. */ 904 } NRF_UICR_Type; /*!< Size = 776 (0x308) */ 905 906 907 908 /* =========================================================================================================================== */ 909 /* ================ APPROTECT ================ */ 910 /* =========================================================================================================================== */ 911 912 913 /** 914 * @brief Access Port Protection (APPROTECT) 915 */ 916 917 typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ 918 __IM uint32_t RESERVED[340]; 919 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until 920 next reset. */ 921 __IM uint32_t RESERVED1; 922 __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ 923 } NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ 924 925 926 927 /* =========================================================================================================================== */ 928 /* ================ CLOCK ================ */ 929 /* =========================================================================================================================== */ 930 931 932 /** 933 * @brief Clock control (CLOCK) 934 */ 935 936 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 937 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ 938 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ 939 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ 940 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ 941 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ 942 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 943 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 944 __IM uint32_t RESERVED[57]; 945 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ 946 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 947 __IM uint32_t RESERVED1; 948 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ 949 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 950 __IM uint32_t RESERVED2[5]; 951 __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready 952 to process new tasks */ 953 __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready 954 to process new tasks */ 955 __IM uint32_t RESERVED3[117]; 956 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 957 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 958 __IM uint32_t RESERVED4[63]; 959 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 960 triggered */ 961 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 962 __IM uint32_t RESERVED5; 963 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 964 triggered */ 965 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 966 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 967 task was triggered */ 968 __IM uint32_t RESERVED6[62]; 969 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 970 __IM uint32_t RESERVED7[3]; 971 __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering 972 the TASKS_HFCLKSTART task. */ 973 __IOM uint32_t LFXODEBOUNCE; /*!< (@ 0x0000052C) LFXO debounce time. The LFXO is started by triggering 974 the TASKS_LFCLKSTART task when the LFCLKSRC 975 register is configured for Xtal. */ 976 __IM uint32_t RESERVED8[2]; 977 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 978 __IM uint32_t RESERVED9[8]; 979 __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ 980 } NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */ 981 982 983 984 /* =========================================================================================================================== */ 985 /* ================ POWER ================ */ 986 /* =========================================================================================================================== */ 987 988 989 /** 990 * @brief Power control (POWER) 991 */ 992 993 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 994 __IM uint32_t RESERVED[30]; 995 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 996 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ 997 __IM uint32_t RESERVED1[34]; 998 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 999 __IM uint32_t RESERVED2[2]; 1000 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1001 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1002 __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ 1003 __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ 1004 __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ 1005 __IM uint32_t RESERVED3[119]; 1006 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1007 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1008 __IM uint32_t RESERVED4[61]; 1009 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1010 __IM uint32_t RESERVED5[9]; 1011 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 1012 __IM uint32_t RESERVED6[3]; 1013 __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ 1014 __IM uint32_t RESERVED7[49]; 1015 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 1016 __IM uint32_t RESERVED8[3]; 1017 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 1018 __IM uint32_t RESERVED9[2]; 1019 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 1020 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 1021 __IM uint32_t RESERVED10[21]; 1022 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */ 1023 __IM uint32_t RESERVED11[49]; 1024 __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ 1025 __IM uint32_t RESERVED12[175]; 1026 __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ 1027 } NRF_POWER_Type; /*!< Size = 2448 (0x990) */ 1028 1029 1030 1031 /* =========================================================================================================================== */ 1032 /* ================ P0 ================ */ 1033 /* =========================================================================================================================== */ 1034 1035 1036 /** 1037 * @brief GPIO Port 1 (P0) 1038 */ 1039 1040 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 1041 __IM uint32_t RESERVED[321]; 1042 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 1043 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 1044 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 1045 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 1046 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 1047 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 1048 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 1049 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 1050 have met the criteria set in the PIN_CNF[n].SENSE 1051 registers */ 1052 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior 1053 and LDETECT mode */ 1054 __IM uint32_t RESERVED1[118]; 1055 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO 1056 pins */ 1057 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 1058 1059 1060 1061 /* =========================================================================================================================== */ 1062 /* ================ RADIO ================ */ 1063 /* =========================================================================================================================== */ 1064 1065 1066 /** 1067 * @brief 2.4 GHz radio (RADIO) 1068 */ 1069 1070 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 1071 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 1072 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 1073 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 1074 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 1075 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 1076 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 1077 the receive signal strength */ 1078 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 1079 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 1080 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 1081 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 1082 802.15.4 mode */ 1083 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 1084 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 1085 802.15.4 mode */ 1086 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 1087 __IM uint32_t RESERVED[51]; 1088 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 1089 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 1090 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 1091 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 1092 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 1093 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 1094 packet */ 1095 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 1096 received packet */ 1097 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 1098 __IM uint32_t RESERVED1[2]; 1099 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 1100 __IM uint32_t RESERVED2; 1101 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 1102 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 1103 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 1104 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 1105 ED sample is ready for readout from the 1106 RADIO.EDSAMPLE register. */ 1107 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 1108 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 1109 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 1110 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 1111 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 1112 from Ble_LR125Kbit to Ble_LR500Kbit. */ 1113 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 1114 TX path */ 1115 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 1116 RX path */ 1117 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 1118 __IM uint32_t RESERVED3[2]; 1119 __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator */ 1120 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received 1121 from air */ 1122 __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving 1123 CTEInfo byte) */ 1124 __IM uint32_t RESERVED4[35]; 1125 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1126 __IM uint32_t RESERVED5[64]; 1127 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1128 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1129 __IM uint32_t RESERVED6[61]; 1130 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 1131 __IM uint32_t RESERVED7; 1132 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 1133 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 1134 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 1135 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 1136 __IM uint32_t RESERVED8[13]; 1137 __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */ 1138 __IM uint32_t RESERVED9[2]; 1139 __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */ 1140 __IM uint32_t RESERVED10[42]; 1141 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 1142 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 1143 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 1144 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 1145 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 1146 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 1147 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 1148 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 1149 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 1150 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 1151 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 1152 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 1153 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 1154 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 1155 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 1156 __IM uint32_t RESERVED11; 1157 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 1158 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 1159 __IM uint32_t RESERVED12; 1160 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 1161 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 1162 __IM uint32_t RESERVED13[2]; 1163 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 1164 __IM uint32_t RESERVED14[39]; 1165 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 1166 n */ 1167 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 1168 n */ 1169 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 1170 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 1171 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 1172 __IM uint32_t RESERVED15; 1173 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 1174 __IM uint32_t RESERVED16[3]; 1175 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 1176 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 1177 __IM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 1178 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 1179 __IM uint32_t RESERVED17[164]; 1180 __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure 1181 (AOD) */ 1182 __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */ 1183 __IM uint32_t RESERVED18[2]; 1184 __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */ 1185 __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */ 1186 __IM uint32_t RESERVED19[4]; 1187 __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */ 1188 __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */ 1189 __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */ 1190 __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */ 1191 __IM uint32_t RESERVED20[424]; 1192 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 1193 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 1194 1195 1196 1197 /* =========================================================================================================================== */ 1198 /* ================ UART0 ================ */ 1199 /* =========================================================================================================================== */ 1200 1201 1202 /** 1203 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 1204 */ 1205 1206 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 1207 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1208 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1209 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1210 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1211 __IM uint32_t RESERVED[3]; 1212 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 1213 __IM uint32_t RESERVED1[56]; 1214 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1215 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1216 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 1217 __IM uint32_t RESERVED2[4]; 1218 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1219 __IM uint32_t RESERVED3; 1220 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1221 __IM uint32_t RESERVED4[7]; 1222 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1223 __IM uint32_t RESERVED5[46]; 1224 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1225 __IM uint32_t RESERVED6[64]; 1226 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1227 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1228 __IM uint32_t RESERVED7[93]; 1229 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1230 __IM uint32_t RESERVED8[31]; 1231 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1232 __IM uint32_t RESERVED9; 1233 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1234 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1235 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1236 __IM uint32_t RESERVED10; 1237 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1238 selected. */ 1239 __IM uint32_t RESERVED11[17]; 1240 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1241 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 1242 1243 1244 1245 /* =========================================================================================================================== */ 1246 /* ================ UARTE0 ================ */ 1247 /* =========================================================================================================================== */ 1248 1249 1250 /** 1251 * @brief UART with EasyDMA 0 (UARTE0) 1252 */ 1253 1254 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 1255 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1256 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1257 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1258 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1259 __IM uint32_t RESERVED[7]; 1260 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1261 __IM uint32_t RESERVED1[52]; 1262 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1263 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1264 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1265 transferred to Data RAM) */ 1266 __IM uint32_t RESERVED2; 1267 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1268 __IM uint32_t RESERVED3[2]; 1269 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1270 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1271 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1272 __IM uint32_t RESERVED4[7]; 1273 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1274 __IM uint32_t RESERVED5; 1275 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1276 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1277 __IM uint32_t RESERVED6; 1278 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1279 __IM uint32_t RESERVED7[41]; 1280 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1281 __IM uint32_t RESERVED8[63]; 1282 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1283 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1284 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1285 __IM uint32_t RESERVED9[93]; 1286 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one 1287 to clear. */ 1288 __IM uint32_t RESERVED10[31]; 1289 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1290 __IM uint32_t RESERVED11; 1291 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1292 __IM uint32_t RESERVED12[3]; 1293 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1294 selected. */ 1295 __IM uint32_t RESERVED13[3]; 1296 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1297 __IM uint32_t RESERVED14; 1298 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1299 __IM uint32_t RESERVED15[7]; 1300 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1301 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1302 1303 1304 1305 /* =========================================================================================================================== */ 1306 /* ================ SPI0 ================ */ 1307 /* =========================================================================================================================== */ 1308 1309 1310 /** 1311 * @brief Serial Peripheral Interface 0 (SPI0) 1312 */ 1313 1314 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1315 __IM uint32_t RESERVED[66]; 1316 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1317 __IM uint32_t RESERVED1[126]; 1318 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1319 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1320 __IM uint32_t RESERVED2[125]; 1321 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1322 __IM uint32_t RESERVED3; 1323 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1324 __IM uint32_t RESERVED4; 1325 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1326 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1327 __IM uint32_t RESERVED5; 1328 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1329 source selected. */ 1330 __IM uint32_t RESERVED6[11]; 1331 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1332 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1333 1334 1335 1336 /* =========================================================================================================================== */ 1337 /* ================ SPIM0 ================ */ 1338 /* =========================================================================================================================== */ 1339 1340 1341 /** 1342 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1343 */ 1344 1345 typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1346 __IM uint32_t RESERVED[4]; 1347 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1348 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1349 __IM uint32_t RESERVED1; 1350 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1351 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1352 __IM uint32_t RESERVED2[56]; 1353 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1354 __IM uint32_t RESERVED3[2]; 1355 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1356 __IM uint32_t RESERVED4; 1357 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1358 __IM uint32_t RESERVED5; 1359 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1360 __IM uint32_t RESERVED6[10]; 1361 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1362 __IM uint32_t RESERVED7[44]; 1363 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1364 __IM uint32_t RESERVED8[64]; 1365 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1366 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1367 __IM uint32_t RESERVED9[61]; 1368 __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields 1369 in this register are set to STALL by hardware 1370 whenever a stall occurs and can be cleared 1371 (set to NOSTALL) by the CPU. */ 1372 __IM uint32_t RESERVED10[63]; 1373 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1374 __IM uint32_t RESERVED11; 1375 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1376 __IM uint32_t RESERVED12[3]; 1377 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1378 source selected. */ 1379 __IM uint32_t RESERVED13[3]; 1380 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1381 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1382 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1383 __IM uint32_t RESERVED14[2]; 1384 __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ 1385 __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ 1386 __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ 1387 __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ 1388 __IM uint32_t RESERVED15[19]; 1389 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1390 been transmitted in the case when RXD.MAXCNT 1391 is greater than TXD.MAXCNT */ 1392 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1393 1394 1395 1396 /* =========================================================================================================================== */ 1397 /* ================ SPIS0 ================ */ 1398 /* =========================================================================================================================== */ 1399 1400 1401 /** 1402 * @brief SPI Slave 0 (SPIS0) 1403 */ 1404 1405 typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1406 __IM uint32_t RESERVED[9]; 1407 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1408 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1409 to acquire it */ 1410 __IM uint32_t RESERVED1[54]; 1411 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1412 __IM uint32_t RESERVED2[2]; 1413 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1414 __IM uint32_t RESERVED3[5]; 1415 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1416 __IM uint32_t RESERVED4[53]; 1417 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1418 __IM uint32_t RESERVED5[64]; 1419 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1420 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1421 __IM uint32_t RESERVED6[61]; 1422 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1423 __IM uint32_t RESERVED7[15]; 1424 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1425 __IM uint32_t RESERVED8[47]; 1426 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1427 __IM uint32_t RESERVED9; 1428 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1429 __IM uint32_t RESERVED10[7]; 1430 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1431 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1432 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1433 __IM uint32_t RESERVED11; 1434 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1435 of an ignored transaction. */ 1436 __IM uint32_t RESERVED12[24]; 1437 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1438 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1439 1440 1441 1442 /* =========================================================================================================================== */ 1443 /* ================ TWI0 ================ */ 1444 /* =========================================================================================================================== */ 1445 1446 1447 /** 1448 * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1449 */ 1450 1451 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1452 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1453 __IM uint32_t RESERVED; 1454 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1455 __IM uint32_t RESERVED1[2]; 1456 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1457 __IM uint32_t RESERVED2; 1458 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1459 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1460 __IM uint32_t RESERVED3[56]; 1461 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1462 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1463 __IM uint32_t RESERVED4[4]; 1464 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1465 __IM uint32_t RESERVED5; 1466 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1467 __IM uint32_t RESERVED6[4]; 1468 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1469 that is sent or received */ 1470 __IM uint32_t RESERVED7[3]; 1471 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1472 __IM uint32_t RESERVED8[45]; 1473 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1474 __IM uint32_t RESERVED9[64]; 1475 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1476 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1477 __IM uint32_t RESERVED10[110]; 1478 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1479 __IM uint32_t RESERVED11[14]; 1480 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1481 __IM uint32_t RESERVED12; 1482 __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1483 __IM uint32_t RESERVED13[2]; 1484 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1485 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1486 __IM uint32_t RESERVED14; 1487 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1488 source selected. */ 1489 __IM uint32_t RESERVED15[24]; 1490 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1491 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1492 1493 1494 1495 /* =========================================================================================================================== */ 1496 /* ================ TWIM0 ================ */ 1497 /* =========================================================================================================================== */ 1498 1499 1500 /** 1501 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1502 */ 1503 1504 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1505 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1506 __IM uint32_t RESERVED; 1507 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1508 __IM uint32_t RESERVED1[2]; 1509 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1510 TWI master is not suspended. */ 1511 __IM uint32_t RESERVED2; 1512 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1513 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1514 __IM uint32_t RESERVED3[56]; 1515 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1516 __IM uint32_t RESERVED4[7]; 1517 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1518 __IM uint32_t RESERVED5[8]; 1519 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1520 now suspended. */ 1521 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1522 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1523 __IM uint32_t RESERVED6[2]; 1524 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1525 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1526 byte */ 1527 __IM uint32_t RESERVED7[39]; 1528 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1529 __IM uint32_t RESERVED8[63]; 1530 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1531 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1532 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1533 __IM uint32_t RESERVED9[110]; 1534 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1535 __IM uint32_t RESERVED10[14]; 1536 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1537 __IM uint32_t RESERVED11; 1538 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1539 __IM uint32_t RESERVED12[5]; 1540 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1541 source selected. */ 1542 __IM uint32_t RESERVED13[3]; 1543 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1544 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1545 __IM uint32_t RESERVED14[13]; 1546 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1547 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1548 1549 1550 1551 /* =========================================================================================================================== */ 1552 /* ================ TWIS0 ================ */ 1553 /* =========================================================================================================================== */ 1554 1555 1556 /** 1557 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1558 */ 1559 1560 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1561 __IM uint32_t RESERVED[5]; 1562 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1563 __IM uint32_t RESERVED1; 1564 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1565 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1566 __IM uint32_t RESERVED2[3]; 1567 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1568 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1569 __IM uint32_t RESERVED3[51]; 1570 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1571 __IM uint32_t RESERVED4[7]; 1572 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1573 __IM uint32_t RESERVED5[9]; 1574 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1575 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1576 __IM uint32_t RESERVED6[4]; 1577 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1578 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1579 __IM uint32_t RESERVED7[37]; 1580 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1581 __IM uint32_t RESERVED8[63]; 1582 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1583 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1584 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1585 __IM uint32_t RESERVED9[113]; 1586 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1587 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1588 a match */ 1589 __IM uint32_t RESERVED10[10]; 1590 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1591 __IM uint32_t RESERVED11; 1592 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1593 __IM uint32_t RESERVED12[9]; 1594 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1595 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1596 __IM uint32_t RESERVED13[13]; 1597 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1598 __IM uint32_t RESERVED14; 1599 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1600 mechanism */ 1601 __IM uint32_t RESERVED15[10]; 1602 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1603 of an over-read of the transmit buffer. */ 1604 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1605 1606 1607 1608 /* =========================================================================================================================== */ 1609 /* ================ NFCT ================ */ 1610 /* =========================================================================================================================== */ 1611 1612 1613 /** 1614 * @brief NFC-A compatible radio (NFCT) 1615 */ 1616 1617 typedef struct { /*!< (@ 0x40005000) NFCT Structure */ 1618 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing 1619 frames, change state to activated */ 1620 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ 1621 __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 1622 sense mode */ 1623 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change 1624 state to transmit */ 1625 __IM uint32_t RESERVED[3]; 1626 __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 1627 __IM uint32_t RESERVED1; 1628 __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 1629 __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 1630 __IM uint32_t RESERVED2[53]; 1631 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send 1632 frames */ 1633 __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 1634 __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 1635 __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 1636 frame */ 1637 __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 1638 symbol of a frame */ 1639 __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 1640 frame */ 1641 __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) 1642 and transferred to RAM, and EasyDMA has 1643 ended accessing the RX buffer */ 1644 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 1645 contains details on the source of the error. */ 1646 __IM uint32_t RESERVED3[2]; 1647 __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 1648 register contains details on the source 1649 of the error. */ 1650 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 1651 in Data RAM full. */ 1652 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 1653 has ended accessing the TX buffer */ 1654 __IM uint32_t RESERVED4; 1655 __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 1656 __IM uint32_t RESERVED5[3]; 1657 __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ 1658 __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ 1659 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 1660 __IM uint32_t RESERVED6[43]; 1661 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1662 __IM uint32_t RESERVED7[63]; 1663 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1664 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1665 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1666 __IM uint32_t RESERVED8[62]; 1667 __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 1668 __IM uint32_t RESERVED9; 1669 __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 1670 __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ 1671 __IM uint32_t RESERVED10[3]; 1672 __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ 1673 __IM uint32_t RESERVED11[6]; 1674 __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 1675 __IM uint32_t RESERVED12[49]; 1676 __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 1677 __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 1678 __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 1679 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 1680 Data RAM */ 1681 __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD 1682 data storage each */ 1683 __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 1684 __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 1685 __IM uint32_t RESERVED13; 1686 __IOM uint32_t MODULATIONCTRL; /*!< (@ 0x0000052C) Enables the modulation output to a GPIO pin which 1687 can be connected to a second external antenna. */ 1688 __IM uint32_t RESERVED14[2]; 1689 __IOM uint32_t MODULATIONPSEL; /*!< (@ 0x00000538) Pin select for Modulation control. */ 1690 __IM uint32_t RESERVED15[21]; 1691 __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 1692 __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 1693 __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 1694 __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. 1695 This setting must be done before the NFCT 1696 peripheral is activated. */ 1697 __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 1698 __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 1699 } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 1700 1701 1702 1703 /* =========================================================================================================================== */ 1704 /* ================ GPIOTE ================ */ 1705 /* =========================================================================================================================== */ 1706 1707 1708 /** 1709 * @brief GPIO Tasks and Events (GPIOTE) 1710 */ 1711 1712 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1713 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1714 specified in CONFIG[n].PSEL. Action on pin 1715 is configured in CONFIG[n].POLARITY. */ 1716 __IM uint32_t RESERVED[4]; 1717 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1718 specified in CONFIG[n].PSEL. Action on pin 1719 is to set it high. */ 1720 __IM uint32_t RESERVED1[4]; 1721 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1722 specified in CONFIG[n].PSEL. Action on pin 1723 is to set it low. */ 1724 __IM uint32_t RESERVED2[32]; 1725 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1726 pin specified in CONFIG[n].PSEL */ 1727 __IM uint32_t RESERVED3[23]; 1728 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1729 with SENSE mechanism enabled */ 1730 __IM uint32_t RESERVED4[97]; 1731 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1732 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1733 __IM uint32_t RESERVED5[129]; 1734 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1735 SET[n], and CLR[n] tasks and IN[n] event */ 1736 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1737 1738 1739 1740 /* =========================================================================================================================== */ 1741 /* ================ SAADC ================ */ 1742 /* =========================================================================================================================== */ 1743 1744 1745 /** 1746 * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) 1747 */ 1748 1749 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1750 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer 1751 in RAM */ 1752 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ 1753 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ 1754 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1755 __IM uint32_t RESERVED[60]; 1756 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ 1757 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ 1758 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1759 on the configuration, multiple conversions 1760 might be needed for a result to be transferred 1761 to RAM. */ 1762 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ 1763 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1764 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ 1765 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1766 __IM uint32_t RESERVED1[106]; 1767 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1768 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1769 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1770 __IM uint32_t RESERVED2[61]; 1771 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1772 __IM uint32_t RESERVED3[63]; 1773 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ 1774 __IM uint32_t RESERVED4[3]; 1775 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1776 __IM uint32_t RESERVED5[24]; 1777 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1778 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is 1779 applied before averaging, thus for high 1780 OVERSAMPLE a higher RESOLUTION should be 1781 used. */ 1782 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1783 __IM uint32_t RESERVED6[12]; 1784 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1785 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1786 1787 1788 1789 /* =========================================================================================================================== */ 1790 /* ================ TIMER0 ================ */ 1791 /* =========================================================================================================================== */ 1792 1793 1794 /** 1795 * @brief Timer/Counter 0 (TIMER0) 1796 */ 1797 1798 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1799 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1800 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1801 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1802 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1803 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1804 __IM uint32_t RESERVED[11]; 1805 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1806 CC[n] register */ 1807 __IM uint32_t RESERVED1[58]; 1808 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1809 match */ 1810 __IM uint32_t RESERVED2[42]; 1811 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1812 __IM uint32_t RESERVED3[64]; 1813 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1814 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1815 __IM uint32_t RESERVED4[126]; 1816 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1817 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1818 __IM uint32_t RESERVED5; 1819 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1820 __IM uint32_t RESERVED6[11]; 1821 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1822 n */ 1823 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1824 1825 1826 1827 /* =========================================================================================================================== */ 1828 /* ================ RTC0 ================ */ 1829 /* =========================================================================================================================== */ 1830 1831 1832 /** 1833 * @brief Real time counter 0 (RTC0) 1834 */ 1835 1836 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1837 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1838 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1839 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1840 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1841 __IM uint32_t RESERVED[60]; 1842 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1843 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1844 __IM uint32_t RESERVED1[14]; 1845 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1846 match */ 1847 __IM uint32_t RESERVED2[109]; 1848 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1849 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1850 __IM uint32_t RESERVED3[13]; 1851 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1852 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1853 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1854 __IM uint32_t RESERVED4[110]; 1855 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1856 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 1857 Must be written when RTC is stopped. */ 1858 __IM uint32_t RESERVED5[13]; 1859 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1860 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1861 1862 1863 1864 /* =========================================================================================================================== */ 1865 /* ================ TEMP ================ */ 1866 /* =========================================================================================================================== */ 1867 1868 1869 /** 1870 * @brief Temperature Sensor (TEMP) 1871 */ 1872 1873 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1874 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1875 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1876 __IM uint32_t RESERVED[62]; 1877 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1878 __IM uint32_t RESERVED1[128]; 1879 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1880 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1881 __IM uint32_t RESERVED2[127]; 1882 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1883 __IM uint32_t RESERVED3[5]; 1884 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ 1885 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ 1886 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ 1887 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ 1888 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ 1889 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ 1890 __IM uint32_t RESERVED4[2]; 1891 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ 1892 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ 1893 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ 1894 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ 1895 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ 1896 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ 1897 __IM uint32_t RESERVED5[2]; 1898 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ 1899 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ 1900 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ 1901 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ 1902 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ 1903 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1904 1905 1906 1907 /* =========================================================================================================================== */ 1908 /* ================ RNG ================ */ 1909 /* =========================================================================================================================== */ 1910 1911 1912 /** 1913 * @brief Random Number Generator (RNG) 1914 */ 1915 1916 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1917 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1918 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1919 __IM uint32_t RESERVED[62]; 1920 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1921 written to the VALUE register */ 1922 __IM uint32_t RESERVED1[63]; 1923 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1924 __IM uint32_t RESERVED2[64]; 1925 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1926 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1927 __IM uint32_t RESERVED3[126]; 1928 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1929 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1930 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1931 1932 1933 1934 /* =========================================================================================================================== */ 1935 /* ================ ECB ================ */ 1936 /* =========================================================================================================================== */ 1937 1938 1939 /** 1940 * @brief AES ECB Mode Encryption (ECB) 1941 */ 1942 1943 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1944 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1945 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1946 __IM uint32_t RESERVED[62]; 1947 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1948 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1949 task or due to an error */ 1950 __IM uint32_t RESERVED1[127]; 1951 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1952 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1953 __IM uint32_t RESERVED2[126]; 1954 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1955 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1956 1957 1958 1959 /* =========================================================================================================================== */ 1960 /* ================ AAR ================ */ 1961 /* =========================================================================================================================== */ 1962 1963 1964 /** 1965 * @brief Accelerated Address Resolver (AAR) 1966 */ 1967 1968 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1969 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1970 in the IRK data structure */ 1971 __IM uint32_t RESERVED; 1972 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1973 __IM uint32_t RESERVED1[61]; 1974 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1975 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1976 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1977 __IM uint32_t RESERVED2[126]; 1978 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1979 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1980 __IM uint32_t RESERVED3[61]; 1981 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1982 __IM uint32_t RESERVED4[63]; 1983 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1984 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1985 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1986 __IM uint32_t RESERVED5; 1987 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1988 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1989 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1990 1991 1992 1993 /* =========================================================================================================================== */ 1994 /* ================ CCM ================ */ 1995 /* =========================================================================================================================== */ 1996 1997 1998 /** 1999 * @brief AES CCM mode encryption (CCM) 2000 */ 2001 2002 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 2003 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 2004 will stop by itself when completed. */ 2005 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 2006 stop by itself when completed. */ 2007 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 2008 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 2009 the contents of the RATEOVERRIDE register 2010 for any ongoing encryption/decryption */ 2011 __IM uint32_t RESERVED[60]; 2012 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 2013 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 2014 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 2015 __IM uint32_t RESERVED1[61]; 2016 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2017 __IM uint32_t RESERVED2[64]; 2018 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2019 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2020 __IM uint32_t RESERVED3[61]; 2021 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 2022 __IM uint32_t RESERVED4[63]; 2023 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 2024 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 2025 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key 2026 and the NONCE vector */ 2027 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 2028 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 2029 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 2030 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 2031 = Extended */ 2032 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 2033 __IOM uint32_t HEADERMASK; /*!< (@ 0x00000520) Header (S0) mask. */ 2034 } NRF_CCM_Type; /*!< Size = 1316 (0x524) */ 2035 2036 2037 2038 /* =========================================================================================================================== */ 2039 /* ================ WDT ================ */ 2040 /* =========================================================================================================================== */ 2041 2042 2043 /** 2044 * @brief Watchdog Timer (WDT) 2045 */ 2046 2047 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 2048 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 2049 __IM uint32_t RESERVED[63]; 2050 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 2051 __IM uint32_t RESERVED1[128]; 2052 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2053 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2054 __IM uint32_t RESERVED2[61]; 2055 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 2056 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 2057 __IM uint32_t RESERVED3[63]; 2058 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 2059 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 2060 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 2061 __IM uint32_t RESERVED4[60]; 2062 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 2063 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 2064 2065 2066 2067 /* =========================================================================================================================== */ 2068 /* ================ QDEC ================ */ 2069 /* =========================================================================================================================== */ 2070 2071 2072 /** 2073 * @brief Quadrature Decoder (QDEC) 2074 */ 2075 2076 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 2077 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 2078 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 2079 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 2080 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 2081 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 2082 __IM uint32_t RESERVED[59]; 2083 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 2084 written to the SAMPLE register */ 2085 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 2086 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 2087 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 2088 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 2089 __IM uint32_t RESERVED1[59]; 2090 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2091 __IM uint32_t RESERVED2[64]; 2092 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2093 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2094 __IM uint32_t RESERVED3[125]; 2095 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 2096 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 2097 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 2098 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 2099 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 2100 and DBLRDY events can be generated */ 2101 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 2102 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 2103 READCLRACC or RDCLRACC task */ 2104 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 2105 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 2106 __IM uint32_t RESERVED4[5]; 2107 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 2108 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 2109 double transitions */ 2110 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 2111 or RDCLRDBL task */ 2112 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 2113 2114 2115 2116 /* =========================================================================================================================== */ 2117 /* ================ COMP ================ */ 2118 /* =========================================================================================================================== */ 2119 2120 2121 /** 2122 * @brief Comparator (COMP) 2123 */ 2124 2125 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 2126 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2127 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2128 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2129 __IM uint32_t RESERVED[61]; 2130 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 2131 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2132 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2133 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2134 __IM uint32_t RESERVED1[60]; 2135 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2136 __IM uint32_t RESERVED2[63]; 2137 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2138 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2139 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2140 __IM uint32_t RESERVED3[61]; 2141 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2142 __IM uint32_t RESERVED4[63]; 2143 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 2144 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 2145 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 2146 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2147 __IM uint32_t RESERVED5[8]; 2148 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 2149 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 2150 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2151 } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 2152 2153 2154 2155 /* =========================================================================================================================== */ 2156 /* ================ LPCOMP ================ */ 2157 /* =========================================================================================================================== */ 2158 2159 2160 /** 2161 * @brief Low-power comparator (LPCOMP) 2162 */ 2163 2164 typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 2165 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2166 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2167 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2168 __IM uint32_t RESERVED[61]; 2169 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 2170 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2171 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2172 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2173 __IM uint32_t RESERVED1[60]; 2174 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2175 __IM uint32_t RESERVED2[64]; 2176 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2177 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2178 __IM uint32_t RESERVED3[61]; 2179 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2180 __IM uint32_t RESERVED4[63]; 2181 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 2182 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 2183 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 2184 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2185 __IM uint32_t RESERVED5[4]; 2186 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 2187 __IM uint32_t RESERVED6[5]; 2188 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2189 } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 2190 2191 2192 2193 /* =========================================================================================================================== */ 2194 /* ================ EGU0 ================ */ 2195 /* =========================================================================================================================== */ 2196 2197 2198 /** 2199 * @brief Event generator unit 0 (EGU0) 2200 */ 2201 2202 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 2203 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 2204 the corresponding TRIGGERED[n] event */ 2205 __IM uint32_t RESERVED[48]; 2206 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 2207 by triggering the corresponding TRIGGER[n] 2208 task */ 2209 __IM uint32_t RESERVED1[112]; 2210 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2211 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2212 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2213 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 2214 2215 2216 2217 /* =========================================================================================================================== */ 2218 /* ================ SWI0 ================ */ 2219 /* =========================================================================================================================== */ 2220 2221 2222 /** 2223 * @brief Software interrupt 0 (SWI0) 2224 */ 2225 2226 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 2227 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2228 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 2229 2230 2231 2232 /* =========================================================================================================================== */ 2233 /* ================ PWM0 ================ */ 2234 /* =========================================================================================================================== */ 2235 2236 2237 /** 2238 * @brief Pulse width modulation unit 0 (PWM0) 2239 */ 2240 2241 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 2242 __IM uint32_t RESERVED; 2243 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2244 the end of current PWM period, and stops 2245 sequence playback */ 2246 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 2247 on all enabled channels from sequence n, 2248 and starts playing that sequence at the 2249 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2250 Causes PWM generation to start if not running. */ 2251 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2252 all enabled channels if DECODER.MODE=NextStep. 2253 Does not cause PWM generation to start if 2254 not running. */ 2255 __IM uint32_t RESERVED1[60]; 2256 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2257 are no longer generated */ 2258 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 2259 on sequence n */ 2260 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 2261 sequence n, when last value from RAM has 2262 been applied to wave counter */ 2263 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2264 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2265 of times defined in LOOP.CNT */ 2266 __IM uint32_t RESERVED2[56]; 2267 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2268 __IM uint32_t RESERVED3[63]; 2269 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2270 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2271 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2272 __IM uint32_t RESERVED4[125]; 2273 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2274 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2275 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2276 counts */ 2277 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2278 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2279 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 2280 __IM uint32_t RESERVED5[2]; 2281 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2282 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2283 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2284 2285 2286 2287 /* =========================================================================================================================== */ 2288 /* ================ PDM ================ */ 2289 /* =========================================================================================================================== */ 2290 2291 2292 /** 2293 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 2294 */ 2295 2296 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 2297 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2298 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2299 __IM uint32_t RESERVED[62]; 2300 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2301 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2302 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2303 by SAMPLE.MAXCNT (or the last sample after 2304 a STOP task has been received) to Data RAM */ 2305 __IM uint32_t RESERVED1[125]; 2306 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2307 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2308 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2309 __IM uint32_t RESERVED2[125]; 2310 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2311 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2312 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2313 signals */ 2314 __IM uint32_t RESERVED3[3]; 2315 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2316 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2317 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 2318 sample rate. Change PDMCLKCTRL accordingly. */ 2319 __IM uint32_t RESERVED4[7]; 2320 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2321 __IM uint32_t RESERVED5[6]; 2322 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2323 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2324 2325 2326 2327 /* =========================================================================================================================== */ 2328 /* ================ ACL ================ */ 2329 /* =========================================================================================================================== */ 2330 2331 2332 /** 2333 * @brief Access control lists (ACL) 2334 */ 2335 2336 typedef struct { /*!< (@ 0x4001E000) ACL Structure */ 2337 __IM uint32_t RESERVED[512]; 2338 __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ 2339 } NRF_ACL_Type; /*!< Size = 2176 (0x880) */ 2340 2341 2342 2343 /* =========================================================================================================================== */ 2344 /* ================ NVMC ================ */ 2345 /* =========================================================================================================================== */ 2346 2347 2348 /** 2349 * @brief Non Volatile Memory Controller (NVMC) 2350 */ 2351 2352 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 2353 __IM uint32_t RESERVED[256]; 2354 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2355 __IM uint32_t RESERVED1; 2356 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 2357 __IM uint32_t RESERVED2[62]; 2358 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2359 2360 union { 2361 __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 2362 __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 2363 page in code area, equivalent to ERASEPAGE */ 2364 }; 2365 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2366 __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 2367 page in code area, equivalent to ERASEPAGE */ 2368 __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 2369 registers */ 2370 __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 2371 area */ 2372 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 2373 __IM uint32_t RESERVED3[8]; 2374 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ 2375 __IM uint32_t RESERVED4; 2376 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ 2377 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ 2378 } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 2379 2380 2381 2382 /* =========================================================================================================================== */ 2383 /* ================ PPI ================ */ 2384 /* =========================================================================================================================== */ 2385 2386 2387 /** 2388 * @brief Programmable Peripheral Interconnect (PPI) 2389 */ 2390 2391 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 2392 __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2393 __IM uint32_t RESERVED[308]; 2394 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2395 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2396 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2397 __IM uint32_t RESERVED1; 2398 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 2399 __IM uint32_t RESERVED2[148]; 2400 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ 2401 __IM uint32_t RESERVED3[62]; 2402 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 2403 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 2404 2405 2406 2407 /* =========================================================================================================================== */ 2408 /* ================ MWU ================ */ 2409 /* =========================================================================================================================== */ 2410 2411 2412 /** 2413 * @brief Memory Watch Unit (MWU) 2414 */ 2415 2416 typedef struct { /*!< (@ 0x40020000) MWU Structure */ 2417 __IM uint32_t RESERVED[64]; 2418 __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */ 2419 __IM uint32_t RESERVED1[16]; 2420 __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */ 2421 __IM uint32_t RESERVED2[100]; 2422 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2423 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2424 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2425 __IM uint32_t RESERVED3[5]; 2426 __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */ 2427 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ 2428 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ 2429 __IM uint32_t RESERVED4[53]; 2430 __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ 2431 __IM uint32_t RESERVED5[64]; 2432 __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ 2433 __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ 2434 __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ 2435 __IM uint32_t RESERVED6[57]; 2436 __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ 2437 __IM uint32_t RESERVED7[32]; 2438 __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ 2439 } NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ 2440 2441 2442 2443 /* =========================================================================================================================== */ 2444 /* ================ I2S ================ */ 2445 /* =========================================================================================================================== */ 2446 2447 2448 /** 2449 * @brief Inter-IC Sound (I2S) 2450 */ 2451 2452 typedef struct { /*!< (@ 0x40025000) I2S Structure */ 2453 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2454 generator when this is enabled. */ 2455 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2456 Triggering this task will cause the STOPPED 2457 event to be generated. */ 2458 __IM uint32_t RESERVED[63]; 2459 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2460 double-buffers. When the I2S module is started 2461 and RX is enabled, this event will be generated 2462 for every RXTXD.MAXCNT words that are received 2463 on the SDIN pin. */ 2464 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2465 __IM uint32_t RESERVED1[2]; 2466 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2467 double-buffers. When the I2S module is started 2468 and TX is enabled, this event will be generated 2469 for every RXTXD.MAXCNT words that are sent 2470 on the SDOUT pin. */ 2471 __IM uint32_t RESERVED2[122]; 2472 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2473 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2474 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2475 __IM uint32_t RESERVED3[125]; 2476 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2477 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2478 __IM uint32_t RESERVED4[3]; 2479 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2480 __IM uint32_t RESERVED5; 2481 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2482 __IM uint32_t RESERVED6[3]; 2483 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2484 __IM uint32_t RESERVED7[3]; 2485 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2486 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2487 2488 2489 2490 /* =========================================================================================================================== */ 2491 /* ================ FPU ================ */ 2492 /* =========================================================================================================================== */ 2493 2494 2495 /** 2496 * @brief FPU (FPU) 2497 */ 2498 2499 typedef struct { /*!< (@ 0x40026000) FPU Structure */ 2500 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2501 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2502 2503 2504 2505 /* =========================================================================================================================== */ 2506 /* ================ USBD ================ */ 2507 /* =========================================================================================================================== */ 2508 2509 2510 /** 2511 * @brief Universal serial bus device (USBD) 2512 */ 2513 2514 typedef struct { /*!< (@ 0x40027000) USBD Structure */ 2515 __IM uint32_t RESERVED; 2516 __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR 2517 and EPIN[n].MAXCNT registers values, and 2518 enables endpoint IN n to respond to traffic 2519 from host */ 2520 __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers 2521 values, and enables sending data on ISO 2522 endpoint */ 2523 __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR 2524 and EPOUT[n].MAXCNT registers values, and 2525 enables endpoint n to respond to traffic 2526 from host */ 2527 __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers 2528 values, and enables receiving of data on 2529 ISO endpoint */ 2530 __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ 2531 __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ 2532 __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint 2533 0 */ 2534 __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined 2535 in the DPDMVALUE register */ 2536 __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state 2537 (USB engine takes control) */ 2538 __IM uint32_t RESERVED1[40]; 2539 __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected 2540 on USB lines */ 2541 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, 2542 or EPOUT[n].PTR and EPOUT[n].MAXCNT registers 2543 have been captured on all endpoints reported 2544 in the EPSTATUS register */ 2545 __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer 2546 has been consumed. The buffer can be accessed 2547 safely by software. */ 2548 __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place 2549 on the control endpoint */ 2550 __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The 2551 buffer can be accessed safely by software. */ 2552 __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer 2553 has been consumed. The buffer can be accessed 2554 safely by software. */ 2555 __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The 2556 buffer can be accessed safely by software. */ 2557 __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition 2558 has been detected on USB lines */ 2559 __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific 2560 events has occurred. Check EVENTCAUSE register 2561 to find the cause. */ 2562 __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) 2563 on the control endpoint */ 2564 __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, 2565 indicated by the EPDATASTATUS register */ 2566 __IM uint32_t RESERVED2[39]; 2567 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2568 __IM uint32_t RESERVED3[63]; 2569 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2570 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2571 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2572 __IM uint32_t RESERVED4[61]; 2573 __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ 2574 __IM uint32_t RESERVED5[7]; 2575 __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ 2576 __IM uint32_t RESERVED6; 2577 __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA 2578 registers have been captured */ 2579 __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an 2580 acknowledged data transfer has occurred 2581 (EPDATA event) */ 2582 __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ 2583 __IM uint32_t RESERVED7[3]; 2584 __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ 2585 __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ 2586 __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ 2587 __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ 2588 __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ 2589 __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ 2590 __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ 2591 __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ 2592 __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ 2593 __IM uint32_t RESERVED8[15]; 2594 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ 2595 __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ 2596 __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by 2597 the DPDMDRIVE task. The DPDMNODRIVE task 2598 reverts the control of the lines to MAC 2599 IP (no forcing). */ 2600 __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ 2601 __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ 2602 __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ 2603 __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ 2604 __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ 2605 __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame 2606 counter */ 2607 __IM uint32_t RESERVED9[2]; 2608 __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during 2609 USB suspend */ 2610 __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint 2611 to an IN token when no data is ready to 2612 be sent */ 2613 __IM uint32_t RESERVED10[51]; 2614 __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ 2615 __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ 2616 __IM uint32_t RESERVED11[21]; 2617 __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ 2618 __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ 2619 } NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ 2620 2621 2622 /** @} */ /* End of group Device_Peripheral_peripherals */ 2623 2624 2625 /* =========================================================================================================================== */ 2626 /* ================ Device Specific Peripheral Address Map ================ */ 2627 /* =========================================================================================================================== */ 2628 2629 2630 /** @addtogroup Device_Peripheral_peripheralAddr 2631 * @{ 2632 */ 2633 2634 #define NRF_FICR_BASE 0x10000000UL 2635 #define NRF_UICR_BASE 0x10001000UL 2636 #define NRF_APPROTECT_BASE 0x40000000UL 2637 #define NRF_CLOCK_BASE 0x40000000UL 2638 #define NRF_POWER_BASE 0x40000000UL 2639 #define NRF_P0_BASE 0x50000000UL 2640 #define NRF_P1_BASE 0x50000300UL 2641 #define NRF_RADIO_BASE 0x40001000UL 2642 #define NRF_UART0_BASE 0x40002000UL 2643 #define NRF_UARTE0_BASE 0x40002000UL 2644 #define NRF_SPI0_BASE 0x40003000UL 2645 #define NRF_SPIM0_BASE 0x40003000UL 2646 #define NRF_SPIS0_BASE 0x40003000UL 2647 #define NRF_TWI0_BASE 0x40003000UL 2648 #define NRF_TWIM0_BASE 0x40003000UL 2649 #define NRF_TWIS0_BASE 0x40003000UL 2650 #define NRF_SPI1_BASE 0x40004000UL 2651 #define NRF_SPIM1_BASE 0x40004000UL 2652 #define NRF_SPIS1_BASE 0x40004000UL 2653 #define NRF_TWI1_BASE 0x40004000UL 2654 #define NRF_TWIM1_BASE 0x40004000UL 2655 #define NRF_TWIS1_BASE 0x40004000UL 2656 #define NRF_NFCT_BASE 0x40005000UL 2657 #define NRF_GPIOTE_BASE 0x40006000UL 2658 #define NRF_SAADC_BASE 0x40007000UL 2659 #define NRF_TIMER0_BASE 0x40008000UL 2660 #define NRF_TIMER1_BASE 0x40009000UL 2661 #define NRF_TIMER2_BASE 0x4000A000UL 2662 #define NRF_RTC0_BASE 0x4000B000UL 2663 #define NRF_TEMP_BASE 0x4000C000UL 2664 #define NRF_RNG_BASE 0x4000D000UL 2665 #define NRF_ECB_BASE 0x4000E000UL 2666 #define NRF_AAR_BASE 0x4000F000UL 2667 #define NRF_CCM_BASE 0x4000F000UL 2668 #define NRF_WDT_BASE 0x40010000UL 2669 #define NRF_RTC1_BASE 0x40011000UL 2670 #define NRF_QDEC_BASE 0x40012000UL 2671 #define NRF_COMP_BASE 0x40013000UL 2672 #define NRF_LPCOMP_BASE 0x40013000UL 2673 #define NRF_EGU0_BASE 0x40014000UL 2674 #define NRF_SWI0_BASE 0x40014000UL 2675 #define NRF_EGU1_BASE 0x40015000UL 2676 #define NRF_SWI1_BASE 0x40015000UL 2677 #define NRF_EGU2_BASE 0x40016000UL 2678 #define NRF_SWI2_BASE 0x40016000UL 2679 #define NRF_EGU3_BASE 0x40017000UL 2680 #define NRF_SWI3_BASE 0x40017000UL 2681 #define NRF_EGU4_BASE 0x40018000UL 2682 #define NRF_SWI4_BASE 0x40018000UL 2683 #define NRF_EGU5_BASE 0x40019000UL 2684 #define NRF_SWI5_BASE 0x40019000UL 2685 #define NRF_TIMER3_BASE 0x4001A000UL 2686 #define NRF_TIMER4_BASE 0x4001B000UL 2687 #define NRF_PWM0_BASE 0x4001C000UL 2688 #define NRF_PDM_BASE 0x4001D000UL 2689 #define NRF_ACL_BASE 0x4001E000UL 2690 #define NRF_NVMC_BASE 0x4001E000UL 2691 #define NRF_PPI_BASE 0x4001F000UL 2692 #define NRF_MWU_BASE 0x40020000UL 2693 #define NRF_PWM1_BASE 0x40021000UL 2694 #define NRF_PWM2_BASE 0x40022000UL 2695 #define NRF_SPI2_BASE 0x40023000UL 2696 #define NRF_SPIM2_BASE 0x40023000UL 2697 #define NRF_SPIS2_BASE 0x40023000UL 2698 #define NRF_RTC2_BASE 0x40024000UL 2699 #define NRF_I2S_BASE 0x40025000UL 2700 #define NRF_FPU_BASE 0x40026000UL 2701 #define NRF_USBD_BASE 0x40027000UL 2702 #define NRF_UARTE1_BASE 0x40028000UL 2703 #define NRF_PWM3_BASE 0x4002D000UL 2704 #define NRF_SPIM3_BASE 0x4002F000UL 2705 2706 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2707 2708 2709 /* =========================================================================================================================== */ 2710 /* ================ Peripheral declaration ================ */ 2711 /* =========================================================================================================================== */ 2712 2713 2714 /** @addtogroup Device_Peripheral_declaration 2715 * @{ 2716 */ 2717 2718 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2719 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2720 #define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) 2721 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2722 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2723 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2724 #define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) 2725 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2726 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2727 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2728 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2729 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2730 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2731 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2732 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2733 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2734 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2735 #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2736 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2737 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 2738 #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 2739 #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 2740 #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) 2741 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2742 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 2743 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2744 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2745 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2746 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2747 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2748 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2749 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2750 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2751 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2752 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2753 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2754 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2755 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2756 #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 2757 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2758 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2759 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2760 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2761 #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 2762 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2763 #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 2764 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2765 #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 2766 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2767 #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 2768 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2769 #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 2770 #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) 2771 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 2772 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 2773 #define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) 2774 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2775 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2776 #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) 2777 #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) 2778 #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) 2779 #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) 2780 #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) 2781 #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) 2782 #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) 2783 #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) 2784 #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) 2785 #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) 2786 #define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) 2787 #define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) 2788 #define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) 2789 2790 /** @} */ /* End of group Device_Peripheral_declaration */ 2791 2792 2793 /* ========================================= End of section using anonymous unions ========================================= */ 2794 #if defined (__CC_ARM) 2795 #pragma pop 2796 #elif defined (__ICCARM__) 2797 /* leave anonymous unions enabled */ 2798 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 2799 #pragma clang diagnostic pop 2800 #elif defined (__GNUC__) 2801 /* anonymous unions are enabled by default */ 2802 #elif defined (__TMS470__) 2803 /* anonymous unions are enabled by default */ 2804 #elif defined (__TASKING__) 2805 #pragma warning restore 2806 #elif defined (__CSMC__) 2807 /* anonymous unions are enabled by default */ 2808 #endif 2809 2810 2811 #ifdef __cplusplus 2812 } 2813 #endif 2814 2815 #endif /* NRF52833_H */ 2816 2817 2818 /** @} */ /* End of group nrf52833 */ 2819 2820 /** @} */ /* End of group Nordic Semiconductor */ 2821
