1 /* 2 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.\n 3 \n 4 SPDX-License-Identifier: BSD-3-Clause\n 5 \n 6 Redistribution and use in source and binary forms, with or without\n 7 modification, are permitted provided that the following conditions are met:\n 8 \n 9 1. Redistributions of source code must retain the above copyright notice, this\n 10 list of conditions and the following disclaimer.\n 11 \n 12 2. Redistributions in binary form must reproduce the above copyright\n 13 notice, this list of conditions and the following disclaimer in the\n 14 documentation and/or other materials provided with the distribution.\n 15 \n 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n 17 contributors may be used to endorse or promote products derived from this\n 18 software without specific prior written permission.\n 19 \n 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n 30 POSSIBILITY OF SUCH DAMAGE.\n 31 * 32 * @file nrf52811.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 04. April 2023 36 * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:31 37 * from File 'nrf52811.svd', 38 * last modified on Tuesday, 04.04.2023 09:57:14 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf52811 49 * @{ 50 */ 51 52 53 #ifndef NRF52811_H 54 #define NRF52811_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 82 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 83 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 84 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 85 /* ========================================== nrf52811 Specific Interrupt Numbers ========================================== */ 86 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 87 RADIO_IRQn = 1, /*!< 1 RADIO */ 88 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 89 TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQn= 3, /*!< 3 TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 */ 90 SPIM0_SPIS0_SPI0_IRQn = 4, /*!< 4 SPIM0_SPIS0_SPI0 */ 91 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 92 SAADC_IRQn = 7, /*!< 7 SAADC */ 93 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 94 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 95 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 96 RTC0_IRQn = 11, /*!< 11 RTC0 */ 97 TEMP_IRQn = 12, /*!< 12 TEMP */ 98 RNG_IRQn = 13, /*!< 13 RNG */ 99 ECB_IRQn = 14, /*!< 14 ECB */ 100 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 101 WDT_IRQn = 16, /*!< 16 WDT */ 102 RTC1_IRQn = 17, /*!< 17 RTC1 */ 103 QDEC_IRQn = 18, /*!< 18 QDEC */ 104 COMP_IRQn = 19, /*!< 19 COMP */ 105 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 106 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 107 SWI2_IRQn = 22, /*!< 22 SWI2 */ 108 SWI3_IRQn = 23, /*!< 23 SWI3 */ 109 SWI4_IRQn = 24, /*!< 24 SWI4 */ 110 SWI5_IRQn = 25, /*!< 25 SWI5 */ 111 PWM0_IRQn = 28, /*!< 28 PWM0 */ 112 PDM_IRQn = 29 /*!< 29 PDM */ 113 } IRQn_Type; 114 115 116 117 /* =========================================================================================================================== */ 118 /* ================ Processor and Core Peripheral Section ================ */ 119 /* =========================================================================================================================== */ 120 121 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 122 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 123 #define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ 124 #define __DSP_PRESENT 1 /*!< DSP present or not */ 125 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 126 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 127 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 128 #define __MPU_PRESENT 1 /*!< MPU present */ 129 #define __FPU_PRESENT 0 /*!< FPU present */ 130 131 132 /** @} */ /* End of group Configuration_of_CMSIS */ 133 134 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 135 #include "system_nrf52811.h" /*!< nrf52811 System */ 136 137 #ifndef __IM /*!< Fallback for older CMSIS versions */ 138 #define __IM __I 139 #endif 140 #ifndef __OM /*!< Fallback for older CMSIS versions */ 141 #define __OM __O 142 #endif 143 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 144 #define __IOM __IO 145 #endif 146 147 148 /* ======================================== Start of section using anonymous unions ======================================== */ 149 #if defined (__CC_ARM) 150 #pragma push 151 #pragma anon_unions 152 #elif defined (__ICCARM__) 153 #pragma language=extended 154 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 155 #pragma clang diagnostic push 156 #pragma clang diagnostic ignored "-Wc11-extensions" 157 #pragma clang diagnostic ignored "-Wreserved-id-macro" 158 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 159 #pragma clang diagnostic ignored "-Wnested-anon-types" 160 #elif defined (__GNUC__) 161 /* anonymous unions are enabled by default */ 162 #elif defined (__TMS470__) 163 /* anonymous unions are enabled by default */ 164 #elif defined (__TASKING__) 165 #pragma warning 586 166 #elif defined (__CSMC__) 167 /* anonymous unions are enabled by default */ 168 #else 169 #warning Not supported compiler type 170 #endif 171 172 173 /* =========================================================================================================================== */ 174 /* ================ Device Specific Cluster Section ================ */ 175 /* =========================================================================================================================== */ 176 177 178 /** @addtogroup Device_Peripheral_clusters 179 * @{ 180 */ 181 182 183 /** 184 * @brief FICR_INFO [INFO] (Device info) 185 */ 186 typedef struct { 187 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 188 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part variant, hardware version and production 189 configuration */ 190 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 191 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 192 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 193 } FICR_INFO_Type; /*!< Size = 20 (0x14) */ 194 195 196 /** 197 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 198 */ 199 typedef struct { 200 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 201 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 202 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 203 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 204 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 205 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 206 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 207 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 208 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 209 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 210 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 211 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 212 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 213 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 214 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 215 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 216 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 217 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 218 219 220 /** 221 * @brief POWER_RAM [RAM] (Unspecified) 222 */ 223 typedef struct { 224 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register. 225 The RAM size will vary depending on product 226 variant, and the RAMn register will only 227 be present if the corresponding RAM AHB 228 slave is present on the device. */ 229 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 230 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 231 register */ 232 __IM uint32_t RESERVED; 233 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 234 235 236 /** 237 * @brief RADIO_PSEL [PSEL] (Unspecified) 238 */ 239 typedef struct { 240 __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin 241 n */ 242 } RADIO_PSEL_Type; /*!< Size = 32 (0x20) */ 243 244 245 /** 246 * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel) 247 */ 248 typedef struct { 249 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 250 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 251 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */ 252 } RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */ 253 254 255 /** 256 * @brief UART_PSEL [PSEL] (Unspecified) 257 */ 258 typedef struct { 259 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 260 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 261 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 262 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 263 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 264 265 266 /** 267 * @brief UARTE_PSEL [PSEL] (Unspecified) 268 */ 269 typedef struct { 270 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 271 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 272 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 273 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 274 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 275 276 277 /** 278 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 279 */ 280 typedef struct { 281 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 282 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 283 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 284 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 285 286 287 /** 288 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 289 */ 290 typedef struct { 291 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 292 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 293 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 294 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 295 296 297 /** 298 * @brief SPI_PSEL [PSEL] (Unspecified) 299 */ 300 typedef struct { 301 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 302 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 303 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 304 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 305 306 307 /** 308 * @brief SPIM_PSEL [PSEL] (Unspecified) 309 */ 310 typedef struct { 311 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 312 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 313 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 314 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 315 316 317 /** 318 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 319 */ 320 typedef struct { 321 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 322 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 323 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 324 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 325 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 326 327 328 /** 329 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 330 */ 331 typedef struct { 332 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 333 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 334 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 335 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 336 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 337 338 339 /** 340 * @brief SPIS_PSEL [PSEL] (Unspecified) 341 */ 342 typedef struct { 343 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 344 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 345 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 346 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 347 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 348 349 350 /** 351 * @brief SPIS_RXD [RXD] (Unspecified) 352 */ 353 typedef struct { 354 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 355 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 356 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 357 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 358 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 359 360 361 /** 362 * @brief SPIS_TXD [TXD] (Unspecified) 363 */ 364 typedef struct { 365 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 366 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 367 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 368 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 369 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 370 371 372 /** 373 * @brief TWI_PSEL [PSEL] (Unspecified) 374 */ 375 typedef struct { 376 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 377 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 378 } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 379 380 381 /** 382 * @brief TWIM_PSEL [PSEL] (Unspecified) 383 */ 384 typedef struct { 385 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 386 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 387 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 388 389 390 /** 391 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 392 */ 393 typedef struct { 394 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 395 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 396 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 397 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 398 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 399 400 401 /** 402 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 403 */ 404 typedef struct { 405 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 406 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 407 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 408 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 409 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 410 411 412 /** 413 * @brief TWIS_PSEL [PSEL] (Unspecified) 414 */ 415 typedef struct { 416 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 417 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 418 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 419 420 421 /** 422 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 423 */ 424 typedef struct { 425 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 426 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 427 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 428 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 429 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 430 431 432 /** 433 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 434 */ 435 typedef struct { 436 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 437 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 438 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 439 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 440 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 441 442 443 /** 444 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 445 */ 446 typedef struct { 447 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 448 above CH[n].LIMIT.HIGH */ 449 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 450 below CH[n].LIMIT.LOW */ 451 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 452 453 454 /** 455 * @brief SAADC_CH [CH] (Unspecified) 456 */ 457 typedef struct { 458 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 459 for CH[n] */ 460 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 461 for CH[n] */ 462 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 463 CH[n] */ 464 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 465 monitoring a channel */ 466 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 467 468 469 /** 470 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 471 */ 472 typedef struct { 473 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 474 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 475 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 476 START */ 477 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 478 479 480 /** 481 * @brief QDEC_PSEL [PSEL] (Unspecified) 482 */ 483 typedef struct { 484 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 485 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 486 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 487 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 488 489 490 /** 491 * @brief PWM_SEQ [SEQ] (Unspecified) 492 */ 493 typedef struct { 494 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 495 of this sequence */ 496 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 497 in this sequence */ 498 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 499 periods between samples loaded into compare 500 register */ 501 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 502 __IM uint32_t RESERVED[4]; 503 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 504 505 506 /** 507 * @brief PWM_PSEL [PSEL] (Unspecified) 508 */ 509 typedef struct { 510 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 511 PWM channel n */ 512 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 513 514 515 /** 516 * @brief PDM_PSEL [PSEL] (Unspecified) 517 */ 518 typedef struct { 519 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 520 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 521 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 522 523 524 /** 525 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 526 */ 527 typedef struct { 528 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 529 EasyDMA */ 530 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 531 mode */ 532 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 533 534 535 /** 536 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 537 */ 538 typedef struct { 539 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 540 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 541 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 542 543 544 /** 545 * @brief PPI_CH [CH] (PPI Channel) 546 */ 547 typedef struct { 548 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ 549 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ 550 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 551 552 553 /** 554 * @brief PPI_FORK [FORK] (Fork) 555 */ 556 typedef struct { 557 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ 558 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 559 560 561 /** @} */ /* End of group Device_Peripheral_clusters */ 562 563 564 /* =========================================================================================================================== */ 565 /* ================ Device Specific Peripheral Section ================ */ 566 /* =========================================================================================================================== */ 567 568 569 /** @addtogroup Device_Peripheral_peripherals 570 * @{ 571 */ 572 573 574 575 /* =========================================================================================================================== */ 576 /* ================ FICR ================ */ 577 /* =========================================================================================================================== */ 578 579 580 /** 581 * @brief Factory information configuration registers (FICR) 582 */ 583 584 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 585 __IM uint32_t RESERVED[4]; 586 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 587 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 588 __IM uint32_t RESERVED1[18]; 589 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ 590 __IM uint32_t RESERVED2[6]; 591 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word 592 n */ 593 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity root, word n */ 594 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 595 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ 596 __IM uint32_t RESERVED3[21]; 597 __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 598 __IM uint32_t RESERVED4[188]; 599 __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 600 coefficients */ 601 } NRF_FICR_Type; /*!< Size = 1096 (0x448) */ 602 603 604 605 /* =========================================================================================================================== */ 606 /* ================ UICR ================ */ 607 /* =========================================================================================================================== */ 608 609 610 /** 611 * @brief User information configuration registers (UICR) 612 */ 613 614 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 615 __IM uint32_t RESERVED[5]; 616 __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware 617 design */ 618 __IM uint32_t RESERVED1[2]; 619 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware 620 design */ 621 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ 622 __IOM uint32_t NRFMDK[8]; /*!< (@ 0x00000100) Description collection: Reserved for Nordic MDK */ 623 __IM uint32_t RESERVED2[56]; 624 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET 625 function (see POWER chapter for details) */ 626 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 627 } NRF_UICR_Type; /*!< Size = 524 (0x20c) */ 628 629 630 631 /* =========================================================================================================================== */ 632 /* ================ APPROTECT ================ */ 633 /* =========================================================================================================================== */ 634 635 636 /** 637 * @brief Access Port Protection (APPROTECT) 638 */ 639 640 typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ 641 __IM uint32_t RESERVED[340]; 642 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until 643 next reset. */ 644 __IM uint32_t RESERVED1; 645 __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ 646 } NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ 647 648 649 650 /* =========================================================================================================================== */ 651 /* ================ BPROT ================ */ 652 /* =========================================================================================================================== */ 653 654 655 /** 656 * @brief Block Protect (BPROT) 657 */ 658 659 typedef struct { /*!< (@ 0x40000000) BPROT Structure */ 660 __IM uint32_t RESERVED[384]; 661 __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ 662 __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ 663 __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ 664 } NRF_BPROT_Type; /*!< Size = 1548 (0x60c) */ 665 666 667 668 /* =========================================================================================================================== */ 669 /* ================ CLOCK ================ */ 670 /* =========================================================================================================================== */ 671 672 673 /** 674 * @brief Clock control (CLOCK) 675 */ 676 677 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 678 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 679 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 680 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 681 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 682 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 683 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 684 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 685 __IM uint32_t RESERVED[57]; 686 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 687 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 688 __IM uint32_t RESERVED1; 689 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ 690 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 691 __IM uint32_t RESERVED2[124]; 692 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 693 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 694 __IM uint32_t RESERVED3[63]; 695 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 696 triggered */ 697 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 698 __IM uint32_t RESERVED4; 699 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 700 triggered */ 701 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 702 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 703 task was triggered */ 704 __IM uint32_t RESERVED5[62]; 705 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 706 __IM uint32_t RESERVED6[7]; 707 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 708 } NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */ 709 710 711 712 /* =========================================================================================================================== */ 713 /* ================ POWER ================ */ 714 /* =========================================================================================================================== */ 715 716 717 /** 718 * @brief Power control (POWER) 719 */ 720 721 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 722 __IM uint32_t RESERVED[30]; 723 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 724 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ 725 __IM uint32_t RESERVED1[34]; 726 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 727 __IM uint32_t RESERVED2[2]; 728 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 729 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 730 __IM uint32_t RESERVED3[122]; 731 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 732 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 733 __IM uint32_t RESERVED4[61]; 734 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 735 __IM uint32_t RESERVED5[63]; 736 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 737 __IM uint32_t RESERVED6[3]; 738 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ 739 __IM uint32_t RESERVED7[2]; 740 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 741 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 742 __IM uint32_t RESERVED8[21]; 743 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ 744 __IM uint32_t RESERVED9[225]; 745 __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ 746 } NRF_POWER_Type; /*!< Size = 2432 (0x980) */ 747 748 749 750 /* =========================================================================================================================== */ 751 /* ================ P0 ================ */ 752 /* =========================================================================================================================== */ 753 754 755 /** 756 * @brief GPIO Port (P0) 757 */ 758 759 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 760 __IM uint32_t RESERVED[321]; 761 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 762 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 763 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 764 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 765 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 766 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 767 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 768 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 769 have met the criteria set in the PIN_CNF[n].SENSE 770 registers */ 771 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 772 and LDETECT mode */ 773 __IM uint32_t RESERVED1[118]; 774 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO 775 pins */ 776 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 777 778 779 780 /* =========================================================================================================================== */ 781 /* ================ RADIO ================ */ 782 /* =========================================================================================================================== */ 783 784 785 /** 786 * @brief 2.4 GHz radio (RADIO) 787 */ 788 789 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 790 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 791 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 792 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 793 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 794 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 795 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 796 the receive signal strength */ 797 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 798 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 799 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 800 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 801 802.15.4 mode */ 802 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 803 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 804 802.15.4 mode */ 805 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 806 __IM uint32_t RESERVED[51]; 807 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 808 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 809 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 810 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 811 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 812 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 813 packet */ 814 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 815 received packet */ 816 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 817 __IM uint32_t RESERVED1[2]; 818 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 819 __IM uint32_t RESERVED2; 820 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 821 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 822 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 823 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 824 ED sample is ready for readout from the 825 RADIO.EDSAMPLE register. */ 826 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 827 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 828 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 829 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 830 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 831 from Ble_LR125Kbit to Ble_LR500Kbit. */ 832 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 833 TX path */ 834 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 835 RX path */ 836 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 837 __IM uint32_t RESERVED3[2]; 838 __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator */ 839 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received 840 from air */ 841 __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving 842 CTEInfo byte) */ 843 __IM uint32_t RESERVED4[35]; 844 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 845 __IM uint32_t RESERVED5[64]; 846 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 847 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 848 __IM uint32_t RESERVED6[61]; 849 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 850 __IM uint32_t RESERVED7; 851 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 852 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 853 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 854 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 855 __IM uint32_t RESERVED8[13]; 856 __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */ 857 __IM uint32_t RESERVED9[2]; 858 __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */ 859 __IM uint32_t RESERVED10[42]; 860 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 861 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 862 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 863 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 864 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 865 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 866 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 867 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 868 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 869 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 870 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 871 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 872 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 873 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 874 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 875 __IM uint32_t RESERVED11; 876 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 877 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 878 __IM uint32_t RESERVED12; 879 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 880 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 881 __IM uint32_t RESERVED13[2]; 882 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 883 __IM uint32_t RESERVED14[39]; 884 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 885 n */ 886 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 887 n */ 888 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 889 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 890 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 891 __IM uint32_t RESERVED15; 892 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 893 __IM uint32_t RESERVED16[3]; 894 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 895 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 896 __IM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 897 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 898 __IM uint32_t RESERVED17[164]; 899 __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure 900 (AOD) */ 901 __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */ 902 __IM uint32_t RESERVED18[2]; 903 __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */ 904 __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */ 905 __IM uint32_t RESERVED19[4]; 906 __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */ 907 __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */ 908 __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */ 909 __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */ 910 __IM uint32_t RESERVED20[424]; 911 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 912 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 913 914 915 916 /* =========================================================================================================================== */ 917 /* ================ UART0 ================ */ 918 /* =========================================================================================================================== */ 919 920 921 /** 922 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 923 */ 924 925 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 926 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 927 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 928 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 929 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 930 __IM uint32_t RESERVED[3]; 931 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 932 __IM uint32_t RESERVED1[56]; 933 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 934 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 935 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 936 __IM uint32_t RESERVED2[4]; 937 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 938 __IM uint32_t RESERVED3; 939 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 940 __IM uint32_t RESERVED4[7]; 941 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 942 __IM uint32_t RESERVED5[46]; 943 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 944 __IM uint32_t RESERVED6[64]; 945 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 946 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 947 __IM uint32_t RESERVED7[93]; 948 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 949 __IM uint32_t RESERVED8[31]; 950 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 951 __IM uint32_t RESERVED9; 952 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 953 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 954 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 955 __IM uint32_t RESERVED10; 956 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 957 selected. */ 958 __IM uint32_t RESERVED11[17]; 959 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 960 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 961 962 963 964 /* =========================================================================================================================== */ 965 /* ================ UARTE0 ================ */ 966 /* =========================================================================================================================== */ 967 968 969 /** 970 * @brief UART with EasyDMA (UARTE0) 971 */ 972 973 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 974 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 975 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 976 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 977 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 978 __IM uint32_t RESERVED[7]; 979 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 980 __IM uint32_t RESERVED1[52]; 981 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 982 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 983 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 984 transferred to Data RAM) */ 985 __IM uint32_t RESERVED2; 986 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 987 __IM uint32_t RESERVED3[2]; 988 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 989 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 990 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 991 __IM uint32_t RESERVED4[7]; 992 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 993 __IM uint32_t RESERVED5; 994 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 995 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 996 __IM uint32_t RESERVED6; 997 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 998 __IM uint32_t RESERVED7[41]; 999 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1000 __IM uint32_t RESERVED8[63]; 1001 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1002 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1003 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1004 __IM uint32_t RESERVED9[93]; 1005 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 1006 one to clear. */ 1007 __IM uint32_t RESERVED10[31]; 1008 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1009 __IM uint32_t RESERVED11; 1010 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1011 __IM uint32_t RESERVED12[3]; 1012 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1013 selected. */ 1014 __IM uint32_t RESERVED13[3]; 1015 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1016 __IM uint32_t RESERVED14; 1017 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1018 __IM uint32_t RESERVED15[7]; 1019 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1020 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1021 1022 1023 1024 /* =========================================================================================================================== */ 1025 /* ================ SPI1 ================ */ 1026 /* =========================================================================================================================== */ 1027 1028 1029 /** 1030 * @brief Serial Peripheral Interface 0 (SPI1) 1031 */ 1032 1033 typedef struct { /*!< (@ 0x40003000) SPI1 Structure */ 1034 __IM uint32_t RESERVED[66]; 1035 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1036 __IM uint32_t RESERVED1[126]; 1037 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1038 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1039 __IM uint32_t RESERVED2[125]; 1040 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1041 __IM uint32_t RESERVED3; 1042 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1043 __IM uint32_t RESERVED4; 1044 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1045 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1046 __IM uint32_t RESERVED5; 1047 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1048 source selected. */ 1049 __IM uint32_t RESERVED6[11]; 1050 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1051 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1052 1053 1054 1055 /* =========================================================================================================================== */ 1056 /* ================ SPIM1 ================ */ 1057 /* =========================================================================================================================== */ 1058 1059 1060 /** 1061 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM1) 1062 */ 1063 1064 typedef struct { /*!< (@ 0x40003000) SPIM1 Structure */ 1065 __IM uint32_t RESERVED[4]; 1066 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1067 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1068 __IM uint32_t RESERVED1; 1069 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1070 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1071 __IM uint32_t RESERVED2[56]; 1072 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1073 __IM uint32_t RESERVED3[2]; 1074 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1075 __IM uint32_t RESERVED4; 1076 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1077 __IM uint32_t RESERVED5; 1078 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1079 __IM uint32_t RESERVED6[10]; 1080 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1081 __IM uint32_t RESERVED7[44]; 1082 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1083 __IM uint32_t RESERVED8[64]; 1084 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1085 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1086 __IM uint32_t RESERVED9[125]; 1087 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1088 __IM uint32_t RESERVED10; 1089 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1090 __IM uint32_t RESERVED11[4]; 1091 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1092 source selected. */ 1093 __IM uint32_t RESERVED12[3]; 1094 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1095 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1096 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1097 __IM uint32_t RESERVED13[26]; 1098 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1099 case and over-read of the TXD buffer. */ 1100 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1101 1102 1103 1104 /* =========================================================================================================================== */ 1105 /* ================ SPIS1 ================ */ 1106 /* =========================================================================================================================== */ 1107 1108 1109 /** 1110 * @brief SPI Slave 0 (SPIS1) 1111 */ 1112 1113 typedef struct { /*!< (@ 0x40003000) SPIS1 Structure */ 1114 __IM uint32_t RESERVED[9]; 1115 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1116 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1117 to acquire it */ 1118 __IM uint32_t RESERVED1[54]; 1119 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1120 __IM uint32_t RESERVED2[2]; 1121 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1122 __IM uint32_t RESERVED3[5]; 1123 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1124 __IM uint32_t RESERVED4[53]; 1125 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1126 __IM uint32_t RESERVED5[64]; 1127 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1128 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1129 __IM uint32_t RESERVED6[61]; 1130 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1131 __IM uint32_t RESERVED7[15]; 1132 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1133 __IM uint32_t RESERVED8[47]; 1134 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1135 __IM uint32_t RESERVED9; 1136 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1137 __IM uint32_t RESERVED10[7]; 1138 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1139 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1140 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1141 __IM uint32_t RESERVED11; 1142 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1143 of an ignored transaction. */ 1144 __IM uint32_t RESERVED12[24]; 1145 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1146 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1147 1148 1149 1150 /* =========================================================================================================================== */ 1151 /* ================ TWI0 ================ */ 1152 /* =========================================================================================================================== */ 1153 1154 1155 /** 1156 * @brief I2C compatible Two-Wire Interface (TWI0) 1157 */ 1158 1159 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1160 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1161 __IM uint32_t RESERVED; 1162 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1163 __IM uint32_t RESERVED1[2]; 1164 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1165 __IM uint32_t RESERVED2; 1166 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1167 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1168 __IM uint32_t RESERVED3[56]; 1169 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1170 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1171 __IM uint32_t RESERVED4[4]; 1172 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1173 __IM uint32_t RESERVED5; 1174 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1175 __IM uint32_t RESERVED6[4]; 1176 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1177 that is sent or received */ 1178 __IM uint32_t RESERVED7[3]; 1179 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1180 __IM uint32_t RESERVED8[45]; 1181 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1182 __IM uint32_t RESERVED9[64]; 1183 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1184 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1185 __IM uint32_t RESERVED10[110]; 1186 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1187 __IM uint32_t RESERVED11[14]; 1188 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1189 __IM uint32_t RESERVED12; 1190 __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1191 __IM uint32_t RESERVED13[2]; 1192 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1193 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1194 __IM uint32_t RESERVED14; 1195 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1196 source selected. */ 1197 __IM uint32_t RESERVED15[24]; 1198 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1199 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1200 1201 1202 1203 /* =========================================================================================================================== */ 1204 /* ================ TWIM0 ================ */ 1205 /* =========================================================================================================================== */ 1206 1207 1208 /** 1209 * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0) 1210 */ 1211 1212 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1213 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1214 __IM uint32_t RESERVED; 1215 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1216 __IM uint32_t RESERVED1[2]; 1217 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1218 TWI master is not suspended. */ 1219 __IM uint32_t RESERVED2; 1220 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1221 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1222 __IM uint32_t RESERVED3[56]; 1223 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1224 __IM uint32_t RESERVED4[7]; 1225 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1226 __IM uint32_t RESERVED5[8]; 1227 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1228 task has been issued, TWI traffic is now 1229 suspended. */ 1230 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1231 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1232 __IM uint32_t RESERVED6[2]; 1233 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1234 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1235 byte */ 1236 __IM uint32_t RESERVED7[39]; 1237 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1238 __IM uint32_t RESERVED8[63]; 1239 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1240 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1241 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1242 __IM uint32_t RESERVED9[110]; 1243 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1244 __IM uint32_t RESERVED10[14]; 1245 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1246 __IM uint32_t RESERVED11; 1247 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1248 __IM uint32_t RESERVED12[5]; 1249 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1250 source selected. */ 1251 __IM uint32_t RESERVED13[3]; 1252 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1253 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1254 __IM uint32_t RESERVED14[13]; 1255 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1256 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1257 1258 1259 1260 /* =========================================================================================================================== */ 1261 /* ================ TWIS0 ================ */ 1262 /* =========================================================================================================================== */ 1263 1264 1265 /** 1266 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0) 1267 */ 1268 1269 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1270 __IM uint32_t RESERVED[5]; 1271 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1272 __IM uint32_t RESERVED1; 1273 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1274 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1275 __IM uint32_t RESERVED2[3]; 1276 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1277 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1278 __IM uint32_t RESERVED3[51]; 1279 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1280 __IM uint32_t RESERVED4[7]; 1281 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1282 __IM uint32_t RESERVED5[9]; 1283 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1284 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1285 __IM uint32_t RESERVED6[4]; 1286 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1287 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1288 __IM uint32_t RESERVED7[37]; 1289 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1290 __IM uint32_t RESERVED8[63]; 1291 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1292 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1293 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1294 __IM uint32_t RESERVED9[113]; 1295 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1296 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1297 a match */ 1298 __IM uint32_t RESERVED10[10]; 1299 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1300 __IM uint32_t RESERVED11; 1301 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1302 __IM uint32_t RESERVED12[9]; 1303 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1304 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1305 __IM uint32_t RESERVED13[13]; 1306 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1307 __IM uint32_t RESERVED14; 1308 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1309 mechanism */ 1310 __IM uint32_t RESERVED15[10]; 1311 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1312 of an over-read of the transmit buffer. */ 1313 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1314 1315 1316 1317 /* =========================================================================================================================== */ 1318 /* ================ GPIOTE ================ */ 1319 /* =========================================================================================================================== */ 1320 1321 1322 /** 1323 * @brief GPIO Tasks and Events (GPIOTE) 1324 */ 1325 1326 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1327 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1328 specified in CONFIG[n].PSEL. Action on pin 1329 is configured in CONFIG[n].POLARITY. */ 1330 __IM uint32_t RESERVED[4]; 1331 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1332 specified in CONFIG[n].PSEL. Action on pin 1333 is to set it high. */ 1334 __IM uint32_t RESERVED1[4]; 1335 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1336 specified in CONFIG[n].PSEL. Action on pin 1337 is to set it low. */ 1338 __IM uint32_t RESERVED2[32]; 1339 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1340 pin specified in CONFIG[n].PSEL */ 1341 __IM uint32_t RESERVED3[23]; 1342 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1343 with SENSE mechanism enabled */ 1344 __IM uint32_t RESERVED4[97]; 1345 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1346 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1347 __IM uint32_t RESERVED5[129]; 1348 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1349 SET[n] and CLR[n] tasks and IN[n] event */ 1350 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1351 1352 1353 1354 /* =========================================================================================================================== */ 1355 /* ================ SAADC ================ */ 1356 /* =========================================================================================================================== */ 1357 1358 1359 /** 1360 * @brief Analog to Digital Converter (SAADC) 1361 */ 1362 1363 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1364 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1365 RAM */ 1366 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1367 are sampled */ 1368 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1369 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1370 __IM uint32_t RESERVED[60]; 1371 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1372 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1373 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1374 on the mode, multiple conversions might 1375 be needed for a result to be transferred 1376 to RAM. */ 1377 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1378 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1379 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1380 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1381 __IM uint32_t RESERVED1[106]; 1382 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1383 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1384 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1385 __IM uint32_t RESERVED2[61]; 1386 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1387 __IM uint32_t RESERVED3[63]; 1388 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1389 __IM uint32_t RESERVED4[3]; 1390 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1391 __IM uint32_t RESERVED5[24]; 1392 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1393 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1394 not be combined with SCAN. The RESOLUTION 1395 is applied before averaging, thus for high 1396 OVERSAMPLE a higher RESOLUTION should be 1397 used. */ 1398 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1399 __IM uint32_t RESERVED6[12]; 1400 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1401 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1402 1403 1404 1405 /* =========================================================================================================================== */ 1406 /* ================ TIMER0 ================ */ 1407 /* =========================================================================================================================== */ 1408 1409 1410 /** 1411 * @brief Timer/Counter 0 (TIMER0) 1412 */ 1413 1414 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1415 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1416 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1417 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1418 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1419 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1420 __IM uint32_t RESERVED[11]; 1421 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1422 CC[n] register */ 1423 __IM uint32_t RESERVED1[58]; 1424 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1425 match */ 1426 __IM uint32_t RESERVED2[42]; 1427 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1428 __IM uint32_t RESERVED3[64]; 1429 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1430 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1431 __IM uint32_t RESERVED4[126]; 1432 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1433 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1434 __IM uint32_t RESERVED5; 1435 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1436 __IM uint32_t RESERVED6[11]; 1437 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1438 n */ 1439 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1440 1441 1442 1443 /* =========================================================================================================================== */ 1444 /* ================ RTC0 ================ */ 1445 /* =========================================================================================================================== */ 1446 1447 1448 /** 1449 * @brief Real time counter 0 (RTC0) 1450 */ 1451 1452 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1453 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1454 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1455 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1456 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1457 __IM uint32_t RESERVED[60]; 1458 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1459 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1460 __IM uint32_t RESERVED1[14]; 1461 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1462 match */ 1463 __IM uint32_t RESERVED2[109]; 1464 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1465 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1466 __IM uint32_t RESERVED3[13]; 1467 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1468 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1469 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1470 __IM uint32_t RESERVED4[110]; 1471 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1472 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1473 t be written when RTC is stopped */ 1474 __IM uint32_t RESERVED5[13]; 1475 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1476 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1477 1478 1479 1480 /* =========================================================================================================================== */ 1481 /* ================ TEMP ================ */ 1482 /* =========================================================================================================================== */ 1483 1484 1485 /** 1486 * @brief Temperature Sensor (TEMP) 1487 */ 1488 1489 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1490 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1491 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1492 __IM uint32_t RESERVED[62]; 1493 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1494 __IM uint32_t RESERVED1[128]; 1495 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1496 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1497 __IM uint32_t RESERVED2[127]; 1498 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1499 __IM uint32_t RESERVED3[5]; 1500 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1501 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1502 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1503 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1504 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1505 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1506 __IM uint32_t RESERVED4[2]; 1507 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1508 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1509 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1510 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1511 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1512 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1513 __IM uint32_t RESERVED5[2]; 1514 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1515 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1516 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1517 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1518 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1519 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1520 1521 1522 1523 /* =========================================================================================================================== */ 1524 /* ================ RNG ================ */ 1525 /* =========================================================================================================================== */ 1526 1527 1528 /** 1529 * @brief Random Number Generator (RNG) 1530 */ 1531 1532 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1533 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1534 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1535 __IM uint32_t RESERVED[62]; 1536 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1537 written to the VALUE register */ 1538 __IM uint32_t RESERVED1[63]; 1539 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1540 __IM uint32_t RESERVED2[64]; 1541 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1542 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1543 __IM uint32_t RESERVED3[126]; 1544 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1545 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1546 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1547 1548 1549 1550 /* =========================================================================================================================== */ 1551 /* ================ ECB ================ */ 1552 /* =========================================================================================================================== */ 1553 1554 1555 /** 1556 * @brief AES ECB Mode Encryption (ECB) 1557 */ 1558 1559 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1560 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1561 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1562 __IM uint32_t RESERVED[62]; 1563 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1564 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1565 task or due to an error */ 1566 __IM uint32_t RESERVED1[127]; 1567 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1568 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1569 __IM uint32_t RESERVED2[126]; 1570 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1571 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1572 1573 1574 1575 /* =========================================================================================================================== */ 1576 /* ================ AAR ================ */ 1577 /* =========================================================================================================================== */ 1578 1579 1580 /** 1581 * @brief Accelerated Address Resolver (AAR) 1582 */ 1583 1584 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1585 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1586 in the IRK data structure */ 1587 __IM uint32_t RESERVED; 1588 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1589 __IM uint32_t RESERVED1[61]; 1590 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1591 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1592 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1593 __IM uint32_t RESERVED2[126]; 1594 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1595 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1596 __IM uint32_t RESERVED3[61]; 1597 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1598 __IM uint32_t RESERVED4[63]; 1599 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1600 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1601 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1602 __IM uint32_t RESERVED5; 1603 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1604 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1605 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1606 1607 1608 1609 /* =========================================================================================================================== */ 1610 /* ================ CCM ================ */ 1611 /* =========================================================================================================================== */ 1612 1613 1614 /** 1615 * @brief AES CCM mode encryption (CCM) 1616 */ 1617 1618 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1619 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 1620 will stop by itself when completed. */ 1621 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1622 stop by itself when completed. */ 1623 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1624 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1625 the contents of the RATEOVERRIDE register 1626 for any ongoing encryption/decryption */ 1627 __IM uint32_t RESERVED[60]; 1628 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 1629 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1630 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1631 __IM uint32_t RESERVED1[61]; 1632 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1633 __IM uint32_t RESERVED2[64]; 1634 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1635 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1636 __IM uint32_t RESERVED3[61]; 1637 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1638 __IM uint32_t RESERVED4[63]; 1639 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1640 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1641 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key 1642 and the NONCE vector */ 1643 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1644 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1645 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1646 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 1647 = Extended */ 1648 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 1649 } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 1650 1651 1652 1653 /* =========================================================================================================================== */ 1654 /* ================ WDT ================ */ 1655 /* =========================================================================================================================== */ 1656 1657 1658 /** 1659 * @brief Watchdog Timer (WDT) 1660 */ 1661 1662 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1663 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1664 __IM uint32_t RESERVED[63]; 1665 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1666 __IM uint32_t RESERVED1[128]; 1667 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1668 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1669 __IM uint32_t RESERVED2[61]; 1670 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1671 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1672 __IM uint32_t RESERVED3[63]; 1673 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1674 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1675 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1676 __IM uint32_t RESERVED4[60]; 1677 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1678 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1679 1680 1681 1682 /* =========================================================================================================================== */ 1683 /* ================ QDEC ================ */ 1684 /* =========================================================================================================================== */ 1685 1686 1687 /** 1688 * @brief Quadrature Decoder (QDEC) 1689 */ 1690 1691 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1692 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1693 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1694 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1695 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1696 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1697 __IM uint32_t RESERVED[59]; 1698 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1699 written to the SAMPLE register */ 1700 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1701 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1702 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1703 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1704 __IM uint32_t RESERVED1[59]; 1705 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1706 __IM uint32_t RESERVED2[64]; 1707 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1708 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1709 __IM uint32_t RESERVED3[125]; 1710 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1711 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1712 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1713 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1714 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1715 and DBLRDY events can be generated */ 1716 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1717 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1718 READCLRACC or RDCLRACC task */ 1719 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1720 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1721 __IM uint32_t RESERVED4[5]; 1722 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1723 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1724 double transitions */ 1725 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1726 or RDCLRDBL task */ 1727 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1728 1729 1730 1731 /* =========================================================================================================================== */ 1732 /* ================ COMP ================ */ 1733 /* =========================================================================================================================== */ 1734 1735 1736 /** 1737 * @brief Comparator (COMP) 1738 */ 1739 1740 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 1741 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1742 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1743 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1744 __IM uint32_t RESERVED[61]; 1745 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 1746 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1747 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1748 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1749 __IM uint32_t RESERVED1[60]; 1750 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1751 __IM uint32_t RESERVED2[63]; 1752 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1753 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1754 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1755 __IM uint32_t RESERVED3[61]; 1756 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1757 __IM uint32_t RESERVED4[63]; 1758 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 1759 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 1760 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 1761 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1762 __IM uint32_t RESERVED5[8]; 1763 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 1764 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 1765 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1766 } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 1767 1768 1769 1770 /* =========================================================================================================================== */ 1771 /* ================ EGU0 ================ */ 1772 /* =========================================================================================================================== */ 1773 1774 1775 /** 1776 * @brief Event generator unit 0 (EGU0) 1777 */ 1778 1779 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1780 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1781 the corresponding TRIGGERED[n] event */ 1782 __IM uint32_t RESERVED[48]; 1783 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1784 by triggering the corresponding TRIGGER[n] 1785 task */ 1786 __IM uint32_t RESERVED1[112]; 1787 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1788 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1789 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1790 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1791 1792 1793 1794 /* =========================================================================================================================== */ 1795 /* ================ SWI0 ================ */ 1796 /* =========================================================================================================================== */ 1797 1798 1799 /** 1800 * @brief Software interrupt 0 (SWI0) 1801 */ 1802 1803 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 1804 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1805 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1806 1807 1808 1809 /* =========================================================================================================================== */ 1810 /* ================ PWM0 ================ */ 1811 /* =========================================================================================================================== */ 1812 1813 1814 /** 1815 * @brief Pulse width modulation unit (PWM0) 1816 */ 1817 1818 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 1819 __IM uint32_t RESERVED; 1820 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 1821 the end of current PWM period, and stops 1822 sequence playback */ 1823 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 1824 on all enabled channels from sequence n, 1825 and starts playing that sequence at the 1826 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 1827 Causes PWM generation to start if not running. */ 1828 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 1829 all enabled channels if DECODER.MODE=NextStep. 1830 Does not cause PWM generation to start if 1831 not running. */ 1832 __IM uint32_t RESERVED1[60]; 1833 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 1834 are no longer generated */ 1835 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 1836 on sequence n */ 1837 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 1838 sequence n, when last value from RAM has 1839 been applied to wave counter */ 1840 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 1841 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 1842 of times defined in LOOP.CNT */ 1843 __IM uint32_t RESERVED2[56]; 1844 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1845 __IM uint32_t RESERVED3[63]; 1846 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1847 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1848 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1849 __IM uint32_t RESERVED4[125]; 1850 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 1851 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 1852 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 1853 counts */ 1854 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 1855 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 1856 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 1857 __IM uint32_t RESERVED5[2]; 1858 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 1859 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 1860 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 1861 1862 1863 1864 /* =========================================================================================================================== */ 1865 /* ================ PDM ================ */ 1866 /* =========================================================================================================================== */ 1867 1868 1869 /** 1870 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 1871 */ 1872 1873 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 1874 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 1875 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 1876 __IM uint32_t RESERVED[62]; 1877 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 1878 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 1879 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 1880 by SAMPLE.MAXCNT (or the last sample after 1881 a STOP task has been received) to Data RAM */ 1882 __IM uint32_t RESERVED1[125]; 1883 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1884 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1885 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1886 __IM uint32_t RESERVED2[125]; 1887 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 1888 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 1889 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 1890 signals */ 1891 __IM uint32_t RESERVED3[3]; 1892 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 1893 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 1894 __IM uint32_t RESERVED4[8]; 1895 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 1896 __IM uint32_t RESERVED5[6]; 1897 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 1898 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 1899 1900 1901 1902 /* =========================================================================================================================== */ 1903 /* ================ NVMC ================ */ 1904 /* =========================================================================================================================== */ 1905 1906 1907 /** 1908 * @brief Non-volatile memory controller (NVMC) 1909 */ 1910 1911 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 1912 __IM uint32_t RESERVED[256]; 1913 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1914 __IM uint32_t RESERVED1[64]; 1915 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1916 1917 union { 1918 __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 1919 __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 1920 page in code area. Equivalent to ERASEPAGE. */ 1921 }; 1922 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1923 __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 1924 page in code area. Equivalent to ERASEPAGE. */ 1925 __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 1926 registers */ 1927 __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 1928 area */ 1929 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1930 } NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ 1931 1932 1933 1934 /* =========================================================================================================================== */ 1935 /* ================ PPI ================ */ 1936 /* =========================================================================================================================== */ 1937 1938 1939 /** 1940 * @brief Programmable Peripheral Interconnect (PPI) 1941 */ 1942 1943 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 1944 __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1945 __IM uint32_t RESERVED[308]; 1946 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1947 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1948 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1949 __IM uint32_t RESERVED1; 1950 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 1951 __IM uint32_t RESERVED2[148]; 1952 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ 1953 __IM uint32_t RESERVED3[62]; 1954 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 1955 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 1956 1957 1958 /** @} */ /* End of group Device_Peripheral_peripherals */ 1959 1960 1961 /* =========================================================================================================================== */ 1962 /* ================ Device Specific Peripheral Address Map ================ */ 1963 /* =========================================================================================================================== */ 1964 1965 1966 /** @addtogroup Device_Peripheral_peripheralAddr 1967 * @{ 1968 */ 1969 1970 #define NRF_FICR_BASE 0x10000000UL 1971 #define NRF_UICR_BASE 0x10001000UL 1972 #define NRF_APPROTECT_BASE 0x40000000UL 1973 #define NRF_BPROT_BASE 0x40000000UL 1974 #define NRF_CLOCK_BASE 0x40000000UL 1975 #define NRF_POWER_BASE 0x40000000UL 1976 #define NRF_P0_BASE 0x50000000UL 1977 #define NRF_RADIO_BASE 0x40001000UL 1978 #define NRF_UART0_BASE 0x40002000UL 1979 #define NRF_UARTE0_BASE 0x40002000UL 1980 #define NRF_SPI1_BASE 0x40003000UL 1981 #define NRF_SPIM1_BASE 0x40003000UL 1982 #define NRF_SPIS1_BASE 0x40003000UL 1983 #define NRF_TWI0_BASE 0x40003000UL 1984 #define NRF_TWIM0_BASE 0x40003000UL 1985 #define NRF_TWIS0_BASE 0x40003000UL 1986 #define NRF_SPI0_BASE 0x40004000UL 1987 #define NRF_SPIM0_BASE 0x40004000UL 1988 #define NRF_SPIS0_BASE 0x40004000UL 1989 #define NRF_GPIOTE_BASE 0x40006000UL 1990 #define NRF_SAADC_BASE 0x40007000UL 1991 #define NRF_TIMER0_BASE 0x40008000UL 1992 #define NRF_TIMER1_BASE 0x40009000UL 1993 #define NRF_TIMER2_BASE 0x4000A000UL 1994 #define NRF_RTC0_BASE 0x4000B000UL 1995 #define NRF_TEMP_BASE 0x4000C000UL 1996 #define NRF_RNG_BASE 0x4000D000UL 1997 #define NRF_ECB_BASE 0x4000E000UL 1998 #define NRF_AAR_BASE 0x4000F000UL 1999 #define NRF_CCM_BASE 0x4000F000UL 2000 #define NRF_WDT_BASE 0x40010000UL 2001 #define NRF_RTC1_BASE 0x40011000UL 2002 #define NRF_QDEC_BASE 0x40012000UL 2003 #define NRF_COMP_BASE 0x40013000UL 2004 #define NRF_EGU0_BASE 0x40014000UL 2005 #define NRF_SWI0_BASE 0x40014000UL 2006 #define NRF_EGU1_BASE 0x40015000UL 2007 #define NRF_SWI1_BASE 0x40015000UL 2008 #define NRF_SWI2_BASE 0x40016000UL 2009 #define NRF_SWI3_BASE 0x40017000UL 2010 #define NRF_SWI4_BASE 0x40018000UL 2011 #define NRF_SWI5_BASE 0x40019000UL 2012 #define NRF_PWM0_BASE 0x4001C000UL 2013 #define NRF_PDM_BASE 0x4001D000UL 2014 #define NRF_NVMC_BASE 0x4001E000UL 2015 #define NRF_PPI_BASE 0x4001F000UL 2016 2017 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2018 2019 2020 /* =========================================================================================================================== */ 2021 /* ================ Peripheral declaration ================ */ 2022 /* =========================================================================================================================== */ 2023 2024 2025 /** @addtogroup Device_Peripheral_declaration 2026 * @{ 2027 */ 2028 2029 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2030 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2031 #define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) 2032 #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) 2033 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2034 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2035 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2036 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2037 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2038 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2039 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2040 #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2041 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2042 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2043 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2044 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2045 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2046 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2047 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2048 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2049 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 2050 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2051 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2052 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2053 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2054 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2055 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2056 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2057 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2058 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2059 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2060 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2061 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2062 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2063 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2064 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2065 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2066 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2067 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2068 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2069 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2070 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2071 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 2072 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 2073 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2074 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2075 2076 /** @} */ /* End of group Device_Peripheral_declaration */ 2077 2078 2079 /* ========================================= End of section using anonymous unions ========================================= */ 2080 #if defined (__CC_ARM) 2081 #pragma pop 2082 #elif defined (__ICCARM__) 2083 /* leave anonymous unions enabled */ 2084 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 2085 #pragma clang diagnostic pop 2086 #elif defined (__GNUC__) 2087 /* anonymous unions are enabled by default */ 2088 #elif defined (__TMS470__) 2089 /* anonymous unions are enabled by default */ 2090 #elif defined (__TASKING__) 2091 #pragma warning restore 2092 #elif defined (__CSMC__) 2093 /* anonymous unions are enabled by default */ 2094 #endif 2095 2096 2097 #ifdef __cplusplus 2098 } 2099 #endif 2100 2101 #endif /* NRF52811_H */ 2102 2103 2104 /** @} */ /* End of group nrf52811 */ 2105 2106 /** @} */ /* End of group Nordic Semiconductor */ 2107
