1 /*
2 
3 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved.
4 
5 SPDX-License-Identifier: BSD-3-Clause
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10 1. Redistributions of source code must retain the above copyright notice, this
11    list of conditions and the following disclaimer.
12 
13 2. Redistributions in binary form must reproduce the above copyright
14    notice, this list of conditions and the following disclaimer in the
15    documentation and/or other materials provided with the distribution.
16 
17 3. Neither the name of Nordic Semiconductor ASA nor the names of its
18    contributors may be used to endorse or promote products derived from this
19    software without specific prior written permission.
20 
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 
33 */
34 
35 #ifndef __NRF52810_BITS_H
36 #define __NRF52810_BITS_H
37 
38 /*lint ++flb "Enter library region" */
39 
40 /* Peripheral: AAR */
41 /* Description: Accelerated Address Resolver */
42 
43 /* Register: AAR_TASKS_START */
44 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
45 
46 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
47 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
48 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
49 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
50 
51 /* Register: AAR_TASKS_STOP */
52 /* Description: Stop resolving addresses */
53 
54 /* Bit 0 : Stop resolving addresses */
55 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
56 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
57 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
58 
59 /* Register: AAR_EVENTS_END */
60 /* Description: Address resolution procedure complete */
61 
62 /* Bit 0 : Address resolution procedure complete */
63 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
64 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
65 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
66 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
67 
68 /* Register: AAR_EVENTS_RESOLVED */
69 /* Description: Address resolved */
70 
71 /* Bit 0 : Address resolved */
72 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
73 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
74 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
75 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
76 
77 /* Register: AAR_EVENTS_NOTRESOLVED */
78 /* Description: Address not resolved */
79 
80 /* Bit 0 : Address not resolved */
81 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
82 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
83 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
84 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
85 
86 /* Register: AAR_INTENSET */
87 /* Description: Enable interrupt */
88 
89 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
90 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
91 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
92 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
93 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
94 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
95 
96 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
97 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
98 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
99 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
100 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
101 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
102 
103 /* Bit 0 : Write '1' to enable interrupt for event END */
104 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
105 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
106 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
107 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
108 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
109 
110 /* Register: AAR_INTENCLR */
111 /* Description: Disable interrupt */
112 
113 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
114 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
115 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
116 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
117 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
118 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
119 
120 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
121 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
122 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
123 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
124 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
125 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
126 
127 /* Bit 0 : Write '1' to disable interrupt for event END */
128 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
129 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
130 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
131 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
132 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
133 
134 /* Register: AAR_STATUS */
135 /* Description: Resolution status */
136 
137 /* Bits 3..0 : The IRK that was used last time an address was resolved */
138 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
139 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
140 
141 /* Register: AAR_ENABLE */
142 /* Description: Enable AAR */
143 
144 /* Bits 1..0 : Enable or disable AAR */
145 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
146 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
147 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
148 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
149 
150 /* Register: AAR_NIRK */
151 /* Description: Number of IRKs */
152 
153 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
154 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
155 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
156 
157 /* Register: AAR_IRKPTR */
158 /* Description: Pointer to IRK data structure */
159 
160 /* Bits 31..0 : Pointer to the IRK data structure */
161 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
162 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
163 
164 /* Register: AAR_ADDRPTR */
165 /* Description: Pointer to the resolvable address */
166 
167 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
168 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
169 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
170 
171 /* Register: AAR_SCRATCHPTR */
172 /* Description: Pointer to data area used for temporary storage */
173 
174 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
175 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
176 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
177 
178 
179 /* Peripheral: APPROTECT */
180 /* Description: Only for emulation on devices that support hardened AP-PROTECT. */
181 
182 /* Register: APPROTECT_FORCEPROTECT */
183 /* Description: Software force enable APPROTECT mechanism until next reset. */
184 
185 /* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */
186 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */
187 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */
188 #define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */
189 
190 /* Register: APPROTECT_DISABLE */
191 /* Description: Software disable APPROTECT mechanism */
192 
193 /* Bits 7..0 : Software disable APPROTECT mechanism */
194 #define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */
195 #define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */
196 #define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */
197 
198 
199 /* Peripheral: BPROT */
200 /* Description: Block Protect */
201 
202 /* Register: BPROT_CONFIG0 */
203 /* Description: Block protect configuration register 0 */
204 
205 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
206 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
207 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
208 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
209 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enabled */
210 
211 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
212 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
213 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
214 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
215 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enabled */
216 
217 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
218 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
219 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
220 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
221 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enabled */
222 
223 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
224 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
225 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
226 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
227 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enabled */
228 
229 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
230 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
231 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
232 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
233 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enabled */
234 
235 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
236 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
237 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
238 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
239 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enabled */
240 
241 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
242 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
243 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
244 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
245 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enabled */
246 
247 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
248 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
249 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
250 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
251 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enabled */
252 
253 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
254 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
255 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
256 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
257 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enabled */
258 
259 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
260 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
261 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
262 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
263 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enabled */
264 
265 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
266 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
267 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
268 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
269 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enabled */
270 
271 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
272 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
273 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
274 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
275 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enabled */
276 
277 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
278 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
279 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
280 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
281 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enabled */
282 
283 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
284 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
285 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
286 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
287 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enabled */
288 
289 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
290 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
291 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
292 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
293 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enabled */
294 
295 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
296 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
297 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
298 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
299 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enabled */
300 
301 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
302 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
303 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
304 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
305 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enabled */
306 
307 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
308 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
309 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
310 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
311 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enabled */
312 
313 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
314 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
315 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
316 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
317 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enabled */
318 
319 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
320 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
321 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
322 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
323 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enabled */
324 
325 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
326 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
327 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
328 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
329 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enabled */
330 
331 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
332 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
333 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
334 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
335 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enabled */
336 
337 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
338 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
339 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
340 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
341 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enabled */
342 
343 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
344 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
345 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
346 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
347 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enabled */
348 
349 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
350 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
351 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
352 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
353 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enabled */
354 
355 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
356 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
357 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
358 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
359 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enabled */
360 
361 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
362 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
363 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
364 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
365 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enabled */
366 
367 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
368 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
369 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
370 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
371 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enabled */
372 
373 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
374 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
375 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
376 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
377 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enabled */
378 
379 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
380 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
381 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
382 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
383 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enabled */
384 
385 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
386 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
387 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
388 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
389 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enabled */
390 
391 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
392 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
393 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
394 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
395 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enabled */
396 
397 /* Register: BPROT_CONFIG1 */
398 /* Description: Block protect configuration register 1 */
399 
400 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
401 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
402 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
403 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
404 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
405 
406 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
407 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
408 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
409 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
410 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
411 
412 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
413 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
414 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
415 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
416 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
417 
418 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
419 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
420 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
421 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
422 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
423 
424 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
425 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
426 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
427 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
428 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
429 
430 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
431 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
432 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
433 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
434 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
435 
436 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
437 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
438 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
439 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
440 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
441 
442 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
443 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
444 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
445 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
446 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
447 
448 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
449 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
450 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
451 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
452 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
453 
454 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
455 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
456 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
457 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
458 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
459 
460 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
461 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
462 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
463 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
464 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
465 
466 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
467 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
468 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
469 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
470 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
471 
472 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
473 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
474 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
475 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
476 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
477 
478 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
479 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
480 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
481 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
482 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
483 
484 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
485 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
486 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
487 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
488 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
489 
490 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
491 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
492 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
493 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
494 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
495 
496 /* Register: BPROT_DISABLEINDEBUG */
497 /* Description: Disable protection mechanism in debug mode */
498 
499 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. */
500 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
501 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
502 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enabled in debug */
503 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disabled in debug */
504 
505 
506 /* Peripheral: CCM */
507 /* Description: AES CCM Mode Encryption */
508 
509 /* Register: CCM_TASKS_KSGEN */
510 /* Description: Start generation of key-stream. This operation will stop by itself when completed. */
511 
512 /* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */
513 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
514 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
515 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
516 
517 /* Register: CCM_TASKS_CRYPT */
518 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */
519 
520 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
521 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
522 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
523 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
524 
525 /* Register: CCM_TASKS_STOP */
526 /* Description: Stop encryption/decryption */
527 
528 /* Bit 0 : Stop encryption/decryption */
529 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
530 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
531 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
532 
533 /* Register: CCM_TASKS_RATEOVERRIDE */
534 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
535 
536 /* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
537 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */
538 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */
539 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */
540 
541 /* Register: CCM_EVENTS_ENDKSGEN */
542 /* Description: Key-stream generation complete */
543 
544 /* Bit 0 : Key-stream generation complete */
545 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
546 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
547 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
548 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
549 
550 /* Register: CCM_EVENTS_ENDCRYPT */
551 /* Description: Encrypt/decrypt complete */
552 
553 /* Bit 0 : Encrypt/decrypt complete */
554 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
555 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
556 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
557 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
558 
559 /* Register: CCM_EVENTS_ERROR */
560 /* Description: Deprecated register - CCM error event */
561 
562 /* Bit 0 : Deprecated field -  CCM error event */
563 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
564 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
565 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
566 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
567 
568 /* Register: CCM_SHORTS */
569 /* Description: Shortcuts between local events and tasks */
570 
571 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
572 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
573 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
574 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
575 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
576 
577 /* Register: CCM_INTENSET */
578 /* Description: Enable interrupt */
579 
580 /* Bit 2 : Deprecated intsetfield -  Write '1' to enable interrupt for event ERROR */
581 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
582 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
583 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
584 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
585 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
586 
587 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
588 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
589 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
590 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
591 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
592 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
593 
594 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
595 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
596 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
597 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
598 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
599 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
600 
601 /* Register: CCM_INTENCLR */
602 /* Description: Disable interrupt */
603 
604 /* Bit 2 : Deprecated intclrfield -  Write '1' to disable interrupt for event ERROR */
605 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
606 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
607 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
608 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
609 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
610 
611 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
612 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
613 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
614 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
615 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
616 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
617 
618 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
619 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
620 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
621 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
622 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
623 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
624 
625 /* Register: CCM_MICSTATUS */
626 /* Description: MIC check result */
627 
628 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
629 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
630 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
631 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
632 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
633 
634 /* Register: CCM_ENABLE */
635 /* Description: Enable */
636 
637 /* Bits 1..0 : Enable or disable CCM */
638 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
639 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
640 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
641 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
642 
643 /* Register: CCM_MODE */
644 /* Description: Operation mode */
645 
646 /* Bit 24 : Packet length configuration */
647 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
648 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
649 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */
650 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */
651 
652 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
653 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
654 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
655 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
656 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
657 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */
658 #define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */
659 
660 /* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */
661 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
662 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
663 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
664 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
665 
666 /* Register: CCM_CNFPTR */
667 /* Description: Pointer to data structure holding AES key and NONCE vector */
668 
669 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
670 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
671 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
672 
673 /* Register: CCM_INPTR */
674 /* Description: Input pointer */
675 
676 /* Bits 31..0 : Input pointer */
677 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
678 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
679 
680 /* Register: CCM_OUTPTR */
681 /* Description: Output pointer */
682 
683 /* Bits 31..0 : Output pointer */
684 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
685 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
686 
687 /* Register: CCM_SCRATCHPTR */
688 /* Description: Pointer to data area used for temporary storage */
689 
690 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation,
691         MIC generation and encryption/decryption. */
692 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
693 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
694 
695 /* Register: CCM_MAXPACKETSIZE */
696 /* Description: Length of key-stream generated when MODE.LENGTH = Extended. */
697 
698 /* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */
699 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
700 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
701 
702 /* Register: CCM_RATEOVERRIDE */
703 /* Description: Data rate override setting. */
704 
705 /* Bits 1..0 : Data rate override setting. */
706 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
707 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
708 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
709 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
710 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */
711 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */
712 
713 
714 /* Peripheral: CLOCK */
715 /* Description: Clock control */
716 
717 /* Register: CLOCK_TASKS_HFCLKSTART */
718 /* Description: Start HFCLK crystal oscillator */
719 
720 /* Bit 0 : Start HFCLK crystal oscillator */
721 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
722 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
723 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
724 
725 /* Register: CLOCK_TASKS_HFCLKSTOP */
726 /* Description: Stop HFCLK crystal oscillator */
727 
728 /* Bit 0 : Stop HFCLK crystal oscillator */
729 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
730 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
731 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
732 
733 /* Register: CLOCK_TASKS_LFCLKSTART */
734 /* Description: Start LFCLK source */
735 
736 /* Bit 0 : Start LFCLK source */
737 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
738 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
739 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
740 
741 /* Register: CLOCK_TASKS_LFCLKSTOP */
742 /* Description: Stop LFCLK source */
743 
744 /* Bit 0 : Stop LFCLK source */
745 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
746 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
747 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
748 
749 /* Register: CLOCK_TASKS_CAL */
750 /* Description: Start calibration of LFRC oscillator */
751 
752 /* Bit 0 : Start calibration of LFRC oscillator */
753 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
754 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
755 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
756 
757 /* Register: CLOCK_TASKS_CTSTART */
758 /* Description: Start calibration timer */
759 
760 /* Bit 0 : Start calibration timer */
761 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */
762 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */
763 #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */
764 
765 /* Register: CLOCK_TASKS_CTSTOP */
766 /* Description: Stop calibration timer */
767 
768 /* Bit 0 : Stop calibration timer */
769 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */
770 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */
771 #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */
772 
773 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
774 /* Description: HFCLK oscillator started */
775 
776 /* Bit 0 : HFCLK oscillator started */
777 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
778 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
779 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
780 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
781 
782 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
783 /* Description: LFCLK started */
784 
785 /* Bit 0 : LFCLK started */
786 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
787 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
788 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
789 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
790 
791 /* Register: CLOCK_EVENTS_DONE */
792 /* Description: Calibration of LFCLK RC oscillator complete event */
793 
794 /* Bit 0 : Calibration of LFCLK RC oscillator complete event */
795 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
796 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
797 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
798 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
799 
800 /* Register: CLOCK_EVENTS_CTTO */
801 /* Description: Calibration timer timeout */
802 
803 /* Bit 0 : Calibration timer timeout */
804 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */
805 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */
806 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */
807 #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */
808 
809 /* Register: CLOCK_INTENSET */
810 /* Description: Enable interrupt */
811 
812 /* Bit 4 : Write '1' to enable interrupt for event CTTO */
813 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
814 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
815 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
816 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
817 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
818 
819 /* Bit 3 : Write '1' to enable interrupt for event DONE */
820 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
821 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
822 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
823 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
824 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
825 
826 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
827 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
828 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
829 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
830 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
831 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
832 
833 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
834 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
835 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
836 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
837 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
838 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
839 
840 /* Register: CLOCK_INTENCLR */
841 /* Description: Disable interrupt */
842 
843 /* Bit 4 : Write '1' to disable interrupt for event CTTO */
844 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
845 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
846 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
847 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
848 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
849 
850 /* Bit 3 : Write '1' to disable interrupt for event DONE */
851 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
852 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
853 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
854 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
855 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
856 
857 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
858 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
859 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
860 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
861 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
862 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
863 
864 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
865 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
866 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
867 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
868 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
869 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
870 
871 /* Register: CLOCK_HFCLKRUN */
872 /* Description: Status indicating that HFCLKSTART task has been triggered */
873 
874 /* Bit 0 : HFCLKSTART task triggered or not */
875 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
876 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
877 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
878 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
879 
880 /* Register: CLOCK_HFCLKSTAT */
881 /* Description: HFCLK status */
882 
883 /* Bit 16 : HFCLK state */
884 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
885 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
886 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
887 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
888 
889 /* Bit 0 : Source of HFCLK */
890 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
891 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
892 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
893 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
894 
895 /* Register: CLOCK_LFCLKRUN */
896 /* Description: Status indicating that LFCLKSTART task has been triggered */
897 
898 /* Bit 0 : LFCLKSTART task triggered or not */
899 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
900 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
901 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
902 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
903 
904 /* Register: CLOCK_LFCLKSTAT */
905 /* Description: LFCLK status */
906 
907 /* Bit 16 : LFCLK state */
908 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
909 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
910 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
911 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
912 
913 /* Bits 1..0 : Source of LFCLK */
914 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
915 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
916 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
917 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
918 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
919 
920 /* Register: CLOCK_LFCLKSRCCOPY */
921 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
922 
923 /* Bits 1..0 : Clock source */
924 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
925 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
926 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
927 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
928 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
929 
930 /* Register: CLOCK_LFCLKSRC */
931 /* Description: Clock source for the LFCLK */
932 
933 /* Bit 17 : Enable or disable external source for LFCLK */
934 #define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
935 #define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
936 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
937 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
938 
939 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
940 #define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
941 #define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
942 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
943 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
944 
945 /* Bits 1..0 : Clock source */
946 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
947 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
948 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
949 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
950 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
951 
952 /* Register: CLOCK_CTIV */
953 /* Description: Calibration timer interval */
954 
955 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
956 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
957 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
958 
959 
960 /* Peripheral: COMP */
961 /* Description: Comparator */
962 
963 /* Register: COMP_TASKS_START */
964 /* Description: Start comparator */
965 
966 /* Bit 0 : Start comparator */
967 #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
968 #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
969 #define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
970 
971 /* Register: COMP_TASKS_STOP */
972 /* Description: Stop comparator */
973 
974 /* Bit 0 : Stop comparator */
975 #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
976 #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
977 #define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
978 
979 /* Register: COMP_TASKS_SAMPLE */
980 /* Description: Sample comparator value */
981 
982 /* Bit 0 : Sample comparator value */
983 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
984 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
985 #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
986 
987 /* Register: COMP_EVENTS_READY */
988 /* Description: COMP is ready and output is valid */
989 
990 /* Bit 0 : COMP is ready and output is valid */
991 #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
992 #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
993 #define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
994 #define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
995 
996 /* Register: COMP_EVENTS_DOWN */
997 /* Description: Downward crossing */
998 
999 /* Bit 0 : Downward crossing */
1000 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */
1001 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */
1002 #define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */
1003 #define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */
1004 
1005 /* Register: COMP_EVENTS_UP */
1006 /* Description: Upward crossing */
1007 
1008 /* Bit 0 : Upward crossing */
1009 #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */
1010 #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */
1011 #define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */
1012 #define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */
1013 
1014 /* Register: COMP_EVENTS_CROSS */
1015 /* Description: Downward or upward crossing */
1016 
1017 /* Bit 0 : Downward or upward crossing */
1018 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */
1019 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */
1020 #define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */
1021 #define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */
1022 
1023 /* Register: COMP_SHORTS */
1024 /* Description: Shortcuts between local events and tasks */
1025 
1026 /* Bit 4 : Shortcut between event CROSS and task STOP */
1027 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
1028 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
1029 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
1030 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
1031 
1032 /* Bit 3 : Shortcut between event UP and task STOP */
1033 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
1034 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
1035 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
1036 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
1037 
1038 /* Bit 2 : Shortcut between event DOWN and task STOP */
1039 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
1040 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
1041 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
1042 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
1043 
1044 /* Bit 1 : Shortcut between event READY and task STOP */
1045 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
1046 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
1047 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
1048 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
1049 
1050 /* Bit 0 : Shortcut between event READY and task SAMPLE */
1051 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
1052 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
1053 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
1054 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
1055 
1056 /* Register: COMP_INTEN */
1057 /* Description: Enable or disable interrupt */
1058 
1059 /* Bit 3 : Enable or disable interrupt for event CROSS */
1060 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1061 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
1062 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
1063 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
1064 
1065 /* Bit 2 : Enable or disable interrupt for event UP */
1066 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
1067 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
1068 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
1069 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
1070 
1071 /* Bit 1 : Enable or disable interrupt for event DOWN */
1072 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1073 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
1074 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
1075 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
1076 
1077 /* Bit 0 : Enable or disable interrupt for event READY */
1078 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
1079 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
1080 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
1081 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
1082 
1083 /* Register: COMP_INTENSET */
1084 /* Description: Enable interrupt */
1085 
1086 /* Bit 3 : Write '1' to enable interrupt for event CROSS */
1087 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1088 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
1089 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
1090 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1091 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
1092 
1093 /* Bit 2 : Write '1' to enable interrupt for event UP */
1094 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
1095 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
1096 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
1097 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1098 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
1099 
1100 /* Bit 1 : Write '1' to enable interrupt for event DOWN */
1101 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1102 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
1103 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
1104 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1105 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
1106 
1107 /* Bit 0 : Write '1' to enable interrupt for event READY */
1108 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
1109 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
1110 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
1111 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1112 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
1113 
1114 /* Register: COMP_INTENCLR */
1115 /* Description: Disable interrupt */
1116 
1117 /* Bit 3 : Write '1' to disable interrupt for event CROSS */
1118 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1119 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
1120 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1121 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1122 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
1123 
1124 /* Bit 2 : Write '1' to disable interrupt for event UP */
1125 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
1126 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
1127 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1128 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1129 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
1130 
1131 /* Bit 1 : Write '1' to disable interrupt for event DOWN */
1132 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1133 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
1134 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1135 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1136 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
1137 
1138 /* Bit 0 : Write '1' to disable interrupt for event READY */
1139 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
1140 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
1141 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1142 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1143 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
1144 
1145 /* Register: COMP_RESULT */
1146 /* Description: Compare result */
1147 
1148 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
1149 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
1150 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
1151 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
1152 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
1153 
1154 /* Register: COMP_ENABLE */
1155 /* Description: COMP enable */
1156 
1157 /* Bits 1..0 : Enable or disable COMP */
1158 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1159 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1160 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1161 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1162 
1163 /* Register: COMP_PSEL */
1164 /* Description: Pin select */
1165 
1166 /* Bits 2..0 : Analog pin select */
1167 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
1168 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
1169 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
1170 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
1171 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
1172 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
1173 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
1174 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
1175 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
1176 #define COMP_PSEL_PSEL_VddDiv2 (7UL) /*!< VDD/2 selected as analog input */
1177 
1178 /* Register: COMP_REFSEL */
1179 /* Description: Reference source select for single-ended mode */
1180 
1181 /* Bits 2..0 : Reference select */
1182 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
1183 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
1184 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
1185 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
1186 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
1187 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
1188 #define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
1189 
1190 /* Register: COMP_EXTREFSEL */
1191 /* Description: External reference select */
1192 
1193 /* Bits 2..0 : External analog reference select */
1194 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
1195 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
1196 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
1197 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
1198 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */
1199 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */
1200 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */
1201 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */
1202 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */
1203 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */
1204 
1205 /* Register: COMP_TH */
1206 /* Description: Threshold configuration for hysteresis unit */
1207 
1208 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
1209 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
1210 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
1211 
1212 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
1213 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
1214 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
1215 
1216 /* Register: COMP_MODE */
1217 /* Description: Mode configuration */
1218 
1219 /* Bit 8 : Main operation modes */
1220 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
1221 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
1222 #define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
1223 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
1224 
1225 /* Bits 1..0 : Speed and power modes */
1226 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
1227 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
1228 #define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
1229 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
1230 #define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1231 
1232 /* Register: COMP_HYST */
1233 /* Description: Comparator hysteresis enable */
1234 
1235 /* Bit 0 : Comparator hysteresis */
1236 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
1237 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
1238 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1239 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1240 
1241 
1242 /* Peripheral: ECB */
1243 /* Description: AES ECB Mode Encryption */
1244 
1245 /* Register: ECB_TASKS_STARTECB */
1246 /* Description: Start ECB block encrypt */
1247 
1248 /* Bit 0 : Start ECB block encrypt */
1249 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
1250 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
1251 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
1252 
1253 /* Register: ECB_TASKS_STOPECB */
1254 /* Description: Abort a possible executing ECB operation */
1255 
1256 /* Bit 0 : Abort a possible executing ECB operation */
1257 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
1258 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
1259 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
1260 
1261 /* Register: ECB_EVENTS_ENDECB */
1262 /* Description: ECB block encrypt complete */
1263 
1264 /* Bit 0 : ECB block encrypt complete */
1265 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
1266 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
1267 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
1268 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
1269 
1270 /* Register: ECB_EVENTS_ERRORECB */
1271 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
1272 
1273 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
1274 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
1275 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
1276 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
1277 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
1278 
1279 /* Register: ECB_INTENSET */
1280 /* Description: Enable interrupt */
1281 
1282 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
1283 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1284 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1285 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1286 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1287 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1288 
1289 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */
1290 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1291 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1292 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1293 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1294 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1295 
1296 /* Register: ECB_INTENCLR */
1297 /* Description: Disable interrupt */
1298 
1299 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
1300 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1301 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1302 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1303 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1304 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1305 
1306 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */
1307 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1308 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1309 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1310 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1311 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1312 
1313 /* Register: ECB_ECBDATAPTR */
1314 /* Description: ECB block encrypt memory pointers */
1315 
1316 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
1317 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
1318 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
1319 
1320 
1321 /* Peripheral: EGU */
1322 /* Description: Event Generator Unit 0 */
1323 
1324 /* Register: EGU_TASKS_TRIGGER */
1325 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
1326 
1327 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
1328 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
1329 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
1330 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
1331 
1332 /* Register: EGU_EVENTS_TRIGGERED */
1333 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
1334 
1335 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
1336 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
1337 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
1338 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
1339 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
1340 
1341 /* Register: EGU_INTEN */
1342 /* Description: Enable or disable interrupt */
1343 
1344 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
1345 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1346 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1347 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1348 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1349 
1350 /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */
1351 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1352 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1353 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1354 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1355 
1356 /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */
1357 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1358 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1359 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1360 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1361 
1362 /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */
1363 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1364 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1365 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1366 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1367 
1368 /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */
1369 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1370 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1371 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1372 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1373 
1374 /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */
1375 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1376 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1377 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1378 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1379 
1380 /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */
1381 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1382 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1383 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1384 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1385 
1386 /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */
1387 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1388 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1389 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1390 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1391 
1392 /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */
1393 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1394 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1395 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1396 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1397 
1398 /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */
1399 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1400 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1401 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1402 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1403 
1404 /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */
1405 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1406 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1407 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1408 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1409 
1410 /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */
1411 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1412 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1413 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1414 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1415 
1416 /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */
1417 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1418 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1419 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1420 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1421 
1422 /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */
1423 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1424 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1425 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1426 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1427 
1428 /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */
1429 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1430 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1431 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1432 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1433 
1434 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
1435 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1436 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1437 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1438 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1439 
1440 /* Register: EGU_INTENSET */
1441 /* Description: Enable interrupt */
1442 
1443 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
1444 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1445 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1446 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1447 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1448 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1449 
1450 /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */
1451 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1452 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1453 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1454 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1455 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1456 
1457 /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */
1458 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1459 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1460 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1461 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1462 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1463 
1464 /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */
1465 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1466 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1467 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1468 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1469 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1470 
1471 /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */
1472 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1473 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1474 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1475 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1476 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1477 
1478 /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */
1479 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1480 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1481 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1482 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1483 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1484 
1485 /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */
1486 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1487 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1488 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1489 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1490 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1491 
1492 /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */
1493 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1494 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1495 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1496 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1497 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1498 
1499 /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */
1500 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1501 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1502 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1503 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1504 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1505 
1506 /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */
1507 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1508 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1509 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1510 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1511 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1512 
1513 /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */
1514 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1515 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1516 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1517 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1518 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1519 
1520 /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */
1521 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1522 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1523 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1524 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1525 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1526 
1527 /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */
1528 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1529 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1530 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1531 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1532 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1533 
1534 /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */
1535 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1536 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1537 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1538 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1539 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1540 
1541 /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */
1542 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1543 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1544 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1545 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1546 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1547 
1548 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
1549 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1550 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1551 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1552 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1553 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1554 
1555 /* Register: EGU_INTENCLR */
1556 /* Description: Disable interrupt */
1557 
1558 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
1559 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1560 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1561 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1562 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1563 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1564 
1565 /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */
1566 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1567 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1568 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1569 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1570 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1571 
1572 /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */
1573 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1574 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1575 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1576 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1577 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1578 
1579 /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */
1580 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1581 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1582 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1583 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1584 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1585 
1586 /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */
1587 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1588 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1589 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1590 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1591 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1592 
1593 /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */
1594 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1595 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1596 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1597 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1598 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1599 
1600 /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */
1601 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1602 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1603 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1604 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1605 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1606 
1607 /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */
1608 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1609 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1610 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1611 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1612 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1613 
1614 /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */
1615 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1616 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1617 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1618 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1619 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1620 
1621 /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */
1622 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1623 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1624 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1625 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1626 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1627 
1628 /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */
1629 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1630 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1631 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1632 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1633 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1634 
1635 /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */
1636 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1637 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1638 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1639 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1640 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1641 
1642 /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */
1643 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1644 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1645 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1646 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1647 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1648 
1649 /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */
1650 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1651 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1652 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1653 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1654 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1655 
1656 /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */
1657 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1658 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1659 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1660 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1661 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1662 
1663 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
1664 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1665 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1666 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1667 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1668 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1669 
1670 
1671 /* Peripheral: FICR */
1672 /* Description: Factory information configuration registers */
1673 
1674 /* Register: FICR_CODEPAGESIZE */
1675 /* Description: Code memory page size */
1676 
1677 /* Bits 31..0 : Code memory page size */
1678 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
1679 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
1680 
1681 /* Register: FICR_CODESIZE */
1682 /* Description: Code memory size */
1683 
1684 /* Bits 31..0 : Code memory size in number of pages */
1685 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
1686 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
1687 
1688 /* Register: FICR_DEVICEID */
1689 /* Description: Description collection: Device identifier */
1690 
1691 /* Bits 31..0 : 64 bit unique device identifier */
1692 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
1693 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
1694 
1695 /* Register: FICR_ER */
1696 /* Description: Description collection: Encryption root, word n */
1697 
1698 /* Bits 31..0 : Encryption root, word n */
1699 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
1700 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
1701 
1702 /* Register: FICR_IR */
1703 /* Description: Description collection: Identity root, word n */
1704 
1705 /* Bits 31..0 : Identity root, word n */
1706 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
1707 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
1708 
1709 /* Register: FICR_DEVICEADDRTYPE */
1710 /* Description: Device address type */
1711 
1712 /* Bit 0 : Device address type */
1713 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
1714 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
1715 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
1716 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
1717 
1718 /* Register: FICR_DEVICEADDR */
1719 /* Description: Description collection: Device address n */
1720 
1721 /* Bits 31..0 : 48 bit device address */
1722 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
1723 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
1724 
1725 /* Register: FICR_INFO_PART */
1726 /* Description: Part code */
1727 
1728 /* Bits 31..0 : Part code */
1729 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
1730 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
1731 #define FICR_INFO_PART_PART_N52810 (0x52810UL) /*!< nRF52810 */
1732 #define FICR_INFO_PART_PART_N52811 (0x52811UL) /*!< nRF52811 */
1733 #define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
1734 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1735 
1736 /* Register: FICR_INFO_VARIANT */
1737 /* Description: Part variant, hardware version and production configuration */
1738 
1739 /* Bits 31..0 : Part variant, hardware version and production configuration, encoded as ASCII */
1740 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
1741 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
1742 #define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */
1743 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
1744 #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
1745 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
1746 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
1747 #define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */
1748 #define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */
1749 #define FICR_INFO_VARIANT_VARIANT_AACB (0x41414342UL) /*!< AACB */
1750 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1751 
1752 /* Register: FICR_INFO_PACKAGE */
1753 /* Description: Package option */
1754 
1755 /* Bits 31..0 : Package option */
1756 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
1757 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
1758 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
1759 #define FICR_INFO_PACKAGE_PACKAGE_QC (0x2003UL) /*!< QCxx - 32-pin QFN */
1760 #define FICR_INFO_PACKAGE_PACKAGE_CA (0x2004UL) /*!< CAxx - WLCSP */
1761 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1762 
1763 /* Register: FICR_INFO_RAM */
1764 /* Description: RAM variant */
1765 
1766 /* Bits 31..0 : RAM variant */
1767 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
1768 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
1769 #define FICR_INFO_RAM_RAM_K24 (0x18UL) /*!< 24 kByte RAM */
1770 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1771 
1772 /* Register: FICR_INFO_FLASH */
1773 /* Description: Flash variant */
1774 
1775 /* Bits 31..0 : Flash variant */
1776 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
1777 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
1778 #define FICR_INFO_FLASH_FLASH_K192 (0xC0UL) /*!< 192 kByte flash */
1779 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1780 
1781 /* Register: FICR_TEMP_A0 */
1782 /* Description: Slope definition A0 */
1783 
1784 /* Bits 11..0 : A (slope definition) register */
1785 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
1786 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
1787 
1788 /* Register: FICR_TEMP_A1 */
1789 /* Description: Slope definition A1 */
1790 
1791 /* Bits 11..0 : A (slope definition) register */
1792 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
1793 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
1794 
1795 /* Register: FICR_TEMP_A2 */
1796 /* Description: Slope definition A2 */
1797 
1798 /* Bits 11..0 : A (slope definition) register */
1799 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
1800 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
1801 
1802 /* Register: FICR_TEMP_A3 */
1803 /* Description: Slope definition A3 */
1804 
1805 /* Bits 11..0 : A (slope definition) register */
1806 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
1807 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
1808 
1809 /* Register: FICR_TEMP_A4 */
1810 /* Description: Slope definition A4 */
1811 
1812 /* Bits 11..0 : A (slope definition) register */
1813 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
1814 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
1815 
1816 /* Register: FICR_TEMP_A5 */
1817 /* Description: Slope definition A5 */
1818 
1819 /* Bits 11..0 : A (slope definition) register */
1820 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
1821 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
1822 
1823 /* Register: FICR_TEMP_B0 */
1824 /* Description: Y-intercept B0 */
1825 
1826 /* Bits 13..0 : B (y-intercept) */
1827 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
1828 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
1829 
1830 /* Register: FICR_TEMP_B1 */
1831 /* Description: Y-intercept B1 */
1832 
1833 /* Bits 13..0 : B (y-intercept) */
1834 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
1835 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
1836 
1837 /* Register: FICR_TEMP_B2 */
1838 /* Description: Y-intercept B2 */
1839 
1840 /* Bits 13..0 : B (y-intercept) */
1841 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
1842 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
1843 
1844 /* Register: FICR_TEMP_B3 */
1845 /* Description: Y-intercept B3 */
1846 
1847 /* Bits 13..0 : B (y-intercept) */
1848 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
1849 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
1850 
1851 /* Register: FICR_TEMP_B4 */
1852 /* Description: Y-intercept B4 */
1853 
1854 /* Bits 13..0 : B (y-intercept) */
1855 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
1856 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
1857 
1858 /* Register: FICR_TEMP_B5 */
1859 /* Description: Y-intercept B5 */
1860 
1861 /* Bits 13..0 : B (y-intercept) */
1862 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
1863 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
1864 
1865 /* Register: FICR_TEMP_T0 */
1866 /* Description: Segment end T0 */
1867 
1868 /* Bits 7..0 : T (segment end) register */
1869 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
1870 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
1871 
1872 /* Register: FICR_TEMP_T1 */
1873 /* Description: Segment end T1 */
1874 
1875 /* Bits 7..0 : T (segment end) register */
1876 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
1877 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
1878 
1879 /* Register: FICR_TEMP_T2 */
1880 /* Description: Segment end T2 */
1881 
1882 /* Bits 7..0 : T (segment end) register */
1883 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
1884 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
1885 
1886 /* Register: FICR_TEMP_T3 */
1887 /* Description: Segment end T3 */
1888 
1889 /* Bits 7..0 : T (segment end) register */
1890 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
1891 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
1892 
1893 /* Register: FICR_TEMP_T4 */
1894 /* Description: Segment end T4 */
1895 
1896 /* Bits 7..0 : T (segment end) register */
1897 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
1898 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
1899 
1900 
1901 /* Peripheral: GPIOTE */
1902 /* Description: GPIO Tasks and Events */
1903 
1904 /* Register: GPIOTE_TASKS_OUT */
1905 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1906 
1907 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */
1908 #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */
1909 #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */
1910 #define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */
1911 
1912 /* Register: GPIOTE_TASKS_SET */
1913 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1914 
1915 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */
1916 #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */
1917 #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */
1918 #define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */
1919 
1920 /* Register: GPIOTE_TASKS_CLR */
1921 /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1922 
1923 /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */
1924 #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */
1925 #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */
1926 #define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */
1927 
1928 /* Register: GPIOTE_EVENTS_IN */
1929 /* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */
1930 
1931 /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */
1932 #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */
1933 #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */
1934 #define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */
1935 #define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */
1936 
1937 /* Register: GPIOTE_EVENTS_PORT */
1938 /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1939 
1940 /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */
1941 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */
1942 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */
1943 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */
1944 #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */
1945 
1946 /* Register: GPIOTE_INTENSET */
1947 /* Description: Enable interrupt */
1948 
1949 /* Bit 31 : Write '1' to enable interrupt for event PORT */
1950 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
1951 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
1952 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1953 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
1954 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
1955 
1956 /* Bit 7 : Write '1' to enable interrupt for event IN[7] */
1957 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
1958 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
1959 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1960 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
1961 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
1962 
1963 /* Bit 6 : Write '1' to enable interrupt for event IN[6] */
1964 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
1965 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
1966 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1967 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
1968 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
1969 
1970 /* Bit 5 : Write '1' to enable interrupt for event IN[5] */
1971 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
1972 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
1973 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1974 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
1975 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
1976 
1977 /* Bit 4 : Write '1' to enable interrupt for event IN[4] */
1978 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
1979 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
1980 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1981 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
1982 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
1983 
1984 /* Bit 3 : Write '1' to enable interrupt for event IN[3] */
1985 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
1986 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
1987 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1988 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
1989 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
1990 
1991 /* Bit 2 : Write '1' to enable interrupt for event IN[2] */
1992 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
1993 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
1994 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1995 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
1996 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
1997 
1998 /* Bit 1 : Write '1' to enable interrupt for event IN[1] */
1999 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
2000 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
2001 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
2002 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
2003 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
2004 
2005 /* Bit 0 : Write '1' to enable interrupt for event IN[0] */
2006 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
2007 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
2008 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
2009 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
2010 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
2011 
2012 /* Register: GPIOTE_INTENCLR */
2013 /* Description: Disable interrupt */
2014 
2015 /* Bit 31 : Write '1' to disable interrupt for event PORT */
2016 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
2017 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
2018 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
2019 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
2020 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
2021 
2022 /* Bit 7 : Write '1' to disable interrupt for event IN[7] */
2023 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
2024 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
2025 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
2026 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
2027 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
2028 
2029 /* Bit 6 : Write '1' to disable interrupt for event IN[6] */
2030 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
2031 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
2032 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
2033 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
2034 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
2035 
2036 /* Bit 5 : Write '1' to disable interrupt for event IN[5] */
2037 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
2038 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
2039 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
2040 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
2041 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
2042 
2043 /* Bit 4 : Write '1' to disable interrupt for event IN[4] */
2044 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
2045 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
2046 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
2047 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2048 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
2049 
2050 /* Bit 3 : Write '1' to disable interrupt for event IN[3] */
2051 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
2052 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
2053 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
2054 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2055 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
2056 
2057 /* Bit 2 : Write '1' to disable interrupt for event IN[2] */
2058 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
2059 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
2060 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
2061 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2062 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
2063 
2064 /* Bit 1 : Write '1' to disable interrupt for event IN[1] */
2065 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
2066 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
2067 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
2068 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2069 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
2070 
2071 /* Bit 0 : Write '1' to disable interrupt for event IN[0] */
2072 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
2073 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
2074 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2075 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2076 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
2077 
2078 /* Register: GPIOTE_CONFIG */
2079 /* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
2080 
2081 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
2082 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
2083 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
2084 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
2085 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
2086 
2087 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
2088 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
2089 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
2090 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
2091 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
2092 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
2093 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
2094 
2095 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
2096 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
2097 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
2098 
2099 /* Bits 1..0 : Mode */
2100 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
2101 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
2102 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
2103 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
2104 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
2105 
2106 
2107 /* Peripheral: NVMC */
2108 /* Description: Non-volatile memory controller */
2109 
2110 /* Register: NVMC_READY */
2111 /* Description: Ready flag */
2112 
2113 /* Bit 0 : NVMC is ready or busy */
2114 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
2115 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
2116 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */
2117 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
2118 
2119 /* Register: NVMC_CONFIG */
2120 /* Description: Configuration register */
2121 
2122 /* Bits 1..0 : Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. */
2123 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
2124 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
2125 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
2126 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
2127 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
2128 
2129 /* Register: NVMC_ERASEPAGE */
2130 /* Description: Register for erasing a page in code area */
2131 
2132 /* Bits 31..0 : Register for starting erase of a page in code area. */
2133 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
2134 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
2135 
2136 /* Register: NVMC_ERASEPCR1 */
2137 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */
2138 
2139 /* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */
2140 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
2141 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
2142 
2143 /* Register: NVMC_ERASEALL */
2144 /* Description: Register for erasing all non-volatile user memory */
2145 
2146 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */
2147 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
2148 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
2149 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
2150 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start erase of chip */
2151 
2152 /* Register: NVMC_ERASEPCR0 */
2153 /* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */
2154 
2155 /* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */
2156 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
2157 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
2158 
2159 /* Register: NVMC_ERASEUICR */
2160 /* Description: Register for erasing user information configuration registers */
2161 
2162 /* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */
2163 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
2164 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
2165 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
2166 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
2167 
2168 /* Register: NVMC_ERASEPAGEPARTIAL */
2169 /* Description: Register for partial erase of a page in code area */
2170 
2171 /* Bits 31..0 : Register for starting partial erase of a page in code area */
2172 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */
2173 #define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */
2174 
2175 /* Register: NVMC_ERASEPAGEPARTIALCFG */
2176 /* Description: Register for partial erase configuration */
2177 
2178 /* Bits 6..0 : Duration of the partial erase in milliseconds */
2179 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
2180 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
2181 
2182 
2183 /* Peripheral: GPIO */
2184 /* Description: GPIO Port */
2185 
2186 /* Register: GPIO_OUT */
2187 /* Description: Write GPIO port */
2188 
2189 /* Bit 31 : Pin 31 */
2190 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2191 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2192 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
2193 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
2194 
2195 /* Bit 30 : Pin 30 */
2196 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2197 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2198 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
2199 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
2200 
2201 /* Bit 29 : Pin 29 */
2202 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2203 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2204 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
2205 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
2206 
2207 /* Bit 28 : Pin 28 */
2208 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2209 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2210 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
2211 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
2212 
2213 /* Bit 27 : Pin 27 */
2214 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2215 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2216 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
2217 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
2218 
2219 /* Bit 26 : Pin 26 */
2220 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2221 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2222 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
2223 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
2224 
2225 /* Bit 25 : Pin 25 */
2226 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2227 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2228 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
2229 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
2230 
2231 /* Bit 24 : Pin 24 */
2232 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2233 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2234 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
2235 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
2236 
2237 /* Bit 23 : Pin 23 */
2238 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2239 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2240 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
2241 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
2242 
2243 /* Bit 22 : Pin 22 */
2244 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2245 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2246 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
2247 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
2248 
2249 /* Bit 21 : Pin 21 */
2250 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2251 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2252 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
2253 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
2254 
2255 /* Bit 20 : Pin 20 */
2256 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2257 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2258 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
2259 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
2260 
2261 /* Bit 19 : Pin 19 */
2262 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2263 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2264 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
2265 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
2266 
2267 /* Bit 18 : Pin 18 */
2268 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2269 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2270 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
2271 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
2272 
2273 /* Bit 17 : Pin 17 */
2274 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2275 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2276 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
2277 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
2278 
2279 /* Bit 16 : Pin 16 */
2280 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2281 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2282 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
2283 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
2284 
2285 /* Bit 15 : Pin 15 */
2286 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2287 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2288 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
2289 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
2290 
2291 /* Bit 14 : Pin 14 */
2292 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2293 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2294 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
2295 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
2296 
2297 /* Bit 13 : Pin 13 */
2298 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2299 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2300 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
2301 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
2302 
2303 /* Bit 12 : Pin 12 */
2304 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2305 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2306 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
2307 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
2308 
2309 /* Bit 11 : Pin 11 */
2310 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2311 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2312 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
2313 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
2314 
2315 /* Bit 10 : Pin 10 */
2316 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2317 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2318 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
2319 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
2320 
2321 /* Bit 9 : Pin 9 */
2322 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2323 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2324 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
2325 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
2326 
2327 /* Bit 8 : Pin 8 */
2328 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2329 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2330 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
2331 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
2332 
2333 /* Bit 7 : Pin 7 */
2334 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2335 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2336 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
2337 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
2338 
2339 /* Bit 6 : Pin 6 */
2340 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2341 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2342 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
2343 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
2344 
2345 /* Bit 5 : Pin 5 */
2346 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
2347 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
2348 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
2349 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
2350 
2351 /* Bit 4 : Pin 4 */
2352 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
2353 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
2354 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
2355 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
2356 
2357 /* Bit 3 : Pin 3 */
2358 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
2359 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
2360 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
2361 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
2362 
2363 /* Bit 2 : Pin 2 */
2364 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2365 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
2366 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
2367 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
2368 
2369 /* Bit 1 : Pin 1 */
2370 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
2371 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
2372 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
2373 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
2374 
2375 /* Bit 0 : Pin 0 */
2376 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
2377 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
2378 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
2379 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
2380 
2381 /* Register: GPIO_OUTSET */
2382 /* Description: Set individual bits in GPIO port */
2383 
2384 /* Bit 31 : Pin 31 */
2385 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2386 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2387 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
2388 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
2389 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2390 
2391 /* Bit 30 : Pin 30 */
2392 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2393 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2394 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
2395 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
2396 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2397 
2398 /* Bit 29 : Pin 29 */
2399 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2400 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2401 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
2402 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
2403 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2404 
2405 /* Bit 28 : Pin 28 */
2406 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2407 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2408 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
2409 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
2410 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2411 
2412 /* Bit 27 : Pin 27 */
2413 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2414 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2415 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
2416 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
2417 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2418 
2419 /* Bit 26 : Pin 26 */
2420 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2421 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2422 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
2423 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
2424 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2425 
2426 /* Bit 25 : Pin 25 */
2427 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2428 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2429 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
2430 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
2431 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2432 
2433 /* Bit 24 : Pin 24 */
2434 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2435 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2436 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
2437 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
2438 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2439 
2440 /* Bit 23 : Pin 23 */
2441 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2442 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2443 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
2444 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
2445 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2446 
2447 /* Bit 22 : Pin 22 */
2448 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2449 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2450 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
2451 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
2452 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2453 
2454 /* Bit 21 : Pin 21 */
2455 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2456 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2457 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
2458 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
2459 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2460 
2461 /* Bit 20 : Pin 20 */
2462 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2463 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2464 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
2465 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
2466 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2467 
2468 /* Bit 19 : Pin 19 */
2469 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2470 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2471 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
2472 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
2473 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2474 
2475 /* Bit 18 : Pin 18 */
2476 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2477 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2478 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
2479 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
2480 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2481 
2482 /* Bit 17 : Pin 17 */
2483 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2484 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2485 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
2486 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
2487 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2488 
2489 /* Bit 16 : Pin 16 */
2490 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2491 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2492 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
2493 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
2494 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2495 
2496 /* Bit 15 : Pin 15 */
2497 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2498 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2499 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
2500 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
2501 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2502 
2503 /* Bit 14 : Pin 14 */
2504 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2505 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2506 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
2507 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
2508 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2509 
2510 /* Bit 13 : Pin 13 */
2511 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2512 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2513 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
2514 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
2515 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2516 
2517 /* Bit 12 : Pin 12 */
2518 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2519 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2520 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
2521 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
2522 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2523 
2524 /* Bit 11 : Pin 11 */
2525 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2526 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2527 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
2528 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
2529 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2530 
2531 /* Bit 10 : Pin 10 */
2532 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2533 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2534 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
2535 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
2536 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2537 
2538 /* Bit 9 : Pin 9 */
2539 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2540 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2541 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
2542 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
2543 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2544 
2545 /* Bit 8 : Pin 8 */
2546 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2547 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2548 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
2549 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
2550 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2551 
2552 /* Bit 7 : Pin 7 */
2553 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2554 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2555 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
2556 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
2557 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2558 
2559 /* Bit 6 : Pin 6 */
2560 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2561 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2562 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
2563 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
2564 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2565 
2566 /* Bit 5 : Pin 5 */
2567 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
2568 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
2569 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
2570 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
2571 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2572 
2573 /* Bit 4 : Pin 4 */
2574 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
2575 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
2576 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
2577 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
2578 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2579 
2580 /* Bit 3 : Pin 3 */
2581 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
2582 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
2583 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
2584 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
2585 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2586 
2587 /* Bit 2 : Pin 2 */
2588 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2589 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
2590 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
2591 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
2592 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2593 
2594 /* Bit 1 : Pin 1 */
2595 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
2596 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
2597 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
2598 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
2599 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2600 
2601 /* Bit 0 : Pin 0 */
2602 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
2603 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
2604 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
2605 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
2606 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
2607 
2608 /* Register: GPIO_OUTCLR */
2609 /* Description: Clear individual bits in GPIO port */
2610 
2611 /* Bit 31 : Pin 31 */
2612 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2613 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2614 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
2615 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
2616 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2617 
2618 /* Bit 30 : Pin 30 */
2619 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2620 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2621 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
2622 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
2623 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2624 
2625 /* Bit 29 : Pin 29 */
2626 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2627 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2628 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
2629 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
2630 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2631 
2632 /* Bit 28 : Pin 28 */
2633 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2634 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2635 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
2636 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
2637 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2638 
2639 /* Bit 27 : Pin 27 */
2640 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2641 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2642 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
2643 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
2644 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2645 
2646 /* Bit 26 : Pin 26 */
2647 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2648 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2649 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
2650 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
2651 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2652 
2653 /* Bit 25 : Pin 25 */
2654 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2655 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2656 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
2657 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
2658 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2659 
2660 /* Bit 24 : Pin 24 */
2661 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2662 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2663 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
2664 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
2665 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2666 
2667 /* Bit 23 : Pin 23 */
2668 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2669 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2670 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
2671 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
2672 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2673 
2674 /* Bit 22 : Pin 22 */
2675 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2676 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2677 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
2678 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
2679 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2680 
2681 /* Bit 21 : Pin 21 */
2682 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2683 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2684 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
2685 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
2686 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2687 
2688 /* Bit 20 : Pin 20 */
2689 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2690 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2691 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
2692 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
2693 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2694 
2695 /* Bit 19 : Pin 19 */
2696 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2697 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2698 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
2699 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
2700 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2701 
2702 /* Bit 18 : Pin 18 */
2703 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2704 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2705 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
2706 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
2707 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2708 
2709 /* Bit 17 : Pin 17 */
2710 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2711 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2712 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
2713 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
2714 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2715 
2716 /* Bit 16 : Pin 16 */
2717 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2718 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2719 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
2720 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
2721 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2722 
2723 /* Bit 15 : Pin 15 */
2724 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2725 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2726 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
2727 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
2728 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2729 
2730 /* Bit 14 : Pin 14 */
2731 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2732 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2733 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
2734 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
2735 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2736 
2737 /* Bit 13 : Pin 13 */
2738 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2739 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2740 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
2741 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
2742 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2743 
2744 /* Bit 12 : Pin 12 */
2745 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2746 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2747 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
2748 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
2749 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2750 
2751 /* Bit 11 : Pin 11 */
2752 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2753 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2754 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
2755 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
2756 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2757 
2758 /* Bit 10 : Pin 10 */
2759 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2760 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2761 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
2762 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
2763 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2764 
2765 /* Bit 9 : Pin 9 */
2766 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2767 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2768 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
2769 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
2770 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2771 
2772 /* Bit 8 : Pin 8 */
2773 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2774 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2775 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
2776 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
2777 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2778 
2779 /* Bit 7 : Pin 7 */
2780 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2781 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2782 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
2783 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
2784 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2785 
2786 /* Bit 6 : Pin 6 */
2787 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2788 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2789 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
2790 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
2791 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2792 
2793 /* Bit 5 : Pin 5 */
2794 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
2795 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
2796 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
2797 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
2798 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2799 
2800 /* Bit 4 : Pin 4 */
2801 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
2802 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
2803 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
2804 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
2805 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2806 
2807 /* Bit 3 : Pin 3 */
2808 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
2809 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
2810 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
2811 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
2812 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2813 
2814 /* Bit 2 : Pin 2 */
2815 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
2816 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
2817 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
2818 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
2819 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2820 
2821 /* Bit 1 : Pin 1 */
2822 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
2823 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
2824 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
2825 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
2826 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2827 
2828 /* Bit 0 : Pin 0 */
2829 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
2830 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
2831 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
2832 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
2833 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
2834 
2835 /* Register: GPIO_IN */
2836 /* Description: Read GPIO port */
2837 
2838 /* Bit 31 : Pin 31 */
2839 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
2840 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
2841 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
2842 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
2843 
2844 /* Bit 30 : Pin 30 */
2845 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
2846 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
2847 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
2848 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
2849 
2850 /* Bit 29 : Pin 29 */
2851 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
2852 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
2853 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
2854 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
2855 
2856 /* Bit 28 : Pin 28 */
2857 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
2858 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
2859 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
2860 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
2861 
2862 /* Bit 27 : Pin 27 */
2863 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
2864 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
2865 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
2866 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
2867 
2868 /* Bit 26 : Pin 26 */
2869 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
2870 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
2871 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
2872 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
2873 
2874 /* Bit 25 : Pin 25 */
2875 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
2876 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
2877 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
2878 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
2879 
2880 /* Bit 24 : Pin 24 */
2881 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
2882 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
2883 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
2884 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
2885 
2886 /* Bit 23 : Pin 23 */
2887 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
2888 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
2889 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
2890 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
2891 
2892 /* Bit 22 : Pin 22 */
2893 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
2894 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
2895 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
2896 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
2897 
2898 /* Bit 21 : Pin 21 */
2899 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
2900 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
2901 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
2902 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
2903 
2904 /* Bit 20 : Pin 20 */
2905 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
2906 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
2907 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
2908 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
2909 
2910 /* Bit 19 : Pin 19 */
2911 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
2912 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
2913 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
2914 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
2915 
2916 /* Bit 18 : Pin 18 */
2917 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
2918 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
2919 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
2920 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
2921 
2922 /* Bit 17 : Pin 17 */
2923 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
2924 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
2925 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
2926 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
2927 
2928 /* Bit 16 : Pin 16 */
2929 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
2930 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
2931 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
2932 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
2933 
2934 /* Bit 15 : Pin 15 */
2935 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
2936 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
2937 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
2938 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
2939 
2940 /* Bit 14 : Pin 14 */
2941 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
2942 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
2943 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
2944 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
2945 
2946 /* Bit 13 : Pin 13 */
2947 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
2948 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
2949 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
2950 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
2951 
2952 /* Bit 12 : Pin 12 */
2953 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
2954 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
2955 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
2956 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
2957 
2958 /* Bit 11 : Pin 11 */
2959 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
2960 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
2961 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
2962 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
2963 
2964 /* Bit 10 : Pin 10 */
2965 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
2966 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
2967 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
2968 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
2969 
2970 /* Bit 9 : Pin 9 */
2971 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
2972 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
2973 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
2974 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
2975 
2976 /* Bit 8 : Pin 8 */
2977 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
2978 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
2979 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
2980 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
2981 
2982 /* Bit 7 : Pin 7 */
2983 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
2984 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
2985 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
2986 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
2987 
2988 /* Bit 6 : Pin 6 */
2989 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
2990 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
2991 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
2992 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
2993 
2994 /* Bit 5 : Pin 5 */
2995 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
2996 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
2997 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
2998 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
2999 
3000 /* Bit 4 : Pin 4 */
3001 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3002 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3003 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
3004 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
3005 
3006 /* Bit 3 : Pin 3 */
3007 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3008 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3009 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
3010 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
3011 
3012 /* Bit 2 : Pin 2 */
3013 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3014 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3015 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
3016 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
3017 
3018 /* Bit 1 : Pin 1 */
3019 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3020 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3021 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
3022 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
3023 
3024 /* Bit 0 : Pin 0 */
3025 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3026 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3027 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
3028 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
3029 
3030 /* Register: GPIO_DIR */
3031 /* Description: Direction of GPIO pins */
3032 
3033 /* Bit 31 : Pin 31 */
3034 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3035 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3036 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
3037 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
3038 
3039 /* Bit 30 : Pin 30 */
3040 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3041 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3042 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
3043 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
3044 
3045 /* Bit 29 : Pin 29 */
3046 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3047 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3048 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
3049 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
3050 
3051 /* Bit 28 : Pin 28 */
3052 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3053 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3054 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
3055 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
3056 
3057 /* Bit 27 : Pin 27 */
3058 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3059 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3060 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
3061 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
3062 
3063 /* Bit 26 : Pin 26 */
3064 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3065 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3066 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
3067 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
3068 
3069 /* Bit 25 : Pin 25 */
3070 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3071 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3072 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
3073 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
3074 
3075 /* Bit 24 : Pin 24 */
3076 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3077 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3078 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
3079 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
3080 
3081 /* Bit 23 : Pin 23 */
3082 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3083 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3084 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
3085 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
3086 
3087 /* Bit 22 : Pin 22 */
3088 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3089 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3090 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
3091 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
3092 
3093 /* Bit 21 : Pin 21 */
3094 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3095 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3096 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
3097 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
3098 
3099 /* Bit 20 : Pin 20 */
3100 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3101 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3102 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
3103 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
3104 
3105 /* Bit 19 : Pin 19 */
3106 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3107 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3108 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
3109 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
3110 
3111 /* Bit 18 : Pin 18 */
3112 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3113 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3114 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
3115 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
3116 
3117 /* Bit 17 : Pin 17 */
3118 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3119 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3120 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
3121 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
3122 
3123 /* Bit 16 : Pin 16 */
3124 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3125 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3126 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
3127 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
3128 
3129 /* Bit 15 : Pin 15 */
3130 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3131 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3132 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
3133 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
3134 
3135 /* Bit 14 : Pin 14 */
3136 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3137 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3138 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
3139 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
3140 
3141 /* Bit 13 : Pin 13 */
3142 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3143 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3144 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
3145 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
3146 
3147 /* Bit 12 : Pin 12 */
3148 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3149 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3150 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
3151 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
3152 
3153 /* Bit 11 : Pin 11 */
3154 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3155 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3156 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
3157 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
3158 
3159 /* Bit 10 : Pin 10 */
3160 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3161 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3162 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
3163 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
3164 
3165 /* Bit 9 : Pin 9 */
3166 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3167 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3168 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
3169 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
3170 
3171 /* Bit 8 : Pin 8 */
3172 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3173 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3174 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
3175 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
3176 
3177 /* Bit 7 : Pin 7 */
3178 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3179 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3180 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
3181 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
3182 
3183 /* Bit 6 : Pin 6 */
3184 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3185 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3186 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
3187 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
3188 
3189 /* Bit 5 : Pin 5 */
3190 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3191 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3192 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
3193 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
3194 
3195 /* Bit 4 : Pin 4 */
3196 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3197 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3198 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
3199 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
3200 
3201 /* Bit 3 : Pin 3 */
3202 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3203 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3204 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
3205 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
3206 
3207 /* Bit 2 : Pin 2 */
3208 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3209 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3210 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
3211 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
3212 
3213 /* Bit 1 : Pin 1 */
3214 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3215 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3216 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
3217 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
3218 
3219 /* Bit 0 : Pin 0 */
3220 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3221 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3222 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
3223 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
3224 
3225 /* Register: GPIO_DIRSET */
3226 /* Description: DIR set register */
3227 
3228 /* Bit 31 : Set as output pin 31 */
3229 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3230 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3231 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
3232 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
3233 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3234 
3235 /* Bit 30 : Set as output pin 30 */
3236 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3237 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3238 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
3239 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
3240 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3241 
3242 /* Bit 29 : Set as output pin 29 */
3243 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3244 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3245 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
3246 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
3247 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3248 
3249 /* Bit 28 : Set as output pin 28 */
3250 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3251 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3252 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
3253 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
3254 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3255 
3256 /* Bit 27 : Set as output pin 27 */
3257 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3258 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3259 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
3260 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
3261 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3262 
3263 /* Bit 26 : Set as output pin 26 */
3264 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3265 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3266 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
3267 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
3268 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3269 
3270 /* Bit 25 : Set as output pin 25 */
3271 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3272 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3273 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
3274 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
3275 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3276 
3277 /* Bit 24 : Set as output pin 24 */
3278 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3279 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3280 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
3281 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
3282 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3283 
3284 /* Bit 23 : Set as output pin 23 */
3285 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3286 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3287 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
3288 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
3289 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3290 
3291 /* Bit 22 : Set as output pin 22 */
3292 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3293 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3294 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
3295 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
3296 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3297 
3298 /* Bit 21 : Set as output pin 21 */
3299 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3300 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3301 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
3302 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
3303 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3304 
3305 /* Bit 20 : Set as output pin 20 */
3306 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3307 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3308 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
3309 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
3310 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3311 
3312 /* Bit 19 : Set as output pin 19 */
3313 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3314 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3315 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
3316 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
3317 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3318 
3319 /* Bit 18 : Set as output pin 18 */
3320 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3321 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3322 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
3323 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
3324 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3325 
3326 /* Bit 17 : Set as output pin 17 */
3327 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3328 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3329 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
3330 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
3331 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3332 
3333 /* Bit 16 : Set as output pin 16 */
3334 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3335 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3336 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
3337 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
3338 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3339 
3340 /* Bit 15 : Set as output pin 15 */
3341 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3342 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3343 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
3344 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
3345 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3346 
3347 /* Bit 14 : Set as output pin 14 */
3348 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3349 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3350 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
3351 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
3352 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3353 
3354 /* Bit 13 : Set as output pin 13 */
3355 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3356 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3357 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
3358 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
3359 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3360 
3361 /* Bit 12 : Set as output pin 12 */
3362 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3363 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3364 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
3365 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
3366 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3367 
3368 /* Bit 11 : Set as output pin 11 */
3369 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3370 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3371 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
3372 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
3373 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3374 
3375 /* Bit 10 : Set as output pin 10 */
3376 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3377 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3378 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
3379 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
3380 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3381 
3382 /* Bit 9 : Set as output pin 9 */
3383 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3384 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3385 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
3386 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
3387 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3388 
3389 /* Bit 8 : Set as output pin 8 */
3390 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3391 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3392 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
3393 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
3394 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3395 
3396 /* Bit 7 : Set as output pin 7 */
3397 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3398 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3399 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
3400 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
3401 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3402 
3403 /* Bit 6 : Set as output pin 6 */
3404 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3405 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3406 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
3407 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
3408 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3409 
3410 /* Bit 5 : Set as output pin 5 */
3411 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3412 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3413 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
3414 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
3415 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3416 
3417 /* Bit 4 : Set as output pin 4 */
3418 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3419 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3420 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
3421 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
3422 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3423 
3424 /* Bit 3 : Set as output pin 3 */
3425 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3426 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3427 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
3428 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
3429 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3430 
3431 /* Bit 2 : Set as output pin 2 */
3432 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3433 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3434 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
3435 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
3436 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3437 
3438 /* Bit 1 : Set as output pin 1 */
3439 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3440 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3441 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
3442 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
3443 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3444 
3445 /* Bit 0 : Set as output pin 0 */
3446 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3447 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3448 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
3449 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
3450 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
3451 
3452 /* Register: GPIO_DIRCLR */
3453 /* Description: DIR clear register */
3454 
3455 /* Bit 31 : Set as input pin 31 */
3456 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3457 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3458 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
3459 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
3460 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3461 
3462 /* Bit 30 : Set as input pin 30 */
3463 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3464 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3465 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
3466 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
3467 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3468 
3469 /* Bit 29 : Set as input pin 29 */
3470 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3471 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3472 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
3473 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
3474 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3475 
3476 /* Bit 28 : Set as input pin 28 */
3477 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3478 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3479 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
3480 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
3481 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3482 
3483 /* Bit 27 : Set as input pin 27 */
3484 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3485 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3486 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
3487 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
3488 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3489 
3490 /* Bit 26 : Set as input pin 26 */
3491 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3492 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3493 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
3494 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
3495 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3496 
3497 /* Bit 25 : Set as input pin 25 */
3498 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3499 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3500 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
3501 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
3502 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3503 
3504 /* Bit 24 : Set as input pin 24 */
3505 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3506 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3507 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
3508 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
3509 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3510 
3511 /* Bit 23 : Set as input pin 23 */
3512 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3513 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3514 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
3515 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
3516 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3517 
3518 /* Bit 22 : Set as input pin 22 */
3519 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3520 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3521 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
3522 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
3523 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3524 
3525 /* Bit 21 : Set as input pin 21 */
3526 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3527 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3528 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
3529 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
3530 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3531 
3532 /* Bit 20 : Set as input pin 20 */
3533 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3534 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3535 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
3536 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
3537 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3538 
3539 /* Bit 19 : Set as input pin 19 */
3540 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3541 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3542 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
3543 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
3544 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3545 
3546 /* Bit 18 : Set as input pin 18 */
3547 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3548 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3549 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
3550 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
3551 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3552 
3553 /* Bit 17 : Set as input pin 17 */
3554 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3555 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3556 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
3557 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
3558 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3559 
3560 /* Bit 16 : Set as input pin 16 */
3561 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3562 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3563 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
3564 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
3565 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3566 
3567 /* Bit 15 : Set as input pin 15 */
3568 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3569 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3570 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
3571 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
3572 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3573 
3574 /* Bit 14 : Set as input pin 14 */
3575 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3576 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3577 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
3578 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
3579 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3580 
3581 /* Bit 13 : Set as input pin 13 */
3582 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3583 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3584 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
3585 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
3586 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3587 
3588 /* Bit 12 : Set as input pin 12 */
3589 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3590 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3591 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
3592 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
3593 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3594 
3595 /* Bit 11 : Set as input pin 11 */
3596 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3597 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3598 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
3599 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
3600 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3601 
3602 /* Bit 10 : Set as input pin 10 */
3603 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3604 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3605 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
3606 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
3607 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3608 
3609 /* Bit 9 : Set as input pin 9 */
3610 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3611 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3612 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
3613 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
3614 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3615 
3616 /* Bit 8 : Set as input pin 8 */
3617 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3618 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3619 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
3620 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
3621 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3622 
3623 /* Bit 7 : Set as input pin 7 */
3624 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3625 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3626 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
3627 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
3628 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3629 
3630 /* Bit 6 : Set as input pin 6 */
3631 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3632 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3633 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
3634 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
3635 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3636 
3637 /* Bit 5 : Set as input pin 5 */
3638 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3639 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3640 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
3641 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
3642 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3643 
3644 /* Bit 4 : Set as input pin 4 */
3645 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3646 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3647 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
3648 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
3649 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3650 
3651 /* Bit 3 : Set as input pin 3 */
3652 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3653 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3654 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
3655 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
3656 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3657 
3658 /* Bit 2 : Set as input pin 2 */
3659 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3660 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3661 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
3662 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
3663 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3664 
3665 /* Bit 1 : Set as input pin 1 */
3666 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3667 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3668 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
3669 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
3670 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3671 
3672 /* Bit 0 : Set as input pin 0 */
3673 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3674 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3675 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
3676 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
3677 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
3678 
3679 /* Register: GPIO_LATCH */
3680 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
3681 
3682 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
3683 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
3684 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
3685 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
3686 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
3687 
3688 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
3689 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
3690 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
3691 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
3692 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
3693 
3694 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
3695 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
3696 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
3697 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
3698 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
3699 
3700 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
3701 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
3702 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
3703 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
3704 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
3705 
3706 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
3707 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
3708 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
3709 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
3710 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
3711 
3712 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
3713 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
3714 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
3715 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
3716 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
3717 
3718 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
3719 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
3720 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
3721 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
3722 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
3723 
3724 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
3725 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
3726 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
3727 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
3728 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
3729 
3730 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
3731 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
3732 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
3733 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
3734 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
3735 
3736 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
3737 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
3738 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
3739 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
3740 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
3741 
3742 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
3743 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
3744 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
3745 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
3746 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
3747 
3748 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
3749 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
3750 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
3751 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
3752 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
3753 
3754 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
3755 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
3756 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
3757 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
3758 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
3759 
3760 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
3761 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
3762 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
3763 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
3764 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
3765 
3766 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
3767 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
3768 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
3769 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
3770 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
3771 
3772 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
3773 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
3774 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
3775 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
3776 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
3777 
3778 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
3779 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
3780 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
3781 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
3782 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
3783 
3784 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
3785 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
3786 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
3787 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
3788 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
3789 
3790 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
3791 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
3792 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
3793 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
3794 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
3795 
3796 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
3797 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
3798 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
3799 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
3800 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
3801 
3802 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
3803 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
3804 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
3805 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
3806 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
3807 
3808 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
3809 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
3810 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
3811 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
3812 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
3813 
3814 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
3815 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
3816 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
3817 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
3818 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
3819 
3820 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
3821 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
3822 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
3823 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
3824 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
3825 
3826 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
3827 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
3828 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
3829 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
3830 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
3831 
3832 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
3833 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
3834 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
3835 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
3836 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
3837 
3838 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
3839 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
3840 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
3841 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
3842 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
3843 
3844 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
3845 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
3846 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
3847 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
3848 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
3849 
3850 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
3851 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
3852 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
3853 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
3854 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
3855 
3856 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
3857 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
3858 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
3859 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
3860 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
3861 
3862 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
3863 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
3864 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
3865 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
3866 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
3867 
3868 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
3869 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
3870 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
3871 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
3872 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
3873 
3874 /* Register: GPIO_DETECTMODE */
3875 /* Description: Select between default DETECT signal behaviour and LDETECT mode */
3876 
3877 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
3878 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
3879 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
3880 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
3881 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
3882 
3883 /* Register: GPIO_PIN_CNF */
3884 /* Description: Description collection: Configuration of GPIO pins */
3885 
3886 /* Bits 17..16 : Pin sensing mechanism */
3887 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
3888 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
3889 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
3890 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
3891 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
3892 
3893 /* Bits 10..8 : Drive configuration */
3894 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
3895 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
3896 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
3897 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
3898 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
3899 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
3900 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
3901 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
3902 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
3903 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
3904 
3905 /* Bits 3..2 : Pull configuration */
3906 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
3907 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
3908 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
3909 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
3910 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
3911 
3912 /* Bit 1 : Connect or disconnect input buffer */
3913 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
3914 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
3915 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
3916 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
3917 
3918 /* Bit 0 : Pin direction. Same physical register as DIR register */
3919 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
3920 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
3921 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
3922 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
3923 
3924 
3925 /* Peripheral: PDM */
3926 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
3927 
3928 /* Register: PDM_TASKS_START */
3929 /* Description: Starts continuous PDM transfer */
3930 
3931 /* Bit 0 : Starts continuous PDM transfer */
3932 #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
3933 #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
3934 #define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
3935 
3936 /* Register: PDM_TASKS_STOP */
3937 /* Description: Stops PDM transfer */
3938 
3939 /* Bit 0 : Stops PDM transfer */
3940 #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
3941 #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
3942 #define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
3943 
3944 /* Register: PDM_EVENTS_STARTED */
3945 /* Description: PDM transfer has started */
3946 
3947 /* Bit 0 : PDM transfer has started */
3948 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
3949 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
3950 #define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
3951 #define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
3952 
3953 /* Register: PDM_EVENTS_STOPPED */
3954 /* Description: PDM transfer has finished */
3955 
3956 /* Bit 0 : PDM transfer has finished */
3957 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
3958 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
3959 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
3960 #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
3961 
3962 /* Register: PDM_EVENTS_END */
3963 /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
3964 
3965 /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */
3966 #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
3967 #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
3968 #define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
3969 #define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
3970 
3971 /* Register: PDM_INTEN */
3972 /* Description: Enable or disable interrupt */
3973 
3974 /* Bit 2 : Enable or disable interrupt for event END */
3975 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
3976 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
3977 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
3978 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
3979 
3980 /* Bit 1 : Enable or disable interrupt for event STOPPED */
3981 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
3982 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
3983 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
3984 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
3985 
3986 /* Bit 0 : Enable or disable interrupt for event STARTED */
3987 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
3988 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
3989 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
3990 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
3991 
3992 /* Register: PDM_INTENSET */
3993 /* Description: Enable interrupt */
3994 
3995 /* Bit 2 : Write '1' to enable interrupt for event END */
3996 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
3997 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
3998 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
3999 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
4000 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
4001 
4002 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
4003 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4004 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4005 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4006 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4007 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
4008 
4009 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
4010 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
4011 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
4012 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4013 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4014 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
4015 
4016 /* Register: PDM_INTENCLR */
4017 /* Description: Disable interrupt */
4018 
4019 /* Bit 2 : Write '1' to disable interrupt for event END */
4020 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
4021 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
4022 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
4023 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
4024 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
4025 
4026 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
4027 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
4028 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
4029 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4030 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
4031 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
4032 
4033 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
4034 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
4035 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
4036 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4037 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4038 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4039 
4040 /* Register: PDM_ENABLE */
4041 /* Description: PDM module enable register */
4042 
4043 /* Bit 0 : Enable or disable PDM module */
4044 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
4045 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
4046 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
4047 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
4048 
4049 /* Register: PDM_PDMCLKCTRL */
4050 /* Description: PDM clock generator control */
4051 
4052 /* Bits 31..0 : PDM_CLK frequency */
4053 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
4054 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
4055 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
4056 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
4057 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
4058 
4059 /* Register: PDM_MODE */
4060 /* Description: Defines the routing of the connected PDM microphones' signals */
4061 
4062 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
4063 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
4064 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
4065 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
4066 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
4067 
4068 /* Bit 0 : Mono or stereo operation */
4069 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
4070 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
4071 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
4072 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
4073 
4074 /* Register: PDM_GAINL */
4075 /* Description: Left output gain adjustment */
4076 
4077 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
4078 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
4079 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
4080 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
4081 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
4082 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
4083 
4084 /* Register: PDM_GAINR */
4085 /* Description: Right output gain adjustment */
4086 
4087 /* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
4088 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
4089 #define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
4090 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
4091 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
4092 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
4093 
4094 /* Register: PDM_PSEL_CLK */
4095 /* Description: Pin number configuration for PDM CLK signal */
4096 
4097 /* Bit 31 : Connection */
4098 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4099 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4100 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
4101 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
4102 
4103 /* Bits 4..0 : Pin number */
4104 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
4105 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
4106 
4107 /* Register: PDM_PSEL_DIN */
4108 /* Description: Pin number configuration for PDM DIN signal */
4109 
4110 /* Bit 31 : Connection */
4111 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4112 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4113 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
4114 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
4115 
4116 /* Bits 4..0 : Pin number */
4117 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
4118 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
4119 
4120 /* Register: PDM_SAMPLE_PTR */
4121 /* Description: RAM address pointer to write samples to with EasyDMA */
4122 
4123 /* Bits 31..0 : Address to write PDM samples to over DMA */
4124 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
4125 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
4126 
4127 /* Register: PDM_SAMPLE_MAXCNT */
4128 /* Description: Number of samples to allocate memory for in EasyDMA mode */
4129 
4130 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
4131 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
4132 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
4133 
4134 
4135 /* Peripheral: POWER */
4136 /* Description: Power control */
4137 
4138 /* Register: POWER_TASKS_CONSTLAT */
4139 /* Description: Enable Constant Latency mode */
4140 
4141 /* Bit 0 : Enable Constant Latency mode */
4142 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */
4143 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */
4144 #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */
4145 
4146 /* Register: POWER_TASKS_LOWPWR */
4147 /* Description: Enable Low-power mode (variable latency) */
4148 
4149 /* Bit 0 : Enable Low-power mode (variable latency) */
4150 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */
4151 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */
4152 #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */
4153 
4154 /* Register: POWER_EVENTS_POFWARN */
4155 /* Description: Power failure warning */
4156 
4157 /* Bit 0 : Power failure warning */
4158 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */
4159 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */
4160 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */
4161 #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */
4162 
4163 /* Register: POWER_EVENTS_SLEEPENTER */
4164 /* Description: CPU entered WFI/WFE sleep */
4165 
4166 /* Bit 0 : CPU entered WFI/WFE sleep */
4167 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */
4168 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */
4169 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */
4170 #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */
4171 
4172 /* Register: POWER_EVENTS_SLEEPEXIT */
4173 /* Description: CPU exited WFI/WFE sleep */
4174 
4175 /* Bit 0 : CPU exited WFI/WFE sleep */
4176 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */
4177 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */
4178 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */
4179 #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */
4180 
4181 /* Register: POWER_INTENSET */
4182 /* Description: Enable interrupt */
4183 
4184 /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */
4185 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
4186 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
4187 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4188 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4189 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
4190 
4191 /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */
4192 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
4193 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
4194 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4195 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4196 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
4197 
4198 /* Bit 2 : Write '1' to enable interrupt for event POFWARN */
4199 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4200 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
4201 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4202 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4203 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
4204 
4205 /* Register: POWER_INTENCLR */
4206 /* Description: Disable interrupt */
4207 
4208 /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */
4209 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
4210 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
4211 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4212 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
4213 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
4214 
4215 /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */
4216 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
4217 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
4218 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4219 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
4220 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
4221 
4222 /* Bit 2 : Write '1' to disable interrupt for event POFWARN */
4223 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
4224 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
4225 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4226 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
4227 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
4228 
4229 /* Register: POWER_RESETREAS */
4230 /* Description: Reset reason */
4231 
4232 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
4233 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
4234 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
4235 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
4236 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
4237 
4238 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
4239 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
4240 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
4241 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
4242 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
4243 
4244 /* Bit 3 : Reset from CPU lock-up detected */
4245 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
4246 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
4247 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
4248 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
4249 
4250 /* Bit 2 : Reset from soft reset detected */
4251 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
4252 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
4253 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
4254 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
4255 
4256 /* Bit 1 : Reset from watchdog detected */
4257 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
4258 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
4259 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
4260 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
4261 
4262 /* Bit 0 : Reset from pin-reset detected */
4263 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
4264 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
4265 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
4266 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
4267 
4268 /* Register: POWER_SYSTEMOFF */
4269 /* Description: System OFF register */
4270 
4271 /* Bit 0 : Enable System OFF mode */
4272 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
4273 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
4274 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
4275 
4276 /* Register: POWER_POFCON */
4277 /* Description: Power failure comparator configuration */
4278 
4279 /* Bits 4..1 : Power failure comparator threshold setting */
4280 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
4281 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
4282 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
4283 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
4284 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
4285 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
4286 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
4287 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
4288 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
4289 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
4290 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
4291 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
4292 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
4293 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
4294 
4295 /* Bit 0 : Enable or disable power failure comparator */
4296 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
4297 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
4298 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
4299 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
4300 
4301 /* Register: POWER_GPREGRET */
4302 /* Description: General purpose retention register */
4303 
4304 /* Bits 7..0 : General purpose retention register */
4305 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
4306 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
4307 
4308 /* Register: POWER_GPREGRET2 */
4309 /* Description: General purpose retention register */
4310 
4311 /* Bits 7..0 : General purpose retention register */
4312 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
4313 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
4314 
4315 /* Register: POWER_DCDCEN */
4316 /* Description: DC/DC enable register */
4317 
4318 /* Bit 0 : Enable or disable DC/DC converter */
4319 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
4320 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
4321 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
4322 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
4323 
4324 /* Register: POWER_RAM_POWER */
4325 /* Description: Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. */
4326 
4327 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
4328 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
4329 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
4330 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
4331 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
4332 
4333 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
4334 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
4335 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
4336 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
4337 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
4338 
4339 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
4340 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
4341 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
4342 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
4343 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
4344 
4345 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
4346 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
4347 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
4348 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
4349 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
4350 
4351 /* Register: POWER_RAM_POWERSET */
4352 /* Description: Description cluster: RAMn power control set register */
4353 
4354 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
4355 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
4356 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
4357 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
4358 
4359 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
4360 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
4361 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
4362 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
4363 
4364 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
4365 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
4366 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
4367 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
4368 
4369 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
4370 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
4371 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
4372 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
4373 
4374 /* Register: POWER_RAM_POWERCLR */
4375 /* Description: Description cluster: RAMn power control clear register */
4376 
4377 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
4378 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
4379 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
4380 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
4381 
4382 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
4383 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
4384 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
4385 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
4386 
4387 /* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */
4388 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
4389 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
4390 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
4391 
4392 /* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */
4393 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
4394 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
4395 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
4396 
4397 
4398 /* Peripheral: PPI */
4399 /* Description: Programmable Peripheral Interconnect */
4400 
4401 /* Register: PPI_TASKS_CHG_EN */
4402 /* Description: Description cluster: Enable channel group n */
4403 
4404 /* Bit 0 : Enable channel group n */
4405 #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
4406 #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
4407 #define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
4408 
4409 /* Register: PPI_TASKS_CHG_DIS */
4410 /* Description: Description cluster: Disable channel group n */
4411 
4412 /* Bit 0 : Disable channel group n */
4413 #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
4414 #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
4415 #define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
4416 
4417 /* Register: PPI_CHEN */
4418 /* Description: Channel enable register */
4419 
4420 /* Bit 31 : Enable or disable channel 31 */
4421 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
4422 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
4423 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
4424 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
4425 
4426 /* Bit 30 : Enable or disable channel 30 */
4427 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
4428 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
4429 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
4430 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
4431 
4432 /* Bit 29 : Enable or disable channel 29 */
4433 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
4434 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
4435 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
4436 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
4437 
4438 /* Bit 28 : Enable or disable channel 28 */
4439 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
4440 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
4441 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
4442 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
4443 
4444 /* Bit 27 : Enable or disable channel 27 */
4445 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
4446 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
4447 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
4448 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
4449 
4450 /* Bit 26 : Enable or disable channel 26 */
4451 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
4452 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
4453 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
4454 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
4455 
4456 /* Bit 25 : Enable or disable channel 25 */
4457 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
4458 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
4459 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
4460 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
4461 
4462 /* Bit 24 : Enable or disable channel 24 */
4463 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
4464 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
4465 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
4466 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
4467 
4468 /* Bit 23 : Enable or disable channel 23 */
4469 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
4470 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
4471 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
4472 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
4473 
4474 /* Bit 22 : Enable or disable channel 22 */
4475 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
4476 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
4477 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
4478 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
4479 
4480 /* Bit 21 : Enable or disable channel 21 */
4481 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
4482 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
4483 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
4484 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
4485 
4486 /* Bit 20 : Enable or disable channel 20 */
4487 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
4488 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
4489 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
4490 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
4491 
4492 /* Bit 19 : Enable or disable channel 19 */
4493 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
4494 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
4495 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
4496 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
4497 
4498 /* Bit 18 : Enable or disable channel 18 */
4499 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
4500 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
4501 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
4502 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
4503 
4504 /* Bit 17 : Enable or disable channel 17 */
4505 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
4506 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
4507 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
4508 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
4509 
4510 /* Bit 16 : Enable or disable channel 16 */
4511 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
4512 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
4513 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
4514 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
4515 
4516 /* Bit 15 : Enable or disable channel 15 */
4517 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
4518 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
4519 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
4520 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
4521 
4522 /* Bit 14 : Enable or disable channel 14 */
4523 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
4524 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
4525 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
4526 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
4527 
4528 /* Bit 13 : Enable or disable channel 13 */
4529 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
4530 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
4531 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
4532 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
4533 
4534 /* Bit 12 : Enable or disable channel 12 */
4535 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
4536 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
4537 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
4538 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
4539 
4540 /* Bit 11 : Enable or disable channel 11 */
4541 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
4542 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
4543 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
4544 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
4545 
4546 /* Bit 10 : Enable or disable channel 10 */
4547 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
4548 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
4549 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
4550 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
4551 
4552 /* Bit 9 : Enable or disable channel 9 */
4553 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
4554 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
4555 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
4556 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
4557 
4558 /* Bit 8 : Enable or disable channel 8 */
4559 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
4560 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
4561 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
4562 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
4563 
4564 /* Bit 7 : Enable or disable channel 7 */
4565 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
4566 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
4567 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
4568 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
4569 
4570 /* Bit 6 : Enable or disable channel 6 */
4571 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
4572 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
4573 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
4574 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
4575 
4576 /* Bit 5 : Enable or disable channel 5 */
4577 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
4578 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
4579 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
4580 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
4581 
4582 /* Bit 4 : Enable or disable channel 4 */
4583 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
4584 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
4585 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
4586 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
4587 
4588 /* Bit 3 : Enable or disable channel 3 */
4589 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
4590 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
4591 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
4592 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
4593 
4594 /* Bit 2 : Enable or disable channel 2 */
4595 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
4596 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
4597 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
4598 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
4599 
4600 /* Bit 1 : Enable or disable channel 1 */
4601 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
4602 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
4603 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
4604 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
4605 
4606 /* Bit 0 : Enable or disable channel 0 */
4607 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
4608 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
4609 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
4610 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
4611 
4612 /* Register: PPI_CHENSET */
4613 /* Description: Channel enable set register */
4614 
4615 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
4616 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
4617 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
4618 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
4619 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
4620 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
4621 
4622 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
4623 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
4624 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
4625 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
4626 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
4627 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
4628 
4629 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
4630 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
4631 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
4632 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
4633 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
4634 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
4635 
4636 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
4637 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
4638 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
4639 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
4640 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
4641 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
4642 
4643 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
4644 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
4645 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
4646 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
4647 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
4648 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
4649 
4650 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
4651 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
4652 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
4653 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
4654 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
4655 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
4656 
4657 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
4658 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
4659 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
4660 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
4661 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
4662 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
4663 
4664 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
4665 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
4666 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
4667 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
4668 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
4669 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
4670 
4671 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
4672 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
4673 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
4674 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
4675 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
4676 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
4677 
4678 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
4679 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
4680 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
4681 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
4682 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
4683 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
4684 
4685 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
4686 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
4687 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
4688 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
4689 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
4690 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
4691 
4692 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
4693 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
4694 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
4695 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
4696 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
4697 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
4698 
4699 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
4700 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
4701 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
4702 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
4703 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
4704 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
4705 
4706 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
4707 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
4708 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
4709 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
4710 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
4711 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
4712 
4713 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
4714 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
4715 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
4716 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
4717 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
4718 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
4719 
4720 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
4721 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
4722 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
4723 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
4724 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
4725 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
4726 
4727 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
4728 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
4729 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
4730 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
4731 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
4732 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
4733 
4734 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
4735 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
4736 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
4737 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
4738 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
4739 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
4740 
4741 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
4742 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
4743 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
4744 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
4745 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
4746 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
4747 
4748 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
4749 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
4750 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
4751 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
4752 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
4753 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
4754 
4755 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
4756 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
4757 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
4758 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
4759 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
4760 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
4761 
4762 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
4763 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
4764 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
4765 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
4766 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
4767 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
4768 
4769 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
4770 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
4771 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
4772 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
4773 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
4774 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
4775 
4776 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
4777 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
4778 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
4779 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
4780 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
4781 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
4782 
4783 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
4784 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
4785 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
4786 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
4787 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
4788 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
4789 
4790 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
4791 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
4792 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
4793 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
4794 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
4795 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
4796 
4797 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
4798 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
4799 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
4800 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
4801 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
4802 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
4803 
4804 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
4805 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
4806 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
4807 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
4808 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
4809 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
4810 
4811 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
4812 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
4813 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
4814 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
4815 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
4816 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
4817 
4818 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
4819 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
4820 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
4821 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
4822 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
4823 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
4824 
4825 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
4826 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
4827 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
4828 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
4829 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
4830 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
4831 
4832 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
4833 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
4834 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
4835 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
4836 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
4837 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
4838 
4839 /* Register: PPI_CHENCLR */
4840 /* Description: Channel enable clear register */
4841 
4842 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
4843 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
4844 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
4845 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
4846 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
4847 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
4848 
4849 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
4850 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
4851 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
4852 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
4853 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
4854 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
4855 
4856 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
4857 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
4858 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
4859 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
4860 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
4861 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
4862 
4863 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
4864 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
4865 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
4866 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
4867 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
4868 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
4869 
4870 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
4871 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
4872 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
4873 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
4874 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
4875 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
4876 
4877 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
4878 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
4879 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
4880 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
4881 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
4882 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
4883 
4884 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
4885 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
4886 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
4887 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
4888 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
4889 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
4890 
4891 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
4892 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
4893 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
4894 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
4895 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
4896 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
4897 
4898 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
4899 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
4900 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
4901 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
4902 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
4903 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
4904 
4905 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
4906 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
4907 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
4908 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
4909 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
4910 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
4911 
4912 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
4913 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
4914 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
4915 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
4916 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
4917 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
4918 
4919 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
4920 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
4921 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
4922 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
4923 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
4924 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
4925 
4926 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
4927 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
4928 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
4929 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
4930 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
4931 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
4932 
4933 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
4934 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
4935 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
4936 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
4937 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
4938 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
4939 
4940 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
4941 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
4942 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
4943 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
4944 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
4945 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
4946 
4947 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
4948 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
4949 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
4950 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
4951 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
4952 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
4953 
4954 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
4955 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
4956 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
4957 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
4958 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
4959 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
4960 
4961 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
4962 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
4963 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
4964 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
4965 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
4966 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
4967 
4968 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
4969 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
4970 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
4971 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
4972 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
4973 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
4974 
4975 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
4976 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
4977 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
4978 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
4979 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
4980 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
4981 
4982 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
4983 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
4984 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
4985 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
4986 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
4987 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
4988 
4989 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
4990 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
4991 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
4992 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
4993 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
4994 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
4995 
4996 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
4997 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
4998 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
4999 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
5000 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
5001 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
5002 
5003 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
5004 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
5005 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
5006 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
5007 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
5008 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
5009 
5010 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
5011 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
5012 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
5013 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
5014 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
5015 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
5016 
5017 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
5018 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
5019 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
5020 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
5021 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
5022 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
5023 
5024 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
5025 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
5026 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
5027 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
5028 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
5029 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
5030 
5031 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
5032 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
5033 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
5034 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
5035 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
5036 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
5037 
5038 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
5039 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
5040 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
5041 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
5042 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
5043 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
5044 
5045 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
5046 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
5047 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
5048 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
5049 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
5050 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
5051 
5052 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
5053 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
5054 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
5055 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
5056 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
5057 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
5058 
5059 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
5060 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
5061 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
5062 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
5063 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
5064 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
5065 
5066 /* Register: PPI_CH_EEP */
5067 /* Description: Description cluster: Channel n event end-point */
5068 
5069 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
5070 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
5071 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
5072 
5073 /* Register: PPI_CH_TEP */
5074 /* Description: Description cluster: Channel n task end-point */
5075 
5076 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
5077 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
5078 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
5079 
5080 /* Register: PPI_CHG */
5081 /* Description: Description collection: Channel group n */
5082 
5083 /* Bit 31 : Include or exclude channel 31 */
5084 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
5085 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
5086 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
5087 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
5088 
5089 /* Bit 30 : Include or exclude channel 30 */
5090 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
5091 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
5092 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
5093 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
5094 
5095 /* Bit 29 : Include or exclude channel 29 */
5096 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
5097 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
5098 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
5099 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
5100 
5101 /* Bit 28 : Include or exclude channel 28 */
5102 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
5103 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
5104 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
5105 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
5106 
5107 /* Bit 27 : Include or exclude channel 27 */
5108 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
5109 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
5110 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
5111 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
5112 
5113 /* Bit 26 : Include or exclude channel 26 */
5114 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
5115 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
5116 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
5117 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
5118 
5119 /* Bit 25 : Include or exclude channel 25 */
5120 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
5121 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
5122 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
5123 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
5124 
5125 /* Bit 24 : Include or exclude channel 24 */
5126 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
5127 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
5128 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
5129 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
5130 
5131 /* Bit 23 : Include or exclude channel 23 */
5132 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
5133 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
5134 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
5135 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
5136 
5137 /* Bit 22 : Include or exclude channel 22 */
5138 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
5139 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
5140 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
5141 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
5142 
5143 /* Bit 21 : Include or exclude channel 21 */
5144 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
5145 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
5146 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
5147 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
5148 
5149 /* Bit 20 : Include or exclude channel 20 */
5150 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
5151 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
5152 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
5153 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
5154 
5155 /* Bit 19 : Include or exclude channel 19 */
5156 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
5157 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
5158 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
5159 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
5160 
5161 /* Bit 18 : Include or exclude channel 18 */
5162 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
5163 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
5164 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
5165 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
5166 
5167 /* Bit 17 : Include or exclude channel 17 */
5168 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
5169 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
5170 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
5171 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
5172 
5173 /* Bit 16 : Include or exclude channel 16 */
5174 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
5175 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
5176 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
5177 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
5178 
5179 /* Bit 15 : Include or exclude channel 15 */
5180 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
5181 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
5182 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
5183 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
5184 
5185 /* Bit 14 : Include or exclude channel 14 */
5186 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
5187 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
5188 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
5189 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
5190 
5191 /* Bit 13 : Include or exclude channel 13 */
5192 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
5193 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
5194 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
5195 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
5196 
5197 /* Bit 12 : Include or exclude channel 12 */
5198 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
5199 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
5200 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
5201 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
5202 
5203 /* Bit 11 : Include or exclude channel 11 */
5204 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
5205 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
5206 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
5207 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
5208 
5209 /* Bit 10 : Include or exclude channel 10 */
5210 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
5211 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
5212 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
5213 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
5214 
5215 /* Bit 9 : Include or exclude channel 9 */
5216 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
5217 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
5218 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
5219 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
5220 
5221 /* Bit 8 : Include or exclude channel 8 */
5222 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
5223 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
5224 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
5225 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
5226 
5227 /* Bit 7 : Include or exclude channel 7 */
5228 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
5229 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
5230 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
5231 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
5232 
5233 /* Bit 6 : Include or exclude channel 6 */
5234 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
5235 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
5236 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
5237 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
5238 
5239 /* Bit 5 : Include or exclude channel 5 */
5240 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
5241 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
5242 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
5243 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
5244 
5245 /* Bit 4 : Include or exclude channel 4 */
5246 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
5247 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
5248 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
5249 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
5250 
5251 /* Bit 3 : Include or exclude channel 3 */
5252 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
5253 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
5254 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
5255 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
5256 
5257 /* Bit 2 : Include or exclude channel 2 */
5258 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
5259 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
5260 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
5261 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
5262 
5263 /* Bit 1 : Include or exclude channel 1 */
5264 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
5265 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
5266 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
5267 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
5268 
5269 /* Bit 0 : Include or exclude channel 0 */
5270 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
5271 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
5272 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
5273 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
5274 
5275 /* Register: PPI_FORK_TEP */
5276 /* Description: Description cluster: Channel n task end-point */
5277 
5278 /* Bits 31..0 : Pointer to task register */
5279 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
5280 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
5281 
5282 
5283 /* Peripheral: PWM */
5284 /* Description: Pulse width modulation unit */
5285 
5286 /* Register: PWM_TASKS_STOP */
5287 /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
5288 
5289 /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */
5290 #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5291 #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5292 #define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5293 
5294 /* Register: PWM_TASKS_SEQSTART */
5295 /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
5296 
5297 /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */
5298 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */
5299 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */
5300 #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */
5301 
5302 /* Register: PWM_TASKS_NEXTSTEP */
5303 /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
5304 
5305 /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */
5306 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */
5307 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */
5308 #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */
5309 
5310 /* Register: PWM_EVENTS_STOPPED */
5311 /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */
5312 
5313 /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */
5314 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
5315 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
5316 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
5317 #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
5318 
5319 /* Register: PWM_EVENTS_SEQSTARTED */
5320 /* Description: Description collection: First PWM period started on sequence n */
5321 
5322 /* Bit 0 : First PWM period started on sequence n */
5323 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */
5324 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */
5325 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */
5326 #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */
5327 
5328 /* Register: PWM_EVENTS_SEQEND */
5329 /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
5330 
5331 /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */
5332 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */
5333 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */
5334 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */
5335 #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */
5336 
5337 /* Register: PWM_EVENTS_PWMPERIODEND */
5338 /* Description: Emitted at the end of each PWM period */
5339 
5340 /* Bit 0 : Emitted at the end of each PWM period */
5341 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */
5342 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */
5343 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */
5344 #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */
5345 
5346 /* Register: PWM_EVENTS_LOOPSDONE */
5347 /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */
5348 
5349 /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */
5350 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */
5351 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */
5352 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */
5353 #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */
5354 
5355 /* Register: PWM_SHORTS */
5356 /* Description: Shortcuts between local events and tasks */
5357 
5358 /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */
5359 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
5360 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
5361 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
5362 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
5363 
5364 /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */
5365 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
5366 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
5367 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
5368 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
5369 
5370 /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */
5371 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
5372 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
5373 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
5374 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
5375 
5376 /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */
5377 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
5378 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
5379 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
5380 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
5381 
5382 /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */
5383 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
5384 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
5385 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
5386 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
5387 
5388 /* Register: PWM_INTEN */
5389 /* Description: Enable or disable interrupt */
5390 
5391 /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */
5392 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
5393 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
5394 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
5395 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
5396 
5397 /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */
5398 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
5399 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
5400 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
5401 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
5402 
5403 /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */
5404 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
5405 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
5406 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
5407 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
5408 
5409 /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */
5410 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
5411 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
5412 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
5413 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
5414 
5415 /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */
5416 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
5417 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
5418 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
5419 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
5420 
5421 /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */
5422 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5423 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
5424 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
5425 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
5426 
5427 /* Bit 1 : Enable or disable interrupt for event STOPPED */
5428 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5429 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5430 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
5431 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
5432 
5433 /* Register: PWM_INTENSET */
5434 /* Description: Enable interrupt */
5435 
5436 /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */
5437 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
5438 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
5439 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5440 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5441 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
5442 
5443 /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */
5444 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
5445 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
5446 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5447 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5448 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
5449 
5450 /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */
5451 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
5452 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
5453 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5454 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5455 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
5456 
5457 /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */
5458 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
5459 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
5460 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5461 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5462 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
5463 
5464 /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */
5465 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
5466 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
5467 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5468 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5469 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
5470 
5471 /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */
5472 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5473 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
5474 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5475 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5476 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
5477 
5478 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
5479 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5480 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5481 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5482 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5483 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
5484 
5485 /* Register: PWM_INTENCLR */
5486 /* Description: Disable interrupt */
5487 
5488 /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */
5489 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
5490 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
5491 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5492 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
5493 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
5494 
5495 /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */
5496 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
5497 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
5498 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5499 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
5500 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
5501 
5502 /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */
5503 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
5504 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
5505 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5506 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
5507 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
5508 
5509 /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */
5510 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
5511 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
5512 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5513 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
5514 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
5515 
5516 /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */
5517 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
5518 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
5519 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5520 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
5521 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
5522 
5523 /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */
5524 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
5525 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
5526 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5527 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
5528 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
5529 
5530 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
5531 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
5532 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5533 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5534 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5535 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
5536 
5537 /* Register: PWM_ENABLE */
5538 /* Description: PWM module enable register */
5539 
5540 /* Bit 0 : Enable or disable PWM module */
5541 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5542 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5543 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
5544 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
5545 
5546 /* Register: PWM_MODE */
5547 /* Description: Selects operating mode of the wave counter */
5548 
5549 /* Bit 0 : Selects up mode or up-and-down mode for the counter */
5550 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
5551 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
5552 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */
5553 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */
5554 
5555 /* Register: PWM_COUNTERTOP */
5556 /* Description: Value up to which the pulse generator counter counts */
5557 
5558 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */
5559 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
5560 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
5561 
5562 /* Register: PWM_PRESCALER */
5563 /* Description: Configuration for PWM_CLK */
5564 
5565 /* Bits 2..0 : Prescaler of PWM_CLK */
5566 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
5567 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
5568 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */
5569 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */
5570 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */
5571 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */
5572 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */
5573 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */
5574 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */
5575 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */
5576 
5577 /* Register: PWM_DECODER */
5578 /* Description: Configuration of the decoder */
5579 
5580 /* Bit 8 : Selects source for advancing the active sequence */
5581 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
5582 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
5583 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
5584 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
5585 
5586 /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
5587 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
5588 #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
5589 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
5590 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
5591 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
5592 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
5593 
5594 /* Register: PWM_LOOP */
5595 /* Description: Number of playbacks of a loop */
5596 
5597 /* Bits 15..0 : Number of playbacks of pattern cycles */
5598 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
5599 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
5600 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
5601 
5602 /* Register: PWM_SEQ_PTR */
5603 /* Description: Description cluster: Beginning address in RAM of this sequence */
5604 
5605 /* Bits 31..0 : Beginning address in RAM of this sequence */
5606 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
5607 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
5608 
5609 /* Register: PWM_SEQ_CNT */
5610 /* Description: Description cluster: Number of values (duty cycles) in this sequence */
5611 
5612 /* Bits 14..0 : Number of values (duty cycles) in this sequence */
5613 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
5614 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
5615 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
5616 
5617 /* Register: PWM_SEQ_REFRESH */
5618 /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */
5619 
5620 /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
5621 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
5622 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
5623 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
5624 
5625 /* Register: PWM_SEQ_ENDDELAY */
5626 /* Description: Description cluster: Time added after the sequence */
5627 
5628 /* Bits 23..0 : Time added after the sequence in PWM periods */
5629 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
5630 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
5631 
5632 /* Register: PWM_PSEL_OUT */
5633 /* Description: Description collection: Output pin select for PWM channel n */
5634 
5635 /* Bit 31 : Connection */
5636 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
5637 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
5638 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
5639 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
5640 
5641 /* Bits 4..0 : Pin number */
5642 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
5643 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
5644 
5645 
5646 /* Peripheral: QDEC */
5647 /* Description: Quadrature Decoder */
5648 
5649 /* Register: QDEC_TASKS_START */
5650 /* Description: Task starting the quadrature decoder */
5651 
5652 /* Bit 0 : Task starting the quadrature decoder */
5653 #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5654 #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5655 #define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5656 
5657 /* Register: QDEC_TASKS_STOP */
5658 /* Description: Task stopping the quadrature decoder */
5659 
5660 /* Bit 0 : Task stopping the quadrature decoder */
5661 #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5662 #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5663 #define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5664 
5665 /* Register: QDEC_TASKS_READCLRACC */
5666 /* Description: Read and clear ACC and ACCDBL */
5667 
5668 /* Bit 0 : Read and clear ACC and ACCDBL */
5669 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */
5670 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */
5671 #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */
5672 
5673 /* Register: QDEC_TASKS_RDCLRACC */
5674 /* Description: Read and clear ACC */
5675 
5676 /* Bit 0 : Read and clear ACC */
5677 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */
5678 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */
5679 #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */
5680 
5681 /* Register: QDEC_TASKS_RDCLRDBL */
5682 /* Description: Read and clear ACCDBL */
5683 
5684 /* Bit 0 : Read and clear ACCDBL */
5685 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */
5686 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */
5687 #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */
5688 
5689 /* Register: QDEC_EVENTS_SAMPLERDY */
5690 /* Description: Event being generated for every new sample value written to the SAMPLE register */
5691 
5692 /* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */
5693 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */
5694 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */
5695 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */
5696 #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */
5697 
5698 /* Register: QDEC_EVENTS_REPORTRDY */
5699 /* Description: Non-null report ready */
5700 
5701 /* Bit 0 : Non-null report ready */
5702 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */
5703 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */
5704 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */
5705 #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */
5706 
5707 /* Register: QDEC_EVENTS_ACCOF */
5708 /* Description: ACC or ACCDBL register overflow */
5709 
5710 /* Bit 0 : ACC or ACCDBL register overflow */
5711 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */
5712 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */
5713 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */
5714 #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */
5715 
5716 /* Register: QDEC_EVENTS_DBLRDY */
5717 /* Description: Double displacement(s) detected */
5718 
5719 /* Bit 0 : Double displacement(s) detected */
5720 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */
5721 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */
5722 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */
5723 #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */
5724 
5725 /* Register: QDEC_EVENTS_STOPPED */
5726 /* Description: QDEC has been stopped */
5727 
5728 /* Bit 0 : QDEC has been stopped */
5729 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
5730 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
5731 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
5732 #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
5733 
5734 /* Register: QDEC_SHORTS */
5735 /* Description: Shortcuts between local events and tasks */
5736 
5737 /* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */
5738 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
5739 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
5740 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
5741 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
5742 
5743 /* Bit 5 : Shortcut between event DBLRDY and task STOP */
5744 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
5745 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
5746 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
5747 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
5748 
5749 /* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */
5750 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
5751 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
5752 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
5753 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
5754 
5755 /* Bit 3 : Shortcut between event REPORTRDY and task STOP */
5756 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
5757 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
5758 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
5759 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
5760 
5761 /* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */
5762 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
5763 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
5764 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
5765 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
5766 
5767 /* Bit 1 : Shortcut between event SAMPLERDY and task STOP */
5768 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
5769 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
5770 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
5771 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
5772 
5773 /* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */
5774 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
5775 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
5776 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
5777 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
5778 
5779 /* Register: QDEC_INTENSET */
5780 /* Description: Enable interrupt */
5781 
5782 /* Bit 4 : Write '1' to enable interrupt for event STOPPED */
5783 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
5784 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5785 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5786 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5787 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
5788 
5789 /* Bit 3 : Write '1' to enable interrupt for event DBLRDY */
5790 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
5791 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
5792 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
5793 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
5794 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
5795 
5796 /* Bit 2 : Write '1' to enable interrupt for event ACCOF */
5797 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
5798 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
5799 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
5800 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
5801 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
5802 
5803 /* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */
5804 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
5805 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
5806 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
5807 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
5808 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
5809 
5810 /* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */
5811 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
5812 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
5813 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
5814 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
5815 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
5816 
5817 /* Register: QDEC_INTENCLR */
5818 /* Description: Disable interrupt */
5819 
5820 /* Bit 4 : Write '1' to disable interrupt for event STOPPED */
5821 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
5822 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
5823 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5824 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
5825 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
5826 
5827 /* Bit 3 : Write '1' to disable interrupt for event DBLRDY */
5828 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
5829 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
5830 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
5831 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
5832 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
5833 
5834 /* Bit 2 : Write '1' to disable interrupt for event ACCOF */
5835 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
5836 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
5837 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
5838 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
5839 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
5840 
5841 /* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */
5842 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
5843 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
5844 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
5845 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
5846 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
5847 
5848 /* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */
5849 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
5850 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
5851 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
5852 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
5853 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
5854 
5855 /* Register: QDEC_ENABLE */
5856 /* Description: Enable the quadrature decoder */
5857 
5858 /* Bit 0 : Enable or disable the quadrature decoder */
5859 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
5860 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
5861 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
5862 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
5863 
5864 /* Register: QDEC_LEDPOL */
5865 /* Description: LED output pin polarity */
5866 
5867 /* Bit 0 : LED output pin polarity */
5868 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
5869 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
5870 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
5871 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
5872 
5873 /* Register: QDEC_SAMPLEPER */
5874 /* Description: Sample period */
5875 
5876 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
5877 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
5878 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
5879 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
5880 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
5881 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
5882 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
5883 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
5884 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
5885 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
5886 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
5887 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
5888 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
5889 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
5890 
5891 /* Register: QDEC_SAMPLE */
5892 /* Description: Motion sample value */
5893 
5894 /* Bits 31..0 : Last motion sample */
5895 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
5896 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
5897 
5898 /* Register: QDEC_REPORTPER */
5899 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
5900 
5901 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
5902 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
5903 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
5904 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
5905 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
5906 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
5907 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
5908 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
5909 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
5910 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
5911 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
5912 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
5913 
5914 /* Register: QDEC_ACC */
5915 /* Description: Register accumulating the valid transitions */
5916 
5917 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
5918 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
5919 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
5920 
5921 /* Register: QDEC_ACCREAD */
5922 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
5923 
5924 /* Bits 31..0 : Snapshot of the ACC register. */
5925 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
5926 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
5927 
5928 /* Register: QDEC_PSEL_LED */
5929 /* Description: Pin select for LED signal */
5930 
5931 /* Bit 31 : Connection */
5932 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
5933 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
5934 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
5935 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
5936 
5937 /* Bits 4..0 : Pin number */
5938 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
5939 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
5940 
5941 /* Register: QDEC_PSEL_A */
5942 /* Description: Pin select for A signal */
5943 
5944 /* Bit 31 : Connection */
5945 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
5946 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
5947 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
5948 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
5949 
5950 /* Bits 4..0 : Pin number */
5951 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
5952 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
5953 
5954 /* Register: QDEC_PSEL_B */
5955 /* Description: Pin select for B signal */
5956 
5957 /* Bit 31 : Connection */
5958 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
5959 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
5960 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
5961 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
5962 
5963 /* Bits 4..0 : Pin number */
5964 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
5965 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
5966 
5967 /* Register: QDEC_DBFEN */
5968 /* Description: Enable input debounce filters */
5969 
5970 /* Bit 0 : Enable input debounce filters */
5971 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
5972 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
5973 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
5974 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
5975 
5976 /* Register: QDEC_LEDPRE */
5977 /* Description: Time period the LED is switched ON prior to sampling */
5978 
5979 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
5980 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
5981 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
5982 
5983 /* Register: QDEC_ACCDBL */
5984 /* Description: Register accumulating the number of detected double transitions */
5985 
5986 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
5987 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
5988 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
5989 
5990 /* Register: QDEC_ACCDBLREAD */
5991 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
5992 
5993 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
5994 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
5995 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
5996 
5997 
5998 /* Peripheral: RADIO */
5999 /* Description: 2.4 GHz Radio */
6000 
6001 /* Register: RADIO_TASKS_TXEN */
6002 /* Description: Enable RADIO in TX mode */
6003 
6004 /* Bit 0 : Enable RADIO in TX mode */
6005 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
6006 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
6007 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */
6008 
6009 /* Register: RADIO_TASKS_RXEN */
6010 /* Description: Enable RADIO in RX mode */
6011 
6012 /* Bit 0 : Enable RADIO in RX mode */
6013 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
6014 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
6015 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */
6016 
6017 /* Register: RADIO_TASKS_START */
6018 /* Description: Start RADIO */
6019 
6020 /* Bit 0 : Start RADIO */
6021 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6022 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6023 #define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6024 
6025 /* Register: RADIO_TASKS_STOP */
6026 /* Description: Stop RADIO */
6027 
6028 /* Bit 0 : Stop RADIO */
6029 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6030 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6031 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6032 
6033 /* Register: RADIO_TASKS_DISABLE */
6034 /* Description: Disable RADIO */
6035 
6036 /* Bit 0 : Disable RADIO */
6037 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
6038 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
6039 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
6040 
6041 /* Register: RADIO_TASKS_RSSISTART */
6042 /* Description: Start the RSSI and take one single sample of the receive signal strength. */
6043 
6044 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength. */
6045 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
6046 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
6047 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */
6048 
6049 /* Register: RADIO_TASKS_RSSISTOP */
6050 /* Description: Stop the RSSI measurement */
6051 
6052 /* Bit 0 : Stop the RSSI measurement */
6053 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
6054 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
6055 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */
6056 
6057 /* Register: RADIO_TASKS_BCSTART */
6058 /* Description: Start the bit counter */
6059 
6060 /* Bit 0 : Start the bit counter */
6061 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
6062 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
6063 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */
6064 
6065 /* Register: RADIO_TASKS_BCSTOP */
6066 /* Description: Stop the bit counter */
6067 
6068 /* Bit 0 : Stop the bit counter */
6069 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
6070 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
6071 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */
6072 
6073 /* Register: RADIO_EVENTS_READY */
6074 /* Description: RADIO has ramped up and is ready to be started */
6075 
6076 /* Bit 0 : RADIO has ramped up and is ready to be started */
6077 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
6078 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
6079 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
6080 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
6081 
6082 /* Register: RADIO_EVENTS_ADDRESS */
6083 /* Description: Address sent or received */
6084 
6085 /* Bit 0 : Address sent or received */
6086 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
6087 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
6088 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */
6089 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */
6090 
6091 /* Register: RADIO_EVENTS_PAYLOAD */
6092 /* Description: Packet payload sent or received */
6093 
6094 /* Bit 0 : Packet payload sent or received */
6095 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
6096 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
6097 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */
6098 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */
6099 
6100 /* Register: RADIO_EVENTS_END */
6101 /* Description: Packet sent or received */
6102 
6103 /* Bit 0 : Packet sent or received */
6104 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
6105 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
6106 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
6107 #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
6108 
6109 /* Register: RADIO_EVENTS_DISABLED */
6110 /* Description: RADIO has been disabled */
6111 
6112 /* Bit 0 : RADIO has been disabled */
6113 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
6114 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
6115 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */
6116 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */
6117 
6118 /* Register: RADIO_EVENTS_DEVMATCH */
6119 /* Description: A device address match occurred on the last received packet */
6120 
6121 /* Bit 0 : A device address match occurred on the last received packet */
6122 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
6123 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
6124 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */
6125 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */
6126 
6127 /* Register: RADIO_EVENTS_DEVMISS */
6128 /* Description: No device address match occurred on the last received packet */
6129 
6130 /* Bit 0 : No device address match occurred on the last received packet */
6131 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
6132 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
6133 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */
6134 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */
6135 
6136 /* Register: RADIO_EVENTS_RSSIEND */
6137 /* Description: Sampling of receive signal strength complete. */
6138 
6139 /* Bit 0 : Sampling of receive signal strength complete. */
6140 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
6141 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
6142 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */
6143 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */
6144 
6145 /* Register: RADIO_EVENTS_BCMATCH */
6146 /* Description: Bit counter reached bit count value. */
6147 
6148 /* Bit 0 : Bit counter reached bit count value. */
6149 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
6150 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
6151 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */
6152 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */
6153 
6154 /* Register: RADIO_EVENTS_CRCOK */
6155 /* Description: Packet received with CRC ok */
6156 
6157 /* Bit 0 : Packet received with CRC ok */
6158 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
6159 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
6160 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */
6161 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */
6162 
6163 /* Register: RADIO_EVENTS_CRCERROR */
6164 /* Description: Packet received with CRC error */
6165 
6166 /* Bit 0 : Packet received with CRC error */
6167 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
6168 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
6169 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */
6170 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */
6171 
6172 /* Register: RADIO_SHORTS */
6173 /* Description: Shortcuts between local events and tasks */
6174 
6175 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
6176 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
6177 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
6178 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
6179 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
6180 
6181 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
6182 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
6183 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
6184 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
6185 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
6186 
6187 /* Bit 5 : Shortcut between event END and task START */
6188 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
6189 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
6190 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
6191 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
6192 
6193 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
6194 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
6195 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
6196 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
6197 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
6198 
6199 /* Bit 3 : Shortcut between event DISABLED and task RXEN */
6200 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
6201 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
6202 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
6203 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
6204 
6205 /* Bit 2 : Shortcut between event DISABLED and task TXEN */
6206 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
6207 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
6208 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
6209 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
6210 
6211 /* Bit 1 : Shortcut between event END and task DISABLE */
6212 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
6213 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
6214 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
6215 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
6216 
6217 /* Bit 0 : Shortcut between event READY and task START */
6218 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
6219 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
6220 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
6221 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
6222 
6223 /* Register: RADIO_INTENSET */
6224 /* Description: Enable interrupt */
6225 
6226 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
6227 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
6228 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
6229 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
6230 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
6231 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
6232 
6233 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */
6234 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
6235 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
6236 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
6237 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
6238 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
6239 
6240 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
6241 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
6242 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
6243 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
6244 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
6245 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
6246 
6247 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
6248 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
6249 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
6250 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
6251 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
6252 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
6253 
6254 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
6255 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
6256 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
6257 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
6258 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
6259 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
6260 
6261 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
6262 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
6263 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
6264 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
6265 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
6266 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
6267 
6268 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */
6269 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
6270 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
6271 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
6272 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
6273 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
6274 
6275 /* Bit 3 : Write '1' to enable interrupt for event END */
6276 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
6277 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
6278 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6279 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6280 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
6281 
6282 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
6283 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
6284 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
6285 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
6286 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
6287 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
6288 
6289 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
6290 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
6291 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
6292 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
6293 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
6294 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
6295 
6296 /* Bit 0 : Write '1' to enable interrupt for event READY */
6297 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
6298 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
6299 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
6300 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
6301 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
6302 
6303 /* Register: RADIO_INTENCLR */
6304 /* Description: Disable interrupt */
6305 
6306 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
6307 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
6308 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
6309 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
6310 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
6311 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
6312 
6313 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */
6314 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
6315 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
6316 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
6317 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
6318 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
6319 
6320 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
6321 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
6322 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
6323 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
6324 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
6325 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
6326 
6327 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
6328 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
6329 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
6330 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
6331 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
6332 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
6333 
6334 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
6335 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
6336 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
6337 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
6338 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
6339 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
6340 
6341 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
6342 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
6343 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
6344 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
6345 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
6346 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
6347 
6348 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */
6349 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
6350 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
6351 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
6352 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
6353 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
6354 
6355 /* Bit 3 : Write '1' to disable interrupt for event END */
6356 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
6357 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
6358 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6359 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6360 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
6361 
6362 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
6363 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
6364 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
6365 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
6366 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
6367 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
6368 
6369 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
6370 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
6371 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
6372 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
6373 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
6374 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
6375 
6376 /* Bit 0 : Write '1' to disable interrupt for event READY */
6377 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
6378 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
6379 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
6380 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
6381 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
6382 
6383 /* Register: RADIO_CRCSTATUS */
6384 /* Description: CRC status */
6385 
6386 /* Bit 0 : CRC status of packet received */
6387 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
6388 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
6389 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
6390 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
6391 
6392 /* Register: RADIO_RXMATCH */
6393 /* Description: Received address */
6394 
6395 /* Bits 2..0 : Received address */
6396 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
6397 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
6398 
6399 /* Register: RADIO_RXCRC */
6400 /* Description: CRC field of previously received packet */
6401 
6402 /* Bits 23..0 : CRC field of previously received packet */
6403 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
6404 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
6405 
6406 /* Register: RADIO_DAI */
6407 /* Description: Device address match index */
6408 
6409 /* Bits 2..0 : Device address match index */
6410 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
6411 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
6412 
6413 /* Register: RADIO_PACKETPTR */
6414 /* Description: Packet pointer */
6415 
6416 /* Bits 31..0 : Packet pointer */
6417 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
6418 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
6419 
6420 /* Register: RADIO_FREQUENCY */
6421 /* Description: Frequency */
6422 
6423 /* Bit 8 : Channel map selection. */
6424 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
6425 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
6426 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
6427 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
6428 
6429 /* Bits 6..0 : Radio channel frequency */
6430 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
6431 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
6432 
6433 /* Register: RADIO_TXPOWER */
6434 /* Description: Output power */
6435 
6436 /* Bits 7..0 : RADIO output power. */
6437 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
6438 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
6439 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
6440 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
6441 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
6442 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
6443 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator -  -40 dBm */
6444 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
6445 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
6446 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
6447 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
6448 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
6449 
6450 /* Register: RADIO_MODE */
6451 /* Description: Data rate and modulation */
6452 
6453 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
6454 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
6455 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
6456 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
6457 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
6458 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
6459 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */
6460 
6461 /* Register: RADIO_PCNF0 */
6462 /* Description: Packet configuration register 0 */
6463 
6464 /* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
6465 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
6466 #define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
6467 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
6468 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
6469 
6470 /* Bit 20 : Include or exclude S1 field in RAM */
6471 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
6472 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
6473 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
6474 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
6475 
6476 /* Bits 19..16 : Length on air of S1 field in number of bits. */
6477 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
6478 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
6479 
6480 /* Bit 8 : Length on air of S0 field in number of bytes. */
6481 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
6482 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
6483 
6484 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */
6485 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
6486 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
6487 
6488 /* Register: RADIO_PCNF1 */
6489 /* Description: Packet configuration register 1 */
6490 
6491 /* Bit 25 : Enable or disable packet whitening */
6492 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
6493 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
6494 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
6495 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
6496 
6497 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
6498 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
6499 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
6500 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
6501 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
6502 
6503 /* Bits 18..16 : Base address length in number of bytes */
6504 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
6505 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
6506 
6507 /* Bits 15..8 : Static length in number of bytes */
6508 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
6509 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
6510 
6511 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
6512 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
6513 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
6514 
6515 /* Register: RADIO_BASE0 */
6516 /* Description: Base address 0 */
6517 
6518 /* Bits 31..0 : Base address 0 */
6519 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
6520 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
6521 
6522 /* Register: RADIO_BASE1 */
6523 /* Description: Base address 1 */
6524 
6525 /* Bits 31..0 : Base address 1 */
6526 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
6527 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
6528 
6529 /* Register: RADIO_PREFIX0 */
6530 /* Description: Prefixes bytes for logical addresses 0-3 */
6531 
6532 /* Bits 31..24 : Address prefix 3. */
6533 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
6534 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
6535 
6536 /* Bits 23..16 : Address prefix 2. */
6537 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
6538 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
6539 
6540 /* Bits 15..8 : Address prefix 1. */
6541 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
6542 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
6543 
6544 /* Bits 7..0 : Address prefix 0. */
6545 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
6546 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
6547 
6548 /* Register: RADIO_PREFIX1 */
6549 /* Description: Prefixes bytes for logical addresses 4-7 */
6550 
6551 /* Bits 31..24 : Address prefix 7. */
6552 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
6553 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
6554 
6555 /* Bits 23..16 : Address prefix 6. */
6556 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
6557 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
6558 
6559 /* Bits 15..8 : Address prefix 5. */
6560 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
6561 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
6562 
6563 /* Bits 7..0 : Address prefix 4. */
6564 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
6565 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
6566 
6567 /* Register: RADIO_TXADDRESS */
6568 /* Description: Transmit address select */
6569 
6570 /* Bits 2..0 : Transmit address select */
6571 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
6572 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
6573 
6574 /* Register: RADIO_RXADDRESSES */
6575 /* Description: Receive address select */
6576 
6577 /* Bit 7 : Enable or disable reception on logical address 7. */
6578 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
6579 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
6580 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
6581 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
6582 
6583 /* Bit 6 : Enable or disable reception on logical address 6. */
6584 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
6585 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
6586 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
6587 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
6588 
6589 /* Bit 5 : Enable or disable reception on logical address 5. */
6590 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
6591 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
6592 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
6593 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
6594 
6595 /* Bit 4 : Enable or disable reception on logical address 4. */
6596 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
6597 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
6598 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
6599 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
6600 
6601 /* Bit 3 : Enable or disable reception on logical address 3. */
6602 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
6603 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
6604 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
6605 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
6606 
6607 /* Bit 2 : Enable or disable reception on logical address 2. */
6608 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
6609 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
6610 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
6611 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
6612 
6613 /* Bit 1 : Enable or disable reception on logical address 1. */
6614 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
6615 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
6616 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
6617 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
6618 
6619 /* Bit 0 : Enable or disable reception on logical address 0. */
6620 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
6621 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
6622 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
6623 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
6624 
6625 /* Register: RADIO_CRCCNF */
6626 /* Description: CRC configuration */
6627 
6628 /* Bit 8 : Include or exclude packet address field out of CRC calculation. */
6629 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
6630 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
6631 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
6632 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
6633 
6634 /* Bits 1..0 : CRC length in number of bytes. */
6635 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
6636 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
6637 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
6638 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
6639 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
6640 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
6641 
6642 /* Register: RADIO_CRCPOLY */
6643 /* Description: CRC polynomial */
6644 
6645 /* Bits 23..0 : CRC polynomial */
6646 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
6647 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
6648 
6649 /* Register: RADIO_CRCINIT */
6650 /* Description: CRC initial value */
6651 
6652 /* Bits 23..0 : CRC initial value */
6653 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
6654 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
6655 
6656 /* Register: RADIO_TIFS */
6657 /* Description: Inter Frame Spacing in us */
6658 
6659 /* Bits 7..0 : Inter Frame Spacing in us */
6660 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
6661 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
6662 
6663 /* Register: RADIO_RSSISAMPLE */
6664 /* Description: RSSI sample */
6665 
6666 /* Bits 6..0 : RSSI sample */
6667 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
6668 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
6669 
6670 /* Register: RADIO_STATE */
6671 /* Description: Current radio state */
6672 
6673 /* Bits 3..0 : Current radio state */
6674 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
6675 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
6676 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
6677 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
6678 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
6679 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
6680 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
6681 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
6682 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
6683 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
6684 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
6685 
6686 /* Register: RADIO_DATAWHITEIV */
6687 /* Description: Data whitening initial value */
6688 
6689 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
6690 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
6691 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
6692 
6693 /* Register: RADIO_BCC */
6694 /* Description: Bit counter compare */
6695 
6696 /* Bits 31..0 : Bit counter compare */
6697 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
6698 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
6699 
6700 /* Register: RADIO_DAB */
6701 /* Description: Description collection: Device address base segment n */
6702 
6703 /* Bits 31..0 : Device address base segment n */
6704 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
6705 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
6706 
6707 /* Register: RADIO_DAP */
6708 /* Description: Description collection: Device address prefix n */
6709 
6710 /* Bits 15..0 : Device address prefix n */
6711 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
6712 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
6713 
6714 /* Register: RADIO_DACNF */
6715 /* Description: Device address match configuration */
6716 
6717 /* Bit 15 : TxAdd for device address 7 */
6718 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
6719 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
6720 
6721 /* Bit 14 : TxAdd for device address 6 */
6722 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
6723 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
6724 
6725 /* Bit 13 : TxAdd for device address 5 */
6726 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
6727 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
6728 
6729 /* Bit 12 : TxAdd for device address 4 */
6730 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
6731 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
6732 
6733 /* Bit 11 : TxAdd for device address 3 */
6734 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
6735 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
6736 
6737 /* Bit 10 : TxAdd for device address 2 */
6738 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
6739 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
6740 
6741 /* Bit 9 : TxAdd for device address 1 */
6742 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
6743 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
6744 
6745 /* Bit 8 : TxAdd for device address 0 */
6746 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
6747 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
6748 
6749 /* Bit 7 : Enable or disable device address matching using device address 7 */
6750 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
6751 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
6752 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
6753 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
6754 
6755 /* Bit 6 : Enable or disable device address matching using device address 6 */
6756 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
6757 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
6758 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
6759 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
6760 
6761 /* Bit 5 : Enable or disable device address matching using device address 5 */
6762 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
6763 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
6764 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
6765 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
6766 
6767 /* Bit 4 : Enable or disable device address matching using device address 4 */
6768 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
6769 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
6770 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
6771 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
6772 
6773 /* Bit 3 : Enable or disable device address matching using device address 3 */
6774 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
6775 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
6776 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
6777 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
6778 
6779 /* Bit 2 : Enable or disable device address matching using device address 2 */
6780 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
6781 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
6782 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
6783 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
6784 
6785 /* Bit 1 : Enable or disable device address matching using device address 1 */
6786 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
6787 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
6788 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
6789 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
6790 
6791 /* Bit 0 : Enable or disable device address matching using device address 0 */
6792 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
6793 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
6794 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
6795 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
6796 
6797 /* Register: RADIO_MODECNF0 */
6798 /* Description: Radio mode configuration register 0 */
6799 
6800 /* Bits 9..8 : Default TX value */
6801 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
6802 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
6803 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
6804 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
6805 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
6806 
6807 /* Bit 0 : Radio ramp-up time */
6808 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
6809 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
6810 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
6811 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
6812 
6813 /* Register: RADIO_POWER */
6814 /* Description: Peripheral power control */
6815 
6816 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
6817 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
6818 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
6819 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
6820 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
6821 
6822 
6823 /* Peripheral: RNG */
6824 /* Description: Random Number Generator */
6825 
6826 /* Register: RNG_TASKS_START */
6827 /* Description: Task starting the random number generator */
6828 
6829 /* Bit 0 : Task starting the random number generator */
6830 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6831 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6832 #define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6833 
6834 /* Register: RNG_TASKS_STOP */
6835 /* Description: Task stopping the random number generator */
6836 
6837 /* Bit 0 : Task stopping the random number generator */
6838 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6839 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6840 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6841 
6842 /* Register: RNG_EVENTS_VALRDY */
6843 /* Description: Event being generated for every new random number written to the VALUE register */
6844 
6845 /* Bit 0 : Event being generated for every new random number written to the VALUE register */
6846 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
6847 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
6848 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */
6849 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */
6850 
6851 /* Register: RNG_SHORTS */
6852 /* Description: Shortcuts between local events and tasks */
6853 
6854 /* Bit 0 : Shortcut between event VALRDY and task STOP */
6855 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
6856 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
6857 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
6858 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
6859 
6860 /* Register: RNG_INTENSET */
6861 /* Description: Enable interrupt */
6862 
6863 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */
6864 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
6865 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
6866 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
6867 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
6868 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
6869 
6870 /* Register: RNG_INTENCLR */
6871 /* Description: Disable interrupt */
6872 
6873 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */
6874 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
6875 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
6876 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
6877 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
6878 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
6879 
6880 /* Register: RNG_CONFIG */
6881 /* Description: Configuration register */
6882 
6883 /* Bit 0 : Bias correction */
6884 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
6885 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
6886 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
6887 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
6888 
6889 /* Register: RNG_VALUE */
6890 /* Description: Output random number */
6891 
6892 /* Bits 7..0 : Generated random number */
6893 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
6894 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
6895 
6896 
6897 /* Peripheral: RTC */
6898 /* Description: Real time counter 0 */
6899 
6900 /* Register: RTC_TASKS_START */
6901 /* Description: Start RTC COUNTER */
6902 
6903 /* Bit 0 : Start RTC COUNTER */
6904 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
6905 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
6906 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
6907 
6908 /* Register: RTC_TASKS_STOP */
6909 /* Description: Stop RTC COUNTER */
6910 
6911 /* Bit 0 : Stop RTC COUNTER */
6912 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
6913 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
6914 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
6915 
6916 /* Register: RTC_TASKS_CLEAR */
6917 /* Description: Clear RTC COUNTER */
6918 
6919 /* Bit 0 : Clear RTC COUNTER */
6920 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
6921 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
6922 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
6923 
6924 /* Register: RTC_TASKS_TRIGOVRFLW */
6925 /* Description: Set COUNTER to 0xFFFFF0 */
6926 
6927 /* Bit 0 : Set COUNTER to 0xFFFFF0 */
6928 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
6929 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
6930 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
6931 
6932 /* Register: RTC_EVENTS_TICK */
6933 /* Description: Event on COUNTER increment */
6934 
6935 /* Bit 0 : Event on COUNTER increment */
6936 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
6937 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
6938 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
6939 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
6940 
6941 /* Register: RTC_EVENTS_OVRFLW */
6942 /* Description: Event on COUNTER overflow */
6943 
6944 /* Bit 0 : Event on COUNTER overflow */
6945 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
6946 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
6947 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
6948 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
6949 
6950 /* Register: RTC_EVENTS_COMPARE */
6951 /* Description: Description collection: Compare event on CC[n] match */
6952 
6953 /* Bit 0 : Compare event on CC[n] match */
6954 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
6955 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
6956 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
6957 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
6958 
6959 /* Register: RTC_INTENSET */
6960 /* Description: Enable interrupt */
6961 
6962 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
6963 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
6964 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
6965 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
6966 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
6967 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
6968 
6969 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
6970 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
6971 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
6972 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
6973 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
6974 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
6975 
6976 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
6977 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
6978 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
6979 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
6980 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
6981 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
6982 
6983 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
6984 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
6985 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
6986 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
6987 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
6988 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
6989 
6990 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
6991 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
6992 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
6993 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
6994 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
6995 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
6996 
6997 /* Bit 0 : Write '1' to enable interrupt for event TICK */
6998 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
6999 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
7000 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
7001 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
7002 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
7003 
7004 /* Register: RTC_INTENCLR */
7005 /* Description: Disable interrupt */
7006 
7007 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
7008 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
7009 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
7010 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
7011 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
7012 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
7013 
7014 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
7015 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
7016 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
7017 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
7018 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
7019 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
7020 
7021 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
7022 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
7023 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
7024 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
7025 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
7026 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
7027 
7028 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
7029 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
7030 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
7031 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
7032 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
7033 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
7034 
7035 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
7036 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
7037 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
7038 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
7039 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
7040 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
7041 
7042 /* Bit 0 : Write '1' to disable interrupt for event TICK */
7043 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
7044 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
7045 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
7046 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
7047 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
7048 
7049 /* Register: RTC_EVTEN */
7050 /* Description: Enable or disable event routing */
7051 
7052 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
7053 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
7054 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
7055 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
7056 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */
7057 
7058 /* Bit 18 : Enable or disable event routing for event COMPARE[2] */
7059 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
7060 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
7061 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
7062 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */
7063 
7064 /* Bit 17 : Enable or disable event routing for event COMPARE[1] */
7065 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
7066 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
7067 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
7068 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */
7069 
7070 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
7071 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
7072 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
7073 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
7074 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */
7075 
7076 /* Bit 1 : Enable or disable event routing for event OVRFLW */
7077 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
7078 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
7079 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
7080 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */
7081 
7082 /* Bit 0 : Enable or disable event routing for event TICK */
7083 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
7084 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
7085 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
7086 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */
7087 
7088 /* Register: RTC_EVTENSET */
7089 /* Description: Enable event routing */
7090 
7091 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
7092 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
7093 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
7094 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
7095 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
7096 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
7097 
7098 /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */
7099 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
7100 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
7101 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
7102 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
7103 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
7104 
7105 /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */
7106 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
7107 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
7108 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
7109 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
7110 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
7111 
7112 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
7113 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
7114 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
7115 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
7116 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
7117 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
7118 
7119 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
7120 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
7121 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
7122 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
7123 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
7124 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
7125 
7126 /* Bit 0 : Write '1' to enable event routing for event TICK */
7127 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
7128 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
7129 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
7130 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
7131 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
7132 
7133 /* Register: RTC_EVTENCLR */
7134 /* Description: Disable event routing */
7135 
7136 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
7137 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
7138 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
7139 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
7140 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
7141 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
7142 
7143 /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */
7144 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
7145 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
7146 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
7147 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
7148 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
7149 
7150 /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */
7151 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
7152 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
7153 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
7154 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
7155 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
7156 
7157 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
7158 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
7159 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
7160 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
7161 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
7162 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
7163 
7164 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
7165 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
7166 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
7167 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
7168 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
7169 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
7170 
7171 /* Bit 0 : Write '1' to disable event routing for event TICK */
7172 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
7173 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
7174 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
7175 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
7176 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
7177 
7178 /* Register: RTC_COUNTER */
7179 /* Description: Current COUNTER value */
7180 
7181 /* Bits 23..0 : Counter value */
7182 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
7183 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
7184 
7185 /* Register: RTC_PRESCALER */
7186 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
7187 
7188 /* Bits 11..0 : Prescaler value */
7189 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
7190 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
7191 
7192 /* Register: RTC_CC */
7193 /* Description: Description collection: Compare register n */
7194 
7195 /* Bits 23..0 : Compare value */
7196 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
7197 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
7198 
7199 
7200 /* Peripheral: SAADC */
7201 /* Description: Analog to Digital Converter */
7202 
7203 /* Register: SAADC_TASKS_START */
7204 /* Description: Start the ADC and prepare the result buffer in RAM */
7205 
7206 /* Bit 0 : Start the ADC and prepare the result buffer in RAM */
7207 #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
7208 #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
7209 #define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
7210 
7211 /* Register: SAADC_TASKS_SAMPLE */
7212 /* Description: Take one ADC sample, if scan is enabled all channels are sampled */
7213 
7214 /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */
7215 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */
7216 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */
7217 #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */
7218 
7219 /* Register: SAADC_TASKS_STOP */
7220 /* Description: Stop the ADC and terminate any on-going conversion */
7221 
7222 /* Bit 0 : Stop the ADC and terminate any on-going conversion */
7223 #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
7224 #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
7225 #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
7226 
7227 /* Register: SAADC_TASKS_CALIBRATEOFFSET */
7228 /* Description: Starts offset auto-calibration */
7229 
7230 /* Bit 0 : Starts offset auto-calibration */
7231 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */
7232 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */
7233 #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */
7234 
7235 /* Register: SAADC_EVENTS_STARTED */
7236 /* Description: The ADC has started */
7237 
7238 /* Bit 0 : The ADC has started */
7239 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
7240 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
7241 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
7242 #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
7243 
7244 /* Register: SAADC_EVENTS_END */
7245 /* Description: The ADC has filled up the Result buffer */
7246 
7247 /* Bit 0 : The ADC has filled up the Result buffer */
7248 #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
7249 #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
7250 #define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
7251 #define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
7252 
7253 /* Register: SAADC_EVENTS_DONE */
7254 /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
7255 
7256 /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */
7257 #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
7258 #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
7259 #define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
7260 #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
7261 
7262 /* Register: SAADC_EVENTS_RESULTDONE */
7263 /* Description: A result is ready to get transferred to RAM. */
7264 
7265 /* Bit 0 : A result is ready to get transferred to RAM. */
7266 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */
7267 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */
7268 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */
7269 #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */
7270 
7271 /* Register: SAADC_EVENTS_CALIBRATEDONE */
7272 /* Description: Calibration is complete */
7273 
7274 /* Bit 0 : Calibration is complete */
7275 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */
7276 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */
7277 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */
7278 #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */
7279 
7280 /* Register: SAADC_EVENTS_STOPPED */
7281 /* Description: The ADC has stopped */
7282 
7283 /* Bit 0 : The ADC has stopped */
7284 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
7285 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
7286 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
7287 #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
7288 
7289 /* Register: SAADC_EVENTS_CH_LIMITH */
7290 /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */
7291 
7292 /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */
7293 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */
7294 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */
7295 #define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */
7296 #define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */
7297 
7298 /* Register: SAADC_EVENTS_CH_LIMITL */
7299 /* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */
7300 
7301 /* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */
7302 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */
7303 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */
7304 #define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */
7305 #define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */
7306 
7307 /* Register: SAADC_INTEN */
7308 /* Description: Enable or disable interrupt */
7309 
7310 /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */
7311 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
7312 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
7313 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
7314 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
7315 
7316 /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */
7317 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
7318 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
7319 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
7320 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
7321 
7322 /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */
7323 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
7324 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
7325 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
7326 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
7327 
7328 /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */
7329 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
7330 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
7331 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
7332 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
7333 
7334 /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */
7335 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
7336 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
7337 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
7338 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
7339 
7340 /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */
7341 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
7342 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
7343 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
7344 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
7345 
7346 /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */
7347 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
7348 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
7349 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
7350 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
7351 
7352 /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */
7353 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
7354 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
7355 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
7356 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
7357 
7358 /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */
7359 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
7360 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
7361 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
7362 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
7363 
7364 /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */
7365 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
7366 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
7367 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
7368 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
7369 
7370 /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */
7371 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
7372 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
7373 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
7374 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
7375 
7376 /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */
7377 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
7378 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
7379 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
7380 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
7381 
7382 /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */
7383 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
7384 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
7385 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
7386 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
7387 
7388 /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */
7389 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
7390 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
7391 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
7392 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
7393 
7394 /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */
7395 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
7396 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
7397 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
7398 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
7399 
7400 /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */
7401 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
7402 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
7403 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
7404 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
7405 
7406 /* Bit 5 : Enable or disable interrupt for event STOPPED */
7407 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
7408 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7409 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
7410 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
7411 
7412 /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */
7413 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
7414 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
7415 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
7416 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
7417 
7418 /* Bit 3 : Enable or disable interrupt for event RESULTDONE */
7419 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
7420 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
7421 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
7422 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
7423 
7424 /* Bit 2 : Enable or disable interrupt for event DONE */
7425 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
7426 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
7427 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
7428 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
7429 
7430 /* Bit 1 : Enable or disable interrupt for event END */
7431 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
7432 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
7433 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
7434 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
7435 
7436 /* Bit 0 : Enable or disable interrupt for event STARTED */
7437 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
7438 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
7439 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
7440 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
7441 
7442 /* Register: SAADC_INTENSET */
7443 /* Description: Enable interrupt */
7444 
7445 /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */
7446 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
7447 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
7448 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
7449 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
7450 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
7451 
7452 /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */
7453 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
7454 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
7455 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
7456 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
7457 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
7458 
7459 /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */
7460 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
7461 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
7462 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
7463 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
7464 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
7465 
7466 /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */
7467 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
7468 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
7469 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
7470 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
7471 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
7472 
7473 /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */
7474 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
7475 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
7476 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
7477 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
7478 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
7479 
7480 /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */
7481 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
7482 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
7483 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
7484 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
7485 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
7486 
7487 /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */
7488 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
7489 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
7490 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
7491 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
7492 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
7493 
7494 /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */
7495 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
7496 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
7497 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
7498 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
7499 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
7500 
7501 /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */
7502 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
7503 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
7504 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
7505 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
7506 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
7507 
7508 /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */
7509 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
7510 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
7511 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
7512 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
7513 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
7514 
7515 /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */
7516 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
7517 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
7518 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
7519 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
7520 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
7521 
7522 /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */
7523 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
7524 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
7525 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
7526 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
7527 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
7528 
7529 /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */
7530 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
7531 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
7532 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
7533 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
7534 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
7535 
7536 /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */
7537 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
7538 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
7539 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
7540 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
7541 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
7542 
7543 /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */
7544 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
7545 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
7546 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
7547 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
7548 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
7549 
7550 /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */
7551 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
7552 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
7553 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
7554 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
7555 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
7556 
7557 /* Bit 5 : Write '1' to enable interrupt for event STOPPED */
7558 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
7559 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7560 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7561 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7562 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
7563 
7564 /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */
7565 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
7566 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
7567 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
7568 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
7569 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
7570 
7571 /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */
7572 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
7573 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
7574 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
7575 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
7576 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
7577 
7578 /* Bit 2 : Write '1' to enable interrupt for event DONE */
7579 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
7580 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
7581 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
7582 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
7583 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
7584 
7585 /* Bit 1 : Write '1' to enable interrupt for event END */
7586 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
7587 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
7588 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7589 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
7590 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
7591 
7592 /* Bit 0 : Write '1' to enable interrupt for event STARTED */
7593 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
7594 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
7595 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
7596 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
7597 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
7598 
7599 /* Register: SAADC_INTENCLR */
7600 /* Description: Disable interrupt */
7601 
7602 /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */
7603 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
7604 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
7605 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
7606 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
7607 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
7608 
7609 /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */
7610 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
7611 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
7612 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
7613 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
7614 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
7615 
7616 /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */
7617 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
7618 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
7619 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
7620 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
7621 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
7622 
7623 /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */
7624 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
7625 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
7626 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
7627 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
7628 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
7629 
7630 /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */
7631 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
7632 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
7633 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
7634 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
7635 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
7636 
7637 /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */
7638 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
7639 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
7640 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
7641 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
7642 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
7643 
7644 /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */
7645 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
7646 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
7647 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
7648 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
7649 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
7650 
7651 /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */
7652 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
7653 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
7654 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
7655 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
7656 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
7657 
7658 /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */
7659 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
7660 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
7661 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
7662 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
7663 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
7664 
7665 /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */
7666 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
7667 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
7668 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
7669 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
7670 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
7671 
7672 /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */
7673 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
7674 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
7675 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
7676 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
7677 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
7678 
7679 /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */
7680 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
7681 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
7682 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
7683 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
7684 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
7685 
7686 /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */
7687 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
7688 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
7689 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
7690 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
7691 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
7692 
7693 /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */
7694 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
7695 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
7696 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
7697 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
7698 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
7699 
7700 /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */
7701 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
7702 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
7703 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
7704 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
7705 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
7706 
7707 /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */
7708 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
7709 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
7710 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
7711 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
7712 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
7713 
7714 /* Bit 5 : Write '1' to disable interrupt for event STOPPED */
7715 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
7716 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7717 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7718 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
7719 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
7720 
7721 /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */
7722 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
7723 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
7724 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
7725 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
7726 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
7727 
7728 /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */
7729 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
7730 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
7731 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
7732 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
7733 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
7734 
7735 /* Bit 2 : Write '1' to disable interrupt for event DONE */
7736 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
7737 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
7738 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
7739 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
7740 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
7741 
7742 /* Bit 1 : Write '1' to disable interrupt for event END */
7743 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
7744 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
7745 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7746 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
7747 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
7748 
7749 /* Bit 0 : Write '1' to disable interrupt for event STARTED */
7750 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
7751 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
7752 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7753 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
7754 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
7755 
7756 /* Register: SAADC_STATUS */
7757 /* Description: Status */
7758 
7759 /* Bit 0 : Status */
7760 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
7761 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
7762 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
7763 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
7764 
7765 /* Register: SAADC_ENABLE */
7766 /* Description: Enable or disable ADC */
7767 
7768 /* Bit 0 : Enable or disable ADC */
7769 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7770 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7771 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
7772 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
7773 
7774 /* Register: SAADC_CH_PSELP */
7775 /* Description: Description cluster: Input positive pin selection for CH[n] */
7776 
7777 /* Bits 4..0 : Analog positive input channel */
7778 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
7779 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
7780 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
7781 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
7782 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
7783 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
7784 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
7785 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
7786 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
7787 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
7788 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
7789 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
7790 
7791 /* Register: SAADC_CH_PSELN */
7792 /* Description: Description cluster: Input negative pin selection for CH[n] */
7793 
7794 /* Bits 4..0 : Analog negative input, enables differential channel */
7795 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
7796 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
7797 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
7798 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
7799 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
7800 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
7801 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
7802 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
7803 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
7804 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
7805 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
7806 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
7807 
7808 /* Register: SAADC_CH_CONFIG */
7809 /* Description: Description cluster: Input configuration for CH[n] */
7810 
7811 /* Bit 24 : Enable burst mode */
7812 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
7813 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
7814 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
7815 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
7816 
7817 /* Bit 20 : Enable differential mode */
7818 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
7819 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
7820 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
7821 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
7822 
7823 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
7824 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
7825 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
7826 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
7827 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
7828 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
7829 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
7830 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
7831 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
7832 
7833 /* Bit 12 : Reference control */
7834 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
7835 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
7836 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
7837 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
7838 
7839 /* Bits 10..8 : Gain control */
7840 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
7841 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
7842 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
7843 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
7844 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
7845 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
7846 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
7847 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
7848 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
7849 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
7850 
7851 /* Bits 5..4 : Negative channel resistor control */
7852 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
7853 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
7854 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
7855 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
7856 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
7857 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
7858 
7859 /* Bits 1..0 : Positive channel resistor control */
7860 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
7861 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
7862 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
7863 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
7864 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
7865 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
7866 
7867 /* Register: SAADC_CH_LIMIT */
7868 /* Description: Description cluster: High/low limits for event monitoring a channel */
7869 
7870 /* Bits 31..16 : High level limit */
7871 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
7872 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
7873 
7874 /* Bits 15..0 : Low level limit */
7875 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
7876 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
7877 
7878 /* Register: SAADC_RESOLUTION */
7879 /* Description: Resolution configuration */
7880 
7881 /* Bits 2..0 : Set the resolution */
7882 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
7883 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
7884 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
7885 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
7886 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
7887 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
7888 
7889 /* Register: SAADC_OVERSAMPLE */
7890 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
7891 
7892 /* Bits 3..0 : Oversample control */
7893 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
7894 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
7895 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
7896 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
7897 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
7898 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
7899 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
7900 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
7901 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
7902 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
7903 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
7904 
7905 /* Register: SAADC_SAMPLERATE */
7906 /* Description: Controls normal or continuous sample rate */
7907 
7908 /* Bit 12 : Select mode for sample rate control */
7909 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
7910 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
7911 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
7912 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
7913 
7914 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
7915 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
7916 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
7917 
7918 /* Register: SAADC_RESULT_PTR */
7919 /* Description: Data pointer */
7920 
7921 /* Bits 31..0 : Data pointer */
7922 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
7923 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
7924 
7925 /* Register: SAADC_RESULT_MAXCNT */
7926 /* Description: Maximum number of buffer words to transfer */
7927 
7928 /* Bits 14..0 : Maximum number of buffer words to transfer */
7929 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
7930 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
7931 
7932 /* Register: SAADC_RESULT_AMOUNT */
7933 /* Description: Number of buffer words transferred since last START */
7934 
7935 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
7936 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
7937 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
7938 
7939 
7940 /* Peripheral: SPI */
7941 /* Description: Serial Peripheral Interface */
7942 
7943 /* Register: SPI_EVENTS_READY */
7944 /* Description: TXD byte sent and RXD byte received */
7945 
7946 /* Bit 0 : TXD byte sent and RXD byte received */
7947 #define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
7948 #define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
7949 #define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
7950 #define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
7951 
7952 /* Register: SPI_INTENSET */
7953 /* Description: Enable interrupt */
7954 
7955 /* Bit 2 : Write '1' to enable interrupt for event READY */
7956 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
7957 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
7958 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
7959 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
7960 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
7961 
7962 /* Register: SPI_INTENCLR */
7963 /* Description: Disable interrupt */
7964 
7965 /* Bit 2 : Write '1' to disable interrupt for event READY */
7966 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
7967 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
7968 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
7969 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
7970 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
7971 
7972 /* Register: SPI_ENABLE */
7973 /* Description: Enable SPI */
7974 
7975 /* Bits 3..0 : Enable or disable SPI */
7976 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
7977 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
7978 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
7979 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
7980 
7981 /* Register: SPI_PSEL_SCK */
7982 /* Description: Pin select for SCK */
7983 
7984 /* Bit 31 : Connection */
7985 #define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7986 #define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
7987 #define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
7988 #define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
7989 
7990 /* Bits 4..0 : Pin number */
7991 #define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
7992 #define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
7993 
7994 /* Register: SPI_PSEL_MOSI */
7995 /* Description: Pin select for MOSI signal */
7996 
7997 /* Bit 31 : Connection */
7998 #define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
7999 #define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8000 #define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
8001 #define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
8002 
8003 /* Bits 4..0 : Pin number */
8004 #define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
8005 #define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
8006 
8007 /* Register: SPI_PSEL_MISO */
8008 /* Description: Pin select for MISO signal */
8009 
8010 /* Bit 31 : Connection */
8011 #define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8012 #define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8013 #define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
8014 #define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
8015 
8016 /* Bits 4..0 : Pin number */
8017 #define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
8018 #define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
8019 
8020 /* Register: SPI_RXD */
8021 /* Description: RXD register */
8022 
8023 /* Bits 7..0 : RX data received. Double buffered */
8024 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
8025 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
8026 
8027 /* Register: SPI_TXD */
8028 /* Description: TXD register */
8029 
8030 /* Bits 7..0 : TX data to send. Double buffered */
8031 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
8032 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
8033 
8034 /* Register: SPI_FREQUENCY */
8035 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
8036 
8037 /* Bits 31..0 : SPI master data rate */
8038 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
8039 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
8040 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
8041 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
8042 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
8043 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
8044 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
8045 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
8046 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
8047 
8048 /* Register: SPI_CONFIG */
8049 /* Description: Configuration register */
8050 
8051 /* Bit 2 : Serial clock (SCK) polarity */
8052 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
8053 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
8054 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
8055 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
8056 
8057 /* Bit 1 : Serial clock (SCK) phase */
8058 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
8059 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
8060 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
8061 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
8062 
8063 /* Bit 0 : Bit order */
8064 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
8065 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
8066 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
8067 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
8068 
8069 
8070 /* Peripheral: SPIM */
8071 /* Description: Serial Peripheral Interface Master with EasyDMA */
8072 
8073 /* Register: SPIM_TASKS_START */
8074 /* Description: Start SPI transaction */
8075 
8076 /* Bit 0 : Start SPI transaction */
8077 #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8078 #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8079 #define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8080 
8081 /* Register: SPIM_TASKS_STOP */
8082 /* Description: Stop SPI transaction */
8083 
8084 /* Bit 0 : Stop SPI transaction */
8085 #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8086 #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8087 #define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8088 
8089 /* Register: SPIM_TASKS_SUSPEND */
8090 /* Description: Suspend SPI transaction */
8091 
8092 /* Bit 0 : Suspend SPI transaction */
8093 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
8094 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
8095 #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
8096 
8097 /* Register: SPIM_TASKS_RESUME */
8098 /* Description: Resume SPI transaction */
8099 
8100 /* Bit 0 : Resume SPI transaction */
8101 #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
8102 #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
8103 #define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
8104 
8105 /* Register: SPIM_EVENTS_STOPPED */
8106 /* Description: SPI transaction has stopped */
8107 
8108 /* Bit 0 : SPI transaction has stopped */
8109 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
8110 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
8111 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
8112 #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
8113 
8114 /* Register: SPIM_EVENTS_ENDRX */
8115 /* Description: End of RXD buffer reached */
8116 
8117 /* Bit 0 : End of RXD buffer reached */
8118 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
8119 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
8120 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
8121 #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
8122 
8123 /* Register: SPIM_EVENTS_END */
8124 /* Description: End of RXD buffer and TXD buffer reached */
8125 
8126 /* Bit 0 : End of RXD buffer and TXD buffer reached */
8127 #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
8128 #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
8129 #define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
8130 #define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
8131 
8132 /* Register: SPIM_EVENTS_ENDTX */
8133 /* Description: End of TXD buffer reached */
8134 
8135 /* Bit 0 : End of TXD buffer reached */
8136 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
8137 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
8138 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
8139 #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
8140 
8141 /* Register: SPIM_EVENTS_STARTED */
8142 /* Description: Transaction started */
8143 
8144 /* Bit 0 : Transaction started */
8145 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */
8146 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */
8147 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */
8148 #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */
8149 
8150 /* Register: SPIM_SHORTS */
8151 /* Description: Shortcuts between local events and tasks */
8152 
8153 /* Bit 17 : Shortcut between event END and task START */
8154 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
8155 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
8156 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
8157 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
8158 
8159 /* Register: SPIM_INTENSET */
8160 /* Description: Enable interrupt */
8161 
8162 /* Bit 19 : Write '1' to enable interrupt for event STARTED */
8163 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
8164 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
8165 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
8166 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
8167 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
8168 
8169 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
8170 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
8171 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
8172 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
8173 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
8174 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
8175 
8176 /* Bit 6 : Write '1' to enable interrupt for event END */
8177 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
8178 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
8179 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
8180 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8181 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
8182 
8183 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
8184 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
8185 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
8186 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
8187 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
8188 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
8189 
8190 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
8191 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8192 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8193 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8194 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8195 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8196 
8197 /* Register: SPIM_INTENCLR */
8198 /* Description: Disable interrupt */
8199 
8200 /* Bit 19 : Write '1' to disable interrupt for event STARTED */
8201 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
8202 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
8203 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
8204 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
8205 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
8206 
8207 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
8208 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
8209 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
8210 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
8211 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
8212 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
8213 
8214 /* Bit 6 : Write '1' to disable interrupt for event END */
8215 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
8216 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
8217 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
8218 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
8219 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
8220 
8221 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
8222 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
8223 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
8224 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
8225 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
8226 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
8227 
8228 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
8229 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8230 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8231 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8232 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8233 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8234 
8235 /* Register: SPIM_ENABLE */
8236 /* Description: Enable SPIM */
8237 
8238 /* Bits 3..0 : Enable or disable SPIM */
8239 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8240 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8241 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
8242 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
8243 
8244 /* Register: SPIM_PSEL_SCK */
8245 /* Description: Pin select for SCK */
8246 
8247 /* Bit 31 : Connection */
8248 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8249 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8250 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
8251 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
8252 
8253 /* Bits 4..0 : Pin number */
8254 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
8255 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
8256 
8257 /* Register: SPIM_PSEL_MOSI */
8258 /* Description: Pin select for MOSI signal */
8259 
8260 /* Bit 31 : Connection */
8261 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8262 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8263 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
8264 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
8265 
8266 /* Bits 4..0 : Pin number */
8267 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
8268 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
8269 
8270 /* Register: SPIM_PSEL_MISO */
8271 /* Description: Pin select for MISO signal */
8272 
8273 /* Bit 31 : Connection */
8274 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8275 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8276 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
8277 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
8278 
8279 /* Bits 4..0 : Pin number */
8280 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
8281 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
8282 
8283 /* Register: SPIM_FREQUENCY */
8284 /* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
8285 
8286 /* Bits 31..0 : SPI master data rate */
8287 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
8288 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
8289 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
8290 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
8291 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
8292 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
8293 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
8294 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
8295 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
8296 
8297 /* Register: SPIM_RXD_PTR */
8298 /* Description: Data pointer */
8299 
8300 /* Bits 31..0 : Data pointer */
8301 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
8302 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
8303 
8304 /* Register: SPIM_RXD_MAXCNT */
8305 /* Description: Maximum number of bytes in receive buffer */
8306 
8307 /* Bits 9..0 : Maximum number of bytes in receive buffer */
8308 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
8309 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
8310 
8311 /* Register: SPIM_RXD_AMOUNT */
8312 /* Description: Number of bytes transferred in the last transaction */
8313 
8314 /* Bits 9..0 : Number of bytes transferred in the last transaction */
8315 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
8316 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
8317 
8318 /* Register: SPIM_RXD_LIST */
8319 /* Description: EasyDMA list type */
8320 
8321 /* Bits 1..0 : List type */
8322 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
8323 #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
8324 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
8325 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
8326 
8327 /* Register: SPIM_TXD_PTR */
8328 /* Description: Data pointer */
8329 
8330 /* Bits 31..0 : Data pointer */
8331 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
8332 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
8333 
8334 /* Register: SPIM_TXD_MAXCNT */
8335 /* Description: Maximum number of bytes in transmit buffer */
8336 
8337 /* Bits 9..0 : Maximum number of bytes in transmit buffer */
8338 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
8339 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
8340 
8341 /* Register: SPIM_TXD_AMOUNT */
8342 /* Description: Number of bytes transferred in the last transaction */
8343 
8344 /* Bits 9..0 : Number of bytes transferred in the last transaction */
8345 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
8346 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
8347 
8348 /* Register: SPIM_TXD_LIST */
8349 /* Description: EasyDMA list type */
8350 
8351 /* Bits 1..0 : List type */
8352 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
8353 #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
8354 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
8355 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
8356 
8357 /* Register: SPIM_CONFIG */
8358 /* Description: Configuration register */
8359 
8360 /* Bit 2 : Serial clock (SCK) polarity */
8361 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
8362 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
8363 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
8364 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
8365 
8366 /* Bit 1 : Serial clock (SCK) phase */
8367 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
8368 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
8369 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
8370 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
8371 
8372 /* Bit 0 : Bit order */
8373 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
8374 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
8375 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
8376 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
8377 
8378 /* Register: SPIM_ORC */
8379 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
8380 
8381 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
8382 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
8383 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
8384 
8385 
8386 /* Peripheral: SPIS */
8387 /* Description: SPI Slave */
8388 
8389 /* Register: SPIS_TASKS_ACQUIRE */
8390 /* Description: Acquire SPI semaphore */
8391 
8392 /* Bit 0 : Acquire SPI semaphore */
8393 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */
8394 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */
8395 #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */
8396 
8397 /* Register: SPIS_TASKS_RELEASE */
8398 /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */
8399 
8400 /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */
8401 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */
8402 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */
8403 #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */
8404 
8405 /* Register: SPIS_EVENTS_END */
8406 /* Description: Granted transaction completed */
8407 
8408 /* Bit 0 : Granted transaction completed */
8409 #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
8410 #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
8411 #define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
8412 #define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
8413 
8414 /* Register: SPIS_EVENTS_ENDRX */
8415 /* Description: End of RXD buffer reached */
8416 
8417 /* Bit 0 : End of RXD buffer reached */
8418 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
8419 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
8420 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
8421 #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
8422 
8423 /* Register: SPIS_EVENTS_ACQUIRED */
8424 /* Description: Semaphore acquired */
8425 
8426 /* Bit 0 : Semaphore acquired */
8427 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */
8428 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */
8429 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */
8430 #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */
8431 
8432 /* Register: SPIS_SHORTS */
8433 /* Description: Shortcuts between local events and tasks */
8434 
8435 /* Bit 2 : Shortcut between event END and task ACQUIRE */
8436 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
8437 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
8438 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
8439 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
8440 
8441 /* Register: SPIS_INTENSET */
8442 /* Description: Enable interrupt */
8443 
8444 /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */
8445 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
8446 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
8447 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
8448 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
8449 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
8450 
8451 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
8452 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
8453 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
8454 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
8455 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
8456 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
8457 
8458 /* Bit 1 : Write '1' to enable interrupt for event END */
8459 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
8460 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
8461 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
8462 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8463 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
8464 
8465 /* Register: SPIS_INTENCLR */
8466 /* Description: Disable interrupt */
8467 
8468 /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */
8469 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
8470 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
8471 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
8472 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
8473 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
8474 
8475 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
8476 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
8477 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
8478 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
8479 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
8480 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
8481 
8482 /* Bit 1 : Write '1' to disable interrupt for event END */
8483 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
8484 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
8485 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
8486 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
8487 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
8488 
8489 /* Register: SPIS_SEMSTAT */
8490 /* Description: Semaphore status register */
8491 
8492 /* Bits 1..0 : Semaphore status */
8493 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
8494 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
8495 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
8496 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
8497 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
8498 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
8499 
8500 /* Register: SPIS_STATUS */
8501 /* Description: Status from last transaction */
8502 
8503 /* Bit 1 : RX buffer overflow detected, and prevented */
8504 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
8505 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
8506 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
8507 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
8508 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
8509 
8510 /* Bit 0 : TX buffer over-read detected, and prevented */
8511 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
8512 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
8513 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
8514 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
8515 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
8516 
8517 /* Register: SPIS_ENABLE */
8518 /* Description: Enable SPI slave */
8519 
8520 /* Bits 3..0 : Enable or disable SPI slave */
8521 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8522 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8523 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
8524 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
8525 
8526 /* Register: SPIS_PSEL_SCK */
8527 /* Description: Pin select for SCK */
8528 
8529 /* Bit 31 : Connection */
8530 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8531 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8532 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
8533 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
8534 
8535 /* Bits 4..0 : Pin number */
8536 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
8537 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
8538 
8539 /* Register: SPIS_PSEL_MISO */
8540 /* Description: Pin select for MISO signal */
8541 
8542 /* Bit 31 : Connection */
8543 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8544 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8545 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
8546 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
8547 
8548 /* Bits 4..0 : Pin number */
8549 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
8550 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
8551 
8552 /* Register: SPIS_PSEL_MOSI */
8553 /* Description: Pin select for MOSI signal */
8554 
8555 /* Bit 31 : Connection */
8556 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8557 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8558 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
8559 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
8560 
8561 /* Bits 4..0 : Pin number */
8562 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
8563 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
8564 
8565 /* Register: SPIS_PSEL_CSN */
8566 /* Description: Pin select for CSN signal */
8567 
8568 /* Bit 31 : Connection */
8569 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8570 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8571 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
8572 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
8573 
8574 /* Bits 4..0 : Pin number */
8575 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
8576 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
8577 
8578 /* Register: SPIS_RXD_PTR */
8579 /* Description: RXD data pointer */
8580 
8581 /* Bits 31..0 : RXD data pointer */
8582 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
8583 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
8584 
8585 /* Register: SPIS_RXD_MAXCNT */
8586 /* Description: Maximum number of bytes in receive buffer */
8587 
8588 /* Bits 9..0 : Maximum number of bytes in receive buffer */
8589 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
8590 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
8591 
8592 /* Register: SPIS_RXD_AMOUNT */
8593 /* Description: Number of bytes received in last granted transaction */
8594 
8595 /* Bits 9..0 : Number of bytes received in the last granted transaction */
8596 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
8597 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
8598 
8599 /* Register: SPIS_RXD_LIST */
8600 /* Description: EasyDMA list type */
8601 
8602 /* Bits 1..0 : List type */
8603 #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
8604 #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
8605 #define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
8606 #define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
8607 
8608 /* Register: SPIS_TXD_PTR */
8609 /* Description: TXD data pointer */
8610 
8611 /* Bits 31..0 : TXD data pointer */
8612 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
8613 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
8614 
8615 /* Register: SPIS_TXD_MAXCNT */
8616 /* Description: Maximum number of bytes in transmit buffer */
8617 
8618 /* Bits 9..0 : Maximum number of bytes in transmit buffer */
8619 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
8620 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
8621 
8622 /* Register: SPIS_TXD_AMOUNT */
8623 /* Description: Number of bytes transmitted in last granted transaction */
8624 
8625 /* Bits 9..0 : Number of bytes transmitted in last granted transaction */
8626 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
8627 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
8628 
8629 /* Register: SPIS_TXD_LIST */
8630 /* Description: EasyDMA list type */
8631 
8632 /* Bits 1..0 : List type */
8633 #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
8634 #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
8635 #define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
8636 #define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
8637 
8638 /* Register: SPIS_CONFIG */
8639 /* Description: Configuration register */
8640 
8641 /* Bit 2 : Serial clock (SCK) polarity */
8642 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
8643 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
8644 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
8645 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
8646 
8647 /* Bit 1 : Serial clock (SCK) phase */
8648 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
8649 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
8650 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
8651 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
8652 
8653 /* Bit 0 : Bit order */
8654 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
8655 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
8656 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
8657 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
8658 
8659 /* Register: SPIS_DEF */
8660 /* Description: Default character. Character clocked out in case of an ignored transaction. */
8661 
8662 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
8663 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
8664 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
8665 
8666 /* Register: SPIS_ORC */
8667 /* Description: Over-read character */
8668 
8669 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
8670 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
8671 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
8672 
8673 
8674 /* Peripheral: TEMP */
8675 /* Description: Temperature Sensor */
8676 
8677 /* Register: TEMP_TASKS_START */
8678 /* Description: Start temperature measurement */
8679 
8680 /* Bit 0 : Start temperature measurement */
8681 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8682 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8683 #define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8684 
8685 /* Register: TEMP_TASKS_STOP */
8686 /* Description: Stop temperature measurement */
8687 
8688 /* Bit 0 : Stop temperature measurement */
8689 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8690 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8691 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8692 
8693 /* Register: TEMP_EVENTS_DATARDY */
8694 /* Description: Temperature measurement complete, data ready */
8695 
8696 /* Bit 0 : Temperature measurement complete, data ready */
8697 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
8698 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
8699 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
8700 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
8701 
8702 /* Register: TEMP_INTENSET */
8703 /* Description: Enable interrupt */
8704 
8705 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */
8706 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
8707 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
8708 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
8709 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
8710 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
8711 
8712 /* Register: TEMP_INTENCLR */
8713 /* Description: Disable interrupt */
8714 
8715 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */
8716 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
8717 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
8718 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
8719 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
8720 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
8721 
8722 /* Register: TEMP_TEMP */
8723 /* Description: Temperature in degC (0.25deg steps) */
8724 
8725 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
8726 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
8727 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
8728 
8729 /* Register: TEMP_A0 */
8730 /* Description: Slope of 1st piece wise linear function */
8731 
8732 /* Bits 11..0 : Slope of 1st piece wise linear function */
8733 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
8734 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
8735 
8736 /* Register: TEMP_A1 */
8737 /* Description: Slope of 2nd piece wise linear function */
8738 
8739 /* Bits 11..0 : Slope of 2nd piece wise linear function */
8740 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
8741 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
8742 
8743 /* Register: TEMP_A2 */
8744 /* Description: Slope of 3rd piece wise linear function */
8745 
8746 /* Bits 11..0 : Slope of 3rd piece wise linear function */
8747 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
8748 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
8749 
8750 /* Register: TEMP_A3 */
8751 /* Description: Slope of 4th piece wise linear function */
8752 
8753 /* Bits 11..0 : Slope of 4th piece wise linear function */
8754 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
8755 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
8756 
8757 /* Register: TEMP_A4 */
8758 /* Description: Slope of 5th piece wise linear function */
8759 
8760 /* Bits 11..0 : Slope of 5th piece wise linear function */
8761 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
8762 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
8763 
8764 /* Register: TEMP_A5 */
8765 /* Description: Slope of 6th piece wise linear function */
8766 
8767 /* Bits 11..0 : Slope of 6th piece wise linear function */
8768 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
8769 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
8770 
8771 /* Register: TEMP_B0 */
8772 /* Description: y-intercept of 1st piece wise linear function */
8773 
8774 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
8775 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
8776 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
8777 
8778 /* Register: TEMP_B1 */
8779 /* Description: y-intercept of 2nd piece wise linear function */
8780 
8781 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
8782 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
8783 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
8784 
8785 /* Register: TEMP_B2 */
8786 /* Description: y-intercept of 3rd piece wise linear function */
8787 
8788 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */
8789 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
8790 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
8791 
8792 /* Register: TEMP_B3 */
8793 /* Description: y-intercept of 4th piece wise linear function */
8794 
8795 /* Bits 13..0 : y-intercept of 4th piece wise linear function */
8796 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
8797 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
8798 
8799 /* Register: TEMP_B4 */
8800 /* Description: y-intercept of 5th piece wise linear function */
8801 
8802 /* Bits 13..0 : y-intercept of 5th piece wise linear function */
8803 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
8804 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
8805 
8806 /* Register: TEMP_B5 */
8807 /* Description: y-intercept of 6th piece wise linear function */
8808 
8809 /* Bits 13..0 : y-intercept of 6th piece wise linear function */
8810 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
8811 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
8812 
8813 /* Register: TEMP_T0 */
8814 /* Description: End point of 1st piece wise linear function */
8815 
8816 /* Bits 7..0 : End point of 1st piece wise linear function */
8817 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
8818 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
8819 
8820 /* Register: TEMP_T1 */
8821 /* Description: End point of 2nd piece wise linear function */
8822 
8823 /* Bits 7..0 : End point of 2nd piece wise linear function */
8824 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
8825 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
8826 
8827 /* Register: TEMP_T2 */
8828 /* Description: End point of 3rd piece wise linear function */
8829 
8830 /* Bits 7..0 : End point of 3rd piece wise linear function */
8831 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
8832 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
8833 
8834 /* Register: TEMP_T3 */
8835 /* Description: End point of 4th piece wise linear function */
8836 
8837 /* Bits 7..0 : End point of 4th piece wise linear function */
8838 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
8839 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
8840 
8841 /* Register: TEMP_T4 */
8842 /* Description: End point of 5th piece wise linear function */
8843 
8844 /* Bits 7..0 : End point of 5th piece wise linear function */
8845 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
8846 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
8847 
8848 
8849 /* Peripheral: TIMER */
8850 /* Description: Timer/Counter 0 */
8851 
8852 /* Register: TIMER_TASKS_START */
8853 /* Description: Start Timer */
8854 
8855 /* Bit 0 : Start Timer */
8856 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
8857 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
8858 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
8859 
8860 /* Register: TIMER_TASKS_STOP */
8861 /* Description: Stop Timer */
8862 
8863 /* Bit 0 : Stop Timer */
8864 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
8865 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
8866 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
8867 
8868 /* Register: TIMER_TASKS_COUNT */
8869 /* Description: Increment Timer (Counter mode only) */
8870 
8871 /* Bit 0 : Increment Timer (Counter mode only) */
8872 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
8873 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
8874 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
8875 
8876 /* Register: TIMER_TASKS_CLEAR */
8877 /* Description: Clear time */
8878 
8879 /* Bit 0 : Clear time */
8880 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
8881 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
8882 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
8883 
8884 /* Register: TIMER_TASKS_SHUTDOWN */
8885 /* Description: Deprecated register - Shut down timer */
8886 
8887 /* Bit 0 : Deprecated field -  Shut down timer */
8888 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
8889 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
8890 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
8891 
8892 /* Register: TIMER_TASKS_CAPTURE */
8893 /* Description: Description collection: Capture Timer value to CC[n] register */
8894 
8895 /* Bit 0 : Capture Timer value to CC[n] register */
8896 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
8897 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
8898 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
8899 
8900 /* Register: TIMER_EVENTS_COMPARE */
8901 /* Description: Description collection: Compare event on CC[n] match */
8902 
8903 /* Bit 0 : Compare event on CC[n] match */
8904 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
8905 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
8906 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
8907 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
8908 
8909 /* Register: TIMER_SHORTS */
8910 /* Description: Shortcuts between local events and tasks */
8911 
8912 /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */
8913 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
8914 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
8915 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
8916 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
8917 
8918 /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */
8919 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
8920 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
8921 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
8922 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
8923 
8924 /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */
8925 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
8926 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
8927 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
8928 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
8929 
8930 /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */
8931 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
8932 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
8933 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
8934 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
8935 
8936 /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */
8937 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
8938 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
8939 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
8940 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
8941 
8942 /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */
8943 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
8944 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
8945 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
8946 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
8947 
8948 /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */
8949 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
8950 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
8951 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8952 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8953 
8954 /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */
8955 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
8956 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
8957 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8958 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8959 
8960 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
8961 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
8962 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
8963 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8964 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8965 
8966 /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */
8967 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
8968 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
8969 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8970 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8971 
8972 /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */
8973 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
8974 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
8975 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8976 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8977 
8978 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
8979 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
8980 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
8981 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
8982 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
8983 
8984 /* Register: TIMER_INTENSET */
8985 /* Description: Enable interrupt */
8986 
8987 /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */
8988 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
8989 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
8990 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8991 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
8992 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
8993 
8994 /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */
8995 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
8996 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
8997 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8998 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
8999 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
9000 
9001 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
9002 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9003 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9004 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9005 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9006 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
9007 
9008 /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */
9009 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9010 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9011 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9012 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9013 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
9014 
9015 /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */
9016 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9017 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9018 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9019 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9020 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
9021 
9022 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
9023 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9024 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9025 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9026 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9027 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
9028 
9029 /* Register: TIMER_INTENCLR */
9030 /* Description: Disable interrupt */
9031 
9032 /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */
9033 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
9034 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
9035 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
9036 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
9037 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
9038 
9039 /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */
9040 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
9041 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
9042 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
9043 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
9044 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
9045 
9046 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
9047 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9048 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9049 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9050 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9051 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
9052 
9053 /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */
9054 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9055 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9056 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9057 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9058 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
9059 
9060 /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */
9061 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9062 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9063 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9064 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9065 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
9066 
9067 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
9068 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9069 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9070 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9071 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9072 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
9073 
9074 /* Register: TIMER_MODE */
9075 /* Description: Timer mode selection */
9076 
9077 /* Bits 1..0 : Timer mode */
9078 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
9079 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
9080 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
9081 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
9082 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
9083 
9084 /* Register: TIMER_BITMODE */
9085 /* Description: Configure the number of bits used by the TIMER */
9086 
9087 /* Bits 1..0 : Timer bit width */
9088 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
9089 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
9090 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
9091 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
9092 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
9093 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
9094 
9095 /* Register: TIMER_PRESCALER */
9096 /* Description: Timer prescaler register */
9097 
9098 /* Bits 3..0 : Prescaler value */
9099 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
9100 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
9101 
9102 /* Register: TIMER_CC */
9103 /* Description: Description collection: Capture/Compare register n */
9104 
9105 /* Bits 31..0 : Capture/Compare value */
9106 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
9107 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
9108 
9109 
9110 /* Peripheral: TWI */
9111 /* Description: I2C compatible Two-Wire Interface */
9112 
9113 /* Register: TWI_TASKS_STARTRX */
9114 /* Description: Start TWI receive sequence */
9115 
9116 /* Bit 0 : Start TWI receive sequence */
9117 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
9118 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
9119 #define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
9120 
9121 /* Register: TWI_TASKS_STARTTX */
9122 /* Description: Start TWI transmit sequence */
9123 
9124 /* Bit 0 : Start TWI transmit sequence */
9125 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
9126 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
9127 #define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
9128 
9129 /* Register: TWI_TASKS_STOP */
9130 /* Description: Stop TWI transaction */
9131 
9132 /* Bit 0 : Stop TWI transaction */
9133 #define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9134 #define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9135 #define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9136 
9137 /* Register: TWI_TASKS_SUSPEND */
9138 /* Description: Suspend TWI transaction */
9139 
9140 /* Bit 0 : Suspend TWI transaction */
9141 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
9142 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
9143 #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
9144 
9145 /* Register: TWI_TASKS_RESUME */
9146 /* Description: Resume TWI transaction */
9147 
9148 /* Bit 0 : Resume TWI transaction */
9149 #define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
9150 #define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
9151 #define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
9152 
9153 /* Register: TWI_EVENTS_STOPPED */
9154 /* Description: TWI stopped */
9155 
9156 /* Bit 0 : TWI stopped */
9157 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9158 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9159 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9160 #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9161 
9162 /* Register: TWI_EVENTS_RXDREADY */
9163 /* Description: TWI RXD byte received */
9164 
9165 /* Bit 0 : TWI RXD byte received */
9166 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */
9167 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */
9168 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */
9169 #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */
9170 
9171 /* Register: TWI_EVENTS_TXDSENT */
9172 /* Description: TWI TXD byte sent */
9173 
9174 /* Bit 0 : TWI TXD byte sent */
9175 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */
9176 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */
9177 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */
9178 #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */
9179 
9180 /* Register: TWI_EVENTS_ERROR */
9181 /* Description: TWI error */
9182 
9183 /* Bit 0 : TWI error */
9184 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
9185 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
9186 #define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
9187 #define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
9188 
9189 /* Register: TWI_EVENTS_BB */
9190 /* Description: TWI byte boundary, generated before each byte that is sent or received */
9191 
9192 /* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */
9193 #define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */
9194 #define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */
9195 #define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */
9196 #define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */
9197 
9198 /* Register: TWI_EVENTS_SUSPENDED */
9199 /* Description: TWI entered the suspended state */
9200 
9201 /* Bit 0 : TWI entered the suspended state */
9202 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
9203 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
9204 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
9205 #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
9206 
9207 /* Register: TWI_SHORTS */
9208 /* Description: Shortcuts between local events and tasks */
9209 
9210 /* Bit 1 : Shortcut between event BB and task STOP */
9211 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
9212 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
9213 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
9214 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
9215 
9216 /* Bit 0 : Shortcut between event BB and task SUSPEND */
9217 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
9218 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
9219 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9220 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9221 
9222 /* Register: TWI_INTENSET */
9223 /* Description: Enable interrupt */
9224 
9225 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
9226 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9227 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9228 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9229 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9230 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
9231 
9232 /* Bit 14 : Write '1' to enable interrupt for event BB */
9233 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
9234 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
9235 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
9236 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
9237 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
9238 
9239 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9240 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9241 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
9242 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9243 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9244 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
9245 
9246 /* Bit 7 : Write '1' to enable interrupt for event TXDSENT */
9247 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
9248 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
9249 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
9250 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
9251 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
9252 
9253 /* Bit 2 : Write '1' to enable interrupt for event RXDREADY */
9254 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
9255 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
9256 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
9257 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
9258 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
9259 
9260 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9261 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9262 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9263 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9264 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9265 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9266 
9267 /* Register: TWI_INTENCLR */
9268 /* Description: Disable interrupt */
9269 
9270 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
9271 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9272 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9273 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9274 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9275 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
9276 
9277 /* Bit 14 : Write '1' to disable interrupt for event BB */
9278 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
9279 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
9280 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
9281 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
9282 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
9283 
9284 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9285 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9286 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
9287 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9288 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9289 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9290 
9291 /* Bit 7 : Write '1' to disable interrupt for event TXDSENT */
9292 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
9293 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
9294 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
9295 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
9296 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
9297 
9298 /* Bit 2 : Write '1' to disable interrupt for event RXDREADY */
9299 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
9300 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
9301 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
9302 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
9303 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
9304 
9305 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9306 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9307 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9308 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9309 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9310 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9311 
9312 /* Register: TWI_ERRORSRC */
9313 /* Description: Error source */
9314 
9315 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
9316 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9317 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
9318 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
9319 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
9320 
9321 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
9322 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
9323 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
9324 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
9325 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
9326 
9327 /* Bit 0 : Overrun error */
9328 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
9329 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
9330 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
9331 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
9332 
9333 /* Register: TWI_ENABLE */
9334 /* Description: Enable TWI */
9335 
9336 /* Bits 3..0 : Enable or disable TWI */
9337 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9338 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9339 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
9340 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
9341 
9342 /* Register: TWI_PSEL_SCL */
9343 /* Description: Pin select for SCL */
9344 
9345 /* Bit 31 : Connection */
9346 #define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9347 #define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9348 #define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
9349 #define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
9350 
9351 /* Bits 4..0 : Pin number */
9352 #define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
9353 #define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
9354 
9355 /* Register: TWI_PSEL_SDA */
9356 /* Description: Pin select for SDA */
9357 
9358 /* Bit 31 : Connection */
9359 #define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9360 #define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9361 #define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
9362 #define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
9363 
9364 /* Bits 4..0 : Pin number */
9365 #define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
9366 #define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
9367 
9368 /* Register: TWI_RXD */
9369 /* Description: RXD register */
9370 
9371 /* Bits 7..0 : RXD register */
9372 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
9373 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
9374 
9375 /* Register: TWI_TXD */
9376 /* Description: TXD register */
9377 
9378 /* Bits 7..0 : TXD register */
9379 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
9380 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
9381 
9382 /* Register: TWI_FREQUENCY */
9383 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
9384 
9385 /* Bits 31..0 : TWI master clock frequency */
9386 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
9387 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
9388 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
9389 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
9390 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
9391 
9392 /* Register: TWI_ADDRESS */
9393 /* Description: Address used in the TWI transfer */
9394 
9395 /* Bits 6..0 : Address used in the TWI transfer */
9396 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
9397 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
9398 
9399 
9400 /* Peripheral: TWIM */
9401 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA */
9402 
9403 /* Register: TWIM_TASKS_STARTRX */
9404 /* Description: Start TWI receive sequence */
9405 
9406 /* Bit 0 : Start TWI receive sequence */
9407 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
9408 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
9409 #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
9410 
9411 /* Register: TWIM_TASKS_STARTTX */
9412 /* Description: Start TWI transmit sequence */
9413 
9414 /* Bit 0 : Start TWI transmit sequence */
9415 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
9416 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
9417 #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
9418 
9419 /* Register: TWIM_TASKS_STOP */
9420 /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */
9421 
9422 /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */
9423 #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9424 #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9425 #define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9426 
9427 /* Register: TWIM_TASKS_SUSPEND */
9428 /* Description: Suspend TWI transaction */
9429 
9430 /* Bit 0 : Suspend TWI transaction */
9431 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
9432 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
9433 #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
9434 
9435 /* Register: TWIM_TASKS_RESUME */
9436 /* Description: Resume TWI transaction */
9437 
9438 /* Bit 0 : Resume TWI transaction */
9439 #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
9440 #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
9441 #define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
9442 
9443 /* Register: TWIM_EVENTS_STOPPED */
9444 /* Description: TWI stopped */
9445 
9446 /* Bit 0 : TWI stopped */
9447 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9448 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9449 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9450 #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9451 
9452 /* Register: TWIM_EVENTS_ERROR */
9453 /* Description: TWI error */
9454 
9455 /* Bit 0 : TWI error */
9456 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
9457 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
9458 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
9459 #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
9460 
9461 /* Register: TWIM_EVENTS_SUSPENDED */
9462 /* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
9463 
9464 /* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */
9465 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */
9466 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */
9467 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */
9468 #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */
9469 
9470 /* Register: TWIM_EVENTS_RXSTARTED */
9471 /* Description: Receive sequence started */
9472 
9473 /* Bit 0 : Receive sequence started */
9474 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
9475 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
9476 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9477 #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
9478 
9479 /* Register: TWIM_EVENTS_TXSTARTED */
9480 /* Description: Transmit sequence started */
9481 
9482 /* Bit 0 : Transmit sequence started */
9483 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
9484 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
9485 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9486 #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
9487 
9488 /* Register: TWIM_EVENTS_LASTRX */
9489 /* Description: Byte boundary, starting to receive the last byte */
9490 
9491 /* Bit 0 : Byte boundary, starting to receive the last byte */
9492 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */
9493 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */
9494 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */
9495 #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */
9496 
9497 /* Register: TWIM_EVENTS_LASTTX */
9498 /* Description: Byte boundary, starting to transmit the last byte */
9499 
9500 /* Bit 0 : Byte boundary, starting to transmit the last byte */
9501 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */
9502 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */
9503 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */
9504 #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */
9505 
9506 /* Register: TWIM_SHORTS */
9507 /* Description: Shortcuts between local events and tasks */
9508 
9509 /* Bit 12 : Shortcut between event LASTRX and task STOP */
9510 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
9511 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
9512 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
9513 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
9514 
9515 /* Bit 11 : Shortcut between event LASTRX and task SUSPEND */
9516 #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */
9517 #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */
9518 #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9519 #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9520 
9521 /* Bit 10 : Shortcut between event LASTRX and task STARTTX */
9522 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
9523 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
9524 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
9525 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
9526 
9527 /* Bit 9 : Shortcut between event LASTTX and task STOP */
9528 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
9529 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
9530 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
9531 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
9532 
9533 /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */
9534 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
9535 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
9536 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9537 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9538 
9539 /* Bit 7 : Shortcut between event LASTTX and task STARTRX */
9540 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
9541 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
9542 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
9543 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
9544 
9545 /* Register: TWIM_INTEN */
9546 /* Description: Enable or disable interrupt */
9547 
9548 /* Bit 24 : Enable or disable interrupt for event LASTTX */
9549 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
9550 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
9551 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
9552 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
9553 
9554 /* Bit 23 : Enable or disable interrupt for event LASTRX */
9555 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
9556 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
9557 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
9558 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
9559 
9560 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
9561 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9562 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9563 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
9564 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
9565 
9566 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
9567 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9568 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9569 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
9570 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
9571 
9572 /* Bit 18 : Enable or disable interrupt for event SUSPENDED */
9573 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9574 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9575 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
9576 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
9577 
9578 /* Bit 9 : Enable or disable interrupt for event ERROR */
9579 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9580 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
9581 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
9582 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
9583 
9584 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9585 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9586 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9587 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9588 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9589 
9590 /* Register: TWIM_INTENSET */
9591 /* Description: Enable interrupt */
9592 
9593 /* Bit 24 : Write '1' to enable interrupt for event LASTTX */
9594 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
9595 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
9596 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
9597 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
9598 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
9599 
9600 /* Bit 23 : Write '1' to enable interrupt for event LASTRX */
9601 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
9602 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
9603 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
9604 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
9605 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
9606 
9607 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
9608 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9609 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9610 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9611 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9612 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
9613 
9614 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
9615 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9616 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9617 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9618 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9619 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
9620 
9621 /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */
9622 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9623 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9624 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9625 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9626 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
9627 
9628 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
9629 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9630 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
9631 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9632 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
9633 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
9634 
9635 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
9636 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9637 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9638 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9639 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9640 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9641 
9642 /* Register: TWIM_INTENCLR */
9643 /* Description: Disable interrupt */
9644 
9645 /* Bit 24 : Write '1' to disable interrupt for event LASTTX */
9646 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
9647 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
9648 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
9649 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
9650 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
9651 
9652 /* Bit 23 : Write '1' to disable interrupt for event LASTRX */
9653 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
9654 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
9655 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
9656 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
9657 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
9658 
9659 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
9660 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9661 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9662 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9663 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9664 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
9665 
9666 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
9667 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9668 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9669 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9670 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
9671 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
9672 
9673 /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */
9674 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
9675 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
9676 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9677 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
9678 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
9679 
9680 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
9681 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9682 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
9683 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9684 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
9685 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
9686 
9687 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
9688 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9689 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9690 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9691 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9692 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9693 
9694 /* Register: TWIM_ERRORSRC */
9695 /* Description: Error source */
9696 
9697 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
9698 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
9699 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
9700 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
9701 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
9702 
9703 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
9704 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
9705 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
9706 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
9707 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
9708 
9709 /* Bit 0 : Overrun error */
9710 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
9711 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
9712 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
9713 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
9714 
9715 /* Register: TWIM_ENABLE */
9716 /* Description: Enable TWIM */
9717 
9718 /* Bits 3..0 : Enable or disable TWIM */
9719 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9720 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9721 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
9722 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
9723 
9724 /* Register: TWIM_PSEL_SCL */
9725 /* Description: Pin select for SCL signal */
9726 
9727 /* Bit 31 : Connection */
9728 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9729 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9730 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
9731 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
9732 
9733 /* Bits 4..0 : Pin number */
9734 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
9735 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
9736 
9737 /* Register: TWIM_PSEL_SDA */
9738 /* Description: Pin select for SDA signal */
9739 
9740 /* Bit 31 : Connection */
9741 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
9742 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
9743 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
9744 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
9745 
9746 /* Bits 4..0 : Pin number */
9747 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
9748 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
9749 
9750 /* Register: TWIM_FREQUENCY */
9751 /* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
9752 
9753 /* Bits 31..0 : TWI master clock frequency */
9754 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
9755 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
9756 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
9757 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
9758 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
9759 
9760 /* Register: TWIM_RXD_PTR */
9761 /* Description: Data pointer */
9762 
9763 /* Bits 31..0 : Data pointer */
9764 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9765 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9766 
9767 /* Register: TWIM_RXD_MAXCNT */
9768 /* Description: Maximum number of bytes in receive buffer */
9769 
9770 /* Bits 9..0 : Maximum number of bytes in receive buffer */
9771 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9772 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9773 
9774 /* Register: TWIM_RXD_AMOUNT */
9775 /* Description: Number of bytes transferred in the last transaction */
9776 
9777 /* Bits 9..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
9778 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9779 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9780 
9781 /* Register: TWIM_RXD_LIST */
9782 /* Description: EasyDMA list type */
9783 
9784 /* Bits 2..0 : List type */
9785 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9786 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9787 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9788 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9789 
9790 /* Register: TWIM_TXD_PTR */
9791 /* Description: Data pointer */
9792 
9793 /* Bits 31..0 : Data pointer */
9794 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
9795 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
9796 
9797 /* Register: TWIM_TXD_MAXCNT */
9798 /* Description: Maximum number of bytes in transmit buffer */
9799 
9800 /* Bits 9..0 : Maximum number of bytes in transmit buffer */
9801 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
9802 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
9803 
9804 /* Register: TWIM_TXD_AMOUNT */
9805 /* Description: Number of bytes transferred in the last transaction */
9806 
9807 /* Bits 9..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
9808 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
9809 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
9810 
9811 /* Register: TWIM_TXD_LIST */
9812 /* Description: EasyDMA list type */
9813 
9814 /* Bits 2..0 : List type */
9815 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
9816 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
9817 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
9818 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
9819 
9820 /* Register: TWIM_ADDRESS */
9821 /* Description: Address used in the TWI transfer */
9822 
9823 /* Bits 6..0 : Address used in the TWI transfer */
9824 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
9825 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
9826 
9827 
9828 /* Peripheral: TWIS */
9829 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA */
9830 
9831 /* Register: TWIS_TASKS_STOP */
9832 /* Description: Stop TWI transaction */
9833 
9834 /* Bit 0 : Stop TWI transaction */
9835 #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
9836 #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
9837 #define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
9838 
9839 /* Register: TWIS_TASKS_SUSPEND */
9840 /* Description: Suspend TWI transaction */
9841 
9842 /* Bit 0 : Suspend TWI transaction */
9843 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
9844 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
9845 #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
9846 
9847 /* Register: TWIS_TASKS_RESUME */
9848 /* Description: Resume TWI transaction */
9849 
9850 /* Bit 0 : Resume TWI transaction */
9851 #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */
9852 #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */
9853 #define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */
9854 
9855 /* Register: TWIS_TASKS_PREPARERX */
9856 /* Description: Prepare the TWI slave to respond to a write command */
9857 
9858 /* Bit 0 : Prepare the TWI slave to respond to a write command */
9859 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */
9860 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */
9861 #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */
9862 
9863 /* Register: TWIS_TASKS_PREPARETX */
9864 /* Description: Prepare the TWI slave to respond to a read command */
9865 
9866 /* Bit 0 : Prepare the TWI slave to respond to a read command */
9867 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */
9868 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */
9869 #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */
9870 
9871 /* Register: TWIS_EVENTS_STOPPED */
9872 /* Description: TWI stopped */
9873 
9874 /* Bit 0 : TWI stopped */
9875 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */
9876 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */
9877 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */
9878 #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */
9879 
9880 /* Register: TWIS_EVENTS_ERROR */
9881 /* Description: TWI error */
9882 
9883 /* Bit 0 : TWI error */
9884 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
9885 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
9886 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
9887 #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
9888 
9889 /* Register: TWIS_EVENTS_RXSTARTED */
9890 /* Description: Receive sequence started */
9891 
9892 /* Bit 0 : Receive sequence started */
9893 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
9894 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
9895 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9896 #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
9897 
9898 /* Register: TWIS_EVENTS_TXSTARTED */
9899 /* Description: Transmit sequence started */
9900 
9901 /* Bit 0 : Transmit sequence started */
9902 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
9903 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
9904 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
9905 #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
9906 
9907 /* Register: TWIS_EVENTS_WRITE */
9908 /* Description: Write command received */
9909 
9910 /* Bit 0 : Write command received */
9911 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */
9912 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */
9913 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */
9914 #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */
9915 
9916 /* Register: TWIS_EVENTS_READ */
9917 /* Description: Read command received */
9918 
9919 /* Bit 0 : Read command received */
9920 #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */
9921 #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */
9922 #define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */
9923 #define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */
9924 
9925 /* Register: TWIS_SHORTS */
9926 /* Description: Shortcuts between local events and tasks */
9927 
9928 /* Bit 14 : Shortcut between event READ and task SUSPEND */
9929 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
9930 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
9931 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9932 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9933 
9934 /* Bit 13 : Shortcut between event WRITE and task SUSPEND */
9935 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
9936 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
9937 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
9938 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
9939 
9940 /* Register: TWIS_INTEN */
9941 /* Description: Enable or disable interrupt */
9942 
9943 /* Bit 26 : Enable or disable interrupt for event READ */
9944 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
9945 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
9946 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
9947 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
9948 
9949 /* Bit 25 : Enable or disable interrupt for event WRITE */
9950 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9951 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
9952 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
9953 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
9954 
9955 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
9956 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9957 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9958 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
9959 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
9960 
9961 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
9962 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
9963 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
9964 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
9965 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
9966 
9967 /* Bit 9 : Enable or disable interrupt for event ERROR */
9968 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
9969 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
9970 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
9971 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
9972 
9973 /* Bit 1 : Enable or disable interrupt for event STOPPED */
9974 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
9975 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9976 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9977 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9978 
9979 /* Register: TWIS_INTENSET */
9980 /* Description: Enable interrupt */
9981 
9982 /* Bit 26 : Write '1' to enable interrupt for event READ */
9983 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
9984 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
9985 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
9986 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
9987 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
9988 
9989 /* Bit 25 : Write '1' to enable interrupt for event WRITE */
9990 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
9991 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
9992 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
9993 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
9994 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
9995 
9996 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
9997 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
9998 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
9999 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10000 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10001 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
10002 
10003 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
10004 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10005 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10006 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10007 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10008 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
10009 
10010 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
10011 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10012 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
10013 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
10014 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
10015 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
10016 
10017 /* Bit 1 : Write '1' to enable interrupt for event STOPPED */
10018 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10019 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10020 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10021 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10022 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
10023 
10024 /* Register: TWIS_INTENCLR */
10025 /* Description: Disable interrupt */
10026 
10027 /* Bit 26 : Write '1' to disable interrupt for event READ */
10028 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
10029 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
10030 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
10031 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
10032 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
10033 
10034 /* Bit 25 : Write '1' to disable interrupt for event WRITE */
10035 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
10036 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
10037 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
10038 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
10039 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
10040 
10041 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
10042 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10043 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10044 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10045 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10046 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
10047 
10048 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
10049 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10050 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10051 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10052 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10053 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
10054 
10055 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
10056 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10057 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
10058 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
10059 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
10060 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
10061 
10062 /* Bit 1 : Write '1' to disable interrupt for event STOPPED */
10063 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10064 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10065 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10066 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10067 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
10068 
10069 /* Register: TWIS_ERRORSRC */
10070 /* Description: Error source */
10071 
10072 /* Bit 3 : TX buffer over-read detected, and prevented */
10073 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
10074 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
10075 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
10076 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
10077 
10078 /* Bit 2 : NACK sent after receiving a data byte */
10079 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
10080 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
10081 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
10082 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
10083 
10084 /* Bit 0 : RX buffer overflow detected, and prevented */
10085 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
10086 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
10087 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
10088 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
10089 
10090 /* Register: TWIS_MATCH */
10091 /* Description: Status register indicating which address had a match */
10092 
10093 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
10094 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
10095 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
10096 
10097 /* Register: TWIS_ENABLE */
10098 /* Description: Enable TWIS */
10099 
10100 /* Bits 3..0 : Enable or disable TWIS */
10101 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10102 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10103 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
10104 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
10105 
10106 /* Register: TWIS_PSEL_SCL */
10107 /* Description: Pin select for SCL signal */
10108 
10109 /* Bit 31 : Connection */
10110 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10111 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10112 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
10113 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
10114 
10115 /* Bits 4..0 : Pin number */
10116 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
10117 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
10118 
10119 /* Register: TWIS_PSEL_SDA */
10120 /* Description: Pin select for SDA signal */
10121 
10122 /* Bit 31 : Connection */
10123 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10124 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10125 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
10126 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
10127 
10128 /* Bits 4..0 : Pin number */
10129 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
10130 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
10131 
10132 /* Register: TWIS_RXD_PTR */
10133 /* Description: RXD Data pointer */
10134 
10135 /* Bits 31..0 : RXD Data pointer */
10136 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10137 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10138 
10139 /* Register: TWIS_RXD_MAXCNT */
10140 /* Description: Maximum number of bytes in RXD buffer */
10141 
10142 /* Bits 9..0 : Maximum number of bytes in RXD buffer */
10143 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10144 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10145 
10146 /* Register: TWIS_RXD_AMOUNT */
10147 /* Description: Number of bytes transferred in the last RXD transaction */
10148 
10149 /* Bits 9..0 : Number of bytes transferred in the last RXD transaction */
10150 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10151 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10152 
10153 /* Register: TWIS_RXD_LIST */
10154 /* Description: EasyDMA list type */
10155 
10156 /* Bits 1..0 : List type */
10157 #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
10158 #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
10159 #define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
10160 #define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
10161 
10162 /* Register: TWIS_TXD_PTR */
10163 /* Description: TXD Data pointer */
10164 
10165 /* Bits 31..0 : TXD Data pointer */
10166 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10167 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10168 
10169 /* Register: TWIS_TXD_MAXCNT */
10170 /* Description: Maximum number of bytes in TXD buffer */
10171 
10172 /* Bits 9..0 : Maximum number of bytes in TXD buffer */
10173 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10174 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10175 
10176 /* Register: TWIS_TXD_AMOUNT */
10177 /* Description: Number of bytes transferred in the last TXD transaction */
10178 
10179 /* Bits 9..0 : Number of bytes transferred in the last TXD transaction */
10180 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10181 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10182 
10183 /* Register: TWIS_TXD_LIST */
10184 /* Description: EasyDMA list type */
10185 
10186 /* Bits 1..0 : List type */
10187 #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
10188 #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
10189 #define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
10190 #define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
10191 
10192 /* Register: TWIS_ADDRESS */
10193 /* Description: Description collection: TWI slave address n */
10194 
10195 /* Bits 6..0 : TWI slave address */
10196 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
10197 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
10198 
10199 /* Register: TWIS_CONFIG */
10200 /* Description: Configuration register for the address match mechanism */
10201 
10202 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
10203 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
10204 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
10205 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
10206 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
10207 
10208 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
10209 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
10210 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
10211 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
10212 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
10213 
10214 /* Register: TWIS_ORC */
10215 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
10216 
10217 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
10218 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
10219 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
10220 
10221 
10222 /* Peripheral: UART */
10223 /* Description: Universal Asynchronous Receiver/Transmitter */
10224 
10225 /* Register: UART_TASKS_STARTRX */
10226 /* Description: Start UART receiver */
10227 
10228 /* Bit 0 : Start UART receiver */
10229 #define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
10230 #define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
10231 #define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
10232 
10233 /* Register: UART_TASKS_STOPRX */
10234 /* Description: Stop UART receiver */
10235 
10236 /* Bit 0 : Stop UART receiver */
10237 #define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
10238 #define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
10239 #define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
10240 
10241 /* Register: UART_TASKS_STARTTX */
10242 /* Description: Start UART transmitter */
10243 
10244 /* Bit 0 : Start UART transmitter */
10245 #define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
10246 #define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
10247 #define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
10248 
10249 /* Register: UART_TASKS_STOPTX */
10250 /* Description: Stop UART transmitter */
10251 
10252 /* Bit 0 : Stop UART transmitter */
10253 #define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
10254 #define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
10255 #define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
10256 
10257 /* Register: UART_TASKS_SUSPEND */
10258 /* Description: Suspend UART */
10259 
10260 /* Bit 0 : Suspend UART */
10261 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */
10262 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */
10263 #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */
10264 
10265 /* Register: UART_EVENTS_CTS */
10266 /* Description: CTS is activated (set low). Clear To Send. */
10267 
10268 /* Bit 0 : CTS is activated (set low). Clear To Send. */
10269 #define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
10270 #define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
10271 #define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
10272 #define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
10273 
10274 /* Register: UART_EVENTS_NCTS */
10275 /* Description: CTS is deactivated (set high). Not Clear To Send. */
10276 
10277 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
10278 #define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
10279 #define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
10280 #define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
10281 #define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
10282 
10283 /* Register: UART_EVENTS_RXDRDY */
10284 /* Description: Data received in RXD */
10285 
10286 /* Bit 0 : Data received in RXD */
10287 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
10288 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
10289 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
10290 #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
10291 
10292 /* Register: UART_EVENTS_TXDRDY */
10293 /* Description: Data sent from TXD */
10294 
10295 /* Bit 0 : Data sent from TXD */
10296 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
10297 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
10298 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
10299 #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
10300 
10301 /* Register: UART_EVENTS_ERROR */
10302 /* Description: Error detected */
10303 
10304 /* Bit 0 : Error detected */
10305 #define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
10306 #define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
10307 #define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
10308 #define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
10309 
10310 /* Register: UART_EVENTS_RXTO */
10311 /* Description: Receiver timeout */
10312 
10313 /* Bit 0 : Receiver timeout */
10314 #define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
10315 #define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
10316 #define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
10317 #define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
10318 
10319 /* Register: UART_SHORTS */
10320 /* Description: Shortcuts between local events and tasks */
10321 
10322 /* Bit 4 : Shortcut between event NCTS and task STOPRX */
10323 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
10324 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
10325 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
10326 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
10327 
10328 /* Bit 3 : Shortcut between event CTS and task STARTRX */
10329 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
10330 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
10331 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
10332 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
10333 
10334 /* Register: UART_INTENSET */
10335 /* Description: Enable interrupt */
10336 
10337 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
10338 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10339 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
10340 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
10341 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
10342 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
10343 
10344 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
10345 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10346 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
10347 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
10348 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
10349 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
10350 
10351 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
10352 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10353 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10354 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10355 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10356 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
10357 
10358 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
10359 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10360 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10361 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10362 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10363 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
10364 
10365 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
10366 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10367 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
10368 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
10369 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
10370 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
10371 
10372 /* Bit 0 : Write '1' to enable interrupt for event CTS */
10373 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
10374 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
10375 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
10376 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
10377 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
10378 
10379 /* Register: UART_INTENCLR */
10380 /* Description: Disable interrupt */
10381 
10382 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
10383 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10384 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
10385 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
10386 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
10387 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
10388 
10389 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
10390 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10391 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
10392 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
10393 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
10394 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
10395 
10396 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
10397 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10398 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10399 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10400 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10401 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
10402 
10403 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
10404 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10405 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10406 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10407 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10408 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
10409 
10410 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
10411 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10412 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
10413 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
10414 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
10415 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
10416 
10417 /* Bit 0 : Write '1' to disable interrupt for event CTS */
10418 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
10419 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
10420 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
10421 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
10422 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
10423 
10424 /* Register: UART_ERRORSRC */
10425 /* Description: Error source */
10426 
10427 /* Bit 3 : Break condition */
10428 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
10429 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
10430 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
10431 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
10432 
10433 /* Bit 2 : Framing error occurred */
10434 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
10435 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
10436 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
10437 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
10438 
10439 /* Bit 1 : Parity error */
10440 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10441 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
10442 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
10443 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
10444 
10445 /* Bit 0 : Overrun error */
10446 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
10447 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
10448 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
10449 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
10450 
10451 /* Register: UART_ENABLE */
10452 /* Description: Enable UART */
10453 
10454 /* Bits 3..0 : Enable or disable UART */
10455 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10456 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10457 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
10458 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
10459 
10460 /* Register: UART_PSEL_RTS */
10461 /* Description: Pin select for RTS */
10462 
10463 /* Bit 31 : Connection */
10464 #define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10465 #define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10466 #define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
10467 #define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
10468 
10469 /* Bits 4..0 : Pin number */
10470 #define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
10471 #define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
10472 
10473 /* Register: UART_PSEL_TXD */
10474 /* Description: Pin select for TXD */
10475 
10476 /* Bit 31 : Connection */
10477 #define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10478 #define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10479 #define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
10480 #define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
10481 
10482 /* Bits 4..0 : Pin number */
10483 #define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
10484 #define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
10485 
10486 /* Register: UART_PSEL_CTS */
10487 /* Description: Pin select for CTS */
10488 
10489 /* Bit 31 : Connection */
10490 #define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10491 #define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10492 #define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
10493 #define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
10494 
10495 /* Bits 4..0 : Pin number */
10496 #define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
10497 #define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
10498 
10499 /* Register: UART_PSEL_RXD */
10500 /* Description: Pin select for RXD */
10501 
10502 /* Bit 31 : Connection */
10503 #define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10504 #define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10505 #define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
10506 #define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
10507 
10508 /* Bits 4..0 : Pin number */
10509 #define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
10510 #define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
10511 
10512 /* Register: UART_RXD */
10513 /* Description: RXD register */
10514 
10515 /* Bits 7..0 : RX data received in previous transfers, double buffered */
10516 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
10517 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
10518 
10519 /* Register: UART_TXD */
10520 /* Description: TXD register */
10521 
10522 /* Bits 7..0 : TX data to be transferred */
10523 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
10524 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
10525 
10526 /* Register: UART_BAUDRATE */
10527 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
10528 
10529 /* Bits 31..0 : Baud rate */
10530 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
10531 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
10532 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
10533 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
10534 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
10535 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
10536 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
10537 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
10538 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
10539 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
10540 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
10541 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
10542 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
10543 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
10544 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
10545 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
10546 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
10547 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
10548 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
10549 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
10550 
10551 /* Register: UART_CONFIG */
10552 /* Description: Configuration of parity and hardware flow control */
10553 
10554 /* Bit 4 : Stop bits */
10555 #define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
10556 #define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
10557 #define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */
10558 #define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
10559 
10560 /* Bits 3..1 : Parity */
10561 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10562 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
10563 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
10564 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
10565 
10566 /* Bit 0 : Hardware flow control */
10567 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
10568 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
10569 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
10570 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
10571 
10572 
10573 /* Peripheral: UARTE */
10574 /* Description: UART with EasyDMA */
10575 
10576 /* Register: UARTE_TASKS_STARTRX */
10577 /* Description: Start UART receiver */
10578 
10579 /* Bit 0 : Start UART receiver */
10580 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */
10581 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */
10582 #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */
10583 
10584 /* Register: UARTE_TASKS_STOPRX */
10585 /* Description: Stop UART receiver */
10586 
10587 /* Bit 0 : Stop UART receiver */
10588 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */
10589 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */
10590 #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */
10591 
10592 /* Register: UARTE_TASKS_STARTTX */
10593 /* Description: Start UART transmitter */
10594 
10595 /* Bit 0 : Start UART transmitter */
10596 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */
10597 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */
10598 #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */
10599 
10600 /* Register: UARTE_TASKS_STOPTX */
10601 /* Description: Stop UART transmitter */
10602 
10603 /* Bit 0 : Stop UART transmitter */
10604 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */
10605 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */
10606 #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */
10607 
10608 /* Register: UARTE_TASKS_FLUSHRX */
10609 /* Description: Flush RX FIFO into RX buffer */
10610 
10611 /* Bit 0 : Flush RX FIFO into RX buffer */
10612 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */
10613 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */
10614 #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */
10615 
10616 /* Register: UARTE_EVENTS_CTS */
10617 /* Description: CTS is activated (set low). Clear To Send. */
10618 
10619 /* Bit 0 : CTS is activated (set low). Clear To Send. */
10620 #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */
10621 #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */
10622 #define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */
10623 #define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */
10624 
10625 /* Register: UARTE_EVENTS_NCTS */
10626 /* Description: CTS is deactivated (set high). Not Clear To Send. */
10627 
10628 /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */
10629 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */
10630 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */
10631 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */
10632 #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */
10633 
10634 /* Register: UARTE_EVENTS_RXDRDY */
10635 /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */
10636 
10637 /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */
10638 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */
10639 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */
10640 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */
10641 #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */
10642 
10643 /* Register: UARTE_EVENTS_ENDRX */
10644 /* Description: Receive buffer is filled up */
10645 
10646 /* Bit 0 : Receive buffer is filled up */
10647 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */
10648 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */
10649 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */
10650 #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */
10651 
10652 /* Register: UARTE_EVENTS_TXDRDY */
10653 /* Description: Data sent from TXD */
10654 
10655 /* Bit 0 : Data sent from TXD */
10656 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */
10657 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */
10658 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */
10659 #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */
10660 
10661 /* Register: UARTE_EVENTS_ENDTX */
10662 /* Description: Last TX byte transmitted */
10663 
10664 /* Bit 0 : Last TX byte transmitted */
10665 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */
10666 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */
10667 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */
10668 #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */
10669 
10670 /* Register: UARTE_EVENTS_ERROR */
10671 /* Description: Error detected */
10672 
10673 /* Bit 0 : Error detected */
10674 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
10675 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
10676 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
10677 #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
10678 
10679 /* Register: UARTE_EVENTS_RXTO */
10680 /* Description: Receiver timeout */
10681 
10682 /* Bit 0 : Receiver timeout */
10683 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */
10684 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */
10685 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */
10686 #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */
10687 
10688 /* Register: UARTE_EVENTS_RXSTARTED */
10689 /* Description: UART receiver has started */
10690 
10691 /* Bit 0 : UART receiver has started */
10692 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */
10693 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */
10694 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */
10695 #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */
10696 
10697 /* Register: UARTE_EVENTS_TXSTARTED */
10698 /* Description: UART transmitter has started */
10699 
10700 /* Bit 0 : UART transmitter has started */
10701 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */
10702 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */
10703 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */
10704 #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */
10705 
10706 /* Register: UARTE_EVENTS_TXSTOPPED */
10707 /* Description: Transmitter stopped */
10708 
10709 /* Bit 0 : Transmitter stopped */
10710 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */
10711 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */
10712 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */
10713 #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */
10714 
10715 /* Register: UARTE_SHORTS */
10716 /* Description: Shortcuts between local events and tasks */
10717 
10718 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
10719 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
10720 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
10721 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
10722 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
10723 
10724 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
10725 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
10726 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
10727 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
10728 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
10729 
10730 /* Register: UARTE_INTEN */
10731 /* Description: Enable or disable interrupt */
10732 
10733 /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */
10734 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10735 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10736 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
10737 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
10738 
10739 /* Bit 20 : Enable or disable interrupt for event TXSTARTED */
10740 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10741 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10742 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
10743 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
10744 
10745 /* Bit 19 : Enable or disable interrupt for event RXSTARTED */
10746 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10747 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10748 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
10749 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
10750 
10751 /* Bit 17 : Enable or disable interrupt for event RXTO */
10752 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10753 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
10754 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
10755 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
10756 
10757 /* Bit 9 : Enable or disable interrupt for event ERROR */
10758 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10759 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
10760 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
10761 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
10762 
10763 /* Bit 8 : Enable or disable interrupt for event ENDTX */
10764 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10765 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10766 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
10767 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
10768 
10769 /* Bit 7 : Enable or disable interrupt for event TXDRDY */
10770 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10771 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10772 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
10773 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
10774 
10775 /* Bit 4 : Enable or disable interrupt for event ENDRX */
10776 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10777 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10778 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
10779 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
10780 
10781 /* Bit 2 : Enable or disable interrupt for event RXDRDY */
10782 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10783 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10784 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
10785 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
10786 
10787 /* Bit 1 : Enable or disable interrupt for event NCTS */
10788 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10789 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
10790 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
10791 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
10792 
10793 /* Bit 0 : Enable or disable interrupt for event CTS */
10794 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
10795 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
10796 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
10797 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
10798 
10799 /* Register: UARTE_INTENSET */
10800 /* Description: Enable interrupt */
10801 
10802 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
10803 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10804 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10805 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10806 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10807 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
10808 
10809 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
10810 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10811 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10812 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10813 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10814 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
10815 
10816 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
10817 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10818 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10819 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10820 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10821 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
10822 
10823 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
10824 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10825 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
10826 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
10827 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
10828 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
10829 
10830 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
10831 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10832 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
10833 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
10834 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
10835 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
10836 
10837 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
10838 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10839 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10840 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10841 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10842 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
10843 
10844 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
10845 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10846 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10847 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10848 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10849 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
10850 
10851 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
10852 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10853 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10854 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10855 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10856 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10857 
10858 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
10859 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10860 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10861 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10862 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10863 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
10864 
10865 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
10866 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10867 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
10868 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
10869 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
10870 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
10871 
10872 /* Bit 0 : Write '1' to enable interrupt for event CTS */
10873 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
10874 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
10875 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
10876 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
10877 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
10878 
10879 /* Register: UARTE_INTENCLR */
10880 /* Description: Disable interrupt */
10881 
10882 /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */
10883 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
10884 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
10885 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10886 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
10887 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
10888 
10889 /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */
10890 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
10891 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
10892 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10893 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10894 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
10895 
10896 /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */
10897 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
10898 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
10899 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10900 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
10901 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
10902 
10903 /* Bit 17 : Write '1' to disable interrupt for event RXTO */
10904 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
10905 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
10906 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
10907 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
10908 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
10909 
10910 /* Bit 9 : Write '1' to disable interrupt for event ERROR */
10911 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
10912 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
10913 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
10914 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
10915 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
10916 
10917 /* Bit 8 : Write '1' to disable interrupt for event ENDTX */
10918 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10919 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10920 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10921 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10922 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
10923 
10924 /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */
10925 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
10926 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
10927 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10928 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
10929 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
10930 
10931 /* Bit 4 : Write '1' to disable interrupt for event ENDRX */
10932 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10933 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10934 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10935 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10936 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10937 
10938 /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */
10939 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
10940 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
10941 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10942 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
10943 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
10944 
10945 /* Bit 1 : Write '1' to disable interrupt for event NCTS */
10946 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
10947 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
10948 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
10949 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
10950 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
10951 
10952 /* Bit 0 : Write '1' to disable interrupt for event CTS */
10953 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
10954 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
10955 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
10956 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
10957 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
10958 
10959 /* Register: UARTE_ERRORSRC */
10960 /* Description: Error source Note : this register is read / write one to clear. */
10961 
10962 /* Bit 3 : Break condition */
10963 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
10964 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
10965 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
10966 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
10967 
10968 /* Bit 2 : Framing error occurred */
10969 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
10970 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
10971 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
10972 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
10973 
10974 /* Bit 1 : Parity error */
10975 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
10976 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
10977 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
10978 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
10979 
10980 /* Bit 0 : Overrun error */
10981 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
10982 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
10983 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
10984 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
10985 
10986 /* Register: UARTE_ENABLE */
10987 /* Description: Enable UART */
10988 
10989 /* Bits 3..0 : Enable or disable UARTE */
10990 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10991 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10992 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
10993 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
10994 
10995 /* Register: UARTE_PSEL_RTS */
10996 /* Description: Pin select for RTS signal */
10997 
10998 /* Bit 31 : Connection */
10999 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11000 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11001 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
11002 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
11003 
11004 /* Bits 4..0 : Pin number */
11005 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
11006 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
11007 
11008 /* Register: UARTE_PSEL_TXD */
11009 /* Description: Pin select for TXD signal */
11010 
11011 /* Bit 31 : Connection */
11012 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11013 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11014 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
11015 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
11016 
11017 /* Bits 4..0 : Pin number */
11018 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
11019 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
11020 
11021 /* Register: UARTE_PSEL_CTS */
11022 /* Description: Pin select for CTS signal */
11023 
11024 /* Bit 31 : Connection */
11025 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11026 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11027 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
11028 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
11029 
11030 /* Bits 4..0 : Pin number */
11031 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
11032 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
11033 
11034 /* Register: UARTE_PSEL_RXD */
11035 /* Description: Pin select for RXD signal */
11036 
11037 /* Bit 31 : Connection */
11038 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11039 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11040 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
11041 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
11042 
11043 /* Bits 4..0 : Pin number */
11044 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
11045 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
11046 
11047 /* Register: UARTE_BAUDRATE */
11048 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
11049 
11050 /* Bits 31..0 : Baud rate */
11051 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
11052 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
11053 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
11054 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
11055 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
11056 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
11057 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
11058 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
11059 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
11060 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
11061 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
11062 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
11063 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
11064 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
11065 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
11066 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
11067 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
11068 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
11069 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
11070 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
11071 
11072 /* Register: UARTE_RXD_PTR */
11073 /* Description: Data pointer */
11074 
11075 /* Bits 31..0 : Data pointer */
11076 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11077 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11078 
11079 /* Register: UARTE_RXD_MAXCNT */
11080 /* Description: Maximum number of bytes in receive buffer */
11081 
11082 /* Bits 9..0 : Maximum number of bytes in receive buffer */
11083 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11084 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11085 
11086 /* Register: UARTE_RXD_AMOUNT */
11087 /* Description: Number of bytes transferred in the last transaction */
11088 
11089 /* Bits 9..0 : Number of bytes transferred in the last transaction */
11090 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11091 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11092 
11093 /* Register: UARTE_TXD_PTR */
11094 /* Description: Data pointer */
11095 
11096 /* Bits 31..0 : Data pointer */
11097 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11098 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11099 
11100 /* Register: UARTE_TXD_MAXCNT */
11101 /* Description: Maximum number of bytes in transmit buffer */
11102 
11103 /* Bits 9..0 : Maximum number of bytes in transmit buffer */
11104 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11105 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11106 
11107 /* Register: UARTE_TXD_AMOUNT */
11108 /* Description: Number of bytes transferred in the last transaction */
11109 
11110 /* Bits 9..0 : Number of bytes transferred in the last transaction */
11111 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11112 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11113 
11114 /* Register: UARTE_CONFIG */
11115 /* Description: Configuration of parity and hardware flow control */
11116 
11117 /* Bit 4 : Stop bits */
11118 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
11119 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
11120 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
11121 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
11122 
11123 /* Bits 3..1 : Parity */
11124 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
11125 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
11126 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
11127 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
11128 
11129 /* Bit 0 : Hardware flow control */
11130 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
11131 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
11132 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
11133 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
11134 
11135 
11136 /* Peripheral: UICR */
11137 /* Description: User information configuration registers */
11138 
11139 /* Register: UICR_NRFFW */
11140 /* Description: Description collection: Reserved for Nordic firmware design */
11141 
11142 /* Bits 31..0 : Reserved for Nordic firmware design */
11143 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
11144 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
11145 
11146 /* Register: UICR_NRFHW */
11147 /* Description: Description collection: Reserved for Nordic hardware design */
11148 
11149 /* Bits 31..0 : Reserved for Nordic hardware design */
11150 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
11151 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
11152 
11153 /* Register: UICR_CUSTOMER */
11154 /* Description: Description collection: Reserved for customer */
11155 
11156 /* Bits 31..0 : Reserved for customer */
11157 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
11158 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
11159 
11160 /* Register: UICR_NRFMDK */
11161 /* Description: Description collection: Reserved for Nordic MDK */
11162 
11163 /* Bits 31..0 : Reserved for Nordic MDK */
11164 #define UICR_NRFMDK_NRFMDK_Pos (0UL) /*!< Position of NRFMDK field. */
11165 #define UICR_NRFMDK_NRFMDK_Msk (0xFFFFFFFFUL << UICR_NRFMDK_NRFMDK_Pos) /*!< Bit mask of NRFMDK field. */
11166 
11167 /* Register: UICR_PSELRESET */
11168 /* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */
11169 
11170 /* Bit 31 : Connection */
11171 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11172 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11173 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
11174 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
11175 
11176 /* Bits 4..0 : GPIO pin number onto which nRESET is exposed */
11177 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
11178 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
11179 
11180 /* Register: UICR_APPROTECT */
11181 /* Description: Access port protection */
11182 
11183 /* Bits 7..0 : Enable or disable access port protection. */
11184 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
11185 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
11186 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
11187 #define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */
11188 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */
11189 
11190 
11191 /* Peripheral: WDT */
11192 /* Description: Watchdog Timer */
11193 
11194 /* Register: WDT_TASKS_START */
11195 /* Description: Start the watchdog */
11196 
11197 /* Bit 0 : Start the watchdog */
11198 #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
11199 #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
11200 #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
11201 
11202 /* Register: WDT_EVENTS_TIMEOUT */
11203 /* Description: Watchdog timeout */
11204 
11205 /* Bit 0 : Watchdog timeout */
11206 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */
11207 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */
11208 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */
11209 #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */
11210 
11211 /* Register: WDT_INTENSET */
11212 /* Description: Enable interrupt */
11213 
11214 /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */
11215 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
11216 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
11217 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
11218 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
11219 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
11220 
11221 /* Register: WDT_INTENCLR */
11222 /* Description: Disable interrupt */
11223 
11224 /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */
11225 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
11226 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
11227 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
11228 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
11229 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
11230 
11231 /* Register: WDT_RUNSTATUS */
11232 /* Description: Run status */
11233 
11234 /* Bit 0 : Indicates whether or not the watchdog is running */
11235 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
11236 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
11237 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
11238 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
11239 
11240 /* Register: WDT_REQSTATUS */
11241 /* Description: Request status */
11242 
11243 /* Bit 7 : Request status for RR[7] register */
11244 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
11245 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
11246 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
11247 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
11248 
11249 /* Bit 6 : Request status for RR[6] register */
11250 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
11251 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
11252 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
11253 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
11254 
11255 /* Bit 5 : Request status for RR[5] register */
11256 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
11257 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
11258 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
11259 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
11260 
11261 /* Bit 4 : Request status for RR[4] register */
11262 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
11263 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
11264 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
11265 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
11266 
11267 /* Bit 3 : Request status for RR[3] register */
11268 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
11269 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
11270 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
11271 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
11272 
11273 /* Bit 2 : Request status for RR[2] register */
11274 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
11275 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
11276 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
11277 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
11278 
11279 /* Bit 1 : Request status for RR[1] register */
11280 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
11281 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
11282 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
11283 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
11284 
11285 /* Bit 0 : Request status for RR[0] register */
11286 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
11287 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
11288 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
11289 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
11290 
11291 /* Register: WDT_CRV */
11292 /* Description: Counter reload value */
11293 
11294 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
11295 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
11296 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
11297 
11298 /* Register: WDT_RREN */
11299 /* Description: Enable register for reload request registers */
11300 
11301 /* Bit 7 : Enable or disable RR[7] register */
11302 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
11303 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
11304 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
11305 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
11306 
11307 /* Bit 6 : Enable or disable RR[6] register */
11308 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
11309 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
11310 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
11311 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
11312 
11313 /* Bit 5 : Enable or disable RR[5] register */
11314 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
11315 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
11316 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
11317 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
11318 
11319 /* Bit 4 : Enable or disable RR[4] register */
11320 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
11321 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
11322 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
11323 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
11324 
11325 /* Bit 3 : Enable or disable RR[3] register */
11326 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
11327 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
11328 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
11329 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
11330 
11331 /* Bit 2 : Enable or disable RR[2] register */
11332 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
11333 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
11334 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
11335 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
11336 
11337 /* Bit 1 : Enable or disable RR[1] register */
11338 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
11339 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
11340 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
11341 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
11342 
11343 /* Bit 0 : Enable or disable RR[0] register */
11344 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
11345 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
11346 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
11347 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
11348 
11349 /* Register: WDT_CONFIG */
11350 /* Description: Configuration register */
11351 
11352 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
11353 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
11354 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
11355 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
11356 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
11357 
11358 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
11359 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
11360 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
11361 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
11362 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
11363 
11364 /* Register: WDT_RR */
11365 /* Description: Description collection: Reload request n */
11366 
11367 /* Bits 31..0 : Reload request register */
11368 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
11369 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
11370 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
11371 
11372 
11373 /*lint --flb "Leave library region" */
11374 #endif
11375