1 /* 2 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. 3 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, this 10 list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its 17 contributors may be used to endorse or promote products derived from this 18 software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 * 32 * @file nrf52.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 22. June 2023 36 * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:14 37 * from File 'nrf52.svd', 38 * last modified on Thursday, 22.06.2023 06:51:53 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf52 49 * @{ 50 */ 51 52 53 #ifndef NRF52_H 54 #define NRF52_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 82 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 83 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 84 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 85 /* =========================================== nrf52 Specific Interrupt Numbers ============================================ */ 86 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 87 RADIO_IRQn = 1, /*!< 1 RADIO */ 88 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 89 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ 90 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ 91 NFCT_IRQn = 5, /*!< 5 NFCT */ 92 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 93 SAADC_IRQn = 7, /*!< 7 SAADC */ 94 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 95 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 96 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 97 RTC0_IRQn = 11, /*!< 11 RTC0 */ 98 TEMP_IRQn = 12, /*!< 12 TEMP */ 99 RNG_IRQn = 13, /*!< 13 RNG */ 100 ECB_IRQn = 14, /*!< 14 ECB */ 101 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 102 WDT_IRQn = 16, /*!< 16 WDT */ 103 RTC1_IRQn = 17, /*!< 17 RTC1 */ 104 QDEC_IRQn = 18, /*!< 18 QDEC */ 105 COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ 106 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 107 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 108 SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ 109 SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ 110 SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ 111 SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ 112 TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 113 TIMER4_IRQn = 27, /*!< 27 TIMER4 */ 114 PWM0_IRQn = 28, /*!< 28 PWM0 */ 115 PDM_IRQn = 29, /*!< 29 PDM */ 116 MWU_IRQn = 32, /*!< 32 MWU */ 117 PWM1_IRQn = 33, /*!< 33 PWM1 */ 118 PWM2_IRQn = 34, /*!< 34 PWM2 */ 119 SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ 120 RTC2_IRQn = 36, /*!< 36 RTC2 */ 121 I2S_IRQn = 37, /*!< 37 I2S */ 122 FPU_IRQn = 38 /*!< 38 FPU */ 123 } IRQn_Type; 124 125 126 127 /* =========================================================================================================================== */ 128 /* ================ Processor and Core Peripheral Section ================ */ 129 /* =========================================================================================================================== */ 130 131 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 132 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 133 #define __INTERRUPTS_MAX 112 /*!< Top interrupt number */ 134 #define __DSP_PRESENT 1 /*!< DSP present or not */ 135 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 136 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 137 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 138 #define __MPU_PRESENT 1 /*!< MPU present */ 139 #define __FPU_PRESENT 1 /*!< FPU present */ 140 141 142 /** @} */ /* End of group Configuration_of_CMSIS */ 143 144 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 145 #include "system_nrf52.h" /*!< nrf52 System */ 146 147 #ifndef __IM /*!< Fallback for older CMSIS versions */ 148 #define __IM __I 149 #endif 150 #ifndef __OM /*!< Fallback for older CMSIS versions */ 151 #define __OM __O 152 #endif 153 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 154 #define __IOM __IO 155 #endif 156 157 158 /* ======================================== Start of section using anonymous unions ======================================== */ 159 #if defined (__CC_ARM) 160 #pragma push 161 #pragma anon_unions 162 #elif defined (__ICCARM__) 163 #pragma language=extended 164 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 165 #pragma clang diagnostic push 166 #pragma clang diagnostic ignored "-Wc11-extensions" 167 #pragma clang diagnostic ignored "-Wreserved-id-macro" 168 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 169 #pragma clang diagnostic ignored "-Wnested-anon-types" 170 #elif defined (__GNUC__) 171 /* anonymous unions are enabled by default */ 172 #elif defined (__TMS470__) 173 /* anonymous unions are enabled by default */ 174 #elif defined (__TASKING__) 175 #pragma warning 586 176 #elif defined (__CSMC__) 177 /* anonymous unions are enabled by default */ 178 #else 179 #warning Not supported compiler type 180 #endif 181 182 183 /* =========================================================================================================================== */ 184 /* ================ Device Specific Cluster Section ================ */ 185 /* =========================================================================================================================== */ 186 187 188 /** @addtogroup Device_Peripheral_clusters 189 * @{ 190 */ 191 192 193 /** 194 * @brief FICR_INFO [INFO] (Device info) 195 */ 196 typedef struct { 197 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 198 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part Variant, Hardware version and Production 199 configuration */ 200 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 201 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 202 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 203 } FICR_INFO_Type; /*!< Size = 20 (0x14) */ 204 205 206 /** 207 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 208 */ 209 typedef struct { 210 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0. */ 211 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1. */ 212 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2. */ 213 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3. */ 214 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4. */ 215 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5. */ 216 __IM uint32_t B0; /*!< (@ 0x00000018) y-intercept B0. */ 217 __IM uint32_t B1; /*!< (@ 0x0000001C) y-intercept B1. */ 218 __IM uint32_t B2; /*!< (@ 0x00000020) y-intercept B2. */ 219 __IM uint32_t B3; /*!< (@ 0x00000024) y-intercept B3. */ 220 __IM uint32_t B4; /*!< (@ 0x00000028) y-intercept B4. */ 221 __IM uint32_t B5; /*!< (@ 0x0000002C) y-intercept B5. */ 222 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0. */ 223 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1. */ 224 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2. */ 225 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3. */ 226 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4. */ 227 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 228 229 230 /** 231 * @brief FICR_NFC [NFC] (Unspecified) 232 */ 233 typedef struct { 234 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read 235 these values to populate NFCID1_3RD_LAST, 236 NFCID1_2ND_LAST and NFCID1_LAST. */ 237 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read 238 these values to populate NFCID1_3RD_LAST, 239 NFCID1_2ND_LAST and NFCID1_LAST. */ 240 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read 241 these values to populate NFCID1_3RD_LAST, 242 NFCID1_2ND_LAST and NFCID1_LAST. */ 243 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read 244 these values to populate NFCID1_3RD_LAST, 245 NFCID1_2ND_LAST and NFCID1_LAST. */ 246 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 247 248 249 /** 250 * @brief POWER_RAM [RAM] (Unspecified) 251 */ 252 typedef struct { 253 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ 254 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 255 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 256 register */ 257 __IM uint32_t RESERVED; 258 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 259 260 261 /** 262 * @brief UARTE_PSEL [PSEL] (Unspecified) 263 */ 264 typedef struct { 265 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 266 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 267 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 268 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 269 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 270 271 272 /** 273 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 274 */ 275 typedef struct { 276 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 277 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 278 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 279 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 280 281 282 /** 283 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 284 */ 285 typedef struct { 286 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 287 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 288 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 289 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 290 291 292 /** 293 * @brief SPI_PSEL [PSEL] (Unspecified) 294 */ 295 typedef struct { 296 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 297 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */ 298 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */ 299 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 300 301 302 /** 303 * @brief SPIM_PSEL [PSEL] (Unspecified) 304 */ 305 typedef struct { 306 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 307 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 308 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 309 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 310 311 312 /** 313 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 314 */ 315 typedef struct { 316 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 317 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 318 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 319 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 320 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 321 322 323 /** 324 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 325 */ 326 typedef struct { 327 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 328 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 329 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 330 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 331 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 332 333 334 /** 335 * @brief SPIS_PSEL [PSEL] (Unspecified) 336 */ 337 typedef struct { 338 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 339 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 340 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 341 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 342 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 343 344 345 /** 346 * @brief SPIS_RXD [RXD] (Unspecified) 347 */ 348 typedef struct { 349 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 350 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 351 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 352 } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 353 354 355 /** 356 * @brief SPIS_TXD [TXD] (Unspecified) 357 */ 358 typedef struct { 359 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 360 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 361 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 362 } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 363 364 365 /** 366 * @brief TWIM_PSEL [PSEL] (Unspecified) 367 */ 368 typedef struct { 369 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 370 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 371 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 372 373 374 /** 375 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 376 */ 377 typedef struct { 378 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 379 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 380 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 381 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 382 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 383 384 385 /** 386 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 387 */ 388 typedef struct { 389 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 390 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 391 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 392 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 393 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 394 395 396 /** 397 * @brief TWIS_PSEL [PSEL] (Unspecified) 398 */ 399 typedef struct { 400 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 401 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 402 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 403 404 405 /** 406 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 407 */ 408 typedef struct { 409 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 410 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 411 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 412 } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 413 414 415 /** 416 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 417 */ 418 typedef struct { 419 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 420 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 421 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 422 } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 423 424 425 /** 426 * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 427 */ 428 typedef struct { 429 __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frames */ 430 } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 431 432 433 /** 434 * @brief NFCT_TXD [TXD] (Unspecified) 435 */ 436 typedef struct { 437 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 438 __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 439 } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 440 441 442 /** 443 * @brief NFCT_RXD [RXD] (Unspecified) 444 */ 445 typedef struct { 446 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 447 __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 448 } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 449 450 451 /** 452 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 453 */ 454 typedef struct { 455 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 456 above CH[n].LIMIT.HIGH */ 457 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 458 below CH[n].LIMIT.LOW */ 459 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 460 461 462 /** 463 * @brief SAADC_CH [CH] (Unspecified) 464 */ 465 typedef struct { 466 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 467 for CH[n] */ 468 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 469 for CH[n] */ 470 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 471 CH[n] */ 472 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 473 monitoring a channel */ 474 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 475 476 477 /** 478 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 479 */ 480 typedef struct { 481 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 482 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 483 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 484 START */ 485 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 486 487 488 /** 489 * @brief QDEC_PSEL [PSEL] (Unspecified) 490 */ 491 typedef struct { 492 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 493 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 494 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 495 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 496 497 498 /** 499 * @brief PWM_SEQ [SEQ] (Unspecified) 500 */ 501 typedef struct { 502 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in Data 503 RAM of this sequence */ 504 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Amount of values (duty cycles) 505 in this sequence */ 506 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Amount of additional PWM 507 periods between samples loaded into compare 508 register */ 509 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 510 __IM uint32_t RESERVED[4]; 511 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 512 513 514 /** 515 * @brief PWM_PSEL [PSEL] (Unspecified) 516 */ 517 typedef struct { 518 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 519 PWM channel n */ 520 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 521 522 523 /** 524 * @brief PDM_PSEL [PSEL] (Unspecified) 525 */ 526 typedef struct { 527 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 528 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 529 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 530 531 532 /** 533 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 534 */ 535 typedef struct { 536 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 537 EasyDMA */ 538 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 539 mode */ 540 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 541 542 543 /** 544 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 545 */ 546 typedef struct { 547 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 548 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 549 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 550 551 552 /** 553 * @brief PPI_CH [CH] (PPI Channel) 554 */ 555 typedef struct { 556 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ 557 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ 558 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 559 560 561 /** 562 * @brief PPI_FORK [FORK] (Fork) 563 */ 564 typedef struct { 565 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ 566 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 567 568 569 /** 570 * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.) 571 */ 572 typedef struct { 573 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n 574 detected */ 575 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n 576 detected */ 577 } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ 578 579 580 /** 581 * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.) 582 */ 583 typedef struct { 584 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral 585 region n detected */ 586 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral 587 region n detected */ 588 } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ 589 590 591 /** 592 * @brief MWU_PERREGION [PERREGION] (Unspecified) 593 */ 594 typedef struct { 595 __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt 596 in region n, write access detected while 597 corresponding subregion was enabled for 598 watching */ 599 __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt 600 in region n, read access detected while 601 corresponding subregion was enabled for 602 watching */ 603 } MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ 604 605 606 /** 607 * @brief MWU_REGION [REGION] (Unspecified) 608 */ 609 typedef struct { 610 __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region 611 n */ 612 __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */ 613 __IM uint32_t RESERVED[2]; 614 } MWU_REGION_Type; /*!< Size = 16 (0x10) */ 615 616 617 /** 618 * @brief MWU_PREGION [PREGION] (Unspecified) 619 */ 620 typedef struct { 621 __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */ 622 __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */ 623 __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */ 624 __IM uint32_t RESERVED; 625 } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ 626 627 628 /** 629 * @brief I2S_CONFIG [CONFIG] (Unspecified) 630 */ 631 typedef struct { 632 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 633 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 634 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 635 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 636 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 637 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 638 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 639 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 640 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 641 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 642 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 643 644 645 /** 646 * @brief I2S_RXD [RXD] (Unspecified) 647 */ 648 typedef struct { 649 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 650 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 651 652 653 /** 654 * @brief I2S_TXD [TXD] (Unspecified) 655 */ 656 typedef struct { 657 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 658 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 659 660 661 /** 662 * @brief I2S_RXTXD [RXTXD] (Unspecified) 663 */ 664 typedef struct { 665 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 666 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 667 668 669 /** 670 * @brief I2S_PSEL [PSEL] (Unspecified) 671 */ 672 typedef struct { 673 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 674 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 675 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 676 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 677 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 678 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 679 680 681 /** @} */ /* End of group Device_Peripheral_clusters */ 682 683 684 /* =========================================================================================================================== */ 685 /* ================ Device Specific Peripheral Section ================ */ 686 /* =========================================================================================================================== */ 687 688 689 /** @addtogroup Device_Peripheral_peripherals 690 * @{ 691 */ 692 693 694 695 /* =========================================================================================================================== */ 696 /* ================ FICR ================ */ 697 /* =========================================================================================================================== */ 698 699 700 /** 701 * @brief Factory Information Configuration Registers (FICR) 702 */ 703 704 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 705 __IM uint32_t RESERVED[4]; 706 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 707 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 708 __IM uint32_t RESERVED1[18]; 709 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ 710 __IM uint32_t RESERVED2[6]; 711 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption Root, word 712 n */ 713 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ 714 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 715 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ 716 __IM uint32_t RESERVED3[21]; 717 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 718 __IM uint32_t RESERVED4[188]; 719 __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 720 coefficients */ 721 __IM uint32_t RESERVED5[2]; 722 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 723 } NRF_FICR_Type; /*!< Size = 1120 (0x460) */ 724 725 726 727 /* =========================================================================================================================== */ 728 /* ================ UICR ================ */ 729 /* =========================================================================================================================== */ 730 731 732 /** 733 * @brief User Information Configuration Registers (UICR) 734 */ 735 736 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 737 __IM uint32_t RESERVED[5]; 738 __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware 739 design */ 740 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware 741 design */ 742 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ 743 __IM uint32_t RESERVED1[64]; 744 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET 745 function (see POWER chapter for details) */ 746 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 747 __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: 748 NFC antenna or GPIO */ 749 } NRF_UICR_Type; /*!< Size = 528 (0x210) */ 750 751 752 753 /* =========================================================================================================================== */ 754 /* ================ APPROTECT ================ */ 755 /* =========================================================================================================================== */ 756 757 758 /** 759 * @brief Access Port Protection (APPROTECT) 760 */ 761 762 typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ 763 __IM uint32_t RESERVED[340]; 764 __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until 765 next reset. This register can only be written 766 once. */ 767 __IM uint32_t RESERVED1; 768 __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ 769 } NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ 770 771 772 773 /* =========================================================================================================================== */ 774 /* ================ BPROT ================ */ 775 /* =========================================================================================================================== */ 776 777 778 /** 779 * @brief Block Protect (BPROT) 780 */ 781 782 typedef struct { /*!< (@ 0x40000000) BPROT Structure */ 783 __IM uint32_t RESERVED[384]; 784 __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ 785 __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ 786 __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface 787 mode */ 788 __IM uint32_t RESERVED1; 789 __IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */ 790 __IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */ 791 } NRF_BPROT_Type; /*!< Size = 1560 (0x618) */ 792 793 794 795 /* =========================================================================================================================== */ 796 /* ================ CLOCK ================ */ 797 /* =========================================================================================================================== */ 798 799 800 /** 801 * @brief Clock control (CLOCK) 802 */ 803 804 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 805 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 806 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 807 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 808 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 809 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 810 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 811 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 812 __IM uint32_t RESERVED[57]; 813 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 814 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 815 __IM uint32_t RESERVED1; 816 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ 817 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 818 __IM uint32_t RESERVED2[124]; 819 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 820 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 821 __IM uint32_t RESERVED3[63]; 822 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 823 triggered */ 824 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 825 __IM uint32_t RESERVED4; 826 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 827 triggered */ 828 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 829 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 830 task was triggered */ 831 __IM uint32_t RESERVED5[62]; 832 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 833 __IM uint32_t RESERVED6[7]; 834 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 835 __IM uint32_t RESERVED7[8]; 836 __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */ 837 } NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */ 838 839 840 841 /* =========================================================================================================================== */ 842 /* ================ POWER ================ */ 843 /* =========================================================================================================================== */ 844 845 846 /** 847 * @brief Power control (POWER) 848 */ 849 850 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 851 __IM uint32_t RESERVED[30]; 852 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ 853 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 854 __IM uint32_t RESERVED1[34]; 855 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 856 __IM uint32_t RESERVED2[2]; 857 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 858 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 859 __IM uint32_t RESERVED3[122]; 860 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 861 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 862 __IM uint32_t RESERVED4[61]; 863 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 864 __IM uint32_t RESERVED5[9]; 865 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 866 __IM uint32_t RESERVED6[53]; 867 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 868 __IM uint32_t RESERVED7[3]; 869 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ 870 __IM uint32_t RESERVED8[2]; 871 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 872 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 873 __IOM uint32_t RAMON; /*!< (@ 0x00000524) Deprecated register - RAM on/off register (this 874 register is retained) */ 875 __IM uint32_t RESERVED9[11]; 876 __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Deprecated register - RAM on/off register (this 877 register is retained) */ 878 __IM uint32_t RESERVED10[8]; 879 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ 880 __IM uint32_t RESERVED11[225]; 881 __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ 882 } NRF_POWER_Type; /*!< Size = 2432 (0x980) */ 883 884 885 886 /* =========================================================================================================================== */ 887 /* ================ P0 ================ */ 888 /* =========================================================================================================================== */ 889 890 891 /** 892 * @brief GPIO Port 1 (P0) 893 */ 894 895 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 896 __IM uint32_t RESERVED[321]; 897 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 898 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 899 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 900 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 901 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 902 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 903 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 904 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 905 have met the criteria set in the PIN_CNF[n].SENSE 906 registers */ 907 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 908 and LDETECT mode */ 909 __IM uint32_t RESERVED1[118]; 910 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO 911 pins */ 912 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 913 914 915 916 /* =========================================================================================================================== */ 917 /* ================ RADIO ================ */ 918 /* =========================================================================================================================== */ 919 920 921 /** 922 * @brief 2.4 GHz Radio (RADIO) 923 */ 924 925 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 926 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 927 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 928 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 929 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 930 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 931 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 932 the receive signal strength. */ 933 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 934 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 935 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 936 __IM uint32_t RESERVED[55]; 937 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 938 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 939 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 940 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 941 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 942 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 943 packet */ 944 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 945 received packet */ 946 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ 947 __IM uint32_t RESERVED1[2]; 948 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ 949 __IM uint32_t RESERVED2; 950 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 951 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 952 __IM uint32_t RESERVED3[50]; 953 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 954 __IM uint32_t RESERVED4[64]; 955 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 956 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 957 __IM uint32_t RESERVED5[61]; 958 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 959 __IM uint32_t RESERVED6; 960 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 961 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 962 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 963 __IM uint32_t RESERVED7[60]; 964 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 965 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 966 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 967 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 968 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 969 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 970 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 971 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 972 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 973 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 974 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 975 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 976 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 977 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 978 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 979 __IM uint32_t RESERVED8; 980 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ 981 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 982 __IM uint32_t RESERVED9; 983 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 984 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 985 __IM uint32_t RESERVED10[2]; 986 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 987 __IM uint32_t RESERVED11[39]; 988 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 989 n */ 990 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 991 n */ 992 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 993 __IM uint32_t RESERVED12[3]; 994 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 995 __IM uint32_t RESERVED13[618]; 996 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 997 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 998 999 1000 1001 /* =========================================================================================================================== */ 1002 /* ================ UART0 ================ */ 1003 /* =========================================================================================================================== */ 1004 1005 1006 /** 1007 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 1008 */ 1009 1010 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 1011 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1012 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1013 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1014 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1015 __IM uint32_t RESERVED[3]; 1016 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 1017 __IM uint32_t RESERVED1[56]; 1018 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1019 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1020 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 1021 __IM uint32_t RESERVED2[4]; 1022 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1023 __IM uint32_t RESERVED3; 1024 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1025 __IM uint32_t RESERVED4[7]; 1026 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1027 __IM uint32_t RESERVED5[46]; 1028 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1029 __IM uint32_t RESERVED6[64]; 1030 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1031 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1032 __IM uint32_t RESERVED7[93]; 1033 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1034 __IM uint32_t RESERVED8[31]; 1035 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1036 __IM uint32_t RESERVED9; 1037 __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */ 1038 __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */ 1039 __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */ 1040 __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */ 1041 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1042 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1043 __IM uint32_t RESERVED10; 1044 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */ 1045 __IM uint32_t RESERVED11[17]; 1046 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1047 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 1048 1049 1050 1051 /* =========================================================================================================================== */ 1052 /* ================ UARTE0 ================ */ 1053 /* =========================================================================================================================== */ 1054 1055 1056 /** 1057 * @brief UART with EasyDMA (UARTE0) 1058 */ 1059 1060 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 1061 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1062 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1063 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1064 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1065 __IM uint32_t RESERVED[7]; 1066 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1067 __IM uint32_t RESERVED1[52]; 1068 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1069 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1070 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1071 transferred to Data RAM) */ 1072 __IM uint32_t RESERVED2; 1073 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1074 __IM uint32_t RESERVED3[2]; 1075 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1076 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1077 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1078 __IM uint32_t RESERVED4[7]; 1079 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1080 __IM uint32_t RESERVED5; 1081 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1082 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1083 __IM uint32_t RESERVED6; 1084 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1085 __IM uint32_t RESERVED7[41]; 1086 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1087 __IM uint32_t RESERVED8[63]; 1088 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1089 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1090 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1091 __IM uint32_t RESERVED9[93]; 1092 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1093 __IM uint32_t RESERVED10[31]; 1094 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1095 __IM uint32_t RESERVED11; 1096 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1097 __IM uint32_t RESERVED12[3]; 1098 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1099 selected. */ 1100 __IM uint32_t RESERVED13[3]; 1101 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1102 __IM uint32_t RESERVED14; 1103 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1104 __IM uint32_t RESERVED15[7]; 1105 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1106 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1107 1108 1109 1110 /* =========================================================================================================================== */ 1111 /* ================ SPI0 ================ */ 1112 /* =========================================================================================================================== */ 1113 1114 1115 /** 1116 * @brief Serial Peripheral Interface 0 (SPI0) 1117 */ 1118 1119 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1120 __IM uint32_t RESERVED[66]; 1121 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1122 __IM uint32_t RESERVED1[126]; 1123 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1124 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1125 __IM uint32_t RESERVED2[125]; 1126 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1127 __IM uint32_t RESERVED3; 1128 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1129 __IM uint32_t RESERVED4; 1130 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1131 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1132 __IM uint32_t RESERVED5; 1133 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ 1134 __IM uint32_t RESERVED6[11]; 1135 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1136 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1137 1138 1139 1140 /* =========================================================================================================================== */ 1141 /* ================ SPIM0 ================ */ 1142 /* =========================================================================================================================== */ 1143 1144 1145 /** 1146 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1147 */ 1148 1149 typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1150 __IM uint32_t RESERVED[4]; 1151 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1152 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1153 __IM uint32_t RESERVED1; 1154 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1155 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1156 __IM uint32_t RESERVED2[56]; 1157 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1158 __IM uint32_t RESERVED3[2]; 1159 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1160 __IM uint32_t RESERVED4; 1161 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1162 __IM uint32_t RESERVED5; 1163 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1164 __IM uint32_t RESERVED6[10]; 1165 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1166 __IM uint32_t RESERVED7[44]; 1167 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1168 __IM uint32_t RESERVED8[64]; 1169 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1170 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1171 __IM uint32_t RESERVED9[125]; 1172 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1173 __IM uint32_t RESERVED10; 1174 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1175 __IM uint32_t RESERVED11[4]; 1176 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1177 source selected. */ 1178 __IM uint32_t RESERVED12[3]; 1179 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1180 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1181 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1182 __IM uint32_t RESERVED13[26]; 1183 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1184 case and over-read of the TXD buffer. */ 1185 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1186 1187 1188 1189 /* =========================================================================================================================== */ 1190 /* ================ SPIS0 ================ */ 1191 /* =========================================================================================================================== */ 1192 1193 1194 /** 1195 * @brief SPI Slave 0 (SPIS0) 1196 */ 1197 1198 typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1199 __IM uint32_t RESERVED[9]; 1200 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1201 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1202 to acquire it */ 1203 __IM uint32_t RESERVED1[54]; 1204 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1205 __IM uint32_t RESERVED2[2]; 1206 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1207 __IM uint32_t RESERVED3[5]; 1208 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1209 __IM uint32_t RESERVED4[53]; 1210 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1211 __IM uint32_t RESERVED5[64]; 1212 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1213 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1214 __IM uint32_t RESERVED6[61]; 1215 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1216 __IM uint32_t RESERVED7[15]; 1217 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1218 __IM uint32_t RESERVED8[47]; 1219 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1220 __IM uint32_t RESERVED9; 1221 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1222 __IM uint32_t RESERVED10[7]; 1223 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1224 __IM uint32_t RESERVED11; 1225 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1226 __IM uint32_t RESERVED12; 1227 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1228 __IM uint32_t RESERVED13; 1229 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1230 of an ignored transaction. */ 1231 __IM uint32_t RESERVED14[24]; 1232 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1233 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1234 1235 1236 1237 /* =========================================================================================================================== */ 1238 /* ================ TWI0 ================ */ 1239 /* =========================================================================================================================== */ 1240 1241 1242 /** 1243 * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1244 */ 1245 1246 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1247 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1248 __IM uint32_t RESERVED; 1249 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1250 __IM uint32_t RESERVED1[2]; 1251 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1252 __IM uint32_t RESERVED2; 1253 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1254 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1255 __IM uint32_t RESERVED3[56]; 1256 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1257 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1258 __IM uint32_t RESERVED4[4]; 1259 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1260 __IM uint32_t RESERVED5; 1261 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1262 __IM uint32_t RESERVED6[4]; 1263 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1264 that is sent or received */ 1265 __IM uint32_t RESERVED7[3]; 1266 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1267 __IM uint32_t RESERVED8[45]; 1268 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1269 __IM uint32_t RESERVED9[64]; 1270 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1271 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1272 __IM uint32_t RESERVED10[110]; 1273 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1274 __IM uint32_t RESERVED11[14]; 1275 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1276 __IM uint32_t RESERVED12; 1277 __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */ 1278 __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */ 1279 __IM uint32_t RESERVED13[2]; 1280 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1281 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1282 __IM uint32_t RESERVED14; 1283 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ 1284 __IM uint32_t RESERVED15[24]; 1285 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1286 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1287 1288 1289 1290 /* =========================================================================================================================== */ 1291 /* ================ TWIM0 ================ */ 1292 /* =========================================================================================================================== */ 1293 1294 1295 /** 1296 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1297 */ 1298 1299 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1300 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1301 __IM uint32_t RESERVED; 1302 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1303 __IM uint32_t RESERVED1[2]; 1304 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1305 TWI master is not suspended. */ 1306 __IM uint32_t RESERVED2; 1307 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1308 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1309 __IM uint32_t RESERVED3[56]; 1310 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1311 __IM uint32_t RESERVED4[7]; 1312 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1313 __IM uint32_t RESERVED5[8]; 1314 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1315 task has been issued, TWI traffic is now 1316 suspended. */ 1317 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1318 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1319 __IM uint32_t RESERVED6[2]; 1320 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1321 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1322 byte */ 1323 __IM uint32_t RESERVED7[39]; 1324 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1325 __IM uint32_t RESERVED8[63]; 1326 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1327 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1328 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1329 __IM uint32_t RESERVED9[110]; 1330 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1331 __IM uint32_t RESERVED10[14]; 1332 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1333 __IM uint32_t RESERVED11; 1334 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1335 __IM uint32_t RESERVED12[5]; 1336 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ 1337 __IM uint32_t RESERVED13[3]; 1338 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1339 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1340 __IM uint32_t RESERVED14[13]; 1341 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1342 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1343 1344 1345 1346 /* =========================================================================================================================== */ 1347 /* ================ TWIS0 ================ */ 1348 /* =========================================================================================================================== */ 1349 1350 1351 /** 1352 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1353 */ 1354 1355 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1356 __IM uint32_t RESERVED[5]; 1357 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1358 __IM uint32_t RESERVED1; 1359 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1360 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1361 __IM uint32_t RESERVED2[3]; 1362 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1363 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1364 __IM uint32_t RESERVED3[51]; 1365 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1366 __IM uint32_t RESERVED4[7]; 1367 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1368 __IM uint32_t RESERVED5[9]; 1369 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1370 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1371 __IM uint32_t RESERVED6[4]; 1372 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1373 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1374 __IM uint32_t RESERVED7[37]; 1375 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1376 __IM uint32_t RESERVED8[63]; 1377 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1378 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1379 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1380 __IM uint32_t RESERVED9[113]; 1381 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1382 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1383 a match */ 1384 __IM uint32_t RESERVED10[10]; 1385 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1386 __IM uint32_t RESERVED11; 1387 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1388 __IM uint32_t RESERVED12[9]; 1389 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1390 __IM uint32_t RESERVED13; 1391 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1392 __IM uint32_t RESERVED14[14]; 1393 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1394 __IM uint32_t RESERVED15; 1395 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1396 mechanism */ 1397 __IM uint32_t RESERVED16[10]; 1398 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1399 of an over-read of the transmit buffer. */ 1400 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1401 1402 1403 1404 /* =========================================================================================================================== */ 1405 /* ================ NFCT ================ */ 1406 /* =========================================================================================================================== */ 1407 1408 1409 /** 1410 * @brief NFC-A compatible radio (NFCT) 1411 */ 1412 1413 typedef struct { /*!< (@ 0x40005000) NFCT Structure */ 1414 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFC peripheral for incoming and outgoing 1415 frames, change state to activated */ 1416 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFC peripheral */ 1417 __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 1418 sense mode */ 1419 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of a outgoing frame, change 1420 state to transmit */ 1421 __IM uint32_t RESERVED[3]; 1422 __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 1423 __IM uint32_t RESERVED1; 1424 __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 1425 __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 1426 __IM uint32_t RESERVED2[53]; 1427 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFC peripheral is ready to receive and send 1428 frames */ 1429 __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 1430 __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 1431 __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 1432 frame */ 1433 __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 1434 symbol of a frame */ 1435 __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 1436 frame */ 1437 __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data have been checked (CRC, parity) 1438 and transferred to RAM, and EasyDMA has 1439 ended accessing the RX buffer */ 1440 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 1441 contains details on the source of the error. */ 1442 __IM uint32_t RESERVED3[2]; 1443 __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 1444 register contains details on the source 1445 of the error. */ 1446 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 1447 in Data RAM full. */ 1448 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 1449 has ended accessing the TX buffer */ 1450 __IM uint32_t RESERVED4; 1451 __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 1452 __IM uint32_t RESERVED5[3]; 1453 __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC Auto collision resolution error reported. */ 1454 __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC Auto collision resolution successfully completed */ 1455 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 1456 __IM uint32_t RESERVED6[43]; 1457 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1458 __IM uint32_t RESERVED7[63]; 1459 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1460 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1461 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1462 __IM uint32_t RESERVED8[62]; 1463 __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 1464 __IM uint32_t RESERVED9; 1465 __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 1466 __IM uint32_t RESERVED10[8]; 1467 __IM uint32_t CURRENTLOADCTRL; /*!< (@ 0x00000430) Current value driven to the NFC Load Control */ 1468 __IM uint32_t RESERVED11[2]; 1469 __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 1470 __IM uint32_t RESERVED12[49]; 1471 __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 1472 __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 1473 __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 1474 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 1475 Data RAM */ 1476 __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of allocated for TXD and RXD data storage 1477 buffer in Data RAM */ 1478 __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 1479 __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 1480 __IM uint32_t RESERVED13[26]; 1481 __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 1482 __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 1483 __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 1484 __IM uint32_t RESERVED14; 1485 __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 1486 __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 1487 } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 1488 1489 1490 1491 /* =========================================================================================================================== */ 1492 /* ================ GPIOTE ================ */ 1493 /* =========================================================================================================================== */ 1494 1495 1496 /** 1497 * @brief GPIO Tasks and Events (GPIOTE) 1498 */ 1499 1500 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1501 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1502 specified in CONFIG[n].PSEL. Action on pin 1503 is configured in CONFIG[n].POLARITY. */ 1504 __IM uint32_t RESERVED[4]; 1505 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1506 specified in CONFIG[n].PSEL. Action on pin 1507 is to set it high. */ 1508 __IM uint32_t RESERVED1[4]; 1509 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1510 specified in CONFIG[n].PSEL. Action on pin 1511 is to set it low. */ 1512 __IM uint32_t RESERVED2[32]; 1513 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1514 pin specified in CONFIG[n].PSEL */ 1515 __IM uint32_t RESERVED3[23]; 1516 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1517 with SENSE mechanism enabled */ 1518 __IM uint32_t RESERVED4[97]; 1519 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1520 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1521 __IM uint32_t RESERVED5[129]; 1522 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1523 SET[n] and CLR[n] tasks and IN[n] event */ 1524 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1525 1526 1527 1528 /* =========================================================================================================================== */ 1529 /* ================ SAADC ================ */ 1530 /* =========================================================================================================================== */ 1531 1532 1533 /** 1534 * @brief Analog to Digital Converter (SAADC) 1535 */ 1536 1537 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1538 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1539 RAM */ 1540 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1541 are sampled */ 1542 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1543 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1544 __IM uint32_t RESERVED[60]; 1545 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1546 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1547 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1548 on the mode, multiple conversions might 1549 be needed for a result to be transferred 1550 to RAM. */ 1551 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1552 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1553 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1554 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1555 __IM uint32_t RESERVED1[106]; 1556 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1557 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1558 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1559 __IM uint32_t RESERVED2[61]; 1560 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1561 __IM uint32_t RESERVED3[63]; 1562 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1563 __IM uint32_t RESERVED4[3]; 1564 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1565 __IM uint32_t RESERVED5[24]; 1566 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1567 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1568 not be combined with SCAN. The RESOLUTION 1569 is applied before averaging, thus for high 1570 OVERSAMPLE a higher RESOLUTION should be 1571 used. */ 1572 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1573 __IM uint32_t RESERVED6[12]; 1574 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1575 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1576 1577 1578 1579 /* =========================================================================================================================== */ 1580 /* ================ TIMER0 ================ */ 1581 /* =========================================================================================================================== */ 1582 1583 1584 /** 1585 * @brief Timer/Counter 0 (TIMER0) 1586 */ 1587 1588 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1589 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1590 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1591 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1592 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1593 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1594 __IM uint32_t RESERVED[11]; 1595 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1596 CC[n] register */ 1597 __IM uint32_t RESERVED1[58]; 1598 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1599 match */ 1600 __IM uint32_t RESERVED2[42]; 1601 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1602 __IM uint32_t RESERVED3[64]; 1603 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1604 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1605 __IM uint32_t RESERVED4[126]; 1606 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1607 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1608 __IM uint32_t RESERVED5; 1609 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1610 __IM uint32_t RESERVED6[11]; 1611 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1612 n */ 1613 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1614 1615 1616 1617 /* =========================================================================================================================== */ 1618 /* ================ RTC0 ================ */ 1619 /* =========================================================================================================================== */ 1620 1621 1622 /** 1623 * @brief Real time counter 0 (RTC0) 1624 */ 1625 1626 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1627 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1628 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1629 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1630 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1631 __IM uint32_t RESERVED[60]; 1632 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1633 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1634 __IM uint32_t RESERVED1[14]; 1635 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1636 match */ 1637 __IM uint32_t RESERVED2[109]; 1638 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1639 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1640 __IM uint32_t RESERVED3[13]; 1641 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1642 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1643 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1644 __IM uint32_t RESERVED4[110]; 1645 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1646 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1647 t be written when RTC is stopped */ 1648 __IM uint32_t RESERVED5[13]; 1649 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1650 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1651 1652 1653 1654 /* =========================================================================================================================== */ 1655 /* ================ TEMP ================ */ 1656 /* =========================================================================================================================== */ 1657 1658 1659 /** 1660 * @brief Temperature Sensor (TEMP) 1661 */ 1662 1663 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1664 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1665 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1666 __IM uint32_t RESERVED[62]; 1667 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1668 __IM uint32_t RESERVED1[128]; 1669 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1670 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1671 __IM uint32_t RESERVED2[127]; 1672 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1673 __IM uint32_t RESERVED3[5]; 1674 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1675 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1676 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1677 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1678 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1679 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1680 __IM uint32_t RESERVED4[2]; 1681 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1682 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1683 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1684 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1685 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1686 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1687 __IM uint32_t RESERVED5[2]; 1688 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1689 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1690 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1691 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1692 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1693 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1694 1695 1696 1697 /* =========================================================================================================================== */ 1698 /* ================ RNG ================ */ 1699 /* =========================================================================================================================== */ 1700 1701 1702 /** 1703 * @brief Random Number Generator (RNG) 1704 */ 1705 1706 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1707 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1708 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1709 __IM uint32_t RESERVED[62]; 1710 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1711 written to the VALUE register */ 1712 __IM uint32_t RESERVED1[63]; 1713 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1714 __IM uint32_t RESERVED2[64]; 1715 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1716 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1717 __IM uint32_t RESERVED3[126]; 1718 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1719 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1720 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1721 1722 1723 1724 /* =========================================================================================================================== */ 1725 /* ================ ECB ================ */ 1726 /* =========================================================================================================================== */ 1727 1728 1729 /** 1730 * @brief AES ECB Mode Encryption (ECB) 1731 */ 1732 1733 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1734 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1735 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1736 __IM uint32_t RESERVED[62]; 1737 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1738 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1739 task or due to an error */ 1740 __IM uint32_t RESERVED1[127]; 1741 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1742 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1743 __IM uint32_t RESERVED2[126]; 1744 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1745 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1746 1747 1748 1749 /* =========================================================================================================================== */ 1750 /* ================ AAR ================ */ 1751 /* =========================================================================================================================== */ 1752 1753 1754 /** 1755 * @brief Accelerated Address Resolver (AAR) 1756 */ 1757 1758 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1759 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1760 in the IRK data structure */ 1761 __IM uint32_t RESERVED; 1762 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1763 __IM uint32_t RESERVED1[61]; 1764 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1765 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1766 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1767 __IM uint32_t RESERVED2[126]; 1768 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1769 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1770 __IM uint32_t RESERVED3[61]; 1771 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1772 __IM uint32_t RESERVED4[63]; 1773 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1774 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1775 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1776 __IM uint32_t RESERVED5; 1777 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1778 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1779 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1780 1781 1782 1783 /* =========================================================================================================================== */ 1784 /* ================ CCM ================ */ 1785 /* =========================================================================================================================== */ 1786 1787 1788 /** 1789 * @brief AES CCM Mode Encryption (CCM) 1790 */ 1791 1792 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1793 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 1794 will stop by itself when completed. */ 1795 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1796 stop by itself when completed. */ 1797 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1798 __IM uint32_t RESERVED[61]; 1799 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ 1800 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1801 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ 1802 __IM uint32_t RESERVED1[61]; 1803 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1804 __IM uint32_t RESERVED2[64]; 1805 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1806 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1807 __IM uint32_t RESERVED3[61]; 1808 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1809 __IM uint32_t RESERVED4[63]; 1810 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1811 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1812 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 1813 NONCE vector */ 1814 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1815 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1816 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1817 } NRF_CCM_Type; /*!< Size = 1304 (0x518) */ 1818 1819 1820 1821 /* =========================================================================================================================== */ 1822 /* ================ WDT ================ */ 1823 /* =========================================================================================================================== */ 1824 1825 1826 /** 1827 * @brief Watchdog Timer (WDT) 1828 */ 1829 1830 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1831 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1832 __IM uint32_t RESERVED[63]; 1833 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1834 __IM uint32_t RESERVED1[128]; 1835 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1836 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1837 __IM uint32_t RESERVED2[61]; 1838 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1839 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1840 __IM uint32_t RESERVED3[63]; 1841 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1842 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1843 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1844 __IM uint32_t RESERVED4[60]; 1845 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1846 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1847 1848 1849 1850 /* =========================================================================================================================== */ 1851 /* ================ QDEC ================ */ 1852 /* =========================================================================================================================== */ 1853 1854 1855 /** 1856 * @brief Quadrature Decoder (QDEC) 1857 */ 1858 1859 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1860 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1861 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1862 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1863 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1864 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1865 __IM uint32_t RESERVED[59]; 1866 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1867 written to the SAMPLE register */ 1868 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1869 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1870 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1871 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1872 __IM uint32_t RESERVED1[59]; 1873 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1874 __IM uint32_t RESERVED2[64]; 1875 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1876 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1877 __IM uint32_t RESERVED3[125]; 1878 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1879 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1880 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1881 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1882 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1883 and DBLRDY events can be generated */ 1884 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1885 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1886 READCLRACC or RDCLRACC task */ 1887 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1888 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1889 __IM uint32_t RESERVED4[5]; 1890 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1891 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1892 double transitions */ 1893 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1894 or RDCLRDBL task */ 1895 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1896 1897 1898 1899 /* =========================================================================================================================== */ 1900 /* ================ COMP ================ */ 1901 /* =========================================================================================================================== */ 1902 1903 1904 /** 1905 * @brief Comparator (COMP) 1906 */ 1907 1908 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 1909 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1910 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1911 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1912 __IM uint32_t RESERVED[61]; 1913 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 1914 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1915 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1916 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1917 __IM uint32_t RESERVED1[60]; 1918 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1919 __IM uint32_t RESERVED2[63]; 1920 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1921 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1922 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1923 __IM uint32_t RESERVED3[61]; 1924 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1925 __IM uint32_t RESERVED4[63]; 1926 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 1927 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 1928 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 1929 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1930 __IM uint32_t RESERVED5[8]; 1931 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 1932 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 1933 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1934 __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ 1935 } NRF_COMP_Type; /*!< Size = 1344 (0x540) */ 1936 1937 1938 1939 /* =========================================================================================================================== */ 1940 /* ================ LPCOMP ================ */ 1941 /* =========================================================================================================================== */ 1942 1943 1944 /** 1945 * @brief Low Power Comparator (LPCOMP) 1946 */ 1947 1948 typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 1949 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 1950 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 1951 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 1952 __IM uint32_t RESERVED[61]; 1953 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 1954 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 1955 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 1956 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 1957 __IM uint32_t RESERVED1[60]; 1958 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1959 __IM uint32_t RESERVED2[64]; 1960 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1961 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1962 __IM uint32_t RESERVED3[61]; 1963 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 1964 __IM uint32_t RESERVED4[63]; 1965 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 1966 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 1967 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 1968 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 1969 __IM uint32_t RESERVED5[4]; 1970 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 1971 __IM uint32_t RESERVED6[5]; 1972 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 1973 } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 1974 1975 1976 1977 /* =========================================================================================================================== */ 1978 /* ================ EGU0 ================ */ 1979 /* =========================================================================================================================== */ 1980 1981 1982 /** 1983 * @brief Event Generator Unit 0 (EGU0) 1984 */ 1985 1986 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1987 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1988 the corresponding TRIGGERED[n] event */ 1989 __IM uint32_t RESERVED[48]; 1990 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1991 by triggering the corresponding TRIGGER[n] 1992 task */ 1993 __IM uint32_t RESERVED1[112]; 1994 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1995 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1996 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1997 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1998 1999 2000 2001 /* =========================================================================================================================== */ 2002 /* ================ SWI0 ================ */ 2003 /* =========================================================================================================================== */ 2004 2005 2006 /** 2007 * @brief Software interrupt 0 (SWI0) 2008 */ 2009 2010 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 2011 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2012 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 2013 2014 2015 2016 /* =========================================================================================================================== */ 2017 /* ================ PWM0 ================ */ 2018 /* =========================================================================================================================== */ 2019 2020 2021 /** 2022 * @brief Pulse Width Modulation Unit 0 (PWM0) 2023 */ 2024 2025 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 2026 __IM uint32_t RESERVED; 2027 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2028 the end of current PWM period, and stops 2029 sequence playback */ 2030 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 2031 on all enabled channels from sequence n, 2032 and starts playing that sequence at the 2033 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2034 Causes PWM generation to start it was not 2035 running. */ 2036 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2037 all enabled channels if DECODER.MODE=NextStep. 2038 Does not cause PWM generation to start it 2039 was not running. */ 2040 __IM uint32_t RESERVED1[60]; 2041 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2042 are no longer generated */ 2043 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 2044 on sequence n */ 2045 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 2046 sequence n, when last value from RAM has 2047 been applied to wave counter */ 2048 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2049 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2050 of times defined in LOOP.CNT */ 2051 __IM uint32_t RESERVED2[56]; 2052 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2053 __IM uint32_t RESERVED3[63]; 2054 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2055 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2056 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2057 __IM uint32_t RESERVED4[125]; 2058 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2059 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2060 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2061 counts */ 2062 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2063 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2064 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Amount of playback of a loop */ 2065 __IM uint32_t RESERVED5[2]; 2066 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2067 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2068 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2069 2070 2071 2072 /* =========================================================================================================================== */ 2073 /* ================ PDM ================ */ 2074 /* =========================================================================================================================== */ 2075 2076 2077 /** 2078 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 2079 */ 2080 2081 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 2082 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2083 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2084 __IM uint32_t RESERVED[62]; 2085 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2086 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2087 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2088 by SAMPLE.MAXCNT (or the last sample after 2089 a STOP task has been received) to Data RAM */ 2090 __IM uint32_t RESERVED1[125]; 2091 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2092 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2093 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2094 __IM uint32_t RESERVED2[125]; 2095 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2096 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2097 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2098 signals */ 2099 __IM uint32_t RESERVED3[3]; 2100 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2101 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2102 __IM uint32_t RESERVED4[8]; 2103 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2104 __IM uint32_t RESERVED5[6]; 2105 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2106 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2107 2108 2109 2110 /* =========================================================================================================================== */ 2111 /* ================ NVMC ================ */ 2112 /* =========================================================================================================================== */ 2113 2114 2115 /** 2116 * @brief Non Volatile Memory Controller (NVMC) 2117 */ 2118 2119 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 2120 __IM uint32_t RESERVED[256]; 2121 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2122 __IM uint32_t RESERVED1[64]; 2123 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2124 2125 union { 2126 __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in Code area */ 2127 __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 2128 page in Code area. Equivalent to ERASEPAGE. */ 2129 }; 2130 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2131 __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 2132 page in Code area. Equivalent to ERASEPAGE. */ 2133 __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing User Information Configuration 2134 Registers */ 2135 __IM uint32_t RESERVED2[10]; 2136 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-Code cache configuration register. */ 2137 __IM uint32_t RESERVED3; 2138 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-Code cache hit counter. */ 2139 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. */ 2140 } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 2141 2142 2143 2144 /* =========================================================================================================================== */ 2145 /* ================ PPI ================ */ 2146 /* =========================================================================================================================== */ 2147 2148 2149 /** 2150 * @brief Programmable Peripheral Interconnect (PPI) 2151 */ 2152 2153 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 2154 __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2155 __IM uint32_t RESERVED[308]; 2156 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2157 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2158 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2159 __IM uint32_t RESERVED1; 2160 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 2161 __IM uint32_t RESERVED2[148]; 2162 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ 2163 __IM uint32_t RESERVED3[62]; 2164 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 2165 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 2166 2167 2168 2169 /* =========================================================================================================================== */ 2170 /* ================ MWU ================ */ 2171 /* =========================================================================================================================== */ 2172 2173 2174 /** 2175 * @brief Memory Watch Unit (MWU) 2176 */ 2177 2178 typedef struct { /*!< (@ 0x40020000) MWU Structure */ 2179 __IM uint32_t RESERVED[64]; 2180 __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */ 2181 __IM uint32_t RESERVED1[16]; 2182 __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */ 2183 __IM uint32_t RESERVED2[100]; 2184 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2185 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2186 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2187 __IM uint32_t RESERVED3[5]; 2188 __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */ 2189 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ 2190 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ 2191 __IM uint32_t RESERVED4[53]; 2192 __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ 2193 __IM uint32_t RESERVED5[64]; 2194 __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ 2195 __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ 2196 __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ 2197 __IM uint32_t RESERVED6[57]; 2198 __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ 2199 __IM uint32_t RESERVED7[32]; 2200 __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ 2201 } NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ 2202 2203 2204 2205 /* =========================================================================================================================== */ 2206 /* ================ I2S ================ */ 2207 /* =========================================================================================================================== */ 2208 2209 2210 /** 2211 * @brief Inter-IC Sound (I2S) 2212 */ 2213 2214 typedef struct { /*!< (@ 0x40025000) I2S Structure */ 2215 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2216 generator when this is enabled. */ 2217 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2218 Triggering this task will cause the {event:STOPPED} 2219 event to be generated. */ 2220 __IM uint32_t RESERVED[63]; 2221 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2222 double-buffers. When the I2S module is started 2223 and RX is enabled, this event will be generated 2224 for every RXTXD.MAXCNT words that are received 2225 on the SDIN pin. */ 2226 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2227 __IM uint32_t RESERVED1[2]; 2228 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2229 double-buffers. When the I2S module is started 2230 and TX is enabled, this event will be generated 2231 for every RXTXD.MAXCNT words that are sent 2232 on the SDOUT pin. */ 2233 __IM uint32_t RESERVED2[122]; 2234 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2235 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2236 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2237 __IM uint32_t RESERVED3[125]; 2238 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2239 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2240 __IM uint32_t RESERVED4[3]; 2241 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2242 __IM uint32_t RESERVED5; 2243 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2244 __IM uint32_t RESERVED6[3]; 2245 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2246 __IM uint32_t RESERVED7[3]; 2247 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2248 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2249 2250 2251 2252 /* =========================================================================================================================== */ 2253 /* ================ FPU ================ */ 2254 /* =========================================================================================================================== */ 2255 2256 2257 /** 2258 * @brief FPU (FPU) 2259 */ 2260 2261 typedef struct { /*!< (@ 0x40026000) FPU Structure */ 2262 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2263 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2264 2265 2266 /** @} */ /* End of group Device_Peripheral_peripherals */ 2267 2268 2269 /* =========================================================================================================================== */ 2270 /* ================ Device Specific Peripheral Address Map ================ */ 2271 /* =========================================================================================================================== */ 2272 2273 2274 /** @addtogroup Device_Peripheral_peripheralAddr 2275 * @{ 2276 */ 2277 2278 #define NRF_FICR_BASE 0x10000000UL 2279 #define NRF_UICR_BASE 0x10001000UL 2280 #define NRF_APPROTECT_BASE 0x40000000UL 2281 #define NRF_BPROT_BASE 0x40000000UL 2282 #define NRF_CLOCK_BASE 0x40000000UL 2283 #define NRF_POWER_BASE 0x40000000UL 2284 #define NRF_P0_BASE 0x50000000UL 2285 #define NRF_RADIO_BASE 0x40001000UL 2286 #define NRF_UART0_BASE 0x40002000UL 2287 #define NRF_UARTE0_BASE 0x40002000UL 2288 #define NRF_SPI0_BASE 0x40003000UL 2289 #define NRF_SPIM0_BASE 0x40003000UL 2290 #define NRF_SPIS0_BASE 0x40003000UL 2291 #define NRF_TWI0_BASE 0x40003000UL 2292 #define NRF_TWIM0_BASE 0x40003000UL 2293 #define NRF_TWIS0_BASE 0x40003000UL 2294 #define NRF_SPI1_BASE 0x40004000UL 2295 #define NRF_SPIM1_BASE 0x40004000UL 2296 #define NRF_SPIS1_BASE 0x40004000UL 2297 #define NRF_TWI1_BASE 0x40004000UL 2298 #define NRF_TWIM1_BASE 0x40004000UL 2299 #define NRF_TWIS1_BASE 0x40004000UL 2300 #define NRF_NFCT_BASE 0x40005000UL 2301 #define NRF_GPIOTE_BASE 0x40006000UL 2302 #define NRF_SAADC_BASE 0x40007000UL 2303 #define NRF_TIMER0_BASE 0x40008000UL 2304 #define NRF_TIMER1_BASE 0x40009000UL 2305 #define NRF_TIMER2_BASE 0x4000A000UL 2306 #define NRF_RTC0_BASE 0x4000B000UL 2307 #define NRF_TEMP_BASE 0x4000C000UL 2308 #define NRF_RNG_BASE 0x4000D000UL 2309 #define NRF_ECB_BASE 0x4000E000UL 2310 #define NRF_AAR_BASE 0x4000F000UL 2311 #define NRF_CCM_BASE 0x4000F000UL 2312 #define NRF_WDT_BASE 0x40010000UL 2313 #define NRF_RTC1_BASE 0x40011000UL 2314 #define NRF_QDEC_BASE 0x40012000UL 2315 #define NRF_COMP_BASE 0x40013000UL 2316 #define NRF_LPCOMP_BASE 0x40013000UL 2317 #define NRF_EGU0_BASE 0x40014000UL 2318 #define NRF_SWI0_BASE 0x40014000UL 2319 #define NRF_EGU1_BASE 0x40015000UL 2320 #define NRF_SWI1_BASE 0x40015000UL 2321 #define NRF_EGU2_BASE 0x40016000UL 2322 #define NRF_SWI2_BASE 0x40016000UL 2323 #define NRF_EGU3_BASE 0x40017000UL 2324 #define NRF_SWI3_BASE 0x40017000UL 2325 #define NRF_EGU4_BASE 0x40018000UL 2326 #define NRF_SWI4_BASE 0x40018000UL 2327 #define NRF_EGU5_BASE 0x40019000UL 2328 #define NRF_SWI5_BASE 0x40019000UL 2329 #define NRF_TIMER3_BASE 0x4001A000UL 2330 #define NRF_TIMER4_BASE 0x4001B000UL 2331 #define NRF_PWM0_BASE 0x4001C000UL 2332 #define NRF_PDM_BASE 0x4001D000UL 2333 #define NRF_NVMC_BASE 0x4001E000UL 2334 #define NRF_PPI_BASE 0x4001F000UL 2335 #define NRF_MWU_BASE 0x40020000UL 2336 #define NRF_PWM1_BASE 0x40021000UL 2337 #define NRF_PWM2_BASE 0x40022000UL 2338 #define NRF_SPI2_BASE 0x40023000UL 2339 #define NRF_SPIM2_BASE 0x40023000UL 2340 #define NRF_SPIS2_BASE 0x40023000UL 2341 #define NRF_RTC2_BASE 0x40024000UL 2342 #define NRF_I2S_BASE 0x40025000UL 2343 #define NRF_FPU_BASE 0x40026000UL 2344 2345 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2346 2347 2348 /* =========================================================================================================================== */ 2349 /* ================ Peripheral declaration ================ */ 2350 /* =========================================================================================================================== */ 2351 2352 2353 /** @addtogroup Device_Peripheral_declaration 2354 * @{ 2355 */ 2356 2357 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2358 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2359 #define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) 2360 #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) 2361 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2362 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2363 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2364 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2365 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2366 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2367 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2368 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2369 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2370 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2371 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2372 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2373 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2374 #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2375 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2376 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 2377 #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 2378 #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 2379 #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) 2380 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2381 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 2382 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2383 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2384 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2385 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2386 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2387 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2388 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2389 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2390 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2391 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2392 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2393 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2394 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2395 #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 2396 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2397 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2398 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2399 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2400 #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 2401 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2402 #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 2403 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2404 #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 2405 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2406 #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 2407 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2408 #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 2409 #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) 2410 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 2411 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 2412 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2413 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2414 #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) 2415 #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) 2416 #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) 2417 #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) 2418 #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) 2419 #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) 2420 #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) 2421 #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) 2422 #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) 2423 2424 /** @} */ /* End of group Device_Peripheral_declaration */ 2425 2426 2427 /* ========================================= End of section using anonymous unions ========================================= */ 2428 #if defined (__CC_ARM) 2429 #pragma pop 2430 #elif defined (__ICCARM__) 2431 /* leave anonymous unions enabled */ 2432 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 2433 #pragma clang diagnostic pop 2434 #elif defined (__GNUC__) 2435 /* anonymous unions are enabled by default */ 2436 #elif defined (__TMS470__) 2437 /* anonymous unions are enabled by default */ 2438 #elif defined (__TASKING__) 2439 #pragma warning restore 2440 #elif defined (__CSMC__) 2441 /* anonymous unions are enabled by default */ 2442 #endif 2443 2444 2445 #ifdef __cplusplus 2446 } 2447 #endif 2448 2449 #endif /* NRF52_H */ 2450 2451 2452 /** @} */ /* End of group nrf52 */ 2453 2454 /** @} */ /* End of group Nordic Semiconductor */ 2455
