1 /* 2 3 Copyright (c) 2010 - 2023, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF51_TO_NRF52840_H 36 #define NRF51_TO_NRF52840_H 37 38 /*lint ++flb "Enter library region */ 39 40 /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices. 41 * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the 42 * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros 43 * from the nrf51_deprecated.h file. */ 44 45 46 /* IRQ */ 47 /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ 48 #ifndef UART0_IRQHandler 49 #define UART0_IRQHandler UARTE0_UART0_IRQHandler 50 #endif 51 #ifndef SPI0_TWI0_IRQHandler 52 #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 53 #endif 54 #ifndef SPI1_TWI1_IRQHandler 55 #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 56 #endif 57 #ifndef ADC_IRQHandler 58 #define ADC_IRQHandler SAADC_IRQHandler 59 #endif 60 #ifndef LPCOMP_IRQHandler 61 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 62 #endif 63 #ifndef SWI0_IRQHandler 64 #define SWI0_IRQHandler SWI0_EGU0_IRQHandler 65 #endif 66 #ifndef SWI1_IRQHandler 67 #define SWI1_IRQHandler SWI1_EGU1_IRQHandler 68 #endif 69 #ifndef SWI2_IRQHandler 70 #define SWI2_IRQHandler SWI2_EGU2_IRQHandler 71 #endif 72 #ifndef SWI3_IRQHandler 73 #define SWI3_IRQHandler SWI3_EGU3_IRQHandler 74 #endif 75 #ifndef SWI4_IRQHandler 76 #define SWI4_IRQHandler SWI4_EGU4_IRQHandler 77 #endif 78 #ifndef SWI5_IRQHandler 79 #define SWI5_IRQHandler SWI5_EGU5_IRQHandler 80 #endif 81 82 #ifndef UART0_IRQn 83 #define UART0_IRQn UARTE0_UART0_IRQn 84 #endif 85 #ifndef SPI0_TWI0_IRQn 86 #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 87 #endif 88 #ifndef SPI1_TWI1_IRQn 89 #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 90 #endif 91 #ifndef ADC_IRQn 92 #define ADC_IRQn SAADC_IRQn 93 #endif 94 #ifndef LPCOMP_IRQn 95 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 96 #endif 97 #ifndef SWI0_IRQn 98 #define SWI0_IRQn SWI0_EGU0_IRQn 99 #endif 100 #ifndef SWI1_IRQn 101 #define SWI1_IRQn SWI1_EGU1_IRQn 102 #endif 103 #ifndef SWI2_IRQn 104 #define SWI2_IRQn SWI2_EGU2_IRQn 105 #endif 106 #ifndef SWI3_IRQn 107 #define SWI3_IRQn SWI3_EGU3_IRQn 108 #endif 109 #ifndef SWI4_IRQn 110 #define SWI4_IRQn SWI4_EGU4_IRQn 111 #endif 112 #ifndef SWI5_IRQn 113 #define SWI5_IRQn SWI5_EGU5_IRQn 114 #endif 115 116 117 /* UICR */ 118 /* Register RBPCONF was renamed to APPROTECT. */ 119 #ifndef RBPCONF 120 #define RBPCONF APPROTECT 121 #endif 122 123 #ifndef UICR_RBPCONF_PALL_Pos 124 #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos 125 #endif 126 #ifndef UICR_RBPCONF_PALL_Msk 127 #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk 128 #endif 129 #ifndef UICR_RBPCONF_PALL_Enabled 130 #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled 131 #endif 132 #ifndef UICR_RBPCONF_PALL_Disabled 133 #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled 134 #endif 135 136 137 /* GPIO */ 138 /* GPIO port was renamed to P0. */ 139 #ifndef NRF_GPIO 140 #define NRF_GPIO NRF_P0 141 #endif 142 #ifndef NRF_GPIO_BASE 143 #define NRF_GPIO_BASE NRF_P0_BASE 144 #endif 145 146 147 /* QDEC */ 148 /* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ 149 #ifndef PSELLED 150 #define PSELLED PSEL.LED 151 #endif 152 #ifndef PSELA 153 #define PSELA PSEL.A 154 #endif 155 #ifndef PSELB 156 #define PSELB PSEL.B 157 #endif 158 159 160 /* SPIS */ 161 /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ 162 #ifndef PSELSCK 163 #define PSELSCK PSEL.SCK 164 #endif 165 #ifndef PSELMISO 166 #define PSELMISO PSEL.MISO 167 #endif 168 #ifndef PSELMOSI 169 #define PSELMOSI PSEL.MOSI 170 #endif 171 #ifndef PSELCSN 172 #define PSELCSN PSEL.CSN 173 #endif 174 175 /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ 176 #ifndef RXDPTR 177 #define RXDPTR RXD.PTR 178 #endif 179 #ifndef MAXRX 180 #define MAXRX RXD.MAXCNT 181 #endif 182 #ifndef AMOUNTRX 183 #define AMOUNTRX RXD.AMOUNT 184 #endif 185 186 #ifndef SPIS_MAXRX_MAXRX_Pos 187 #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos 188 #endif 189 #ifndef SPIS_MAXRX_MAXRX_Msk 190 #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk 191 #endif 192 193 #ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos 194 #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos 195 #endif 196 #ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk 197 #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk 198 #endif 199 200 /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ 201 #ifndef TXDPTR 202 #define TXDPTR TXD.PTR 203 #endif 204 #ifndef MAXTX 205 #define MAXTX TXD.MAXCNT 206 #endif 207 #ifndef AMOUNTTX 208 #define AMOUNTTX TXD.AMOUNT 209 #endif 210 211 #ifndef SPIS_MAXTX_MAXTX_Pos 212 #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos 213 #endif 214 #ifndef SPIS_MAXTX_MAXTX_Msk 215 #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk 216 #endif 217 218 #ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos 219 #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos 220 #endif 221 #ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk 222 #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk 223 #endif 224 225 226 /* UART */ 227 /* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ 228 #ifndef PSELRTS 229 #define PSELRTS PSEL.RTS 230 #endif 231 #ifndef PSELTXD 232 #define PSELTXD PSEL.TXD 233 #endif 234 #ifndef PSELCTS 235 #define PSELCTS PSEL.CTS 236 #endif 237 #ifndef PSELRXD 238 #define PSELRXD PSEL.RXD 239 #endif 240 241 /* TWI */ 242 /* The registers PSELSCL, PSELSDA were restructured into a struct. */ 243 #ifndef PSELSCL 244 #define PSELSCL PSEL.SCL 245 #endif 246 #ifndef PSELSDA 247 #define PSELSDA PSEL.SDA 248 #endif 249 250 251 /* From nrf51_deprecated.h */ 252 253 /* NVMC */ 254 /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ 255 #ifndef ERASEPROTECTEDPAGE 256 #define ERASEPROTECTEDPAGE ERASEPCR0 257 #endif 258 259 260 /* IRQ */ 261 /* COMP module was eliminated. Adapted to nrf52840 headers. */ 262 #ifndef LPCOMP_COMP_IRQHandler 263 #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler 264 #endif 265 #ifndef LPCOMP_COMP_IRQn 266 #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn 267 #endif 268 269 270 /* REFSEL register redefined enumerated values and added some more. */ 271 #ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling 272 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd 273 #endif 274 #ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling 275 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd 276 #endif 277 #ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling 278 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd 279 #endif 280 #ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling 281 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd 282 #endif 283 #ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling 284 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd 285 #endif 286 #ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling 287 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd 288 #endif 289 #ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling 290 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd 291 #endif 292 293 294 /* RADIO */ 295 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ 296 #ifndef RADIO_CRCCNF_SKIP_ADDR_Pos 297 #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos 298 #endif 299 #ifndef RADIO_CRCCNF_SKIP_ADDR_Msk 300 #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk 301 #endif 302 #ifndef RADIO_CRCCNF_SKIP_ADDR_Include 303 #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include 304 #endif 305 #ifndef RADIO_CRCCNF_SKIP_ADDR_Skip 306 #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip 307 #endif 308 309 310 /* FICR */ 311 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ 312 #ifndef DEVICEID0 313 #define DEVICEID0 DEVICEID[0] 314 #endif 315 #ifndef DEVICEID1 316 #define DEVICEID1 DEVICEID[1] 317 #endif 318 319 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ 320 #ifndef ER0 321 #define ER0 ER[0] 322 #endif 323 #ifndef ER1 324 #define ER1 ER[1] 325 #endif 326 #ifndef ER2 327 #define ER2 ER[2] 328 #endif 329 #ifndef ER3 330 #define ER3 ER[3] 331 #endif 332 333 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ 334 #ifndef IR0 335 #define IR0 IR[0] 336 #endif 337 #ifndef IR1 338 #define IR1 IR[1] 339 #endif 340 #ifndef IR2 341 #define IR2 IR[2] 342 #endif 343 #ifndef IR3 344 #define IR3 IR[3] 345 #endif 346 347 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ 348 #ifndef DEVICEADDR0 349 #define DEVICEADDR0 DEVICEADDR[0] 350 #endif 351 #ifndef DEVICEADDR1 352 #define DEVICEADDR1 DEVICEADDR[1] 353 #endif 354 355 356 /* PPI */ 357 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ 358 #ifndef TASKS_CHG0EN 359 #define TASKS_CHG0EN TASKS_CHG[0].EN 360 #endif 361 #ifndef TASKS_CHG0DIS 362 #define TASKS_CHG0DIS TASKS_CHG[0].DIS 363 #endif 364 #ifndef TASKS_CHG1EN 365 #define TASKS_CHG1EN TASKS_CHG[1].EN 366 #endif 367 #ifndef TASKS_CHG1DIS 368 #define TASKS_CHG1DIS TASKS_CHG[1].DIS 369 #endif 370 #ifndef TASKS_CHG2EN 371 #define TASKS_CHG2EN TASKS_CHG[2].EN 372 #endif 373 #ifndef TASKS_CHG2DIS 374 #define TASKS_CHG2DIS TASKS_CHG[2].DIS 375 #endif 376 #ifndef TASKS_CHG3EN 377 #define TASKS_CHG3EN TASKS_CHG[3].EN 378 #endif 379 #ifndef TASKS_CHG3DIS 380 #define TASKS_CHG3DIS TASKS_CHG[3].DIS 381 #endif 382 383 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ 384 #ifndef CH0_EEP 385 #define CH0_EEP CH[0].EEP 386 #endif 387 #ifndef CH0_TEP 388 #define CH0_TEP CH[0].TEP 389 #endif 390 #ifndef CH1_EEP 391 #define CH1_EEP CH[1].EEP 392 #endif 393 #ifndef CH1_TEP 394 #define CH1_TEP CH[1].TEP 395 #endif 396 #ifndef CH2_EEP 397 #define CH2_EEP CH[2].EEP 398 #endif 399 #ifndef CH2_TEP 400 #define CH2_TEP CH[2].TEP 401 #endif 402 #ifndef CH3_EEP 403 #define CH3_EEP CH[3].EEP 404 #endif 405 #ifndef CH3_TEP 406 #define CH3_TEP CH[3].TEP 407 #endif 408 #ifndef CH4_EEP 409 #define CH4_EEP CH[4].EEP 410 #endif 411 #ifndef CH4_TEP 412 #define CH4_TEP CH[4].TEP 413 #endif 414 #ifndef CH5_EEP 415 #define CH5_EEP CH[5].EEP 416 #endif 417 #ifndef CH5_TEP 418 #define CH5_TEP CH[5].TEP 419 #endif 420 #ifndef CH6_EEP 421 #define CH6_EEP CH[6].EEP 422 #endif 423 #ifndef CH6_TEP 424 #define CH6_TEP CH[6].TEP 425 #endif 426 #ifndef CH7_EEP 427 #define CH7_EEP CH[7].EEP 428 #endif 429 #ifndef CH7_TEP 430 #define CH7_TEP CH[7].TEP 431 #endif 432 #ifndef CH8_EEP 433 #define CH8_EEP CH[8].EEP 434 #endif 435 #ifndef CH8_TEP 436 #define CH8_TEP CH[8].TEP 437 #endif 438 #ifndef CH9_EEP 439 #define CH9_EEP CH[9].EEP 440 #endif 441 #ifndef CH9_TEP 442 #define CH9_TEP CH[9].TEP 443 #endif 444 #ifndef CH10_EEP 445 #define CH10_EEP CH[10].EEP 446 #endif 447 #ifndef CH10_TEP 448 #define CH10_TEP CH[10].TEP 449 #endif 450 #ifndef CH11_EEP 451 #define CH11_EEP CH[11].EEP 452 #endif 453 #ifndef CH11_TEP 454 #define CH11_TEP CH[11].TEP 455 #endif 456 #ifndef CH12_EEP 457 #define CH12_EEP CH[12].EEP 458 #endif 459 #ifndef CH12_TEP 460 #define CH12_TEP CH[12].TEP 461 #endif 462 #ifndef CH13_EEP 463 #define CH13_EEP CH[13].EEP 464 #endif 465 #ifndef CH13_TEP 466 #define CH13_TEP CH[13].TEP 467 #endif 468 #ifndef CH14_EEP 469 #define CH14_EEP CH[14].EEP 470 #endif 471 #ifndef CH14_TEP 472 #define CH14_TEP CH[14].TEP 473 #endif 474 #ifndef CH15_EEP 475 #define CH15_EEP CH[15].EEP 476 #endif 477 #ifndef CH15_TEP 478 #define CH15_TEP CH[15].TEP 479 #endif 480 481 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ 482 #ifndef CHG0 483 #define CHG0 CHG[0] 484 #endif 485 #ifndef CHG1 486 #define CHG1 CHG[1] 487 #endif 488 #ifndef CHG2 489 #define CHG2 CHG[2] 490 #endif 491 #ifndef CHG3 492 #define CHG3 CHG[3] 493 #endif 494 495 /* All bitfield macros for the CHGx registers therefore changed name. */ 496 #ifndef PPI_CHG0_CH15_Pos 497 #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos 498 #endif 499 #ifndef PPI_CHG0_CH15_Msk 500 #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk 501 #endif 502 #ifndef PPI_CHG0_CH15_Excluded 503 #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded 504 #endif 505 #ifndef PPI_CHG0_CH15_Included 506 #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included 507 #endif 508 509 #ifndef PPI_CHG0_CH14_Pos 510 #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos 511 #endif 512 #ifndef PPI_CHG0_CH14_Msk 513 #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk 514 #endif 515 #ifndef PPI_CHG0_CH14_Excluded 516 #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded 517 #endif 518 #ifndef PPI_CHG0_CH14_Included 519 #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included 520 #endif 521 522 #ifndef PPI_CHG0_CH13_Pos 523 #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos 524 #endif 525 #ifndef PPI_CHG0_CH13_Msk 526 #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk 527 #endif 528 #ifndef PPI_CHG0_CH13_Excluded 529 #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded 530 #endif 531 #ifndef PPI_CHG0_CH13_Included 532 #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included 533 #endif 534 535 #ifndef PPI_CHG0_CH12_Pos 536 #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos 537 #endif 538 #ifndef PPI_CHG0_CH12_Msk 539 #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk 540 #endif 541 #ifndef PPI_CHG0_CH12_Excluded 542 #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded 543 #endif 544 #ifndef PPI_CHG0_CH12_Included 545 #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included 546 #endif 547 548 #ifndef PPI_CHG0_CH11_Pos 549 #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos 550 #endif 551 #ifndef PPI_CHG0_CH11_Msk 552 #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk 553 #endif 554 #ifndef PPI_CHG0_CH11_Excluded 555 #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded 556 #endif 557 #ifndef PPI_CHG0_CH11_Included 558 #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included 559 #endif 560 561 #ifndef PPI_CHG0_CH10_Pos 562 #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos 563 #endif 564 #ifndef PPI_CHG0_CH10_Msk 565 #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk 566 #endif 567 #ifndef PPI_CHG0_CH10_Excluded 568 #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded 569 #endif 570 #ifndef PPI_CHG0_CH10_Included 571 #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included 572 #endif 573 574 #ifndef PPI_CHG0_CH9_Pos 575 #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos 576 #endif 577 #ifndef PPI_CHG0_CH9_Msk 578 #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk 579 #endif 580 #ifndef PPI_CHG0_CH9_Excluded 581 #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded 582 #endif 583 #ifndef PPI_CHG0_CH9_Included 584 #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included 585 #endif 586 587 #ifndef PPI_CHG0_CH8_Pos 588 #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos 589 #endif 590 #ifndef PPI_CHG0_CH8_Msk 591 #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk 592 #endif 593 #ifndef PPI_CHG0_CH8_Excluded 594 #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded 595 #endif 596 #ifndef PPI_CHG0_CH8_Included 597 #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included 598 #endif 599 600 #ifndef PPI_CHG0_CH7_Pos 601 #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos 602 #endif 603 #ifndef PPI_CHG0_CH7_Msk 604 #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk 605 #endif 606 #ifndef PPI_CHG0_CH7_Excluded 607 #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded 608 #endif 609 #ifndef PPI_CHG0_CH7_Included 610 #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included 611 #endif 612 613 #ifndef PPI_CHG0_CH6_Pos 614 #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos 615 #endif 616 #ifndef PPI_CHG0_CH6_Msk 617 #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk 618 #endif 619 #ifndef PPI_CHG0_CH6_Excluded 620 #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded 621 #endif 622 #ifndef PPI_CHG0_CH6_Included 623 #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included 624 #endif 625 626 #ifndef PPI_CHG0_CH5_Pos 627 #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos 628 #endif 629 #ifndef PPI_CHG0_CH5_Msk 630 #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk 631 #endif 632 #ifndef PPI_CHG0_CH5_Excluded 633 #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded 634 #endif 635 #ifndef PPI_CHG0_CH5_Included 636 #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included 637 #endif 638 639 #ifndef PPI_CHG0_CH4_Pos 640 #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos 641 #endif 642 #ifndef PPI_CHG0_CH4_Msk 643 #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk 644 #endif 645 #ifndef PPI_CHG0_CH4_Excluded 646 #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded 647 #endif 648 #ifndef PPI_CHG0_CH4_Included 649 #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included 650 #endif 651 652 #ifndef PPI_CHG0_CH3_Pos 653 #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos 654 #endif 655 #ifndef PPI_CHG0_CH3_Msk 656 #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk 657 #endif 658 #ifndef PPI_CHG0_CH3_Excluded 659 #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded 660 #endif 661 #ifndef PPI_CHG0_CH3_Included 662 #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included 663 #endif 664 665 #ifndef PPI_CHG0_CH2_Pos 666 #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos 667 #endif 668 #ifndef PPI_CHG0_CH2_Msk 669 #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk 670 #endif 671 #ifndef PPI_CHG0_CH2_Excluded 672 #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded 673 #endif 674 #ifndef PPI_CHG0_CH2_Included 675 #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included 676 #endif 677 678 #ifndef PPI_CHG0_CH1_Pos 679 #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos 680 #endif 681 #ifndef PPI_CHG0_CH1_Msk 682 #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk 683 #endif 684 #ifndef PPI_CHG0_CH1_Excluded 685 #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded 686 #endif 687 #ifndef PPI_CHG0_CH1_Included 688 #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included 689 #endif 690 691 #ifndef PPI_CHG0_CH0_Pos 692 #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos 693 #endif 694 #ifndef PPI_CHG0_CH0_Msk 695 #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk 696 #endif 697 #ifndef PPI_CHG0_CH0_Excluded 698 #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded 699 #endif 700 #ifndef PPI_CHG0_CH0_Included 701 #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included 702 #endif 703 704 #ifndef PPI_CHG1_CH15_Pos 705 #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos 706 #endif 707 #ifndef PPI_CHG1_CH15_Msk 708 #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk 709 #endif 710 #ifndef PPI_CHG1_CH15_Excluded 711 #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded 712 #endif 713 #ifndef PPI_CHG1_CH15_Included 714 #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included 715 #endif 716 717 #ifndef PPI_CHG1_CH14_Pos 718 #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos 719 #endif 720 #ifndef PPI_CHG1_CH14_Msk 721 #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk 722 #endif 723 #ifndef PPI_CHG1_CH14_Excluded 724 #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded 725 #endif 726 #ifndef PPI_CHG1_CH14_Included 727 #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included 728 #endif 729 730 #ifndef PPI_CHG1_CH13_Pos 731 #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos 732 #endif 733 #ifndef PPI_CHG1_CH13_Msk 734 #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk 735 #endif 736 #ifndef PPI_CHG1_CH13_Excluded 737 #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded 738 #endif 739 #ifndef PPI_CHG1_CH13_Included 740 #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included 741 #endif 742 743 #ifndef PPI_CHG1_CH12_Pos 744 #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos 745 #endif 746 #ifndef PPI_CHG1_CH12_Msk 747 #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk 748 #endif 749 #ifndef PPI_CHG1_CH12_Excluded 750 #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded 751 #endif 752 #ifndef PPI_CHG1_CH12_Included 753 #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included 754 #endif 755 756 #ifndef PPI_CHG1_CH11_Pos 757 #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos 758 #endif 759 #ifndef PPI_CHG1_CH11_Msk 760 #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk 761 #endif 762 #ifndef PPI_CHG1_CH11_Excluded 763 #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded 764 #endif 765 #ifndef PPI_CHG1_CH11_Included 766 #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included 767 #endif 768 769 #ifndef PPI_CHG1_CH10_Pos 770 #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos 771 #endif 772 #ifndef PPI_CHG1_CH10_Msk 773 #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk 774 #endif 775 #ifndef PPI_CHG1_CH10_Excluded 776 #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded 777 #endif 778 #ifndef PPI_CHG1_CH10_Included 779 #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included 780 #endif 781 782 #ifndef PPI_CHG1_CH9_Pos 783 #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos 784 #endif 785 #ifndef PPI_CHG1_CH9_Msk 786 #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk 787 #endif 788 #ifndef PPI_CHG1_CH9_Excluded 789 #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded 790 #endif 791 #ifndef PPI_CHG1_CH9_Included 792 #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included 793 #endif 794 795 #ifndef PPI_CHG1_CH8_Pos 796 #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos 797 #endif 798 #ifndef PPI_CHG1_CH8_Msk 799 #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk 800 #endif 801 #ifndef PPI_CHG1_CH8_Excluded 802 #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded 803 #endif 804 #ifndef PPI_CHG1_CH8_Included 805 #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included 806 #endif 807 808 #ifndef PPI_CHG1_CH7_Pos 809 #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos 810 #endif 811 #ifndef PPI_CHG1_CH7_Msk 812 #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk 813 #endif 814 #ifndef PPI_CHG1_CH7_Excluded 815 #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded 816 #endif 817 #ifndef PPI_CHG1_CH7_Included 818 #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included 819 #endif 820 821 #ifndef PPI_CHG1_CH6_Pos 822 #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos 823 #endif 824 #ifndef PPI_CHG1_CH6_Msk 825 #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk 826 #endif 827 #ifndef PPI_CHG1_CH6_Excluded 828 #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded 829 #endif 830 #ifndef PPI_CHG1_CH6_Included 831 #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included 832 #endif 833 834 #ifndef PPI_CHG1_CH5_Pos 835 #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos 836 #endif 837 #ifndef PPI_CHG1_CH5_Msk 838 #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk 839 #endif 840 #ifndef PPI_CHG1_CH5_Excluded 841 #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded 842 #endif 843 #ifndef PPI_CHG1_CH5_Included 844 #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included 845 #endif 846 847 #ifndef PPI_CHG1_CH4_Pos 848 #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos 849 #endif 850 #ifndef PPI_CHG1_CH4_Msk 851 #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk 852 #endif 853 #ifndef PPI_CHG1_CH4_Excluded 854 #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded 855 #endif 856 #ifndef PPI_CHG1_CH4_Included 857 #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included 858 #endif 859 860 #ifndef PPI_CHG1_CH3_Pos 861 #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos 862 #endif 863 #ifndef PPI_CHG1_CH3_Msk 864 #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk 865 #endif 866 #ifndef PPI_CHG1_CH3_Excluded 867 #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded 868 #endif 869 #ifndef PPI_CHG1_CH3_Included 870 #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included 871 #endif 872 873 #ifndef PPI_CHG1_CH2_Pos 874 #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos 875 #endif 876 #ifndef PPI_CHG1_CH2_Msk 877 #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk 878 #endif 879 #ifndef PPI_CHG1_CH2_Excluded 880 #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded 881 #endif 882 #ifndef PPI_CHG1_CH2_Included 883 #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included 884 #endif 885 886 #ifndef PPI_CHG1_CH1_Pos 887 #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos 888 #endif 889 #ifndef PPI_CHG1_CH1_Msk 890 #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk 891 #endif 892 #ifndef PPI_CHG1_CH1_Excluded 893 #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded 894 #endif 895 #ifndef PPI_CHG1_CH1_Included 896 #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included 897 #endif 898 899 #ifndef PPI_CHG1_CH0_Pos 900 #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos 901 #endif 902 #ifndef PPI_CHG1_CH0_Msk 903 #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk 904 #endif 905 #ifndef PPI_CHG1_CH0_Excluded 906 #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded 907 #endif 908 #ifndef PPI_CHG1_CH0_Included 909 #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included 910 #endif 911 912 #ifndef PPI_CHG2_CH15_Pos 913 #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos 914 #endif 915 #ifndef PPI_CHG2_CH15_Msk 916 #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk 917 #endif 918 #ifndef PPI_CHG2_CH15_Excluded 919 #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded 920 #endif 921 #ifndef PPI_CHG2_CH15_Included 922 #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included 923 #endif 924 925 #ifndef PPI_CHG2_CH14_Pos 926 #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos 927 #endif 928 #ifndef PPI_CHG2_CH14_Msk 929 #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk 930 #endif 931 #ifndef PPI_CHG2_CH14_Excluded 932 #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded 933 #endif 934 #ifndef PPI_CHG2_CH14_Included 935 #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included 936 #endif 937 938 #ifndef PPI_CHG2_CH13_Pos 939 #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos 940 #endif 941 #ifndef PPI_CHG2_CH13_Msk 942 #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk 943 #endif 944 #ifndef PPI_CHG2_CH13_Excluded 945 #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded 946 #endif 947 #ifndef PPI_CHG2_CH13_Included 948 #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included 949 #endif 950 951 #ifndef PPI_CHG2_CH12_Pos 952 #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos 953 #endif 954 #ifndef PPI_CHG2_CH12_Msk 955 #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk 956 #endif 957 #ifndef PPI_CHG2_CH12_Excluded 958 #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded 959 #endif 960 #ifndef PPI_CHG2_CH12_Included 961 #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included 962 #endif 963 964 #ifndef PPI_CHG2_CH11_Pos 965 #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos 966 #endif 967 #ifndef PPI_CHG2_CH11_Msk 968 #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk 969 #endif 970 #ifndef PPI_CHG2_CH11_Excluded 971 #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded 972 #endif 973 #ifndef PPI_CHG2_CH11_Included 974 #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included 975 #endif 976 977 #ifndef PPI_CHG2_CH10_Pos 978 #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos 979 #endif 980 #ifndef PPI_CHG2_CH10_Msk 981 #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk 982 #endif 983 #ifndef PPI_CHG2_CH10_Excluded 984 #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded 985 #endif 986 #ifndef PPI_CHG2_CH10_Included 987 #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included 988 #endif 989 990 #ifndef PPI_CHG2_CH9_Pos 991 #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos 992 #endif 993 #ifndef PPI_CHG2_CH9_Msk 994 #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk 995 #endif 996 #ifndef PPI_CHG2_CH9_Excluded 997 #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded 998 #endif 999 #ifndef PPI_CHG2_CH9_Included 1000 #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included 1001 #endif 1002 1003 #ifndef PPI_CHG2_CH8_Pos 1004 #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos 1005 #endif 1006 #ifndef PPI_CHG2_CH8_Msk 1007 #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk 1008 #endif 1009 #ifndef PPI_CHG2_CH8_Excluded 1010 #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded 1011 #endif 1012 #ifndef PPI_CHG2_CH8_Included 1013 #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included 1014 #endif 1015 1016 #ifndef PPI_CHG2_CH7_Pos 1017 #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos 1018 #endif 1019 #ifndef PPI_CHG2_CH7_Msk 1020 #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk 1021 #endif 1022 #ifndef PPI_CHG2_CH7_Excluded 1023 #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded 1024 #endif 1025 #ifndef PPI_CHG2_CH7_Included 1026 #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included 1027 #endif 1028 1029 #ifndef PPI_CHG2_CH6_Pos 1030 #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos 1031 #endif 1032 #ifndef PPI_CHG2_CH6_Msk 1033 #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk 1034 #endif 1035 #ifndef PPI_CHG2_CH6_Excluded 1036 #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded 1037 #endif 1038 #ifndef PPI_CHG2_CH6_Included 1039 #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included 1040 #endif 1041 1042 #ifndef PPI_CHG2_CH5_Pos 1043 #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos 1044 #endif 1045 #ifndef PPI_CHG2_CH5_Msk 1046 #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk 1047 #endif 1048 #ifndef PPI_CHG2_CH5_Excluded 1049 #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded 1050 #endif 1051 #ifndef PPI_CHG2_CH5_Included 1052 #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included 1053 #endif 1054 1055 #ifndef PPI_CHG2_CH4_Pos 1056 #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos 1057 #endif 1058 #ifndef PPI_CHG2_CH4_Msk 1059 #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk 1060 #endif 1061 #ifndef PPI_CHG2_CH4_Excluded 1062 #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded 1063 #endif 1064 #ifndef PPI_CHG2_CH4_Included 1065 #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included 1066 #endif 1067 1068 #ifndef PPI_CHG2_CH3_Pos 1069 #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos 1070 #endif 1071 #ifndef PPI_CHG2_CH3_Msk 1072 #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk 1073 #endif 1074 #ifndef PPI_CHG2_CH3_Excluded 1075 #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded 1076 #endif 1077 #ifndef PPI_CHG2_CH3_Included 1078 #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included 1079 #endif 1080 1081 #ifndef PPI_CHG2_CH2_Pos 1082 #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos 1083 #endif 1084 #ifndef PPI_CHG2_CH2_Msk 1085 #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk 1086 #endif 1087 #ifndef PPI_CHG2_CH2_Excluded 1088 #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded 1089 #endif 1090 #ifndef PPI_CHG2_CH2_Included 1091 #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included 1092 #endif 1093 1094 #ifndef PPI_CHG2_CH1_Pos 1095 #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos 1096 #endif 1097 #ifndef PPI_CHG2_CH1_Msk 1098 #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk 1099 #endif 1100 #ifndef PPI_CHG2_CH1_Excluded 1101 #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded 1102 #endif 1103 #ifndef PPI_CHG2_CH1_Included 1104 #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included 1105 #endif 1106 1107 #ifndef PPI_CHG2_CH0_Pos 1108 #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos 1109 #endif 1110 #ifndef PPI_CHG2_CH0_Msk 1111 #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk 1112 #endif 1113 #ifndef PPI_CHG2_CH0_Excluded 1114 #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded 1115 #endif 1116 #ifndef PPI_CHG2_CH0_Included 1117 #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included 1118 #endif 1119 1120 #ifndef PPI_CHG3_CH15_Pos 1121 #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos 1122 #endif 1123 #ifndef PPI_CHG3_CH15_Msk 1124 #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk 1125 #endif 1126 #ifndef PPI_CHG3_CH15_Excluded 1127 #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded 1128 #endif 1129 #ifndef PPI_CHG3_CH15_Included 1130 #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included 1131 #endif 1132 1133 #ifndef PPI_CHG3_CH14_Pos 1134 #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos 1135 #endif 1136 #ifndef PPI_CHG3_CH14_Msk 1137 #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk 1138 #endif 1139 #ifndef PPI_CHG3_CH14_Excluded 1140 #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded 1141 #endif 1142 #ifndef PPI_CHG3_CH14_Included 1143 #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included 1144 #endif 1145 1146 #ifndef PPI_CHG3_CH13_Pos 1147 #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos 1148 #endif 1149 #ifndef PPI_CHG3_CH13_Msk 1150 #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk 1151 #endif 1152 #ifndef PPI_CHG3_CH13_Excluded 1153 #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded 1154 #endif 1155 #ifndef PPI_CHG3_CH13_Included 1156 #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included 1157 #endif 1158 1159 #ifndef PPI_CHG3_CH12_Pos 1160 #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos 1161 #endif 1162 #ifndef PPI_CHG3_CH12_Msk 1163 #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk 1164 #endif 1165 #ifndef PPI_CHG3_CH12_Excluded 1166 #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded 1167 #endif 1168 #ifndef PPI_CHG3_CH12_Included 1169 #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included 1170 #endif 1171 1172 #ifndef PPI_CHG3_CH11_Pos 1173 #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos 1174 #endif 1175 #ifndef PPI_CHG3_CH11_Msk 1176 #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk 1177 #endif 1178 #ifndef PPI_CHG3_CH11_Excluded 1179 #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded 1180 #endif 1181 #ifndef PPI_CHG3_CH11_Included 1182 #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included 1183 #endif 1184 1185 #ifndef PPI_CHG3_CH10_Pos 1186 #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos 1187 #endif 1188 #ifndef PPI_CHG3_CH10_Msk 1189 #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk 1190 #endif 1191 #ifndef PPI_CHG3_CH10_Excluded 1192 #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded 1193 #endif 1194 #ifndef PPI_CHG3_CH10_Included 1195 #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included 1196 #endif 1197 1198 #ifndef PPI_CHG3_CH9_Pos 1199 #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos 1200 #endif 1201 #ifndef PPI_CHG3_CH9_Msk 1202 #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk 1203 #endif 1204 #ifndef PPI_CHG3_CH9_Excluded 1205 #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded 1206 #endif 1207 #ifndef PPI_CHG3_CH9_Included 1208 #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included 1209 #endif 1210 1211 #ifndef PPI_CHG3_CH8_Pos 1212 #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos 1213 #endif 1214 #ifndef PPI_CHG3_CH8_Msk 1215 #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk 1216 #endif 1217 #ifndef PPI_CHG3_CH8_Excluded 1218 #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded 1219 #endif 1220 #ifndef PPI_CHG3_CH8_Included 1221 #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included 1222 #endif 1223 1224 #ifndef PPI_CHG3_CH7_Pos 1225 #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos 1226 #endif 1227 #ifndef PPI_CHG3_CH7_Msk 1228 #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk 1229 #endif 1230 #ifndef PPI_CHG3_CH7_Excluded 1231 #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded 1232 #endif 1233 #ifndef PPI_CHG3_CH7_Included 1234 #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included 1235 #endif 1236 1237 #ifndef PPI_CHG3_CH6_Pos 1238 #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos 1239 #endif 1240 #ifndef PPI_CHG3_CH6_Msk 1241 #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk 1242 #endif 1243 #ifndef PPI_CHG3_CH6_Excluded 1244 #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded 1245 #endif 1246 #ifndef PPI_CHG3_CH6_Included 1247 #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included 1248 #endif 1249 1250 #ifndef PPI_CHG3_CH5_Pos 1251 #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos 1252 #endif 1253 #ifndef PPI_CHG3_CH5_Msk 1254 #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk 1255 #endif 1256 #ifndef PPI_CHG3_CH5_Excluded 1257 #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded 1258 #endif 1259 #ifndef PPI_CHG3_CH5_Included 1260 #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included 1261 #endif 1262 1263 #ifndef PPI_CHG3_CH4_Pos 1264 #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos 1265 #endif 1266 #ifndef PPI_CHG3_CH4_Msk 1267 #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk 1268 #endif 1269 #ifndef PPI_CHG3_CH4_Excluded 1270 #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded 1271 #endif 1272 #ifndef PPI_CHG3_CH4_Included 1273 #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included 1274 #endif 1275 1276 #ifndef PPI_CHG3_CH3_Pos 1277 #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos 1278 #endif 1279 #ifndef PPI_CHG3_CH3_Msk 1280 #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk 1281 #endif 1282 #ifndef PPI_CHG3_CH3_Excluded 1283 #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded 1284 #endif 1285 #ifndef PPI_CHG3_CH3_Included 1286 #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included 1287 #endif 1288 1289 #ifndef PPI_CHG3_CH2_Pos 1290 #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos 1291 #endif 1292 #ifndef PPI_CHG3_CH2_Msk 1293 #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk 1294 #endif 1295 #ifndef PPI_CHG3_CH2_Excluded 1296 #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded 1297 #endif 1298 #ifndef PPI_CHG3_CH2_Included 1299 #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included 1300 #endif 1301 1302 #ifndef PPI_CHG3_CH1_Pos 1303 #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos 1304 #endif 1305 #ifndef PPI_CHG3_CH1_Msk 1306 #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk 1307 #endif 1308 #ifndef PPI_CHG3_CH1_Excluded 1309 #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded 1310 #endif 1311 #ifndef PPI_CHG3_CH1_Included 1312 #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included 1313 #endif 1314 1315 #ifndef PPI_CHG3_CH0_Pos 1316 #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos 1317 #endif 1318 #ifndef PPI_CHG3_CH0_Msk 1319 #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk 1320 #endif 1321 #ifndef PPI_CHG3_CH0_Excluded 1322 #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded 1323 #endif 1324 #ifndef PPI_CHG3_CH0_Included 1325 #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included 1326 #endif 1327 1328 1329 1330 1331 1332 /*lint --flb "Leave library region" */ 1333 1334 #endif /* NRF51_TO_NRF52840_H */ 1335 1336
