1 /* 2 3 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 4 5 SPDX-License-Identifier: BSD-3-Clause 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, this 11 list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of Nordic Semiconductor ASA nor the names of its 18 contributors may be used to endorse or promote products derived from this 19 software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 35 #ifndef NRF51_TO_NRF52_H 36 #define NRF51_TO_NRF52_H 37 38 /*lint ++flb "Enter library region */ 39 40 /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. 41 * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the 42 * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros 43 * from the nrf51_deprecated.h file. */ 44 45 46 /* IRQ */ 47 /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ 48 #ifndef UART0_IRQHandler 49 #define UART0_IRQHandler UARTE0_UART0_IRQHandler 50 #endif 51 #ifndef SPI0_TWI0_IRQHandler 52 #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 53 #endif 54 #ifndef SPI1_TWI1_IRQHandler 55 #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 56 #endif 57 #ifndef ADC_IRQHandler 58 #define ADC_IRQHandler SAADC_IRQHandler 59 #endif 60 #ifndef LPCOMP_IRQHandler 61 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 62 #endif 63 #ifndef SWI0_IRQHandler 64 #define SWI0_IRQHandler SWI0_EGU0_IRQHandler 65 #endif 66 #ifndef SWI1_IRQHandler 67 #define SWI1_IRQHandler SWI1_EGU1_IRQHandler 68 #endif 69 #ifndef SWI2_IRQHandler 70 #define SWI2_IRQHandler SWI2_EGU2_IRQHandler 71 #endif 72 #ifndef SWI3_IRQHandler 73 #define SWI3_IRQHandler SWI3_EGU3_IRQHandler 74 #endif 75 #ifndef SWI4_IRQHandler 76 #define SWI4_IRQHandler SWI4_EGU4_IRQHandler 77 #endif 78 #ifndef SWI5_IRQHandler 79 #define SWI5_IRQHandler SWI5_EGU5_IRQHandler 80 #endif 81 82 #ifndef UART0_IRQn 83 #define UART0_IRQn UARTE0_UART0_IRQn 84 #endif 85 #ifndef SPI0_TWI0_IRQn 86 #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 87 #endif 88 #ifndef SPI1_TWI1_IRQn 89 #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 90 #endif 91 #ifndef ADC_IRQn 92 #define ADC_IRQn SAADC_IRQn 93 #endif 94 #ifndef LPCOMP_IRQn 95 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 96 #endif 97 #ifndef SWI0_IRQn 98 #define SWI0_IRQn SWI0_EGU0_IRQn 99 #endif 100 #ifndef SWI1_IRQn 101 #define SWI1_IRQn SWI1_EGU1_IRQn 102 #endif 103 #ifndef SWI2_IRQn 104 #define SWI2_IRQn SWI2_EGU2_IRQn 105 #endif 106 #ifndef SWI3_IRQn 107 #define SWI3_IRQn SWI3_EGU3_IRQn 108 #endif 109 #ifndef SWI4_IRQn 110 #define SWI4_IRQn SWI4_EGU4_IRQn 111 #endif 112 #ifndef SWI5_IRQn 113 #define SWI5_IRQn SWI5_EGU5_IRQn 114 #endif 115 116 117 /* UICR */ 118 /* Register RBPCONF was renamed to APPROTECT. */ 119 #ifndef RBPCONF 120 #define RBPCONF APPROTECT 121 #endif 122 123 #ifndef UICR_RBPCONF_PALL_Pos 124 #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos 125 #endif 126 #ifndef UICR_RBPCONF_PALL_Msk 127 #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk 128 #endif 129 #ifndef UICR_RBPCONF_PALL_Enabled 130 #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled 131 #endif 132 #ifndef UICR_RBPCONF_PALL_Disabled 133 #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled 134 #endif 135 136 /* GPIO */ 137 /* GPIO port was renamed to P0. */ 138 #ifndef NRF_GPIO 139 #define NRF_GPIO NRF_P0 140 #endif 141 #ifndef NRF_GPIO_BASE 142 #define NRF_GPIO_BASE NRF_P0_BASE 143 #endif 144 145 /* QDEC */ 146 /* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ 147 #ifndef PSELLED 148 #define PSELLED PSEL.LED 149 #endif 150 #ifndef PSELA 151 #define PSELA PSEL.A 152 #endif 153 #ifndef PSELB 154 #define PSELB PSEL.B 155 #endif 156 157 158 /* SPIS */ 159 /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ 160 #ifndef PSELSCK 161 #define PSELSCK PSEL.SCK 162 #endif 163 #ifndef PSELMISO 164 #define PSELMISO PSEL.MISO 165 #endif 166 #ifndef PSELMOSI 167 #define PSELMOSI PSEL.MOSI 168 #endif 169 #ifndef PSELCSN 170 #define PSELCSN PSEL.CSN 171 #endif 172 173 /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ 174 #ifndef RXDPTR 175 #define RXDPTR RXD.PTR 176 #endif 177 #ifndef MAXRX 178 #define MAXRX RXD.MAXCNT 179 #endif 180 #ifndef AMOUNTRX 181 #define AMOUNTRX RXD.AMOUNT 182 #endif 183 184 #ifndef SPIS_MAXRX_MAXRX_Pos 185 #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos 186 #endif 187 #ifndef SPIS_MAXRX_MAXRX_Msk 188 #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk 189 #endif 190 191 #ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos 192 #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos 193 #endif 194 #ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk 195 #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk 196 #endif 197 198 /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ 199 #ifndef TXDPTR 200 #define TXDPTR TXD.PTR 201 #endif 202 #ifndef MAXTX 203 #define MAXTX TXD.MAXCNT 204 #endif 205 #ifndef AMOUNTTX 206 #define AMOUNTTX TXD.AMOUNT 207 #endif 208 209 #ifndef SPIS_MAXTX_MAXTX_Pos 210 #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos 211 #endif 212 #ifndef SPIS_MAXTX_MAXTX_Msk 213 #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk 214 #endif 215 216 #ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos 217 #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos 218 #endif 219 #ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk 220 #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk 221 #endif 222 223 /* MPU */ 224 /* Part of MPU module was renamed BPROT, while the rest was eliminated. */ 225 #ifndef NRF_MPU 226 #define NRF_MPU NRF_BPROT 227 #endif 228 229 /* Register DISABLEINDEBUG macros were affected. */ 230 #ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos 231 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos 232 #endif 233 #ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk 234 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk 235 #endif 236 #ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled 237 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled 238 #endif 239 #ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled 240 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled 241 #endif 242 243 /* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ 244 #ifndef PROTENSET0 245 #define PROTENSET0 CONFIG0 246 #endif 247 #ifndef PROTENSET1 248 #define PROTENSET1 CONFIG1 249 #endif 250 251 #ifndef MPU_PROTENSET1_PROTREG63_Pos 252 #define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos 253 #endif 254 #ifndef MPU_PROTENSET1_PROTREG63_Msk 255 #define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk 256 #endif 257 #ifndef MPU_PROTENSET1_PROTREG63_Disabled 258 #define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled 259 #endif 260 #ifndef MPU_PROTENSET1_PROTREG63_Enabled 261 #define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled 262 #endif 263 #ifndef MPU_PROTENSET1_PROTREG63_Set 264 #define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled 265 #endif 266 267 #ifndef MPU_PROTENSET1_PROTREG62_Pos 268 #define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos 269 #endif 270 #ifndef MPU_PROTENSET1_PROTREG62_Msk 271 #define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk 272 #endif 273 #ifndef MPU_PROTENSET1_PROTREG62_Disabled 274 #define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled 275 #endif 276 #ifndef MPU_PROTENSET1_PROTREG62_Enabled 277 #define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled 278 #endif 279 #ifndef MPU_PROTENSET1_PROTREG62_Set 280 #define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled 281 #endif 282 283 #ifndef MPU_PROTENSET1_PROTREG61_Pos 284 #define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos 285 #endif 286 #ifndef MPU_PROTENSET1_PROTREG61_Msk 287 #define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk 288 #endif 289 #ifndef MPU_PROTENSET1_PROTREG61_Disabled 290 #define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled 291 #endif 292 #ifndef MPU_PROTENSET1_PROTREG61_Enabled 293 #define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled 294 #endif 295 #ifndef MPU_PROTENSET1_PROTREG61_Set 296 #define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled 297 #endif 298 299 #ifndef MPU_PROTENSET1_PROTREG60_Pos 300 #define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos 301 #endif 302 #ifndef MPU_PROTENSET1_PROTREG60_Msk 303 #define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk 304 #endif 305 #ifndef MPU_PROTENSET1_PROTREG60_Disabled 306 #define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled 307 #endif 308 #ifndef MPU_PROTENSET1_PROTREG60_Enabled 309 #define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled 310 #endif 311 #ifndef MPU_PROTENSET1_PROTREG60_Set 312 #define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled 313 #endif 314 315 #ifndef MPU_PROTENSET1_PROTREG59_Pos 316 #define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos 317 #endif 318 #ifndef MPU_PROTENSET1_PROTREG59_Msk 319 #define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk 320 #endif 321 #ifndef MPU_PROTENSET1_PROTREG59_Disabled 322 #define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled 323 #endif 324 #ifndef MPU_PROTENSET1_PROTREG59_Enabled 325 #define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled 326 #endif 327 #ifndef MPU_PROTENSET1_PROTREG59_Set 328 #define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled 329 #endif 330 331 #ifndef MPU_PROTENSET1_PROTREG58_Pos 332 #define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos 333 #endif 334 #ifndef MPU_PROTENSET1_PROTREG58_Msk 335 #define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk 336 #endif 337 #ifndef MPU_PROTENSET1_PROTREG58_Disabled 338 #define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled 339 #endif 340 #ifndef MPU_PROTENSET1_PROTREG58_Enabled 341 #define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled 342 #endif 343 #ifndef MPU_PROTENSET1_PROTREG58_Set 344 #define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled 345 #endif 346 347 #ifndef MPU_PROTENSET1_PROTREG57_Pos 348 #define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos 349 #endif 350 #ifndef MPU_PROTENSET1_PROTREG57_Msk 351 #define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk 352 #endif 353 #ifndef MPU_PROTENSET1_PROTREG57_Disabled 354 #define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled 355 #endif 356 #ifndef MPU_PROTENSET1_PROTREG57_Enabled 357 #define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled 358 #endif 359 #ifndef MPU_PROTENSET1_PROTREG57_Set 360 #define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled 361 #endif 362 363 #ifndef MPU_PROTENSET1_PROTREG56_Pos 364 #define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos 365 #endif 366 #ifndef MPU_PROTENSET1_PROTREG56_Msk 367 #define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk 368 #endif 369 #ifndef MPU_PROTENSET1_PROTREG56_Disabled 370 #define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled 371 #endif 372 #ifndef MPU_PROTENSET1_PROTREG56_Enabled 373 #define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled 374 #endif 375 #ifndef MPU_PROTENSET1_PROTREG56_Set 376 #define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled 377 #endif 378 379 #ifndef MPU_PROTENSET1_PROTREG55_Pos 380 #define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos 381 #endif 382 #ifndef MPU_PROTENSET1_PROTREG55_Msk 383 #define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk 384 #endif 385 #ifndef MPU_PROTENSET1_PROTREG55_Disabled 386 #define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled 387 #endif 388 #ifndef MPU_PROTENSET1_PROTREG55_Enabled 389 #define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled 390 #endif 391 #ifndef MPU_PROTENSET1_PROTREG55_Set 392 #define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled 393 #endif 394 395 #ifndef MPU_PROTENSET1_PROTREG54_Pos 396 #define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos 397 #endif 398 #ifndef MPU_PROTENSET1_PROTREG54_Msk 399 #define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk 400 #endif 401 #ifndef MPU_PROTENSET1_PROTREG54_Disabled 402 #define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled 403 #endif 404 #ifndef MPU_PROTENSET1_PROTREG54_Enabled 405 #define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled 406 #endif 407 #ifndef MPU_PROTENSET1_PROTREG54_Set 408 #define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled 409 #endif 410 411 #ifndef MPU_PROTENSET1_PROTREG53_Pos 412 #define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos 413 #endif 414 #ifndef MPU_PROTENSET1_PROTREG53_Msk 415 #define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk 416 #endif 417 #ifndef MPU_PROTENSET1_PROTREG53_Disabled 418 #define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled 419 #endif 420 #ifndef MPU_PROTENSET1_PROTREG53_Enabled 421 #define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled 422 #endif 423 #ifndef MPU_PROTENSET1_PROTREG53_Set 424 #define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled 425 #endif 426 427 #ifndef MPU_PROTENSET1_PROTREG52_Pos 428 #define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos 429 #endif 430 #ifndef MPU_PROTENSET1_PROTREG52_Msk 431 #define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk 432 #endif 433 #ifndef MPU_PROTENSET1_PROTREG52_Disabled 434 #define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled 435 #endif 436 #ifndef MPU_PROTENSET1_PROTREG52_Enabled 437 #define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled 438 #endif 439 #ifndef MPU_PROTENSET1_PROTREG52_Set 440 #define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled 441 #endif 442 443 #ifndef MPU_PROTENSET1_PROTREG51_Pos 444 #define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos 445 #endif 446 #ifndef MPU_PROTENSET1_PROTREG51_Msk 447 #define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk 448 #endif 449 #ifndef MPU_PROTENSET1_PROTREG51_Disabled 450 #define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled 451 #endif 452 #ifndef MPU_PROTENSET1_PROTREG51_Enabled 453 #define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled 454 #endif 455 #ifndef MPU_PROTENSET1_PROTREG51_Set 456 #define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled 457 #endif 458 459 #ifndef MPU_PROTENSET1_PROTREG50_Pos 460 #define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos 461 #endif 462 #ifndef MPU_PROTENSET1_PROTREG50_Msk 463 #define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk 464 #endif 465 #ifndef MPU_PROTENSET1_PROTREG50_Disabled 466 #define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled 467 #endif 468 #ifndef MPU_PROTENSET1_PROTREG50_Enabled 469 #define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled 470 #endif 471 #ifndef MPU_PROTENSET1_PROTREG50_Set 472 #define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled 473 #endif 474 475 #ifndef MPU_PROTENSET1_PROTREG49_Pos 476 #define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos 477 #endif 478 #ifndef MPU_PROTENSET1_PROTREG49_Msk 479 #define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk 480 #endif 481 #ifndef MPU_PROTENSET1_PROTREG49_Disabled 482 #define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled 483 #endif 484 #ifndef MPU_PROTENSET1_PROTREG49_Enabled 485 #define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled 486 #endif 487 #ifndef MPU_PROTENSET1_PROTREG49_Set 488 #define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled 489 #endif 490 491 #ifndef MPU_PROTENSET1_PROTREG48_Pos 492 #define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos 493 #endif 494 #ifndef MPU_PROTENSET1_PROTREG48_Msk 495 #define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk 496 #endif 497 #ifndef MPU_PROTENSET1_PROTREG48_Disabled 498 #define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled 499 #endif 500 #ifndef MPU_PROTENSET1_PROTREG48_Enabled 501 #define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled 502 #endif 503 #ifndef MPU_PROTENSET1_PROTREG48_Set 504 #define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled 505 #endif 506 507 #ifndef MPU_PROTENSET1_PROTREG47_Pos 508 #define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos 509 #endif 510 #ifndef MPU_PROTENSET1_PROTREG47_Msk 511 #define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk 512 #endif 513 #ifndef MPU_PROTENSET1_PROTREG47_Disabled 514 #define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled 515 #endif 516 #ifndef MPU_PROTENSET1_PROTREG47_Enabled 517 #define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled 518 #endif 519 #ifndef MPU_PROTENSET1_PROTREG47_Set 520 #define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled 521 #endif 522 523 #ifndef MPU_PROTENSET1_PROTREG46_Pos 524 #define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos 525 #endif 526 #ifndef MPU_PROTENSET1_PROTREG46_Msk 527 #define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk 528 #endif 529 #ifndef MPU_PROTENSET1_PROTREG46_Disabled 530 #define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled 531 #endif 532 #ifndef MPU_PROTENSET1_PROTREG46_Enabled 533 #define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled 534 #endif 535 #ifndef MPU_PROTENSET1_PROTREG46_Set 536 #define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled 537 #endif 538 539 #ifndef MPU_PROTENSET1_PROTREG45_Pos 540 #define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos 541 #endif 542 #ifndef MPU_PROTENSET1_PROTREG45_Msk 543 #define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk 544 #endif 545 #ifndef MPU_PROTENSET1_PROTREG45_Disabled 546 #define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled 547 #endif 548 #ifndef MPU_PROTENSET1_PROTREG45_Enabled 549 #define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled 550 #endif 551 #ifndef MPU_PROTENSET1_PROTREG45_Set 552 #define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled 553 #endif 554 555 #ifndef MPU_PROTENSET1_PROTREG44_Pos 556 #define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos 557 #endif 558 #ifndef MPU_PROTENSET1_PROTREG44_Msk 559 #define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk 560 #endif 561 #ifndef MPU_PROTENSET1_PROTREG44_Disabled 562 #define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled 563 #endif 564 #ifndef MPU_PROTENSET1_PROTREG44_Enabled 565 #define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled 566 #endif 567 #ifndef MPU_PROTENSET1_PROTREG44_Set 568 #define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled 569 #endif 570 571 #ifndef MPU_PROTENSET1_PROTREG43_Pos 572 #define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos 573 #endif 574 #ifndef MPU_PROTENSET1_PROTREG43_Msk 575 #define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk 576 #endif 577 #ifndef MPU_PROTENSET1_PROTREG43_Disabled 578 #define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled 579 #endif 580 #ifndef MPU_PROTENSET1_PROTREG43_Enabled 581 #define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled 582 #endif 583 #ifndef MPU_PROTENSET1_PROTREG43_Set 584 #define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled 585 #endif 586 587 #ifndef MPU_PROTENSET1_PROTREG42_Pos 588 #define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos 589 #endif 590 #ifndef MPU_PROTENSET1_PROTREG42_Msk 591 #define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk 592 #endif 593 #ifndef MPU_PROTENSET1_PROTREG42_Disabled 594 #define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled 595 #endif 596 #ifndef MPU_PROTENSET1_PROTREG42_Enabled 597 #define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled 598 #endif 599 #ifndef MPU_PROTENSET1_PROTREG42_Set 600 #define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled 601 #endif 602 603 #ifndef MPU_PROTENSET1_PROTREG41_Pos 604 #define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos 605 #endif 606 #ifndef MPU_PROTENSET1_PROTREG41_Msk 607 #define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk 608 #endif 609 #ifndef MPU_PROTENSET1_PROTREG41_Disabled 610 #define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled 611 #endif 612 #ifndef MPU_PROTENSET1_PROTREG41_Enabled 613 #define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled 614 #endif 615 #ifndef MPU_PROTENSET1_PROTREG41_Set 616 #define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled 617 #endif 618 619 #ifndef MPU_PROTENSET1_PROTREG40_Pos 620 #define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos 621 #endif 622 #ifndef MPU_PROTENSET1_PROTREG40_Msk 623 #define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk 624 #endif 625 #ifndef MPU_PROTENSET1_PROTREG40_Disabled 626 #define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled 627 #endif 628 #ifndef MPU_PROTENSET1_PROTREG40_Enabled 629 #define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled 630 #endif 631 #ifndef MPU_PROTENSET1_PROTREG40_Set 632 #define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled 633 #endif 634 635 #ifndef MPU_PROTENSET1_PROTREG39_Pos 636 #define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos 637 #endif 638 #ifndef MPU_PROTENSET1_PROTREG39_Msk 639 #define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk 640 #endif 641 #ifndef MPU_PROTENSET1_PROTREG39_Disabled 642 #define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled 643 #endif 644 #ifndef MPU_PROTENSET1_PROTREG39_Enabled 645 #define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled 646 #endif 647 #ifndef MPU_PROTENSET1_PROTREG39_Set 648 #define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled 649 #endif 650 651 #ifndef MPU_PROTENSET1_PROTREG38_Pos 652 #define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos 653 #endif 654 #ifndef MPU_PROTENSET1_PROTREG38_Msk 655 #define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk 656 #endif 657 #ifndef MPU_PROTENSET1_PROTREG38_Disabled 658 #define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled 659 #endif 660 #ifndef MPU_PROTENSET1_PROTREG38_Enabled 661 #define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled 662 #endif 663 #ifndef MPU_PROTENSET1_PROTREG38_Set 664 #define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled 665 #endif 666 667 #ifndef MPU_PROTENSET1_PROTREG37_Pos 668 #define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos 669 #endif 670 #ifndef MPU_PROTENSET1_PROTREG37_Msk 671 #define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk 672 #endif 673 #ifndef MPU_PROTENSET1_PROTREG37_Disabled 674 #define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled 675 #endif 676 #ifndef MPU_PROTENSET1_PROTREG37_Enabled 677 #define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled 678 #endif 679 #ifndef MPU_PROTENSET1_PROTREG37_Set 680 #define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled 681 #endif 682 683 #ifndef MPU_PROTENSET1_PROTREG36_Pos 684 #define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos 685 #endif 686 #ifndef MPU_PROTENSET1_PROTREG36_Msk 687 #define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk 688 #endif 689 #ifndef MPU_PROTENSET1_PROTREG36_Disabled 690 #define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled 691 #endif 692 #ifndef MPU_PROTENSET1_PROTREG36_Enabled 693 #define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled 694 #endif 695 #ifndef MPU_PROTENSET1_PROTREG36_Set 696 #define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled 697 #endif 698 699 #ifndef MPU_PROTENSET1_PROTREG35_Pos 700 #define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos 701 #endif 702 #ifndef MPU_PROTENSET1_PROTREG35_Msk 703 #define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk 704 #endif 705 #ifndef MPU_PROTENSET1_PROTREG35_Disabled 706 #define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled 707 #endif 708 #ifndef MPU_PROTENSET1_PROTREG35_Enabled 709 #define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled 710 #endif 711 #ifndef MPU_PROTENSET1_PROTREG35_Set 712 #define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled 713 #endif 714 715 #ifndef MPU_PROTENSET1_PROTREG34_Pos 716 #define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos 717 #endif 718 #ifndef MPU_PROTENSET1_PROTREG34_Msk 719 #define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk 720 #endif 721 #ifndef MPU_PROTENSET1_PROTREG34_Disabled 722 #define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled 723 #endif 724 #ifndef MPU_PROTENSET1_PROTREG34_Enabled 725 #define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled 726 #endif 727 #ifndef MPU_PROTENSET1_PROTREG34_Set 728 #define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled 729 #endif 730 731 #ifndef MPU_PROTENSET1_PROTREG33_Pos 732 #define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos 733 #endif 734 #ifndef MPU_PROTENSET1_PROTREG33_Msk 735 #define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk 736 #endif 737 #ifndef MPU_PROTENSET1_PROTREG33_Disabled 738 #define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled 739 #endif 740 #ifndef MPU_PROTENSET1_PROTREG33_Enabled 741 #define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled 742 #endif 743 #ifndef MPU_PROTENSET1_PROTREG33_Set 744 #define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled 745 #endif 746 747 #ifndef MPU_PROTENSET1_PROTREG32_Pos 748 #define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos 749 #endif 750 #ifndef MPU_PROTENSET1_PROTREG32_Msk 751 #define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk 752 #endif 753 #ifndef MPU_PROTENSET1_PROTREG32_Disabled 754 #define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled 755 #endif 756 #ifndef MPU_PROTENSET1_PROTREG32_Enabled 757 #define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled 758 #endif 759 #ifndef MPU_PROTENSET1_PROTREG32_Set 760 #define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled 761 #endif 762 763 #ifndef MPU_PROTENSET0_PROTREG31_Pos 764 #define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos 765 #endif 766 #ifndef MPU_PROTENSET0_PROTREG31_Msk 767 #define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk 768 #endif 769 #ifndef MPU_PROTENSET0_PROTREG31_Disabled 770 #define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled 771 #endif 772 #ifndef MPU_PROTENSET0_PROTREG31_Enabled 773 #define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled 774 #endif 775 #ifndef MPU_PROTENSET0_PROTREG31_Set 776 #define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled 777 #endif 778 779 #ifndef MPU_PROTENSET0_PROTREG30_Pos 780 #define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos 781 #endif 782 #ifndef MPU_PROTENSET0_PROTREG30_Msk 783 #define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk 784 #endif 785 #ifndef MPU_PROTENSET0_PROTREG30_Disabled 786 #define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled 787 #endif 788 #ifndef MPU_PROTENSET0_PROTREG30_Enabled 789 #define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled 790 #endif 791 #ifndef MPU_PROTENSET0_PROTREG30_Set 792 #define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled 793 #endif 794 795 #ifndef MPU_PROTENSET0_PROTREG29_Pos 796 #define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos 797 #endif 798 #ifndef MPU_PROTENSET0_PROTREG29_Msk 799 #define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk 800 #endif 801 #ifndef MPU_PROTENSET0_PROTREG29_Disabled 802 #define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled 803 #endif 804 #ifndef MPU_PROTENSET0_PROTREG29_Enabled 805 #define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled 806 #endif 807 #ifndef MPU_PROTENSET0_PROTREG29_Set 808 #define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled 809 #endif 810 811 #ifndef MPU_PROTENSET0_PROTREG28_Pos 812 #define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos 813 #endif 814 #ifndef MPU_PROTENSET0_PROTREG28_Msk 815 #define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk 816 #endif 817 #ifndef MPU_PROTENSET0_PROTREG28_Disabled 818 #define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled 819 #endif 820 #ifndef MPU_PROTENSET0_PROTREG28_Enabled 821 #define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled 822 #endif 823 #ifndef MPU_PROTENSET0_PROTREG28_Set 824 #define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled 825 #endif 826 827 #ifndef MPU_PROTENSET0_PROTREG27_Pos 828 #define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos 829 #endif 830 #ifndef MPU_PROTENSET0_PROTREG27_Msk 831 #define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk 832 #endif 833 #ifndef MPU_PROTENSET0_PROTREG27_Disabled 834 #define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled 835 #endif 836 #ifndef MPU_PROTENSET0_PROTREG27_Enabled 837 #define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled 838 #endif 839 #ifndef MPU_PROTENSET0_PROTREG27_Set 840 #define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled 841 #endif 842 843 #ifndef MPU_PROTENSET0_PROTREG26_Pos 844 #define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos 845 #endif 846 #ifndef MPU_PROTENSET0_PROTREG26_Msk 847 #define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk 848 #endif 849 #ifndef MPU_PROTENSET0_PROTREG26_Disabled 850 #define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled 851 #endif 852 #ifndef MPU_PROTENSET0_PROTREG26_Enabled 853 #define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled 854 #endif 855 #ifndef MPU_PROTENSET0_PROTREG26_Set 856 #define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled 857 #endif 858 859 #ifndef MPU_PROTENSET0_PROTREG25_Pos 860 #define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos 861 #endif 862 #ifndef MPU_PROTENSET0_PROTREG25_Msk 863 #define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk 864 #endif 865 #ifndef MPU_PROTENSET0_PROTREG25_Disabled 866 #define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled 867 #endif 868 #ifndef MPU_PROTENSET0_PROTREG25_Enabled 869 #define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled 870 #endif 871 #ifndef MPU_PROTENSET0_PROTREG25_Set 872 #define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled 873 #endif 874 875 #ifndef MPU_PROTENSET0_PROTREG24_Pos 876 #define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos 877 #endif 878 #ifndef MPU_PROTENSET0_PROTREG24_Msk 879 #define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk 880 #endif 881 #ifndef MPU_PROTENSET0_PROTREG24_Disabled 882 #define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled 883 #endif 884 #ifndef MPU_PROTENSET0_PROTREG24_Enabled 885 #define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled 886 #endif 887 #ifndef MPU_PROTENSET0_PROTREG24_Set 888 #define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled 889 #endif 890 891 #ifndef MPU_PROTENSET0_PROTREG23_Pos 892 #define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos 893 #endif 894 #ifndef MPU_PROTENSET0_PROTREG23_Msk 895 #define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk 896 #endif 897 #ifndef MPU_PROTENSET0_PROTREG23_Disabled 898 #define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled 899 #endif 900 #ifndef MPU_PROTENSET0_PROTREG23_Enabled 901 #define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled 902 #endif 903 #ifndef MPU_PROTENSET0_PROTREG23_Set 904 #define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled 905 #endif 906 907 #ifndef MPU_PROTENSET0_PROTREG22_Pos 908 #define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos 909 #endif 910 #ifndef MPU_PROTENSET0_PROTREG22_Msk 911 #define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk 912 #endif 913 #ifndef MPU_PROTENSET0_PROTREG22_Disabled 914 #define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled 915 #endif 916 #ifndef MPU_PROTENSET0_PROTREG22_Enabled 917 #define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled 918 #endif 919 #ifndef MPU_PROTENSET0_PROTREG22_Set 920 #define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled 921 #endif 922 923 #ifndef MPU_PROTENSET0_PROTREG21_Pos 924 #define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos 925 #endif 926 #ifndef MPU_PROTENSET0_PROTREG21_Msk 927 #define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk 928 #endif 929 #ifndef MPU_PROTENSET0_PROTREG21_Disabled 930 #define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled 931 #endif 932 #ifndef MPU_PROTENSET0_PROTREG21_Enabled 933 #define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled 934 #endif 935 #ifndef MPU_PROTENSET0_PROTREG21_Set 936 #define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled 937 #endif 938 939 #ifndef MPU_PROTENSET0_PROTREG20_Pos 940 #define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos 941 #endif 942 #ifndef MPU_PROTENSET0_PROTREG20_Msk 943 #define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk 944 #endif 945 #ifndef MPU_PROTENSET0_PROTREG20_Disabled 946 #define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled 947 #endif 948 #ifndef MPU_PROTENSET0_PROTREG20_Enabled 949 #define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled 950 #endif 951 #ifndef MPU_PROTENSET0_PROTREG20_Set 952 #define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled 953 #endif 954 955 #ifndef MPU_PROTENSET0_PROTREG19_Pos 956 #define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos 957 #endif 958 #ifndef MPU_PROTENSET0_PROTREG19_Msk 959 #define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk 960 #endif 961 #ifndef MPU_PROTENSET0_PROTREG19_Disabled 962 #define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled 963 #endif 964 #ifndef MPU_PROTENSET0_PROTREG19_Enabled 965 #define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled 966 #endif 967 #ifndef MPU_PROTENSET0_PROTREG19_Set 968 #define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled 969 #endif 970 971 #ifndef MPU_PROTENSET0_PROTREG18_Pos 972 #define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos 973 #endif 974 #ifndef MPU_PROTENSET0_PROTREG18_Msk 975 #define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk 976 #endif 977 #ifndef MPU_PROTENSET0_PROTREG18_Disabled 978 #define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled 979 #endif 980 #ifndef MPU_PROTENSET0_PROTREG18_Enabled 981 #define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled 982 #endif 983 #ifndef MPU_PROTENSET0_PROTREG18_Set 984 #define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled 985 #endif 986 987 #ifndef MPU_PROTENSET0_PROTREG17_Pos 988 #define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos 989 #endif 990 #ifndef MPU_PROTENSET0_PROTREG17_Msk 991 #define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk 992 #endif 993 #ifndef MPU_PROTENSET0_PROTREG17_Disabled 994 #define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled 995 #endif 996 #ifndef MPU_PROTENSET0_PROTREG17_Enabled 997 #define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled 998 #endif 999 #ifndef MPU_PROTENSET0_PROTREG17_Set 1000 #define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled 1001 #endif 1002 1003 #ifndef MPU_PROTENSET0_PROTREG16_Pos 1004 #define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos 1005 #endif 1006 #ifndef MPU_PROTENSET0_PROTREG16_Msk 1007 #define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk 1008 #endif 1009 #ifndef MPU_PROTENSET0_PROTREG16_Disabled 1010 #define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled 1011 #endif 1012 #ifndef MPU_PROTENSET0_PROTREG16_Enabled 1013 #define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled 1014 #endif 1015 #ifndef MPU_PROTENSET0_PROTREG16_Set 1016 #define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled 1017 #endif 1018 1019 #ifndef MPU_PROTENSET0_PROTREG16_Set 1020 #define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos 1021 #endif 1022 #ifndef MPU_PROTENSET0_PROTREG15_Msk 1023 #define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk 1024 #endif 1025 #ifndef MPU_PROTENSET0_PROTREG15_Disabled 1026 #define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled 1027 #endif 1028 #ifndef MPU_PROTENSET0_PROTREG15_Enabled 1029 #define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled 1030 #endif 1031 #ifndef MPU_PROTENSET0_PROTREG15_Set 1032 #define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled 1033 #endif 1034 1035 #ifndef MPU_PROTENSET0_PROTREG14_Pos 1036 #define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos 1037 #endif 1038 #ifndef MPU_PROTENSET0_PROTREG14_Msk 1039 #define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk 1040 #endif 1041 #ifndef MPU_PROTENSET0_PROTREG14_Disabled 1042 #define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled 1043 #endif 1044 #ifndef MPU_PROTENSET0_PROTREG14_Enabled 1045 #define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled 1046 #endif 1047 #ifndef MPU_PROTENSET0_PROTREG14_Set 1048 #define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled 1049 #endif 1050 1051 #ifndef MPU_PROTENSET0_PROTREG13_Pos 1052 #define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos 1053 #endif 1054 #ifndef MPU_PROTENSET0_PROTREG13_Msk 1055 #define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk 1056 #endif 1057 #ifndef MPU_PROTENSET0_PROTREG13_Disabled 1058 #define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled 1059 #endif 1060 #ifndef MPU_PROTENSET0_PROTREG13_Enabled 1061 #define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled 1062 #endif 1063 #ifndef MPU_PROTENSET0_PROTREG13_Set 1064 #define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled 1065 #endif 1066 1067 #ifndef MPU_PROTENSET0_PROTREG12_Pos 1068 #define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos 1069 #endif 1070 #ifndef MPU_PROTENSET0_PROTREG12_Msk 1071 #define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk 1072 #endif 1073 #ifndef MPU_PROTENSET0_PROTREG12_Disabled 1074 #define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled 1075 #endif 1076 #ifndef MPU_PROTENSET0_PROTREG12_Enabled 1077 #define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled 1078 #endif 1079 #ifndef MPU_PROTENSET0_PROTREG12_Set 1080 #define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled 1081 #endif 1082 1083 #ifndef MPU_PROTENSET0_PROTREG11_Pos 1084 #define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos 1085 #endif 1086 #ifndef MPU_PROTENSET0_PROTREG11_Msk 1087 #define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk 1088 #endif 1089 #ifndef MPU_PROTENSET0_PROTREG11_Disabled 1090 #define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled 1091 #endif 1092 #ifndef MPU_PROTENSET0_PROTREG11_Enabled 1093 #define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled 1094 #endif 1095 #ifndef MPU_PROTENSET0_PROTREG11_Set 1096 #define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled 1097 #endif 1098 1099 #ifndef MPU_PROTENSET0_PROTREG10_Pos 1100 #define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos 1101 #endif 1102 #ifndef MPU_PROTENSET0_PROTREG10_Msk 1103 #define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk 1104 #endif 1105 #ifndef MPU_PROTENSET0_PROTREG10_Disabled 1106 #define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled 1107 #endif 1108 #ifndef MPU_PROTENSET0_PROTREG10_Enabled 1109 #define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled 1110 #endif 1111 #ifndef MPU_PROTENSET0_PROTREG10_Set 1112 #define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled 1113 #endif 1114 1115 #ifndef MPU_PROTENSET0_PROTREG9_Pos 1116 #define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos 1117 #endif 1118 #ifndef MPU_PROTENSET0_PROTREG9_Msk 1119 #define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk 1120 #endif 1121 #ifndef MPU_PROTENSET0_PROTREG9_Disabled 1122 #define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled 1123 #endif 1124 #ifndef MPU_PROTENSET0_PROTREG9_Enabled 1125 #define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled 1126 #endif 1127 #ifndef MPU_PROTENSET0_PROTREG9_Set 1128 #define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled 1129 #endif 1130 1131 #ifndef MPU_PROTENSET0_PROTREG8_Pos 1132 #define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos 1133 #endif 1134 #ifndef MPU_PROTENSET0_PROTREG8_Msk 1135 #define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk 1136 #endif 1137 #ifndef MPU_PROTENSET0_PROTREG8_Disabled 1138 #define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled 1139 #endif 1140 #ifndef MPU_PROTENSET0_PROTREG8_Enabled 1141 #define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled 1142 #endif 1143 #ifndef MPU_PROTENSET0_PROTREG8_Set 1144 #define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled 1145 #endif 1146 1147 #ifndef MPU_PROTENSET0_PROTREG7_Pos 1148 #define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos 1149 #endif 1150 #ifndef MPU_PROTENSET0_PROTREG7_Msk 1151 #define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk 1152 #endif 1153 #ifndef MPU_PROTENSET0_PROTREG7_Disabled 1154 #define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled 1155 #endif 1156 #ifndef MPU_PROTENSET0_PROTREG7_Enabled 1157 #define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled 1158 #endif 1159 #ifndef MPU_PROTENSET0_PROTREG7_Set 1160 #define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled 1161 #endif 1162 1163 #ifndef MPU_PROTENSET0_PROTREG6_Pos 1164 #define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos 1165 #endif 1166 #ifndef MPU_PROTENSET0_PROTREG6_Msk 1167 #define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk 1168 #endif 1169 #ifndef MPU_PROTENSET0_PROTREG6_Disabled 1170 #define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled 1171 #endif 1172 #ifndef MPU_PROTENSET0_PROTREG6_Enabled 1173 #define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled 1174 #endif 1175 #ifndef MPU_PROTENSET0_PROTREG6_Set 1176 #define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled 1177 #endif 1178 1179 #ifndef MPU_PROTENSET0_PROTREG5_Pos 1180 #define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos 1181 #endif 1182 #ifndef MPU_PROTENSET0_PROTREG5_Msk 1183 #define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk 1184 #endif 1185 #ifndef MPU_PROTENSET0_PROTREG5_Disabled 1186 #define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled 1187 #endif 1188 #ifndef MPU_PROTENSET0_PROTREG5_Enabled 1189 #define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled 1190 #endif 1191 #ifndef MPU_PROTENSET0_PROTREG5_Set 1192 #define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled 1193 #endif 1194 1195 #ifndef MPU_PROTENSET0_PROTREG4_Pos 1196 #define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos 1197 #endif 1198 #ifndef MPU_PROTENSET0_PROTREG4_Msk 1199 #define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk 1200 #endif 1201 #ifndef MPU_PROTENSET0_PROTREG4_Disabled 1202 #define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled 1203 #endif 1204 #ifndef MPU_PROTENSET0_PROTREG4_Enabled 1205 #define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled 1206 #endif 1207 #ifndef MPU_PROTENSET0_PROTREG4_Set 1208 #define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled 1209 #endif 1210 1211 #ifndef MPU_PROTENSET0_PROTREG3_Pos 1212 #define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos 1213 #endif 1214 #ifndef MPU_PROTENSET0_PROTREG3_Msk 1215 #define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk 1216 #endif 1217 #ifndef MPU_PROTENSET0_PROTREG3_Disabled 1218 #define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled 1219 #endif 1220 #ifndef MPU_PROTENSET0_PROTREG3_Enabled 1221 #define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled 1222 #endif 1223 #ifndef MPU_PROTENSET0_PROTREG3_Set 1224 #define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled 1225 #endif 1226 1227 #ifndef MPU_PROTENSET0_PROTREG2_Pos 1228 #define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos 1229 #endif 1230 #ifndef MPU_PROTENSET0_PROTREG2_Msk 1231 #define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk 1232 #endif 1233 #ifndef MPU_PROTENSET0_PROTREG2_Disabled 1234 #define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled 1235 #endif 1236 #ifndef MPU_PROTENSET0_PROTREG2_Enabled 1237 #define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled 1238 #endif 1239 #ifndef MPU_PROTENSET0_PROTREG2_Set 1240 #define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled 1241 #endif 1242 1243 #ifndef MPU_PROTENSET0_PROTREG1_Pos 1244 #define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos 1245 #endif 1246 #ifndef MPU_PROTENSET0_PROTREG1_Msk 1247 #define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk 1248 #endif 1249 #ifndef MPU_PROTENSET0_PROTREG1_Disabled 1250 #define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled 1251 #endif 1252 #ifndef MPU_PROTENSET0_PROTREG1_Enabled 1253 #define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled 1254 #endif 1255 #ifndef MPU_PROTENSET0_PROTREG1_Set 1256 #define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled 1257 #endif 1258 1259 #ifndef MPU_PROTENSET0_PROTREG0_Pos 1260 #define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos 1261 #endif 1262 #ifndef MPU_PROTENSET0_PROTREG0_Msk 1263 #define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk 1264 #endif 1265 #ifndef MPU_PROTENSET0_PROTREG0_Disabled 1266 #define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled 1267 #endif 1268 #ifndef MPU_PROTENSET0_PROTREG0_Enabled 1269 #define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled 1270 #endif 1271 #ifndef MPU_PROTENSET0_PROTREG0_Set 1272 #define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled 1273 #endif 1274 1275 1276 /* From nrf51_deprecated.h */ 1277 1278 /* NVMC */ 1279 /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. ERASEPCR0 and ERASEPCR1 have been deprecated for some time and are removed, since they are equivalent to ERASEPAGE. */ 1280 #ifndef ERASEPROTECTEDPAGE 1281 #define ERASEPROTECTEDPAGE ERASEPAGE 1282 #endif 1283 #ifndef ERASEPCR1 1284 #define ERASEPCR1 ERASEPAGE 1285 #endif 1286 #ifndef ERASEPCR0 1287 #define ERASEPCR0 ERASEPAGE 1288 #endif 1289 1290 #ifndef NVMC_ERASEPCR1_ERASEPCR1_Pos 1291 #define NVMC_ERASEPCR1_ERASEPCR1_Pos NVMC_ERASEPAGE_ERASEPAGE_Pos 1292 #endif 1293 #ifndef NVMC_ERASEPCR1_ERASEPCR1_Msk 1294 #define NVMC_ERASEPCR1_ERASEPCR1_Msk NVMC_ERASEPAGE_ERASEPAGE_Msk 1295 #endif 1296 #ifndef NVMC_ERASEPCR0_ERASEPCR0_Pos 1297 #define NVMC_ERASEPCR0_ERASEPCR0_Pos NVMC_ERASEPAGE_ERASEPAGE_Pos 1298 #endif 1299 #ifndef NVMC_ERASEPCR0_ERASEPCR0_Msk 1300 #define NVMC_ERASEPCR0_ERASEPCR0_Msk NVMC_ERASEPAGE_ERASEPAGE_Msk 1301 #endif 1302 1303 1304 /* IRQ */ 1305 /* COMP module was eliminated. Adapted to nrf52 headers. */ 1306 #ifndef LPCOMP_COMP_IRQHandler 1307 #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler 1308 #endif 1309 #ifndef LPCOMP_COMP_IRQn 1310 #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn 1311 #endif 1312 1313 1314 /* REFSEL register redefined enumerated values and added some more. */ 1315 #ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling 1316 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd 1317 #endif 1318 #ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling 1319 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd 1320 #endif 1321 #ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling 1322 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd 1323 #endif 1324 #ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling 1325 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd 1326 #endif 1327 #ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling 1328 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd 1329 #endif 1330 #ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling 1331 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd 1332 #endif 1333 #ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling 1334 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd 1335 #endif 1336 1337 /* RADIO */ 1338 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ 1339 #ifndef RADIO_CRCCNF_SKIP_ADDR_Pos 1340 #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos 1341 #endif 1342 #ifndef RADIO_CRCCNF_SKIP_ADDR_Msk 1343 #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk 1344 #endif 1345 #ifndef RADIO_CRCCNF_SKIP_ADDR_Include 1346 #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include 1347 #endif 1348 #ifndef RADIO_CRCCNF_SKIP_ADDR_Skip 1349 #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip 1350 #endif 1351 1352 1353 /* FICR */ 1354 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ 1355 #ifndef DEVICEID0 1356 #define DEVICEID0 DEVICEID[0] 1357 #endif 1358 #ifndef DEVICEID1 1359 #define DEVICEID1 DEVICEID[1] 1360 #endif 1361 1362 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ 1363 #ifndef ER0 1364 #define ER0 ER[0] 1365 #endif 1366 #ifndef ER1 1367 #define ER1 ER[1] 1368 #endif 1369 #ifndef ER2 1370 #define ER2 ER[2] 1371 #endif 1372 #ifndef ER3 1373 #define ER3 ER[3] 1374 #endif 1375 1376 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ 1377 #ifndef IR0 1378 #define IR0 IR[0] 1379 #endif 1380 #ifndef IR1 1381 #define IR1 IR[1] 1382 #endif 1383 #ifndef IR2 1384 #define IR2 IR[2] 1385 #endif 1386 #ifndef IR3 1387 #define IR3 IR[3] 1388 #endif 1389 1390 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ 1391 #ifndef DEVICEADDR0 1392 #define DEVICEADDR0 DEVICEADDR[0] 1393 #endif 1394 #ifndef DEVICEADDR1 1395 #define DEVICEADDR1 DEVICEADDR[1] 1396 #endif 1397 1398 1399 /* PPI */ 1400 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ 1401 #ifndef TASKS_CHG0EN 1402 #define TASKS_CHG0EN TASKS_CHG[0].EN 1403 #endif 1404 #ifndef TASKS_CHG0DIS 1405 #define TASKS_CHG0DIS TASKS_CHG[0].DIS 1406 #endif 1407 #ifndef TASKS_CHG1EN 1408 #define TASKS_CHG1EN TASKS_CHG[1].EN 1409 #endif 1410 #ifndef TASKS_CHG1DIS 1411 #define TASKS_CHG1DIS TASKS_CHG[1].DIS 1412 #endif 1413 #ifndef TASKS_CHG2EN 1414 #define TASKS_CHG2EN TASKS_CHG[2].EN 1415 #endif 1416 #ifndef TASKS_CHG2DIS 1417 #define TASKS_CHG2DIS TASKS_CHG[2].DIS 1418 #endif 1419 #ifndef TASKS_CHG3EN 1420 #define TASKS_CHG3EN TASKS_CHG[3].EN 1421 #endif 1422 #ifndef TASKS_CHG3DIS 1423 #define TASKS_CHG3DIS TASKS_CHG[3].DIS 1424 #endif 1425 1426 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ 1427 #ifndef CH0_EEP 1428 #define CH0_EEP CH[0].EEP 1429 #endif 1430 #ifndef CH0_TEP 1431 #define CH0_TEP CH[0].TEP 1432 #endif 1433 #ifndef CH1_EEP 1434 #define CH1_EEP CH[1].EEP 1435 #endif 1436 #ifndef CH1_TEP 1437 #define CH1_TEP CH[1].TEP 1438 #endif 1439 #ifndef CH2_EEP 1440 #define CH2_EEP CH[2].EEP 1441 #endif 1442 #ifndef CH2_TEP 1443 #define CH2_TEP CH[2].TEP 1444 #endif 1445 #ifndef CH3_EEP 1446 #define CH3_EEP CH[3].EEP 1447 #endif 1448 #ifndef CH3_TEP 1449 #define CH3_TEP CH[3].TEP 1450 #endif 1451 #ifndef CH4_EEP 1452 #define CH4_EEP CH[4].EEP 1453 #endif 1454 #ifndef CH4_TEP 1455 #define CH4_TEP CH[4].TEP 1456 #endif 1457 #ifndef CH5_EEP 1458 #define CH5_EEP CH[5].EEP 1459 #endif 1460 #ifndef CH5_TEP 1461 #define CH5_TEP CH[5].TEP 1462 #endif 1463 #ifndef CH6_EEP 1464 #define CH6_EEP CH[6].EEP 1465 #endif 1466 #ifndef CH6_TEP 1467 #define CH6_TEP CH[6].TEP 1468 #endif 1469 #ifndef CH7_EEP 1470 #define CH7_EEP CH[7].EEP 1471 #endif 1472 #ifndef CH7_TEP 1473 #define CH7_TEP CH[7].TEP 1474 #endif 1475 #ifndef CH8_EEP 1476 #define CH8_EEP CH[8].EEP 1477 #endif 1478 #ifndef CH8_TEP 1479 #define CH8_TEP CH[8].TEP 1480 #endif 1481 #ifndef CH9_EEP 1482 #define CH9_EEP CH[9].EEP 1483 #endif 1484 #ifndef CH9_TEP 1485 #define CH9_TEP CH[9].TEP 1486 #endif 1487 #ifndef CH10_EEP 1488 #define CH10_EEP CH[10].EEP 1489 #endif 1490 #ifndef CH10_TEP 1491 #define CH10_TEP CH[10].TEP 1492 #endif 1493 #ifndef CH11_EEP 1494 #define CH11_EEP CH[11].EEP 1495 #endif 1496 #ifndef CH11_TEP 1497 #define CH11_TEP CH[11].TEP 1498 #endif 1499 #ifndef CH12_EEP 1500 #define CH12_EEP CH[12].EEP 1501 #endif 1502 #ifndef CH12_TEP 1503 #define CH12_TEP CH[12].TEP 1504 #endif 1505 #ifndef CH13_EEP 1506 #define CH13_EEP CH[13].EEP 1507 #endif 1508 #ifndef CH13_TEP 1509 #define CH13_TEP CH[13].TEP 1510 #endif 1511 #ifndef CH14_EEP 1512 #define CH14_EEP CH[14].EEP 1513 #endif 1514 #ifndef CH14_TEP 1515 #define CH14_TEP CH[14].TEP 1516 #endif 1517 #ifndef CH15_EEP 1518 #define CH15_EEP CH[15].EEP 1519 #endif 1520 #ifndef CH15_TEP 1521 #define CH15_TEP CH[15].TEP 1522 #endif 1523 1524 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ 1525 #ifndef CHG0 1526 #define CHG0 CHG[0] 1527 #endif 1528 #ifndef CHG1 1529 #define CHG1 CHG[1] 1530 #endif 1531 #ifndef CHG2 1532 #define CHG2 CHG[2] 1533 #endif 1534 #ifndef CHG3 1535 #define CHG3 CHG[3] 1536 #endif 1537 1538 /* All bitfield macros for the CHGx registers therefore changed name. */ 1539 #ifndef PPI_CHG0_CH15_Pos 1540 #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos 1541 #endif 1542 #ifndef PPI_CHG0_CH15_Msk 1543 #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk 1544 #endif 1545 #ifndef PPI_CHG0_CH15_Excluded 1546 #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded 1547 #endif 1548 #ifndef PPI_CHG0_CH15_Included 1549 #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included 1550 #endif 1551 1552 #ifndef PPI_CHG0_CH14_Pos 1553 #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos 1554 #endif 1555 #ifndef PPI_CHG0_CH14_Msk 1556 #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk 1557 #endif 1558 #ifndef PPI_CHG0_CH14_Excluded 1559 #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded 1560 #endif 1561 #ifndef PPI_CHG0_CH14_Included 1562 #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included 1563 #endif 1564 1565 #ifndef PPI_CHG0_CH13_Pos 1566 #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos 1567 #endif 1568 #ifndef PPI_CHG0_CH13_Msk 1569 #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk 1570 #endif 1571 #ifndef PPI_CHG0_CH13_Excluded 1572 #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded 1573 #endif 1574 #ifndef PPI_CHG0_CH13_Included 1575 #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included 1576 #endif 1577 1578 #ifndef PPI_CHG0_CH12_Pos 1579 #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos 1580 #endif 1581 #ifndef PPI_CHG0_CH12_Msk 1582 #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk 1583 #endif 1584 #ifndef PPI_CHG0_CH12_Excluded 1585 #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded 1586 #endif 1587 #ifndef PPI_CHG0_CH12_Included 1588 #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included 1589 #endif 1590 1591 #ifndef PPI_CHG0_CH11_Pos 1592 #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos 1593 #endif 1594 #ifndef PPI_CHG0_CH11_Msk 1595 #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk 1596 #endif 1597 #ifndef PPI_CHG0_CH11_Excluded 1598 #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded 1599 #endif 1600 #ifndef PPI_CHG0_CH11_Included 1601 #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included 1602 #endif 1603 1604 #ifndef PPI_CHG0_CH10_Pos 1605 #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos 1606 #endif 1607 #ifndef PPI_CHG0_CH10_Msk 1608 #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk 1609 #endif 1610 #ifndef PPI_CHG0_CH10_Excluded 1611 #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded 1612 #endif 1613 #ifndef PPI_CHG0_CH10_Included 1614 #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included 1615 #endif 1616 1617 #ifndef PPI_CHG0_CH9_Pos 1618 #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos 1619 #endif 1620 #ifndef PPI_CHG0_CH9_Msk 1621 #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk 1622 #endif 1623 #ifndef PPI_CHG0_CH9_Excluded 1624 #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded 1625 #endif 1626 #ifndef PPI_CHG0_CH9_Included 1627 #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included 1628 #endif 1629 1630 #ifndef PPI_CHG0_CH8_Pos 1631 #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos 1632 #endif 1633 #ifndef PPI_CHG0_CH8_Msk 1634 #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk 1635 #endif 1636 #ifndef PPI_CHG0_CH8_Excluded 1637 #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded 1638 #endif 1639 #ifndef PPI_CHG0_CH8_Included 1640 #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included 1641 #endif 1642 1643 #ifndef PPI_CHG0_CH7_Pos 1644 #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos 1645 #endif 1646 #ifndef PPI_CHG0_CH7_Msk 1647 #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk 1648 #endif 1649 #ifndef PPI_CHG0_CH7_Excluded 1650 #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded 1651 #endif 1652 #ifndef PPI_CHG0_CH7_Included 1653 #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included 1654 #endif 1655 1656 #ifndef PPI_CHG0_CH6_Pos 1657 #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos 1658 #endif 1659 #ifndef PPI_CHG0_CH6_Msk 1660 #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk 1661 #endif 1662 #ifndef PPI_CHG0_CH6_Excluded 1663 #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded 1664 #endif 1665 #ifndef PPI_CHG0_CH6_Included 1666 #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included 1667 #endif 1668 1669 #ifndef PPI_CHG0_CH5_Pos 1670 #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos 1671 #endif 1672 #ifndef PPI_CHG0_CH5_Msk 1673 #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk 1674 #endif 1675 #ifndef PPI_CHG0_CH5_Excluded 1676 #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded 1677 #endif 1678 #ifndef PPI_CHG0_CH5_Included 1679 #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included 1680 #endif 1681 1682 #ifndef PPI_CHG0_CH4_Pos 1683 #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos 1684 #endif 1685 #ifndef PPI_CHG0_CH4_Msk 1686 #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk 1687 #endif 1688 #ifndef PPI_CHG0_CH4_Excluded 1689 #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded 1690 #endif 1691 #ifndef PPI_CHG0_CH4_Included 1692 #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included 1693 #endif 1694 1695 #ifndef PPI_CHG0_CH3_Pos 1696 #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos 1697 #endif 1698 #ifndef PPI_CHG0_CH3_Msk 1699 #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk 1700 #endif 1701 #ifndef PPI_CHG0_CH3_Excluded 1702 #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded 1703 #endif 1704 #ifndef PPI_CHG0_CH3_Included 1705 #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included 1706 #endif 1707 1708 #ifndef PPI_CHG0_CH2_Pos 1709 #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos 1710 #endif 1711 #ifndef PPI_CHG0_CH2_Msk 1712 #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk 1713 #endif 1714 #ifndef PPI_CHG0_CH2_Excluded 1715 #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded 1716 #endif 1717 #ifndef PPI_CHG0_CH2_Included 1718 #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included 1719 #endif 1720 1721 #ifndef PPI_CHG0_CH1_Pos 1722 #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos 1723 #endif 1724 #ifndef PPI_CHG0_CH1_Msk 1725 #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk 1726 #endif 1727 #ifndef PPI_CHG0_CH1_Excluded 1728 #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded 1729 #endif 1730 #ifndef PPI_CHG0_CH1_Included 1731 #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included 1732 #endif 1733 1734 #ifndef PPI_CHG0_CH0_Pos 1735 #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos 1736 #endif 1737 #ifndef PPI_CHG0_CH0_Msk 1738 #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk 1739 #endif 1740 #ifndef PPI_CHG0_CH0_Excluded 1741 #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded 1742 #endif 1743 #ifndef PPI_CHG0_CH0_Included 1744 #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included 1745 #endif 1746 1747 #ifndef PPI_CHG1_CH15_Pos 1748 #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos 1749 #endif 1750 #ifndef PPI_CHG1_CH15_Msk 1751 #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk 1752 #endif 1753 #ifndef PPI_CHG1_CH15_Excluded 1754 #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded 1755 #endif 1756 #ifndef PPI_CHG1_CH15_Included 1757 #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included 1758 #endif 1759 1760 #ifndef PPI_CHG1_CH14_Pos 1761 #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos 1762 #endif 1763 #ifndef PPI_CHG1_CH14_Msk 1764 #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk 1765 #endif 1766 #ifndef PPI_CHG1_CH14_Excluded 1767 #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded 1768 #endif 1769 #ifndef PPI_CHG1_CH14_Included 1770 #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included 1771 #endif 1772 1773 #ifndef PPI_CHG1_CH13_Pos 1774 #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos 1775 #endif 1776 #ifndef PPI_CHG1_CH13_Msk 1777 #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk 1778 #endif 1779 #ifndef PPI_CHG1_CH13_Excluded 1780 #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded 1781 #endif 1782 #ifndef PPI_CHG1_CH13_Included 1783 #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included 1784 #endif 1785 1786 #ifndef PPI_CHG1_CH12_Pos 1787 #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos 1788 #endif 1789 #ifndef PPI_CHG1_CH12_Msk 1790 #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk 1791 #endif 1792 #ifndef PPI_CHG1_CH12_Excluded 1793 #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded 1794 #endif 1795 #ifndef PPI_CHG1_CH12_Included 1796 #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included 1797 #endif 1798 1799 #ifndef PPI_CHG1_CH11_Pos 1800 #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos 1801 #endif 1802 #ifndef PPI_CHG1_CH11_Msk 1803 #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk 1804 #endif 1805 #ifndef PPI_CHG1_CH11_Excluded 1806 #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded 1807 #endif 1808 #ifndef PPI_CHG1_CH11_Included 1809 #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included 1810 #endif 1811 1812 #ifndef PPI_CHG1_CH10_Pos 1813 #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos 1814 #endif 1815 #ifndef PPI_CHG1_CH10_Msk 1816 #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk 1817 #endif 1818 #ifndef PPI_CHG1_CH10_Excluded 1819 #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded 1820 #endif 1821 #ifndef PPI_CHG1_CH10_Included 1822 #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included 1823 #endif 1824 1825 #ifndef PPI_CHG1_CH9_Pos 1826 #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos 1827 #endif 1828 #ifndef PPI_CHG1_CH9_Msk 1829 #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk 1830 #endif 1831 #ifndef PPI_CHG1_CH9_Excluded 1832 #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded 1833 #endif 1834 #ifndef PPI_CHG1_CH9_Included 1835 #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included 1836 #endif 1837 1838 #ifndef PPI_CHG1_CH8_Pos 1839 #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos 1840 #endif 1841 #ifndef PPI_CHG1_CH8_Msk 1842 #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk 1843 #endif 1844 #ifndef PPI_CHG1_CH8_Excluded 1845 #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded 1846 #endif 1847 #ifndef PPI_CHG1_CH8_Included 1848 #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included 1849 #endif 1850 1851 #ifndef PPI_CHG1_CH7_Pos 1852 #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos 1853 #endif 1854 #ifndef PPI_CHG1_CH7_Msk 1855 #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk 1856 #endif 1857 #ifndef PPI_CHG1_CH7_Excluded 1858 #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded 1859 #endif 1860 #ifndef PPI_CHG1_CH7_Included 1861 #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included 1862 #endif 1863 1864 #ifndef PPI_CHG1_CH6_Pos 1865 #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos 1866 #endif 1867 #ifndef PPI_CHG1_CH6_Msk 1868 #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk 1869 #endif 1870 #ifndef PPI_CHG1_CH6_Excluded 1871 #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded 1872 #endif 1873 #ifndef PPI_CHG1_CH6_Included 1874 #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included 1875 #endif 1876 1877 #ifndef PPI_CHG1_CH5_Pos 1878 #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos 1879 #endif 1880 #ifndef PPI_CHG1_CH5_Msk 1881 #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk 1882 #endif 1883 #ifndef PPI_CHG1_CH5_Excluded 1884 #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded 1885 #endif 1886 #ifndef PPI_CHG1_CH5_Included 1887 #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included 1888 #endif 1889 1890 #ifndef PPI_CHG1_CH4_Pos 1891 #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos 1892 #endif 1893 #ifndef PPI_CHG1_CH4_Msk 1894 #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk 1895 #endif 1896 #ifndef PPI_CHG1_CH4_Excluded 1897 #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded 1898 #endif 1899 #ifndef PPI_CHG1_CH4_Included 1900 #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included 1901 #endif 1902 1903 #ifndef PPI_CHG1_CH3_Pos 1904 #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos 1905 #endif 1906 #ifndef PPI_CHG1_CH3_Msk 1907 #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk 1908 #endif 1909 #ifndef PPI_CHG1_CH3_Excluded 1910 #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded 1911 #endif 1912 #ifndef PPI_CHG1_CH3_Included 1913 #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included 1914 #endif 1915 1916 #ifndef PPI_CHG1_CH2_Pos 1917 #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos 1918 #endif 1919 #ifndef PPI_CHG1_CH2_Msk 1920 #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk 1921 #endif 1922 #ifndef PPI_CHG1_CH2_Excluded 1923 #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded 1924 #endif 1925 #ifndef PPI_CHG1_CH2_Included 1926 #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included 1927 #endif 1928 1929 #ifndef PPI_CHG1_CH1_Pos 1930 #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos 1931 #endif 1932 #ifndef PPI_CHG1_CH1_Msk 1933 #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk 1934 #endif 1935 #ifndef PPI_CHG1_CH1_Excluded 1936 #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded 1937 #endif 1938 #ifndef PPI_CHG1_CH1_Included 1939 #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included 1940 #endif 1941 1942 #ifndef PPI_CHG1_CH0_Pos 1943 #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos 1944 #endif 1945 #ifndef PPI_CHG1_CH0_Msk 1946 #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk 1947 #endif 1948 #ifndef PPI_CHG1_CH0_Excluded 1949 #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded 1950 #endif 1951 #ifndef PPI_CHG1_CH0_Included 1952 #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included 1953 #endif 1954 1955 #ifndef PPI_CHG2_CH15_Pos 1956 #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos 1957 #endif 1958 #ifndef PPI_CHG2_CH15_Msk 1959 #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk 1960 #endif 1961 #ifndef PPI_CHG2_CH15_Excluded 1962 #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded 1963 #endif 1964 #ifndef PPI_CHG2_CH15_Included 1965 #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included 1966 #endif 1967 1968 #ifndef PPI_CHG2_CH14_Pos 1969 #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos 1970 #endif 1971 #ifndef PPI_CHG2_CH14_Msk 1972 #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk 1973 #endif 1974 #ifndef PPI_CHG2_CH14_Excluded 1975 #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded 1976 #endif 1977 #ifndef PPI_CHG2_CH14_Included 1978 #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included 1979 #endif 1980 1981 #ifndef PPI_CHG2_CH13_Pos 1982 #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos 1983 #endif 1984 #ifndef PPI_CHG2_CH13_Msk 1985 #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk 1986 #endif 1987 #ifndef PPI_CHG2_CH13_Excluded 1988 #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded 1989 #endif 1990 #ifndef PPI_CHG2_CH13_Included 1991 #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included 1992 #endif 1993 1994 #ifndef PPI_CHG2_CH12_Pos 1995 #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos 1996 #endif 1997 #ifndef PPI_CHG2_CH12_Msk 1998 #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk 1999 #endif 2000 #ifndef PPI_CHG2_CH12_Excluded 2001 #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded 2002 #endif 2003 #ifndef PPI_CHG2_CH12_Included 2004 #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included 2005 #endif 2006 2007 #ifndef PPI_CHG2_CH11_Pos 2008 #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos 2009 #endif 2010 #ifndef PPI_CHG2_CH11_Msk 2011 #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk 2012 #endif 2013 #ifndef PPI_CHG2_CH11_Excluded 2014 #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded 2015 #endif 2016 #ifndef PPI_CHG2_CH11_Included 2017 #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included 2018 #endif 2019 2020 #ifndef PPI_CHG2_CH10_Pos 2021 #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos 2022 #endif 2023 #ifndef PPI_CHG2_CH10_Msk 2024 #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk 2025 #endif 2026 #ifndef PPI_CHG2_CH10_Excluded 2027 #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded 2028 #endif 2029 #ifndef PPI_CHG2_CH10_Included 2030 #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included 2031 #endif 2032 2033 #ifndef PPI_CHG2_CH9_Pos 2034 #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos 2035 #endif 2036 #ifndef PPI_CHG2_CH9_Msk 2037 #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk 2038 #endif 2039 #ifndef PPI_CHG2_CH9_Excluded 2040 #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded 2041 #endif 2042 #ifndef PPI_CHG2_CH9_Included 2043 #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included 2044 #endif 2045 2046 #ifndef PPI_CHG2_CH8_Pos 2047 #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos 2048 #endif 2049 #ifndef PPI_CHG2_CH8_Msk 2050 #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk 2051 #endif 2052 #ifndef PPI_CHG2_CH8_Excluded 2053 #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded 2054 #endif 2055 #ifndef PPI_CHG2_CH8_Included 2056 #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included 2057 #endif 2058 2059 #ifndef PPI_CHG2_CH7_Pos 2060 #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos 2061 #endif 2062 #ifndef PPI_CHG2_CH7_Msk 2063 #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk 2064 #endif 2065 #ifndef PPI_CHG2_CH7_Excluded 2066 #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded 2067 #endif 2068 #ifndef PPI_CHG2_CH7_Included 2069 #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included 2070 #endif 2071 2072 #ifndef PPI_CHG2_CH6_Pos 2073 #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos 2074 #endif 2075 #ifndef PPI_CHG2_CH6_Msk 2076 #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk 2077 #endif 2078 #ifndef PPI_CHG2_CH6_Excluded 2079 #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded 2080 #endif 2081 #ifndef PPI_CHG2_CH6_Included 2082 #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included 2083 #endif 2084 2085 #ifndef PPI_CHG2_CH5_Pos 2086 #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos 2087 #endif 2088 #ifndef PPI_CHG2_CH5_Msk 2089 #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk 2090 #endif 2091 #ifndef PPI_CHG2_CH5_Excluded 2092 #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded 2093 #endif 2094 #ifndef PPI_CHG2_CH5_Included 2095 #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included 2096 #endif 2097 2098 #ifndef PPI_CHG2_CH4_Pos 2099 #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos 2100 #endif 2101 #ifndef PPI_CHG2_CH4_Msk 2102 #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk 2103 #endif 2104 #ifndef PPI_CHG2_CH4_Excluded 2105 #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded 2106 #endif 2107 #ifndef PPI_CHG2_CH4_Included 2108 #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included 2109 #endif 2110 2111 #ifndef PPI_CHG2_CH3_Pos 2112 #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos 2113 #endif 2114 #ifndef PPI_CHG2_CH3_Msk 2115 #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk 2116 #endif 2117 #ifndef PPI_CHG2_CH3_Excluded 2118 #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded 2119 #endif 2120 #ifndef PPI_CHG2_CH3_Included 2121 #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included 2122 #endif 2123 2124 #ifndef PPI_CHG2_CH2_Pos 2125 #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos 2126 #endif 2127 #ifndef PPI_CHG2_CH2_Msk 2128 #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk 2129 #endif 2130 #ifndef PPI_CHG2_CH2_Excluded 2131 #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded 2132 #endif 2133 #ifndef PPI_CHG2_CH2_Included 2134 #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included 2135 #endif 2136 2137 #ifndef PPI_CHG2_CH1_Pos 2138 #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos 2139 #endif 2140 #ifndef PPI_CHG2_CH1_Msk 2141 #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk 2142 #endif 2143 #ifndef PPI_CHG2_CH1_Excluded 2144 #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded 2145 #endif 2146 #ifndef PPI_CHG2_CH1_Included 2147 #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included 2148 #endif 2149 2150 #ifndef PPI_CHG2_CH0_Pos 2151 #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos 2152 #endif 2153 #ifndef PPI_CHG2_CH0_Msk 2154 #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk 2155 #endif 2156 #ifndef PPI_CHG2_CH0_Excluded 2157 #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded 2158 #endif 2159 #ifndef PPI_CHG2_CH0_Included 2160 #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included 2161 #endif 2162 2163 #ifndef PPI_CHG3_CH15_Pos 2164 #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos 2165 #endif 2166 #ifndef PPI_CHG3_CH15_Msk 2167 #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk 2168 #endif 2169 #ifndef PPI_CHG3_CH15_Excluded 2170 #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded 2171 #endif 2172 #ifndef PPI_CHG3_CH15_Included 2173 #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included 2174 #endif 2175 2176 #ifndef PPI_CHG3_CH14_Pos 2177 #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos 2178 #endif 2179 #ifndef PPI_CHG3_CH14_Msk 2180 #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk 2181 #endif 2182 #ifndef PPI_CHG3_CH14_Excluded 2183 #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded 2184 #endif 2185 #ifndef PPI_CHG3_CH14_Included 2186 #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included 2187 #endif 2188 2189 #ifndef PPI_CHG3_CH13_Pos 2190 #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos 2191 #endif 2192 #ifndef PPI_CHG3_CH13_Msk 2193 #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk 2194 #endif 2195 #ifndef PPI_CHG3_CH13_Excluded 2196 #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded 2197 #endif 2198 #ifndef PPI_CHG3_CH13_Included 2199 #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included 2200 #endif 2201 2202 #ifndef PPI_CHG3_CH12_Pos 2203 #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos 2204 #endif 2205 #ifndef PPI_CHG3_CH12_Msk 2206 #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk 2207 #endif 2208 #ifndef PPI_CHG3_CH12_Excluded 2209 #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded 2210 #endif 2211 #ifndef PPI_CHG3_CH12_Included 2212 #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included 2213 #endif 2214 2215 #ifndef PPI_CHG3_CH11_Pos 2216 #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos 2217 #endif 2218 #ifndef PPI_CHG3_CH11_Msk 2219 #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk 2220 #endif 2221 #ifndef PPI_CHG3_CH11_Excluded 2222 #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded 2223 #endif 2224 #ifndef PPI_CHG3_CH11_Included 2225 #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included 2226 #endif 2227 2228 #ifndef PPI_CHG3_CH10_Pos 2229 #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos 2230 #endif 2231 #ifndef PPI_CHG3_CH10_Msk 2232 #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk 2233 #endif 2234 #ifndef PPI_CHG3_CH10_Excluded 2235 #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded 2236 #endif 2237 #ifndef PPI_CHG3_CH10_Included 2238 #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included 2239 #endif 2240 2241 #ifndef PPI_CHG3_CH9_Pos 2242 #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos 2243 #endif 2244 #ifndef PPI_CHG3_CH9_Msk 2245 #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk 2246 #endif 2247 #ifndef PPI_CHG3_CH9_Excluded 2248 #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded 2249 #endif 2250 #ifndef PPI_CHG3_CH9_Included 2251 #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included 2252 #endif 2253 2254 #ifndef PPI_CHG3_CH8_Pos 2255 #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos 2256 #endif 2257 #ifndef PPI_CHG3_CH8_Msk 2258 #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk 2259 #endif 2260 #ifndef PPI_CHG3_CH8_Excluded 2261 #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded 2262 #endif 2263 #ifndef PPI_CHG3_CH8_Included 2264 #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included 2265 #endif 2266 2267 #ifndef PPI_CHG3_CH7_Pos 2268 #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos 2269 #endif 2270 #ifndef PPI_CHG3_CH7_Msk 2271 #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk 2272 #endif 2273 #ifndef PPI_CHG3_CH7_Excluded 2274 #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded 2275 #endif 2276 #ifndef PPI_CHG3_CH7_Included 2277 #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included 2278 #endif 2279 2280 #ifndef PPI_CHG3_CH6_Pos 2281 #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos 2282 #endif 2283 #ifndef PPI_CHG3_CH6_Msk 2284 #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk 2285 #endif 2286 #ifndef PPI_CHG3_CH6_Excluded 2287 #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded 2288 #endif 2289 #ifndef PPI_CHG3_CH6_Included 2290 #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included 2291 #endif 2292 2293 #ifndef PPI_CHG3_CH5_Pos 2294 #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos 2295 #endif 2296 #ifndef PPI_CHG3_CH5_Msk 2297 #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk 2298 #endif 2299 #ifndef PPI_CHG3_CH5_Excluded 2300 #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded 2301 #endif 2302 #ifndef PPI_CHG3_CH5_Included 2303 #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included 2304 #endif 2305 2306 #ifndef PPI_CHG3_CH4_Pos 2307 #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos 2308 #endif 2309 #ifndef PPI_CHG3_CH4_Msk 2310 #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk 2311 #endif 2312 #ifndef PPI_CHG3_CH4_Excluded 2313 #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded 2314 #endif 2315 #ifndef PPI_CHG3_CH4_Included 2316 #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included 2317 #endif 2318 2319 #ifndef PPI_CHG3_CH3_Pos 2320 #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos 2321 #endif 2322 #ifndef PPI_CHG3_CH3_Msk 2323 #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk 2324 #endif 2325 #ifndef PPI_CHG3_CH3_Excluded 2326 #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded 2327 #endif 2328 #ifndef PPI_CHG3_CH3_Included 2329 #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included 2330 #endif 2331 2332 #ifndef PPI_CHG3_CH2_Pos 2333 #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos 2334 #endif 2335 #ifndef PPI_CHG3_CH2_Msk 2336 #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk 2337 #endif 2338 #ifndef PPI_CHG3_CH2_Excluded 2339 #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded 2340 #endif 2341 #ifndef PPI_CHG3_CH2_Included 2342 #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included 2343 #endif 2344 2345 #ifndef PPI_CHG3_CH1_Pos 2346 #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos 2347 #endif 2348 #ifndef PPI_CHG3_CH1_Msk 2349 #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk 2350 #endif 2351 #ifndef PPI_CHG3_CH1_Excluded 2352 #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded 2353 #endif 2354 #ifndef PPI_CHG3_CH1_Included 2355 #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included 2356 #endif 2357 2358 #ifndef PPI_CHG3_CH0_Pos 2359 #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos 2360 #endif 2361 #ifndef PPI_CHG3_CH0_Msk 2362 #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk 2363 #endif 2364 #ifndef PPI_CHG3_CH0_Excluded 2365 #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded 2366 #endif 2367 #ifndef PPI_CHG3_CH0_Included 2368 #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included 2369 #endif 2370 2371 2372 2373 /*lint --flb "Leave library region" */ 2374 2375 #endif /* NRF51_TO_NRF52_H */ 2376 2377
